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ppc: load/store multiple and string insns don't do LE
[qemu/kevin.git] / target-ppc / translate.c
blob379d3d46c47eba8cae856d47f808752e119a9640
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 bool need_access_type;
199 int mem_idx;
200 int access_type;
201 /* Translation flags */
202 TCGMemOp default_tcg_memop_mask;
203 #if defined(TARGET_PPC64)
204 bool sf_mode;
205 bool has_cfar;
206 #endif
207 bool fpu_enabled;
208 bool altivec_enabled;
209 bool vsx_enabled;
210 bool spe_enabled;
211 bool tm_enabled;
212 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled;
214 uint64_t insns_flags;
215 uint64_t insns_flags2;
216 };
217
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext *ctx)
220 {
221 #if defined(TARGET_WORDS_BIGENDIAN)
222 return ctx->le_mode;
223 #else
224 return !ctx->le_mode;
225 #endif
226 }
227
228 /* True when active word size < size of target_long. */
229 #ifdef TARGET_PPC64
230 # define NARROW_MODE(C) (!(C)->sf_mode)
231 #else
232 # define NARROW_MODE(C) 0
233 #endif
234
235 struct opc_handler_t {
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 uint32_t inval1;
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 uint32_t inval2;
240 /* instruction type */
241 uint64_t type;
242 /* extended instruction type */
243 uint64_t type2;
244 /* handler */
245 void (*handler)(DisasContext *ctx);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
247 const char *oname;
248 #endif
249 #if defined(DO_PPC_STATISTICS)
250 uint64_t count;
251 #endif
252 };
253
254 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
255 {
256 if (ctx->need_access_type && ctx->access_type != access_type) {
257 tcg_gen_movi_i32(cpu_access_type, access_type);
258 ctx->access_type = access_type;
259 }
260 }
261
262 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
263 {
264 if (NARROW_MODE(ctx)) {
265 nip = (uint32_t)nip;
266 }
267 tcg_gen_movi_tl(cpu_nip, nip);
268 }
269
270 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
271 {
272 TCGv_i32 t0, t1;
273
274 /* These are all synchronous exceptions, we set the PC back to
275 * the faulting instruction
276 */
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->nip - 4);
279 }
280 t0 = tcg_const_i32(excp);
281 t1 = tcg_const_i32(error);
282 gen_helper_raise_exception_err(cpu_env, t0, t1);
283 tcg_temp_free_i32(t0);
284 tcg_temp_free_i32(t1);
285 ctx->exception = (excp);
286 }
287
288 static void gen_exception(DisasContext *ctx, uint32_t excp)
289 {
290 TCGv_i32 t0;
291
292 /* These are all synchronous exceptions, we set the PC back to
293 * the faulting instruction
294 */
295 if (ctx->exception == POWERPC_EXCP_NONE) {
296 gen_update_nip(ctx, ctx->nip - 4);
297 }
298 t0 = tcg_const_i32(excp);
299 gen_helper_raise_exception(cpu_env, t0);
300 tcg_temp_free_i32(t0);
301 ctx->exception = (excp);
302 }
303
304 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
305 target_ulong nip)
306 {
307 TCGv_i32 t0;
308
309 gen_update_nip(ctx, nip);
310 t0 = tcg_const_i32(excp);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 ctx->exception = (excp);
314 }
315
316 static void gen_debug_exception(DisasContext *ctx)
317 {
318 TCGv_i32 t0;
319
320 /* These are all synchronous exceptions, we set the PC back to
321 * the faulting instruction
322 */
323 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
324 (ctx->exception != POWERPC_EXCP_SYNC)) {
325 gen_update_nip(ctx, ctx->nip - 4);
326 }
327 t0 = tcg_const_i32(EXCP_DEBUG);
328 gen_helper_raise_exception(cpu_env, t0);
329 tcg_temp_free_i32(t0);
330 }
331
332 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
333 {
334 /* Will be converted to program check if needed */
335 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
336 }
337
338 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
339 {
340 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
341 }
342
343 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
344 {
345 /* Will be converted to program check if needed */
346 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
347 }
348
349 /* Stop translation */
350 static inline void gen_stop_exception(DisasContext *ctx)
351 {
352 gen_update_nip(ctx, ctx->nip);
353 ctx->exception = POWERPC_EXCP_STOP;
354 }
355
356 #ifndef CONFIG_USER_ONLY
357 /* No need to update nip here, as execution flow will change */
358 static inline void gen_sync_exception(DisasContext *ctx)
359 {
360 ctx->exception = POWERPC_EXCP_SYNC;
361 }
362 #endif
363
364 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
366
367 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
369
370 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
371 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
372
373 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
374 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
375
376 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
377 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
378
379 typedef struct opcode_t {
380 unsigned char opc1, opc2, opc3, opc4;
381 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
382 unsigned char pad[4];
383 #endif
384 opc_handler_t handler;
385 const char *oname;
386 } opcode_t;
387
388 /* Helpers for priv. check */
389 #define GEN_PRIV \
390 do { \
391 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
392 } while (0)
393
394 #if defined(CONFIG_USER_ONLY)
395 #define CHK_HV GEN_PRIV
396 #define CHK_SV GEN_PRIV
397 #define CHK_HVRM GEN_PRIV
398 #else
399 #define CHK_HV \
400 do { \
401 if (unlikely(ctx->pr || !ctx->hv)) { \
402 GEN_PRIV; \
403 } \
404 } while (0)
405 #define CHK_SV \
406 do { \
407 if (unlikely(ctx->pr)) { \
408 GEN_PRIV; \
409 } \
410 } while (0)
411 #define CHK_HVRM \
412 do { \
413 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
414 GEN_PRIV; \
415 } \
416 } while (0)
417 #endif
418
419 #define CHK_NONE
420
421
422 /*****************************************************************************/
423 /*** Instruction decoding ***/
424 #define EXTRACT_HELPER(name, shift, nb) \
425 static inline uint32_t name(uint32_t opcode) \
426 { \
427 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
428 }
429
430 #define EXTRACT_SHELPER(name, shift, nb) \
431 static inline int32_t name(uint32_t opcode) \
432 { \
433 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
434 }
435
436 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
437 static inline uint32_t name(uint32_t opcode) \
438 { \
439 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
440 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
441 }
442
443 #define EXTRACT_HELPER_DXFORM(name, \
444 d0_bits, shift_op_d0, shift_d0, \
445 d1_bits, shift_op_d1, shift_d1, \
446 d2_bits, shift_op_d2, shift_d2) \
447 static inline int16_t name(uint32_t opcode) \
448 { \
449 return \
450 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
451 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
452 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
453 }
454
455
456 /* Opcode part 1 */
457 EXTRACT_HELPER(opc1, 26, 6);
458 /* Opcode part 2 */
459 EXTRACT_HELPER(opc2, 1, 5);
460 /* Opcode part 3 */
461 EXTRACT_HELPER(opc3, 6, 5);
462 /* Opcode part 4 */
463 EXTRACT_HELPER(opc4, 16, 5);
464 /* Update Cr0 flags */
465 EXTRACT_HELPER(Rc, 0, 1);
466 /* Update Cr6 flags (Altivec) */
467 EXTRACT_HELPER(Rc21, 10, 1);
468 /* Destination */
469 EXTRACT_HELPER(rD, 21, 5);
470 /* Source */
471 EXTRACT_HELPER(rS, 21, 5);
472 /* First operand */
473 EXTRACT_HELPER(rA, 16, 5);
474 /* Second operand */
475 EXTRACT_HELPER(rB, 11, 5);
476 /* Third operand */
477 EXTRACT_HELPER(rC, 6, 5);
478 /*** Get CRn ***/
479 EXTRACT_HELPER(crfD, 23, 3);
480 EXTRACT_HELPER(crfS, 18, 3);
481 EXTRACT_HELPER(crbD, 21, 5);
482 EXTRACT_HELPER(crbA, 16, 5);
483 EXTRACT_HELPER(crbB, 11, 5);
484 /* SPR / TBL */
485 EXTRACT_HELPER(_SPR, 11, 10);
486 static inline uint32_t SPR(uint32_t opcode)
487 {
488 uint32_t sprn = _SPR(opcode);
489
490 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
491 }
492 /*** Get constants ***/
493 /* 16 bits signed immediate value */
494 EXTRACT_SHELPER(SIMM, 0, 16);
495 /* 16 bits unsigned immediate value */
496 EXTRACT_HELPER(UIMM, 0, 16);
497 /* 5 bits signed immediate value */
498 EXTRACT_HELPER(SIMM5, 16, 5);
499 /* 5 bits signed immediate value */
500 EXTRACT_HELPER(UIMM5, 16, 5);
501 /* Bit count */
502 EXTRACT_HELPER(NB, 11, 5);
503 /* Shift count */
504 EXTRACT_HELPER(SH, 11, 5);
505 /* Vector shift count */
506 EXTRACT_HELPER(VSH, 6, 4);
507 /* Mask start */
508 EXTRACT_HELPER(MB, 6, 5);
509 /* Mask end */
510 EXTRACT_HELPER(ME, 1, 5);
511 /* Trap operand */
512 EXTRACT_HELPER(TO, 21, 5);
513
514 EXTRACT_HELPER(CRM, 12, 8);
515
516 #ifndef CONFIG_USER_ONLY
517 EXTRACT_HELPER(SR, 16, 4);
518 #endif
519
520 /* mtfsf/mtfsfi */
521 EXTRACT_HELPER(FPBF, 23, 3);
522 EXTRACT_HELPER(FPIMM, 12, 4);
523 EXTRACT_HELPER(FPL, 25, 1);
524 EXTRACT_HELPER(FPFLM, 17, 8);
525 EXTRACT_HELPER(FPW, 16, 1);
526
527 /* addpcis */
528 EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
529
530 /*** Jump target decoding ***/
531 /* Immediate address */
532 static inline target_ulong LI(uint32_t opcode)
533 {
534 return (opcode >> 0) & 0x03FFFFFC;
535 }
536
537 static inline uint32_t BD(uint32_t opcode)
538 {
539 return (opcode >> 0) & 0xFFFC;
540 }
541
542 EXTRACT_HELPER(BO, 21, 5);
543 EXTRACT_HELPER(BI, 16, 5);
544 /* Absolute/relative address */
545 EXTRACT_HELPER(AA, 1, 1);
546 /* Link */
547 EXTRACT_HELPER(LK, 0, 1);
548
549 /* DFP Z22-form */
550 EXTRACT_HELPER(DCM, 10, 6)
551
552 /* DFP Z23-form */
553 EXTRACT_HELPER(RMC, 9, 2)
554
555 /* Create a mask between <start> and <end> bits */
556 static inline target_ulong MASK(uint32_t start, uint32_t end)
557 {
558 target_ulong ret;
559
560 #if defined(TARGET_PPC64)
561 if (likely(start == 0)) {
562 ret = UINT64_MAX << (63 - end);
563 } else if (likely(end == 63)) {
564 ret = UINT64_MAX >> start;
565 }
566 #else
567 if (likely(start == 0)) {
568 ret = UINT32_MAX << (31 - end);
569 } else if (likely(end == 31)) {
570 ret = UINT32_MAX >> start;
571 }
572 #endif
573 else {
574 ret = (((target_ulong)(-1ULL)) >> (start)) ^
575 (((target_ulong)(-1ULL) >> (end)) >> 1);
576 if (unlikely(start > end))
577 return ~ret;
578 }
579
580 return ret;
581 }
582
583 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
584 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
585 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
586 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
587 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
588 EXTRACT_HELPER(DM, 8, 2);
589 EXTRACT_HELPER(UIM, 16, 2);
590 EXTRACT_HELPER(SHW, 8, 2);
591 EXTRACT_HELPER(SP, 19, 2);
592 /*****************************************************************************/
593 /* PowerPC instructions table */
594
595 #if defined(DO_PPC_STATISTICS)
596 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
597 { \
598 .opc1 = op1, \
599 .opc2 = op2, \
600 .opc3 = op3, \
601 .opc4 = 0xff, \
602 .handler = { \
603 .inval1 = invl, \
604 .type = _typ, \
605 .type2 = _typ2, \
606 .handler = &gen_##name, \
607 .oname = stringify(name), \
608 }, \
609 .oname = stringify(name), \
610 }
611 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
612 { \
613 .opc1 = op1, \
614 .opc2 = op2, \
615 .opc3 = op3, \
616 .opc4 = 0xff, \
617 .handler = { \
618 .inval1 = invl1, \
619 .inval2 = invl2, \
620 .type = _typ, \
621 .type2 = _typ2, \
622 .handler = &gen_##name, \
623 .oname = stringify(name), \
624 }, \
625 .oname = stringify(name), \
626 }
627 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
628 { \
629 .opc1 = op1, \
630 .opc2 = op2, \
631 .opc3 = op3, \
632 .opc4 = 0xff, \
633 .handler = { \
634 .inval1 = invl, \
635 .type = _typ, \
636 .type2 = _typ2, \
637 .handler = &gen_##name, \
638 .oname = onam, \
639 }, \
640 .oname = onam, \
641 }
642 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
643 { \
644 .opc1 = op1, \
645 .opc2 = op2, \
646 .opc3 = op3, \
647 .opc4 = op4, \
648 .handler = { \
649 .inval1 = invl, \
650 .type = _typ, \
651 .type2 = _typ2, \
652 .handler = &gen_##name, \
653 .oname = stringify(name), \
654 }, \
655 .oname = stringify(name), \
656 }
657 #else
658 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
659 { \
660 .opc1 = op1, \
661 .opc2 = op2, \
662 .opc3 = op3, \
663 .opc4 = 0xff, \
664 .handler = { \
665 .inval1 = invl, \
666 .type = _typ, \
667 .type2 = _typ2, \
668 .handler = &gen_##name, \
669 }, \
670 .oname = stringify(name), \
671 }
672 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
673 { \
674 .opc1 = op1, \
675 .opc2 = op2, \
676 .opc3 = op3, \
677 .opc4 = 0xff, \
678 .handler = { \
679 .inval1 = invl1, \
680 .inval2 = invl2, \
681 .type = _typ, \
682 .type2 = _typ2, \
683 .handler = &gen_##name, \
684 }, \
685 .oname = stringify(name), \
686 }
687 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
688 { \
689 .opc1 = op1, \
690 .opc2 = op2, \
691 .opc3 = op3, \
692 .opc4 = 0xff, \
693 .handler = { \
694 .inval1 = invl, \
695 .type = _typ, \
696 .type2 = _typ2, \
697 .handler = &gen_##name, \
698 }, \
699 .oname = onam, \
700 }
701 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
702 { \
703 .opc1 = op1, \
704 .opc2 = op2, \
705 .opc3 = op3, \
706 .opc4 = op4, \
707 .handler = { \
708 .inval1 = invl, \
709 .type = _typ, \
710 .type2 = _typ2, \
711 .handler = &gen_##name, \
712 }, \
713 .oname = stringify(name), \
714 }
715 #endif
716
717 /* SPR load/store helpers */
718 static inline void gen_load_spr(TCGv t, int reg)
719 {
720 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
721 }
722
723 static inline void gen_store_spr(int reg, TCGv t)
724 {
725 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
726 }
727
728 /* Invalid instruction */
729 static void gen_invalid(DisasContext *ctx)
730 {
731 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
732 }
733
734 static opc_handler_t invalid_handler = {
735 .inval1 = 0xFFFFFFFF,
736 .inval2 = 0xFFFFFFFF,
737 .type = PPC_NONE,
738 .type2 = PPC_NONE,
739 .handler = gen_invalid,
740 };
741
742 /*** Integer comparison ***/
743
744 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
745 {
746 TCGv t0 = tcg_temp_new();
747 TCGv_i32 t1 = tcg_temp_new_i32();
748
749 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
750
751 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
752 tcg_gen_trunc_tl_i32(t1, t0);
753 tcg_gen_shli_i32(t1, t1, CRF_LT);
754 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
755
756 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
757 tcg_gen_trunc_tl_i32(t1, t0);
758 tcg_gen_shli_i32(t1, t1, CRF_GT);
759 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
760
761 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
762 tcg_gen_trunc_tl_i32(t1, t0);
763 tcg_gen_shli_i32(t1, t1, CRF_EQ);
764 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
765
766 tcg_temp_free(t0);
767 tcg_temp_free_i32(t1);
768 }
769
770 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
771 {
772 TCGv t0 = tcg_const_tl(arg1);
773 gen_op_cmp(arg0, t0, s, crf);
774 tcg_temp_free(t0);
775 }
776
777 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
778 {
779 TCGv t0, t1;
780 t0 = tcg_temp_new();
781 t1 = tcg_temp_new();
782 if (s) {
783 tcg_gen_ext32s_tl(t0, arg0);
784 tcg_gen_ext32s_tl(t1, arg1);
785 } else {
786 tcg_gen_ext32u_tl(t0, arg0);
787 tcg_gen_ext32u_tl(t1, arg1);
788 }
789 gen_op_cmp(t0, t1, s, crf);
790 tcg_temp_free(t1);
791 tcg_temp_free(t0);
792 }
793
794 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
795 {
796 TCGv t0 = tcg_const_tl(arg1);
797 gen_op_cmp32(arg0, t0, s, crf);
798 tcg_temp_free(t0);
799 }
800
801 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
802 {
803 if (NARROW_MODE(ctx)) {
804 gen_op_cmpi32(reg, 0, 1, 0);
805 } else {
806 gen_op_cmpi(reg, 0, 1, 0);
807 }
808 }
809
810 /* cmp */
811 static void gen_cmp(DisasContext *ctx)
812 {
813 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
814 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
815 1, crfD(ctx->opcode));
816 } else {
817 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
818 1, crfD(ctx->opcode));
819 }
820 }
821
822 /* cmpi */
823 static void gen_cmpi(DisasContext *ctx)
824 {
825 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
826 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
827 1, crfD(ctx->opcode));
828 } else {
829 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
830 1, crfD(ctx->opcode));
831 }
832 }
833
834 /* cmpl */
835 static void gen_cmpl(DisasContext *ctx)
836 {
837 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
838 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
839 0, crfD(ctx->opcode));
840 } else {
841 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
842 0, crfD(ctx->opcode));
843 }
844 }
845
846 /* cmpli */
847 static void gen_cmpli(DisasContext *ctx)
848 {
849 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
850 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
851 0, crfD(ctx->opcode));
852 } else {
853 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
854 0, crfD(ctx->opcode));
855 }
856 }
857
858 /* cmprb - range comparison: isupper, isaplha, islower*/
859 static void gen_cmprb(DisasContext *ctx)
860 {
861 TCGv_i32 src1 = tcg_temp_new_i32();
862 TCGv_i32 src2 = tcg_temp_new_i32();
863 TCGv_i32 src2lo = tcg_temp_new_i32();
864 TCGv_i32 src2hi = tcg_temp_new_i32();
865 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
866
867 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
868 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
869
870 tcg_gen_andi_i32(src1, src1, 0xFF);
871 tcg_gen_ext8u_i32(src2lo, src2);
872 tcg_gen_shri_i32(src2, src2, 8);
873 tcg_gen_ext8u_i32(src2hi, src2);
874
875 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
876 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
877 tcg_gen_and_i32(crf, src2lo, src2hi);
878
879 if (ctx->opcode & 0x00200000) {
880 tcg_gen_shri_i32(src2, src2, 8);
881 tcg_gen_ext8u_i32(src2lo, src2);
882 tcg_gen_shri_i32(src2, src2, 8);
883 tcg_gen_ext8u_i32(src2hi, src2);
884 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
885 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
886 tcg_gen_and_i32(src2lo, src2lo, src2hi);
887 tcg_gen_or_i32(crf, crf, src2lo);
888 }
889 tcg_gen_shli_i32(crf, crf, CRF_GT);
890 tcg_temp_free_i32(src1);
891 tcg_temp_free_i32(src2);
892 tcg_temp_free_i32(src2lo);
893 tcg_temp_free_i32(src2hi);
894 }
895
896 #if defined(TARGET_PPC64)
897 /* cmpeqb */
898 static void gen_cmpeqb(DisasContext *ctx)
899 {
900 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
901 cpu_gpr[rB(ctx->opcode)]);
902 }
903 #endif
904
905 /* isel (PowerPC 2.03 specification) */
906 static void gen_isel(DisasContext *ctx)
907 {
908 uint32_t bi = rC(ctx->opcode);
909 uint32_t mask = 0x08 >> (bi & 0x03);
910 TCGv t0 = tcg_temp_new();
911 TCGv zr;
912
913 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
914 tcg_gen_andi_tl(t0, t0, mask);
915
916 zr = tcg_const_tl(0);
917 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
918 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
919 cpu_gpr[rB(ctx->opcode)]);
920 tcg_temp_free(zr);
921 tcg_temp_free(t0);
922 }
923
924 /* cmpb: PowerPC 2.05 specification */
925 static void gen_cmpb(DisasContext *ctx)
926 {
927 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
928 cpu_gpr[rB(ctx->opcode)]);
929 }
930
931 /*** Integer arithmetic ***/
932
933 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
934 TCGv arg1, TCGv arg2, int sub)
935 {
936 TCGv t0 = tcg_temp_new();
937
938 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
939 tcg_gen_xor_tl(t0, arg1, arg2);
940 if (sub) {
941 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
942 } else {
943 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
944 }
945 tcg_temp_free(t0);
946 if (NARROW_MODE(ctx)) {
947 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
948 }
949 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
950 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
951 }
952
953 /* Common add function */
954 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
955 TCGv arg2, bool add_ca, bool compute_ca,
956 bool compute_ov, bool compute_rc0)
957 {
958 TCGv t0 = ret;
959
960 if (compute_ca || compute_ov) {
961 t0 = tcg_temp_new();
962 }
963
964 if (compute_ca) {
965 if (NARROW_MODE(ctx)) {
966 /* Caution: a non-obvious corner case of the spec is that we
967 must produce the *entire* 64-bit addition, but produce the
968 carry into bit 32. */
969 TCGv t1 = tcg_temp_new();
970 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
971 tcg_gen_add_tl(t0, arg1, arg2);
972 if (add_ca) {
973 tcg_gen_add_tl(t0, t0, cpu_ca);
974 }
975 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
976 tcg_temp_free(t1);
977 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
978 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
979 } else {
980 TCGv zero = tcg_const_tl(0);
981 if (add_ca) {
982 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
983 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
984 } else {
985 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
986 }
987 tcg_temp_free(zero);
988 }
989 } else {
990 tcg_gen_add_tl(t0, arg1, arg2);
991 if (add_ca) {
992 tcg_gen_add_tl(t0, t0, cpu_ca);
993 }
994 }
995
996 if (compute_ov) {
997 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
998 }
999 if (unlikely(compute_rc0)) {
1000 gen_set_Rc0(ctx, t0);
1001 }
1002
1003 if (!TCGV_EQUAL(t0, ret)) {
1004 tcg_gen_mov_tl(ret, t0);
1005 tcg_temp_free(t0);
1006 }
1007 }
1008 /* Add functions with two operands */
1009 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
1010 static void glue(gen_, name)(DisasContext *ctx) \
1011 { \
1012 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1013 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1014 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1015 }
1016 /* Add functions with one operand and one immediate */
1017 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
1018 add_ca, compute_ca, compute_ov) \
1019 static void glue(gen_, name)(DisasContext *ctx) \
1020 { \
1021 TCGv t0 = tcg_const_tl(const_val); \
1022 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1023 cpu_gpr[rA(ctx->opcode)], t0, \
1024 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1025 tcg_temp_free(t0); \
1026 }
1027
1028 /* add add. addo addo. */
1029 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1030 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1031 /* addc addc. addco addco. */
1032 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1033 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1034 /* adde adde. addeo addeo. */
1035 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1036 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1037 /* addme addme. addmeo addmeo. */
1038 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1039 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1040 /* addze addze. addzeo addzeo.*/
1041 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1042 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1043 /* addi */
1044 static void gen_addi(DisasContext *ctx)
1045 {
1046 target_long simm = SIMM(ctx->opcode);
1047
1048 if (rA(ctx->opcode) == 0) {
1049 /* li case */
1050 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1051 } else {
1052 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1053 cpu_gpr[rA(ctx->opcode)], simm);
1054 }
1055 }
1056 /* addic addic.*/
1057 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1058 {
1059 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1060 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1061 c, 0, 1, 0, compute_rc0);
1062 tcg_temp_free(c);
1063 }
1064
1065 static void gen_addic(DisasContext *ctx)
1066 {
1067 gen_op_addic(ctx, 0);
1068 }
1069
1070 static void gen_addic_(DisasContext *ctx)
1071 {
1072 gen_op_addic(ctx, 1);
1073 }
1074
1075 /* addis */
1076 static void gen_addis(DisasContext *ctx)
1077 {
1078 target_long simm = SIMM(ctx->opcode);
1079
1080 if (rA(ctx->opcode) == 0) {
1081 /* lis case */
1082 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1083 } else {
1084 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1085 cpu_gpr[rA(ctx->opcode)], simm << 16);
1086 }
1087 }
1088
1089 /* addpcis */
1090 static void gen_addpcis(DisasContext *ctx)
1091 {
1092 target_long d = DX(ctx->opcode);
1093
1094 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
1095 }
1096
1097 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1098 TCGv arg2, int sign, int compute_ov)
1099 {
1100 TCGLabel *l1 = gen_new_label();
1101 TCGLabel *l2 = gen_new_label();
1102 TCGv_i32 t0 = tcg_temp_local_new_i32();
1103 TCGv_i32 t1 = tcg_temp_local_new_i32();
1104
1105 tcg_gen_trunc_tl_i32(t0, arg1);
1106 tcg_gen_trunc_tl_i32(t1, arg2);
1107 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1108 if (sign) {
1109 TCGLabel *l3 = gen_new_label();
1110 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1111 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1112 gen_set_label(l3);
1113 tcg_gen_div_i32(t0, t0, t1);
1114 } else {
1115 tcg_gen_divu_i32(t0, t0, t1);
1116 }
1117 if (compute_ov) {
1118 tcg_gen_movi_tl(cpu_ov, 0);
1119 }
1120 tcg_gen_br(l2);
1121 gen_set_label(l1);
1122 if (sign) {
1123 tcg_gen_sari_i32(t0, t0, 31);
1124 } else {
1125 tcg_gen_movi_i32(t0, 0);
1126 }
1127 if (compute_ov) {
1128 tcg_gen_movi_tl(cpu_ov, 1);
1129 tcg_gen_movi_tl(cpu_so, 1);
1130 }
1131 gen_set_label(l2);
1132 tcg_gen_extu_i32_tl(ret, t0);
1133 tcg_temp_free_i32(t0);
1134 tcg_temp_free_i32(t1);
1135 if (unlikely(Rc(ctx->opcode) != 0))
1136 gen_set_Rc0(ctx, ret);
1137 }
1138 /* Div functions */
1139 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1140 static void glue(gen_, name)(DisasContext *ctx) \
1141 { \
1142 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1143 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1144 sign, compute_ov); \
1145 }
1146 /* divwu divwu. divwuo divwuo. */
1147 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1148 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1149 /* divw divw. divwo divwo. */
1150 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1151 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1152
1153 /* div[wd]eu[o][.] */
1154 #define GEN_DIVE(name, hlpr, compute_ov) \
1155 static void gen_##name(DisasContext *ctx) \
1156 { \
1157 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1158 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1159 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1160 tcg_temp_free_i32(t0); \
1161 if (unlikely(Rc(ctx->opcode) != 0)) { \
1162 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1163 } \
1164 }
1165
1166 GEN_DIVE(divweu, divweu, 0);
1167 GEN_DIVE(divweuo, divweu, 1);
1168 GEN_DIVE(divwe, divwe, 0);
1169 GEN_DIVE(divweo, divwe, 1);
1170
1171 #if defined(TARGET_PPC64)
1172 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1173 TCGv arg2, int sign, int compute_ov)
1174 {
1175 TCGLabel *l1 = gen_new_label();
1176 TCGLabel *l2 = gen_new_label();
1177
1178 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1179 if (sign) {
1180 TCGLabel *l3 = gen_new_label();
1181 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1182 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1183 gen_set_label(l3);
1184 tcg_gen_div_i64(ret, arg1, arg2);
1185 } else {
1186 tcg_gen_divu_i64(ret, arg1, arg2);
1187 }
1188 if (compute_ov) {
1189 tcg_gen_movi_tl(cpu_ov, 0);
1190 }
1191 tcg_gen_br(l2);
1192 gen_set_label(l1);
1193 if (sign) {
1194 tcg_gen_sari_i64(ret, arg1, 63);
1195 } else {
1196 tcg_gen_movi_i64(ret, 0);
1197 }
1198 if (compute_ov) {
1199 tcg_gen_movi_tl(cpu_ov, 1);
1200 tcg_gen_movi_tl(cpu_so, 1);
1201 }
1202 gen_set_label(l2);
1203 if (unlikely(Rc(ctx->opcode) != 0))
1204 gen_set_Rc0(ctx, ret);
1205 }
1206 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1207 static void glue(gen_, name)(DisasContext *ctx) \
1208 { \
1209 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1210 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1211 sign, compute_ov); \
1212 }
1213 /* divwu divwu. divwuo divwuo. */
1214 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1215 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1216 /* divw divw. divwo divwo. */
1217 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1218 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1219
1220 GEN_DIVE(divdeu, divdeu, 0);
1221 GEN_DIVE(divdeuo, divdeu, 1);
1222 GEN_DIVE(divde, divde, 0);
1223 GEN_DIVE(divdeo, divde, 1);
1224 #endif
1225
1226 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1227 TCGv arg2, int sign)
1228 {
1229 TCGv_i32 t0 = tcg_temp_new_i32();
1230 TCGv_i32 t1 = tcg_temp_new_i32();
1231
1232 tcg_gen_trunc_tl_i32(t0, arg1);
1233 tcg_gen_trunc_tl_i32(t1, arg2);
1234 if (sign) {
1235 TCGv_i32 t2 = tcg_temp_new_i32();
1236 TCGv_i32 t3 = tcg_temp_new_i32();
1237 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1238 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1239 tcg_gen_and_i32(t2, t2, t3);
1240 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1241 tcg_gen_or_i32(t2, t2, t3);
1242 tcg_gen_movi_i32(t3, 0);
1243 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1244 tcg_gen_rem_i32(t3, t0, t1);
1245 tcg_gen_ext_i32_tl(ret, t3);
1246 tcg_temp_free_i32(t2);
1247 tcg_temp_free_i32(t3);
1248 } else {
1249 TCGv_i32 t2 = tcg_const_i32(1);
1250 TCGv_i32 t3 = tcg_const_i32(0);
1251 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1252 tcg_gen_remu_i32(t3, t0, t1);
1253 tcg_gen_extu_i32_tl(ret, t3);
1254 tcg_temp_free_i32(t2);
1255 tcg_temp_free_i32(t3);
1256 }
1257 tcg_temp_free_i32(t0);
1258 tcg_temp_free_i32(t1);
1259 }
1260
1261 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1262 static void glue(gen_, name)(DisasContext *ctx) \
1263 { \
1264 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1265 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1266 sign); \
1267 }
1268
1269 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1270 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1271
1272 #if defined(TARGET_PPC64)
1273 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1274 TCGv arg2, int sign)
1275 {
1276 TCGv_i64 t0 = tcg_temp_new_i64();
1277 TCGv_i64 t1 = tcg_temp_new_i64();
1278
1279 tcg_gen_mov_i64(t0, arg1);
1280 tcg_gen_mov_i64(t1, arg2);
1281 if (sign) {
1282 TCGv_i64 t2 = tcg_temp_new_i64();
1283 TCGv_i64 t3 = tcg_temp_new_i64();
1284 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1285 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1286 tcg_gen_and_i64(t2, t2, t3);
1287 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1288 tcg_gen_or_i64(t2, t2, t3);
1289 tcg_gen_movi_i64(t3, 0);
1290 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1291 tcg_gen_rem_i64(ret, t0, t1);
1292 tcg_temp_free_i64(t2);
1293 tcg_temp_free_i64(t3);
1294 } else {
1295 TCGv_i64 t2 = tcg_const_i64(1);
1296 TCGv_i64 t3 = tcg_const_i64(0);
1297 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1298 tcg_gen_remu_i64(ret, t0, t1);
1299 tcg_temp_free_i64(t2);
1300 tcg_temp_free_i64(t3);
1301 }
1302 tcg_temp_free_i64(t0);
1303 tcg_temp_free_i64(t1);
1304 }
1305
1306 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1307 static void glue(gen_, name)(DisasContext *ctx) \
1308 { \
1309 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1310 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1311 sign); \
1312 }
1313
1314 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1315 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1316 #endif
1317
1318 /* mulhw mulhw. */
1319 static void gen_mulhw(DisasContext *ctx)
1320 {
1321 TCGv_i32 t0 = tcg_temp_new_i32();
1322 TCGv_i32 t1 = tcg_temp_new_i32();
1323
1324 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1325 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1326 tcg_gen_muls2_i32(t0, t1, t0, t1);
1327 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1328 tcg_temp_free_i32(t0);
1329 tcg_temp_free_i32(t1);
1330 if (unlikely(Rc(ctx->opcode) != 0))
1331 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1332 }
1333
1334 /* mulhwu mulhwu. */
1335 static void gen_mulhwu(DisasContext *ctx)
1336 {
1337 TCGv_i32 t0 = tcg_temp_new_i32();
1338 TCGv_i32 t1 = tcg_temp_new_i32();
1339
1340 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1341 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1342 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1343 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1344 tcg_temp_free_i32(t0);
1345 tcg_temp_free_i32(t1);
1346 if (unlikely(Rc(ctx->opcode) != 0))
1347 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1348 }
1349
1350 /* mullw mullw. */
1351 static void gen_mullw(DisasContext *ctx)
1352 {
1353 #if defined(TARGET_PPC64)
1354 TCGv_i64 t0, t1;
1355 t0 = tcg_temp_new_i64();
1356 t1 = tcg_temp_new_i64();
1357 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1358 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1359 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1360 tcg_temp_free(t0);
1361 tcg_temp_free(t1);
1362 #else
1363 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1364 cpu_gpr[rB(ctx->opcode)]);
1365 #endif
1366 if (unlikely(Rc(ctx->opcode) != 0))
1367 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1368 }
1369
1370 /* mullwo mullwo. */
1371 static void gen_mullwo(DisasContext *ctx)
1372 {
1373 TCGv_i32 t0 = tcg_temp_new_i32();
1374 TCGv_i32 t1 = tcg_temp_new_i32();
1375
1376 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1377 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1378 tcg_gen_muls2_i32(t0, t1, t0, t1);
1379 #if defined(TARGET_PPC64)
1380 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1381 #else
1382 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1383 #endif
1384
1385 tcg_gen_sari_i32(t0, t0, 31);
1386 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1387 tcg_gen_extu_i32_tl(cpu_ov, t0);
1388 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1389
1390 tcg_temp_free_i32(t0);
1391 tcg_temp_free_i32(t1);
1392 if (unlikely(Rc(ctx->opcode) != 0))
1393 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1394 }
1395
1396 /* mulli */
1397 static void gen_mulli(DisasContext *ctx)
1398 {
1399 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1400 SIMM(ctx->opcode));
1401 }
1402
1403 #if defined(TARGET_PPC64)
1404 /* mulhd mulhd. */
1405 static void gen_mulhd(DisasContext *ctx)
1406 {
1407 TCGv lo = tcg_temp_new();
1408 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1409 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1410 tcg_temp_free(lo);
1411 if (unlikely(Rc(ctx->opcode) != 0)) {
1412 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1413 }
1414 }
1415
1416 /* mulhdu mulhdu. */
1417 static void gen_mulhdu(DisasContext *ctx)
1418 {
1419 TCGv lo = tcg_temp_new();
1420 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1421 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1422 tcg_temp_free(lo);
1423 if (unlikely(Rc(ctx->opcode) != 0)) {
1424 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1425 }
1426 }
1427
1428 /* mulld mulld. */
1429 static void gen_mulld(DisasContext *ctx)
1430 {
1431 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1432 cpu_gpr[rB(ctx->opcode)]);
1433 if (unlikely(Rc(ctx->opcode) != 0))
1434 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1435 }
1436
1437 /* mulldo mulldo. */
1438 static void gen_mulldo(DisasContext *ctx)
1439 {
1440 TCGv_i64 t0 = tcg_temp_new_i64();
1441 TCGv_i64 t1 = tcg_temp_new_i64();
1442
1443 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1444 cpu_gpr[rB(ctx->opcode)]);
1445 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1446
1447 tcg_gen_sari_i64(t0, t0, 63);
1448 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1449 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1450
1451 tcg_temp_free_i64(t0);
1452 tcg_temp_free_i64(t1);
1453
1454 if (unlikely(Rc(ctx->opcode) != 0)) {
1455 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1456 }
1457 }
1458 #endif
1459
1460 /* Common subf function */
1461 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1462 TCGv arg2, bool add_ca, bool compute_ca,
1463 bool compute_ov, bool compute_rc0)
1464 {
1465 TCGv t0 = ret;
1466
1467 if (compute_ca || compute_ov) {
1468 t0 = tcg_temp_new();
1469 }
1470
1471 if (compute_ca) {
1472 /* dest = ~arg1 + arg2 [+ ca]. */
1473 if (NARROW_MODE(ctx)) {
1474 /* Caution: a non-obvious corner case of the spec is that we
1475 must produce the *entire* 64-bit addition, but produce the
1476 carry into bit 32. */
1477 TCGv inv1 = tcg_temp_new();
1478 TCGv t1 = tcg_temp_new();
1479 tcg_gen_not_tl(inv1, arg1);
1480 if (add_ca) {
1481 tcg_gen_add_tl(t0, arg2, cpu_ca);
1482 } else {
1483 tcg_gen_addi_tl(t0, arg2, 1);
1484 }
1485 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1486 tcg_gen_add_tl(t0, t0, inv1);
1487 tcg_temp_free(inv1);
1488 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1489 tcg_temp_free(t1);
1490 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1491 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1492 } else if (add_ca) {
1493 TCGv zero, inv1 = tcg_temp_new();
1494 tcg_gen_not_tl(inv1, arg1);
1495 zero = tcg_const_tl(0);
1496 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1497 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1498 tcg_temp_free(zero);
1499 tcg_temp_free(inv1);
1500 } else {
1501 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1502 tcg_gen_sub_tl(t0, arg2, arg1);
1503 }
1504 } else if (add_ca) {
1505 /* Since we're ignoring carry-out, we can simplify the
1506 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1507 tcg_gen_sub_tl(t0, arg2, arg1);
1508 tcg_gen_add_tl(t0, t0, cpu_ca);
1509 tcg_gen_subi_tl(t0, t0, 1);
1510 } else {
1511 tcg_gen_sub_tl(t0, arg2, arg1);
1512 }
1513
1514 if (compute_ov) {
1515 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1516 }
1517 if (unlikely(compute_rc0)) {
1518 gen_set_Rc0(ctx, t0);
1519 }
1520
1521 if (!TCGV_EQUAL(t0, ret)) {
1522 tcg_gen_mov_tl(ret, t0);
1523 tcg_temp_free(t0);
1524 }
1525 }
1526 /* Sub functions with Two operands functions */
1527 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1528 static void glue(gen_, name)(DisasContext *ctx) \
1529 { \
1530 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1531 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1532 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1533 }
1534 /* Sub functions with one operand and one immediate */
1535 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1536 add_ca, compute_ca, compute_ov) \
1537 static void glue(gen_, name)(DisasContext *ctx) \
1538 { \
1539 TCGv t0 = tcg_const_tl(const_val); \
1540 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1541 cpu_gpr[rA(ctx->opcode)], t0, \
1542 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1543 tcg_temp_free(t0); \
1544 }
1545 /* subf subf. subfo subfo. */
1546 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1547 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1548 /* subfc subfc. subfco subfco. */
1549 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1550 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1551 /* subfe subfe. subfeo subfo. */
1552 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1553 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1554 /* subfme subfme. subfmeo subfmeo. */
1555 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1556 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1557 /* subfze subfze. subfzeo subfzeo.*/
1558 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1559 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1560
1561 /* subfic */
1562 static void gen_subfic(DisasContext *ctx)
1563 {
1564 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1565 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1566 c, 0, 1, 0, 0);
1567 tcg_temp_free(c);
1568 }
1569
1570 /* neg neg. nego nego. */
1571 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1572 {
1573 TCGv zero = tcg_const_tl(0);
1574 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1575 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1576 tcg_temp_free(zero);
1577 }
1578
1579 static void gen_neg(DisasContext *ctx)
1580 {
1581 gen_op_arith_neg(ctx, 0);
1582 }
1583
1584 static void gen_nego(DisasContext *ctx)
1585 {
1586 gen_op_arith_neg(ctx, 1);
1587 }
1588
1589 /*** Integer logical ***/
1590 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1591 static void glue(gen_, name)(DisasContext *ctx) \
1592 { \
1593 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1594 cpu_gpr[rB(ctx->opcode)]); \
1595 if (unlikely(Rc(ctx->opcode) != 0)) \
1596 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1597 }
1598
1599 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1600 static void glue(gen_, name)(DisasContext *ctx) \
1601 { \
1602 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1603 if (unlikely(Rc(ctx->opcode) != 0)) \
1604 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1605 }
1606
1607 /* and & and. */
1608 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1609 /* andc & andc. */
1610 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1611
1612 /* andi. */
1613 static void gen_andi_(DisasContext *ctx)
1614 {
1615 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1616 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1617 }
1618
1619 /* andis. */
1620 static void gen_andis_(DisasContext *ctx)
1621 {
1622 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1623 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1624 }
1625
1626 /* cntlzw */
1627 static void gen_cntlzw(DisasContext *ctx)
1628 {
1629 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1630 if (unlikely(Rc(ctx->opcode) != 0))
1631 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1632 }
1633
1634 /* cnttzw */
1635 static void gen_cnttzw(DisasContext *ctx)
1636 {
1637 gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1638 if (unlikely(Rc(ctx->opcode) != 0)) {
1639 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1640 }
1641 }
1642
1643 /* eqv & eqv. */
1644 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1645 /* extsb & extsb. */
1646 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1647 /* extsh & extsh. */
1648 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1649 /* nand & nand. */
1650 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1651 /* nor & nor. */
1652 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1653
1654 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1655 static void gen_pause(DisasContext *ctx)
1656 {
1657 TCGv_i32 t0 = tcg_const_i32(0);
1658 tcg_gen_st_i32(t0, cpu_env,
1659 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1660 tcg_temp_free_i32(t0);
1661
1662 /* Stop translation, this gives other CPUs a chance to run */
1663 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1664 }
1665 #endif /* defined(TARGET_PPC64) */
1666
1667 /* or & or. */
1668 static void gen_or(DisasContext *ctx)
1669 {
1670 int rs, ra, rb;
1671
1672 rs = rS(ctx->opcode);
1673 ra = rA(ctx->opcode);
1674 rb = rB(ctx->opcode);
1675 /* Optimisation for mr. ri case */
1676 if (rs != ra || rs != rb) {
1677 if (rs != rb)
1678 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1679 else
1680 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1681 if (unlikely(Rc(ctx->opcode) != 0))
1682 gen_set_Rc0(ctx, cpu_gpr[ra]);
1683 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1684 gen_set_Rc0(ctx, cpu_gpr[rs]);
1685 #if defined(TARGET_PPC64)
1686 } else if (rs != 0) { /* 0 is nop */
1687 int prio = 0;
1688
1689 switch (rs) {
1690 case 1:
1691 /* Set process priority to low */
1692 prio = 2;
1693 break;
1694 case 6:
1695 /* Set process priority to medium-low */
1696 prio = 3;
1697 break;
1698 case 2:
1699 /* Set process priority to normal */
1700 prio = 4;
1701 break;
1702 #if !defined(CONFIG_USER_ONLY)
1703 case 31:
1704 if (!ctx->pr) {
1705 /* Set process priority to very low */
1706 prio = 1;
1707 }
1708 break;
1709 case 5:
1710 if (!ctx->pr) {
1711 /* Set process priority to medium-hight */
1712 prio = 5;
1713 }
1714 break;
1715 case 3:
1716 if (!ctx->pr) {
1717 /* Set process priority to high */
1718 prio = 6;
1719 }
1720 break;
1721 case 7:
1722 if (ctx->hv && !ctx->pr) {
1723 /* Set process priority to very high */
1724 prio = 7;
1725 }
1726 break;
1727 #endif
1728 default:
1729 break;
1730 }
1731 if (prio) {
1732 TCGv t0 = tcg_temp_new();
1733 gen_load_spr(t0, SPR_PPR);
1734 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1735 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1736 gen_store_spr(SPR_PPR, t0);
1737 tcg_temp_free(t0);
1738 }
1739 #if !defined(CONFIG_USER_ONLY)
1740 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1741 * CPU and the kernel hangs. This applies to all encodings other
1742 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1743 * and all currently undefined.
1744 */
1745 gen_pause(ctx);
1746 #endif
1747 #endif
1748 }
1749 }
1750 /* orc & orc. */
1751 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1752
1753 /* xor & xor. */
1754 static void gen_xor(DisasContext *ctx)
1755 {
1756 /* Optimisation for "set to zero" case */
1757 if (rS(ctx->opcode) != rB(ctx->opcode))
1758 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1759 else
1760 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1761 if (unlikely(Rc(ctx->opcode) != 0))
1762 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1763 }
1764
1765 /* ori */
1766 static void gen_ori(DisasContext *ctx)
1767 {
1768 target_ulong uimm = UIMM(ctx->opcode);
1769
1770 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1771 return;
1772 }
1773 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1774 }
1775
1776 /* oris */
1777 static void gen_oris(DisasContext *ctx)
1778 {
1779 target_ulong uimm = UIMM(ctx->opcode);
1780
1781 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1782 /* NOP */
1783 return;
1784 }
1785 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1786 }
1787
1788 /* xori */
1789 static void gen_xori(DisasContext *ctx)
1790 {
1791 target_ulong uimm = UIMM(ctx->opcode);
1792
1793 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1794 /* NOP */
1795 return;
1796 }
1797 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1798 }
1799
1800 /* xoris */
1801 static void gen_xoris(DisasContext *ctx)
1802 {
1803 target_ulong uimm = UIMM(ctx->opcode);
1804
1805 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1806 /* NOP */
1807 return;
1808 }
1809 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1810 }
1811
1812 /* popcntb : PowerPC 2.03 specification */
1813 static void gen_popcntb(DisasContext *ctx)
1814 {
1815 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1816 }
1817
1818 static void gen_popcntw(DisasContext *ctx)
1819 {
1820 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1821 }
1822
1823 #if defined(TARGET_PPC64)
1824 /* popcntd: PowerPC 2.06 specification */
1825 static void gen_popcntd(DisasContext *ctx)
1826 {
1827 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1828 }
1829 #endif
1830
1831 /* prtyw: PowerPC 2.05 specification */
1832 static void gen_prtyw(DisasContext *ctx)
1833 {
1834 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1835 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1836 TCGv t0 = tcg_temp_new();
1837 tcg_gen_shri_tl(t0, rs, 16);
1838 tcg_gen_xor_tl(ra, rs, t0);
1839 tcg_gen_shri_tl(t0, ra, 8);
1840 tcg_gen_xor_tl(ra, ra, t0);
1841 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1842 tcg_temp_free(t0);
1843 }
1844
1845 #if defined(TARGET_PPC64)
1846 /* prtyd: PowerPC 2.05 specification */
1847 static void gen_prtyd(DisasContext *ctx)
1848 {
1849 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1850 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1851 TCGv t0 = tcg_temp_new();
1852 tcg_gen_shri_tl(t0, rs, 32);
1853 tcg_gen_xor_tl(ra, rs, t0);
1854 tcg_gen_shri_tl(t0, ra, 16);
1855 tcg_gen_xor_tl(ra, ra, t0);
1856 tcg_gen_shri_tl(t0, ra, 8);
1857 tcg_gen_xor_tl(ra, ra, t0);
1858 tcg_gen_andi_tl(ra, ra, 1);
1859 tcg_temp_free(t0);
1860 }
1861 #endif
1862
1863 #if defined(TARGET_PPC64)
1864 /* bpermd */
1865 static void gen_bpermd(DisasContext *ctx)
1866 {
1867 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1868 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1869 }
1870 #endif
1871
1872 #if defined(TARGET_PPC64)
1873 /* extsw & extsw. */
1874 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1875
1876 /* cntlzd */
1877 static void gen_cntlzd(DisasContext *ctx)
1878 {
1879 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1880 if (unlikely(Rc(ctx->opcode) != 0))
1881 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1882 }
1883
1884 /* cnttzd */
1885 static void gen_cnttzd(DisasContext *ctx)
1886 {
1887 gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1888 if (unlikely(Rc(ctx->opcode) != 0)) {
1889 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1890 }
1891 }
1892 #endif
1893
1894 /*** Integer rotate ***/
1895
1896 /* rlwimi & rlwimi. */
1897 static void gen_rlwimi(DisasContext *ctx)
1898 {
1899 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1900 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1901 uint32_t sh = SH(ctx->opcode);
1902 uint32_t mb = MB(ctx->opcode);
1903 uint32_t me = ME(ctx->opcode);
1904
1905 if (sh == (31-me) && mb <= me) {
1906 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1907 } else {
1908 target_ulong mask;
1909 TCGv t1;
1910
1911 #if defined(TARGET_PPC64)
1912 mb += 32;
1913 me += 32;
1914 #endif
1915 mask = MASK(mb, me);
1916
1917 t1 = tcg_temp_new();
1918 if (mask <= 0xffffffffu) {
1919 TCGv_i32 t0 = tcg_temp_new_i32();
1920 tcg_gen_trunc_tl_i32(t0, t_rs);
1921 tcg_gen_rotli_i32(t0, t0, sh);
1922 tcg_gen_extu_i32_tl(t1, t0);
1923 tcg_temp_free_i32(t0);
1924 } else {
1925 #if defined(TARGET_PPC64)
1926 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1927 tcg_gen_rotli_i64(t1, t1, sh);
1928 #else
1929 g_assert_not_reached();
1930 #endif
1931 }
1932
1933 tcg_gen_andi_tl(t1, t1, mask);
1934 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1935 tcg_gen_or_tl(t_ra, t_ra, t1);
1936 tcg_temp_free(t1);
1937 }
1938 if (unlikely(Rc(ctx->opcode) != 0)) {
1939 gen_set_Rc0(ctx, t_ra);
1940 }
1941 }
1942
1943 /* rlwinm & rlwinm. */
1944 static void gen_rlwinm(DisasContext *ctx)
1945 {
1946 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1947 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1948 uint32_t sh = SH(ctx->opcode);
1949 uint32_t mb = MB(ctx->opcode);
1950 uint32_t me = ME(ctx->opcode);
1951
1952 if (mb == 0 && me == (31 - sh)) {
1953 tcg_gen_shli_tl(t_ra, t_rs, sh);
1954 tcg_gen_ext32u_tl(t_ra, t_ra);
1955 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1956 tcg_gen_ext32u_tl(t_ra, t_rs);
1957 tcg_gen_shri_tl(t_ra, t_ra, mb);
1958 } else {
1959 target_ulong mask;
1960 #if defined(TARGET_PPC64)
1961 mb += 32;
1962 me += 32;
1963 #endif
1964 mask = MASK(mb, me);
1965
1966 if (mask <= 0xffffffffu) {
1967 TCGv_i32 t0 = tcg_temp_new_i32();
1968 tcg_gen_trunc_tl_i32(t0, t_rs);
1969 tcg_gen_rotli_i32(t0, t0, sh);
1970 tcg_gen_andi_i32(t0, t0, mask);
1971 tcg_gen_extu_i32_tl(t_ra, t0);
1972 tcg_temp_free_i32(t0);
1973 } else {
1974 #if defined(TARGET_PPC64)
1975 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1976 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1977 tcg_gen_andi_i64(t_ra, t_ra, mask);
1978 #else
1979 g_assert_not_reached();
1980 #endif
1981 }
1982 }
1983 if (unlikely(Rc(ctx->opcode) != 0)) {
1984 gen_set_Rc0(ctx, t_ra);
1985 }
1986 }
1987
1988 /* rlwnm & rlwnm. */
1989 static void gen_rlwnm(DisasContext *ctx)
1990 {
1991 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1992 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1993 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1994 uint32_t mb = MB(ctx->opcode);
1995 uint32_t me = ME(ctx->opcode);
1996 target_ulong mask;
1997
1998 #if defined(TARGET_PPC64)
1999 mb += 32;
2000 me += 32;
2001 #endif
2002 mask = MASK(mb, me);
2003
2004 if (mask <= 0xffffffffu) {
2005 TCGv_i32 t0 = tcg_temp_new_i32();
2006 TCGv_i32 t1 = tcg_temp_new_i32();
2007 tcg_gen_trunc_tl_i32(t0, t_rb);
2008 tcg_gen_trunc_tl_i32(t1, t_rs);
2009 tcg_gen_andi_i32(t0, t0, 0x1f);
2010 tcg_gen_rotl_i32(t1, t1, t0);
2011 tcg_gen_extu_i32_tl(t_ra, t1);
2012 tcg_temp_free_i32(t0);
2013 tcg_temp_free_i32(t1);
2014 } else {
2015 #if defined(TARGET_PPC64)
2016 TCGv_i64 t0 = tcg_temp_new_i64();
2017 tcg_gen_andi_i64(t0, t_rb, 0x1f);
2018 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2019 tcg_gen_rotl_i64(t_ra, t_ra, t0);
2020 tcg_temp_free_i64(t0);
2021 #else
2022 g_assert_not_reached();
2023 #endif
2024 }
2025
2026 tcg_gen_andi_tl(t_ra, t_ra, mask);
2027
2028 if (unlikely(Rc(ctx->opcode) != 0)) {
2029 gen_set_Rc0(ctx, t_ra);
2030 }
2031 }
2032
2033 #if defined(TARGET_PPC64)
2034 #define GEN_PPC64_R2(name, opc1, opc2) \
2035 static void glue(gen_, name##0)(DisasContext *ctx) \
2036 { \
2037 gen_##name(ctx, 0); \
2038 } \
2039 \
2040 static void glue(gen_, name##1)(DisasContext *ctx) \
2041 { \
2042 gen_##name(ctx, 1); \
2043 }
2044 #define GEN_PPC64_R4(name, opc1, opc2) \
2045 static void glue(gen_, name##0)(DisasContext *ctx) \
2046 { \
2047 gen_##name(ctx, 0, 0); \
2048 } \
2049 \
2050 static void glue(gen_, name##1)(DisasContext *ctx) \
2051 { \
2052 gen_##name(ctx, 0, 1); \
2053 } \
2054 \
2055 static void glue(gen_, name##2)(DisasContext *ctx) \
2056 { \
2057 gen_##name(ctx, 1, 0); \
2058 } \
2059 \
2060 static void glue(gen_, name##3)(DisasContext *ctx) \
2061 { \
2062 gen_##name(ctx, 1, 1); \
2063 }
2064
2065 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2066 {
2067 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2068 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2069
2070 if (sh != 0 && mb == 0 && me == (63 - sh)) {
2071 tcg_gen_shli_tl(t_ra, t_rs, sh);
2072 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
2073 tcg_gen_shri_tl(t_ra, t_rs, mb);
2074 } else {
2075 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2076 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2077 }
2078 if (unlikely(Rc(ctx->opcode) != 0)) {
2079 gen_set_Rc0(ctx, t_ra);
2080 }
2081 }
2082
2083 /* rldicl - rldicl. */
2084 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2085 {
2086 uint32_t sh, mb;
2087
2088 sh = SH(ctx->opcode) | (shn << 5);
2089 mb = MB(ctx->opcode) | (mbn << 5);
2090 gen_rldinm(ctx, mb, 63, sh);
2091 }
2092 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2093
2094 /* rldicr - rldicr. */
2095 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2096 {
2097 uint32_t sh, me;
2098
2099 sh = SH(ctx->opcode) | (shn << 5);
2100 me = MB(ctx->opcode) | (men << 5);
2101 gen_rldinm(ctx, 0, me, sh);
2102 }
2103 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2104
2105 /* rldic - rldic. */
2106 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2107 {
2108 uint32_t sh, mb;
2109
2110 sh = SH(ctx->opcode) | (shn << 5);
2111 mb = MB(ctx->opcode) | (mbn << 5);
2112 gen_rldinm(ctx, mb, 63 - sh, sh);
2113 }
2114 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2115
2116 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2117 {
2118 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2119 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2120 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2121 TCGv t0;
2122
2123 t0 = tcg_temp_new();
2124 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2125 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2126 tcg_temp_free(t0);
2127
2128 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2129 if (unlikely(Rc(ctx->opcode) != 0)) {
2130 gen_set_Rc0(ctx, t_ra);
2131 }
2132 }
2133
2134 /* rldcl - rldcl. */
2135 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2136 {
2137 uint32_t mb;
2138
2139 mb = MB(ctx->opcode) | (mbn << 5);
2140 gen_rldnm(ctx, mb, 63);
2141 }
2142 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2143
2144 /* rldcr - rldcr. */
2145 static inline void gen_rldcr(DisasContext *ctx, int men)
2146 {
2147 uint32_t me;
2148
2149 me = MB(ctx->opcode) | (men << 5);
2150 gen_rldnm(ctx, 0, me);
2151 }
2152 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2153
2154 /* rldimi - rldimi. */
2155 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2156 {
2157 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2158 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2159 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2160 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2161 uint32_t me = 63 - sh;
2162
2163 if (mb <= me) {
2164 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2165 } else {
2166 target_ulong mask = MASK(mb, me);
2167 TCGv t1 = tcg_temp_new();
2168
2169 tcg_gen_rotli_tl(t1, t_rs, sh);
2170 tcg_gen_andi_tl(t1, t1, mask);
2171 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2172 tcg_gen_or_tl(t_ra, t_ra, t1);
2173 tcg_temp_free(t1);
2174 }
2175 if (unlikely(Rc(ctx->opcode) != 0)) {
2176 gen_set_Rc0(ctx, t_ra);
2177 }
2178 }
2179 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2180 #endif
2181
2182 /*** Integer shift ***/
2183
2184 /* slw & slw. */
2185 static void gen_slw(DisasContext *ctx)
2186 {
2187 TCGv t0, t1;
2188
2189 t0 = tcg_temp_new();
2190 /* AND rS with a mask that is 0 when rB >= 0x20 */
2191 #if defined(TARGET_PPC64)
2192 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2193 tcg_gen_sari_tl(t0, t0, 0x3f);
2194 #else
2195 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2196 tcg_gen_sari_tl(t0, t0, 0x1f);
2197 #endif
2198 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2199 t1 = tcg_temp_new();
2200 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2201 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2202 tcg_temp_free(t1);
2203 tcg_temp_free(t0);
2204 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2205 if (unlikely(Rc(ctx->opcode) != 0))
2206 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2207 }
2208
2209 /* sraw & sraw. */
2210 static void gen_sraw(DisasContext *ctx)
2211 {
2212 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2213 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2214 if (unlikely(Rc(ctx->opcode) != 0))
2215 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2216 }
2217
2218 /* srawi & srawi. */
2219 static void gen_srawi(DisasContext *ctx)
2220 {
2221 int sh = SH(ctx->opcode);
2222 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2223 TCGv src = cpu_gpr[rS(ctx->opcode)];
2224 if (sh == 0) {
2225 tcg_gen_ext32s_tl(dst, src);
2226 tcg_gen_movi_tl(cpu_ca, 0);
2227 } else {
2228 TCGv t0;
2229 tcg_gen_ext32s_tl(dst, src);
2230 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2231 t0 = tcg_temp_new();
2232 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2233 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2234 tcg_temp_free(t0);
2235 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2236 tcg_gen_sari_tl(dst, dst, sh);
2237 }
2238 if (unlikely(Rc(ctx->opcode) != 0)) {
2239 gen_set_Rc0(ctx, dst);
2240 }
2241 }
2242
2243 /* srw & srw. */
2244 static void gen_srw(DisasContext *ctx)
2245 {
2246 TCGv t0, t1;
2247
2248 t0 = tcg_temp_new();
2249 /* AND rS with a mask that is 0 when rB >= 0x20 */
2250 #if defined(TARGET_PPC64)
2251 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2252 tcg_gen_sari_tl(t0, t0, 0x3f);
2253 #else
2254 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2255 tcg_gen_sari_tl(t0, t0, 0x1f);
2256 #endif
2257 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2258 tcg_gen_ext32u_tl(t0, t0);
2259 t1 = tcg_temp_new();
2260 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2261 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2262 tcg_temp_free(t1);
2263 tcg_temp_free(t0);
2264 if (unlikely(Rc(ctx->opcode) != 0))
2265 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2266 }
2267
2268 #if defined(TARGET_PPC64)
2269 /* sld & sld. */
2270 static void gen_sld(DisasContext *ctx)
2271 {
2272 TCGv t0, t1;
2273
2274 t0 = tcg_temp_new();
2275 /* AND rS with a mask that is 0 when rB >= 0x40 */
2276 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2277 tcg_gen_sari_tl(t0, t0, 0x3f);
2278 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2279 t1 = tcg_temp_new();
2280 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2281 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2282 tcg_temp_free(t1);
2283 tcg_temp_free(t0);
2284 if (unlikely(Rc(ctx->opcode) != 0))
2285 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2286 }
2287
2288 /* srad & srad. */
2289 static void gen_srad(DisasContext *ctx)
2290 {
2291 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2292 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2293 if (unlikely(Rc(ctx->opcode) != 0))
2294 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2295 }
2296 /* sradi & sradi. */
2297 static inline void gen_sradi(DisasContext *ctx, int n)
2298 {
2299 int sh = SH(ctx->opcode) + (n << 5);
2300 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2301 TCGv src = cpu_gpr[rS(ctx->opcode)];
2302 if (sh == 0) {
2303 tcg_gen_mov_tl(dst, src);
2304 tcg_gen_movi_tl(cpu_ca, 0);
2305 } else {
2306 TCGv t0;
2307 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2308 t0 = tcg_temp_new();
2309 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2310 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2311 tcg_temp_free(t0);
2312 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2313 tcg_gen_sari_tl(dst, src, sh);
2314 }
2315 if (unlikely(Rc(ctx->opcode) != 0)) {
2316 gen_set_Rc0(ctx, dst);
2317 }
2318 }
2319
2320 static void gen_sradi0(DisasContext *ctx)
2321 {
2322 gen_sradi(ctx, 0);
2323 }
2324
2325 static void gen_sradi1(DisasContext *ctx)
2326 {
2327 gen_sradi(ctx, 1);
2328 }
2329
2330 /* srd & srd. */
2331 static void gen_srd(DisasContext *ctx)
2332 {
2333 TCGv t0, t1;
2334
2335 t0 = tcg_temp_new();
2336 /* AND rS with a mask that is 0 when rB >= 0x40 */
2337 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2338 tcg_gen_sari_tl(t0, t0, 0x3f);
2339 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2340 t1 = tcg_temp_new();
2341 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2342 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2343 tcg_temp_free(t1);
2344 tcg_temp_free(t0);
2345 if (unlikely(Rc(ctx->opcode) != 0))
2346 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2347 }
2348 #endif
2349
2350 /*** Addressing modes ***/
2351 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2352 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2353 target_long maskl)
2354 {
2355 target_long simm = SIMM(ctx->opcode);
2356
2357 simm &= ~maskl;
2358 if (rA(ctx->opcode) == 0) {
2359 if (NARROW_MODE(ctx)) {
2360 simm = (uint32_t)simm;
2361 }
2362 tcg_gen_movi_tl(EA, simm);
2363 } else if (likely(simm != 0)) {
2364 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2365 if (NARROW_MODE(ctx)) {
2366 tcg_gen_ext32u_tl(EA, EA);
2367 }
2368 } else {
2369 if (NARROW_MODE(ctx)) {
2370 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2371 } else {
2372 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2373 }
2374 }
2375 }
2376
2377 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2378 {
2379 if (rA(ctx->opcode) == 0) {
2380 if (NARROW_MODE(ctx)) {
2381 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2382 } else {
2383 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2384 }
2385 } else {
2386 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2387 if (NARROW_MODE(ctx)) {
2388 tcg_gen_ext32u_tl(EA, EA);
2389 }
2390 }
2391 }
2392
2393 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2394 {
2395 if (rA(ctx->opcode) == 0) {
2396 tcg_gen_movi_tl(EA, 0);
2397 } else if (NARROW_MODE(ctx)) {
2398 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2399 } else {
2400 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2401 }
2402 }
2403
2404 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2405 target_long val)
2406 {
2407 tcg_gen_addi_tl(ret, arg1, val);
2408 if (NARROW_MODE(ctx)) {
2409 tcg_gen_ext32u_tl(ret, ret);
2410 }
2411 }
2412
2413 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2414 {
2415 TCGLabel *l1 = gen_new_label();
2416 TCGv t0 = tcg_temp_new();
2417 TCGv_i32 t1, t2;
2418 tcg_gen_andi_tl(t0, EA, mask);
2419 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2420 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2421 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2422 gen_update_nip(ctx, ctx->nip - 4);
2423 gen_helper_raise_exception_err(cpu_env, t1, t2);
2424 tcg_temp_free_i32(t1);
2425 tcg_temp_free_i32(t2);
2426 gen_set_label(l1);
2427 tcg_temp_free(t0);
2428 }
2429
2430 static inline void gen_align_no_le(DisasContext *ctx)
2431 {
2432 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2433 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2434 }
2435
2436 /*** Integer load ***/
2437 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2438 {
2439 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2440 }
2441
2442 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2443 {
2444 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2445 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2446 }
2447
2448 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2449 {
2450 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2451 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2452 }
2453
2454 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2455 {
2456 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2457 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2458 }
2459
2460 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2461 {
2462 TCGv tmp = tcg_temp_new();
2463 gen_qemu_ld32u(ctx, tmp, addr);
2464 tcg_gen_extu_tl_i64(val, tmp);
2465 tcg_temp_free(tmp);
2466 }
2467
2468 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2469 {
2470 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2471 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2472 }
2473
2474 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2475 {
2476 TCGv tmp = tcg_temp_new();
2477 gen_qemu_ld32s(ctx, tmp, addr);
2478 tcg_gen_ext_tl_i64(val, tmp);
2479 tcg_temp_free(tmp);
2480 }
2481
2482 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2483 {
2484 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2485 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2486 }
2487
2488 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2489 {
2490 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2491 }
2492
2493 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2494 {
2495 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2496 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2497 }
2498
2499 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2500 {
2501 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2502 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2503 }
2504
2505 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2506 {
2507 TCGv tmp = tcg_temp_new();
2508 tcg_gen_trunc_i64_tl(tmp, val);
2509 gen_qemu_st32(ctx, tmp, addr);
2510 tcg_temp_free(tmp);
2511 }
2512
2513 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2514 {
2515 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2516 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2517 }
2518
2519 #define GEN_LD(name, ldop, opc, type) \
2520 static void glue(gen_, name)(DisasContext *ctx) \
2521 { \
2522 TCGv EA; \
2523 gen_set_access_type(ctx, ACCESS_INT); \
2524 EA = tcg_temp_new(); \
2525 gen_addr_imm_index(ctx, EA, 0); \
2526 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2527 tcg_temp_free(EA); \
2528 }
2529
2530 #define GEN_LDU(name, ldop, opc, type) \
2531 static void glue(gen_, name##u)(DisasContext *ctx) \
2532 { \
2533 TCGv EA; \
2534 if (unlikely(rA(ctx->opcode) == 0 || \
2535 rA(ctx->opcode) == rD(ctx->opcode))) { \
2536 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2537 return; \
2538 } \
2539 gen_set_access_type(ctx, ACCESS_INT); \
2540 EA = tcg_temp_new(); \
2541 if (type == PPC_64B) \
2542 gen_addr_imm_index(ctx, EA, 0x03); \
2543 else \
2544 gen_addr_imm_index(ctx, EA, 0); \
2545 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2546 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2547 tcg_temp_free(EA); \
2548 }
2549
2550 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2551 static void glue(gen_, name##ux)(DisasContext *ctx) \
2552 { \
2553 TCGv EA; \
2554 if (unlikely(rA(ctx->opcode) == 0 || \
2555 rA(ctx->opcode) == rD(ctx->opcode))) { \
2556 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2557 return; \
2558 } \
2559 gen_set_access_type(ctx, ACCESS_INT); \
2560 EA = tcg_temp_new(); \
2561 gen_addr_reg_index(ctx, EA); \
2562 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2563 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2564 tcg_temp_free(EA); \
2565 }
2566
2567 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2568 static void glue(gen_, name##x)(DisasContext *ctx) \
2569 { \
2570 TCGv EA; \
2571 chk; \
2572 gen_set_access_type(ctx, ACCESS_INT); \
2573 EA = tcg_temp_new(); \
2574 gen_addr_reg_index(ctx, EA); \
2575 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2576 tcg_temp_free(EA); \
2577 }
2578
2579 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2580 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2581
2582 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2583 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2584
2585 #define GEN_LDS(name, ldop, op, type) \
2586 GEN_LD(name, ldop, op | 0x20, type); \
2587 GEN_LDU(name, ldop, op | 0x21, type); \
2588 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2589 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2590
2591 /* lbz lbzu lbzux lbzx */
2592 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2593 /* lha lhau lhaux lhax */
2594 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2595 /* lhz lhzu lhzux lhzx */
2596 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2597 /* lwz lwzu lwzux lwzx */
2598 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2599 #if defined(TARGET_PPC64)
2600 /* lwaux */
2601 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2602 /* lwax */
2603 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2604 /* ldux */
2605 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2606 /* ldx */
2607 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2608
2609 /* CI load/store variants */
2610 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
2611 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2612 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2613 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2614
2615 static void gen_ld(DisasContext *ctx)
2616 {
2617 TCGv EA;
2618 if (Rc(ctx->opcode)) {
2619 if (unlikely(rA(ctx->opcode) == 0 ||
2620 rA(ctx->opcode) == rD(ctx->opcode))) {
2621 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2622 return;
2623 }
2624 }
2625 gen_set_access_type(ctx, ACCESS_INT);
2626 EA = tcg_temp_new();
2627 gen_addr_imm_index(ctx, EA, 0x03);
2628 if (ctx->opcode & 0x02) {
2629 /* lwa (lwau is undefined) */
2630 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2631 } else {
2632 /* ld - ldu */
2633 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2634 }
2635 if (Rc(ctx->opcode))
2636 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2637 tcg_temp_free(EA);
2638 }
2639
2640 /* lq */
2641 static void gen_lq(DisasContext *ctx)
2642 {
2643 int ra, rd;
2644 TCGv EA;
2645
2646 /* lq is a legal user mode instruction starting in ISA 2.07 */
2647 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2648 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2649
2650 if (!legal_in_user_mode && ctx->pr) {
2651 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2652 return;
2653 }
2654
2655 if (!le_is_supported && ctx->le_mode) {
2656 gen_align_no_le(ctx);
2657 return;
2658 }
2659 ra = rA(ctx->opcode);
2660 rd = rD(ctx->opcode);
2661 if (unlikely((rd & 1) || rd == ra)) {
2662 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2663 return;
2664 }
2665
2666 gen_set_access_type(ctx, ACCESS_INT);
2667 EA = tcg_temp_new();
2668 gen_addr_imm_index(ctx, EA, 0x0F);
2669
2670 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2671 64-bit byteswap already. */
2672 if (unlikely(ctx->le_mode)) {
2673 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2674 gen_addr_add(ctx, EA, EA, 8);
2675 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2676 } else {
2677 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2678 gen_addr_add(ctx, EA, EA, 8);
2679 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2680 }
2681 tcg_temp_free(EA);
2682 }
2683 #endif
2684
2685 /*** Integer store ***/
2686 #define GEN_ST(name, stop, opc, type) \
2687 static void glue(gen_, name)(DisasContext *ctx) \
2688 { \
2689 TCGv EA; \
2690 gen_set_access_type(ctx, ACCESS_INT); \
2691 EA = tcg_temp_new(); \
2692 gen_addr_imm_index(ctx, EA, 0); \
2693 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2694 tcg_temp_free(EA); \
2695 }
2696
2697 #define GEN_STU(name, stop, opc, type) \
2698 static void glue(gen_, stop##u)(DisasContext *ctx) \
2699 { \
2700 TCGv EA; \
2701 if (unlikely(rA(ctx->opcode) == 0)) { \
2702 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2703 return; \
2704 } \
2705 gen_set_access_type(ctx, ACCESS_INT); \
2706 EA = tcg_temp_new(); \
2707 if (type == PPC_64B) \
2708 gen_addr_imm_index(ctx, EA, 0x03); \
2709 else \
2710 gen_addr_imm_index(ctx, EA, 0); \
2711 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2712 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2713 tcg_temp_free(EA); \
2714 }
2715
2716 #define GEN_STUX(name, stop, opc2, opc3, type) \
2717 static void glue(gen_, name##ux)(DisasContext *ctx) \
2718 { \
2719 TCGv EA; \
2720 if (unlikely(rA(ctx->opcode) == 0)) { \
2721 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2722 return; \
2723 } \
2724 gen_set_access_type(ctx, ACCESS_INT); \
2725 EA = tcg_temp_new(); \
2726 gen_addr_reg_index(ctx, EA); \
2727 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2728 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2729 tcg_temp_free(EA); \
2730 }
2731
2732 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2733 static void glue(gen_, name##x)(DisasContext *ctx) \
2734 { \
2735 TCGv EA; \
2736 chk; \
2737 gen_set_access_type(ctx, ACCESS_INT); \
2738 EA = tcg_temp_new(); \
2739 gen_addr_reg_index(ctx, EA); \
2740 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2741 tcg_temp_free(EA); \
2742 }
2743 #define GEN_STX(name, stop, opc2, opc3, type) \
2744 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2745
2746 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2747 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2748
2749 #define GEN_STS(name, stop, op, type) \
2750 GEN_ST(name, stop, op | 0x20, type); \
2751 GEN_STU(name, stop, op | 0x21, type); \
2752 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2753 GEN_STX(name, stop, 0x17, op | 0x00, type)
2754
2755 /* stb stbu stbux stbx */
2756 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2757 /* sth sthu sthux sthx */
2758 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2759 /* stw stwu stwux stwx */
2760 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2761 #if defined(TARGET_PPC64)
2762 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2763 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2764 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
2765 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2766 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2767 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2768
2769 static void gen_std(DisasContext *ctx)
2770 {
2771 int rs;
2772 TCGv EA;
2773
2774 rs = rS(ctx->opcode);
2775 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2776 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2777 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2778
2779 if (!(ctx->insns_flags & PPC_64BX)) {
2780 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2781 }
2782
2783 if (!legal_in_user_mode && ctx->pr) {
2784 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2785 return;
2786 }
2787
2788 if (!le_is_supported && ctx->le_mode) {
2789 gen_align_no_le(ctx);
2790 return;
2791 }
2792
2793 if (unlikely(rs & 1)) {
2794 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2795 return;
2796 }
2797 gen_set_access_type(ctx, ACCESS_INT);
2798 EA = tcg_temp_new();
2799 gen_addr_imm_index(ctx, EA, 0x03);
2800
2801 /* We only need to swap high and low halves. gen_qemu_st64 does
2802 necessary 64-bit byteswap already. */
2803 if (unlikely(ctx->le_mode)) {
2804 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2805 gen_addr_add(ctx, EA, EA, 8);
2806 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2807 } else {
2808 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2809 gen_addr_add(ctx, EA, EA, 8);
2810 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2811 }
2812 tcg_temp_free(EA);
2813 } else {
2814 /* std / stdu*/
2815 if (Rc(ctx->opcode)) {
2816 if (unlikely(rA(ctx->opcode) == 0)) {
2817 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2818 return;
2819 }
2820 }
2821 gen_set_access_type(ctx, ACCESS_INT);
2822 EA = tcg_temp_new();
2823 gen_addr_imm_index(ctx, EA, 0x03);
2824 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2825 if (Rc(ctx->opcode))
2826 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2827 tcg_temp_free(EA);
2828 }
2829 }
2830 #endif
2831 /*** Integer load and store with byte reverse ***/
2832
2833 /* lhbrx */
2834 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2835 {
2836 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2837 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2838 }
2839 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2840
2841 /* lwbrx */
2842 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2843 {
2844 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2845 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2846 }
2847 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2848
2849 #if defined(TARGET_PPC64)
2850 /* ldbrx */
2851 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2852 {
2853 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2854 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2855 }
2856 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2857 #endif /* TARGET_PPC64 */
2858
2859 /* sthbrx */
2860 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2861 {
2862 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2863 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2864 }
2865 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2866
2867 /* stwbrx */
2868 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2869 {
2870 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2871 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2872 }
2873 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2874
2875 #if defined(TARGET_PPC64)
2876 /* stdbrx */
2877 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2878 {
2879 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2880 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2881 }
2882 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2883 #endif /* TARGET_PPC64 */
2884
2885 /*** Integer load and store multiple ***/
2886
2887 /* lmw */
2888 static void gen_lmw(DisasContext *ctx)
2889 {
2890 TCGv t0;
2891 TCGv_i32 t1;
2892
2893 if (ctx->le_mode) {
2894 gen_align_no_le(ctx);
2895 return;
2896 }
2897 gen_set_access_type(ctx, ACCESS_INT);
2898 t0 = tcg_temp_new();
2899 t1 = tcg_const_i32(rD(ctx->opcode));
2900 gen_addr_imm_index(ctx, t0, 0);
2901 gen_helper_lmw(cpu_env, t0, t1);
2902 tcg_temp_free(t0);
2903 tcg_temp_free_i32(t1);
2904 }
2905
2906 /* stmw */
2907 static void gen_stmw(DisasContext *ctx)
2908 {
2909 TCGv t0;
2910 TCGv_i32 t1;
2911
2912 if (ctx->le_mode) {
2913 gen_align_no_le(ctx);
2914 return;
2915 }
2916 gen_set_access_type(ctx, ACCESS_INT);
2917 t0 = tcg_temp_new();
2918 t1 = tcg_const_i32(rS(ctx->opcode));
2919 gen_addr_imm_index(ctx, t0, 0);
2920 gen_helper_stmw(cpu_env, t0, t1);
2921 tcg_temp_free(t0);
2922 tcg_temp_free_i32(t1);
2923 }
2924
2925 /*** Integer load and store strings ***/
2926
2927 /* lswi */
2928 /* PowerPC32 specification says we must generate an exception if
2929 * rA is in the range of registers to be loaded.
2930 * In an other hand, IBM says this is valid, but rA won't be loaded.
2931 * For now, I'll follow the spec...
2932 */
2933 static void gen_lswi(DisasContext *ctx)
2934 {
2935 TCGv t0;
2936 TCGv_i32 t1, t2;
2937 int nb = NB(ctx->opcode);
2938 int start = rD(ctx->opcode);
2939 int ra = rA(ctx->opcode);
2940 int nr;
2941
2942 if (ctx->le_mode) {
2943 gen_align_no_le(ctx);
2944 return;
2945 }
2946 if (nb == 0)
2947 nb = 32;
2948 nr = (nb + 3) / 4;
2949 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2950 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2951 return;
2952 }
2953 gen_set_access_type(ctx, ACCESS_INT);
2954 t0 = tcg_temp_new();
2955 gen_addr_register(ctx, t0);
2956 t1 = tcg_const_i32(nb);
2957 t2 = tcg_const_i32(start);
2958 gen_helper_lsw(cpu_env, t0, t1, t2);
2959 tcg_temp_free(t0);
2960 tcg_temp_free_i32(t1);
2961 tcg_temp_free_i32(t2);
2962 }
2963
2964 /* lswx */
2965 static void gen_lswx(DisasContext *ctx)
2966 {
2967 TCGv t0;
2968 TCGv_i32 t1, t2, t3;
2969
2970 if (ctx->le_mode) {
2971 gen_align_no_le(ctx);
2972 return;
2973 }
2974 gen_set_access_type(ctx, ACCESS_INT);
2975 t0 = tcg_temp_new();
2976 gen_addr_reg_index(ctx, t0);
2977 t1 = tcg_const_i32(rD(ctx->opcode));
2978 t2 = tcg_const_i32(rA(ctx->opcode));
2979 t3 = tcg_const_i32(rB(ctx->opcode));
2980 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2981 tcg_temp_free(t0);
2982 tcg_temp_free_i32(t1);
2983 tcg_temp_free_i32(t2);
2984 tcg_temp_free_i32(t3);
2985 }
2986
2987 /* stswi */
2988 static void gen_stswi(DisasContext *ctx)
2989 {
2990 TCGv t0;
2991 TCGv_i32 t1, t2;
2992 int nb = NB(ctx->opcode);
2993
2994 if (ctx->le_mode) {
2995 gen_align_no_le(ctx);
2996 return;
2997 }
2998 gen_set_access_type(ctx, ACCESS_INT);
2999 t0 = tcg_temp_new();
3000 gen_addr_register(ctx, t0);
3001 if (nb == 0)
3002 nb = 32;
3003 t1 = tcg_const_i32(nb);
3004 t2 = tcg_const_i32(rS(ctx->opcode));
3005 gen_helper_stsw(cpu_env, t0, t1, t2);
3006 tcg_temp_free(t0);
3007 tcg_temp_free_i32(t1);
3008 tcg_temp_free_i32(t2);
3009 }
3010
3011 /* stswx */
3012 static void gen_stswx(DisasContext *ctx)
3013 {
3014 TCGv t0;
3015 TCGv_i32 t1, t2;
3016
3017 if (ctx->le_mode) {
3018 gen_align_no_le(ctx);
3019 return;
3020 }
3021 gen_set_access_type(ctx, ACCESS_INT);
3022 t0 = tcg_temp_new();
3023 gen_addr_reg_index(ctx, t0);
3024 t1 = tcg_temp_new_i32();
3025 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3026 tcg_gen_andi_i32(t1, t1, 0x7F);
3027 t2 = tcg_const_i32(rS(ctx->opcode));
3028 gen_helper_stsw(cpu_env, t0, t1, t2);
3029 tcg_temp_free(t0);
3030 tcg_temp_free_i32(t1);
3031 tcg_temp_free_i32(t2);
3032 }
3033
3034 /*** Memory synchronisation ***/
3035 /* eieio */
3036 static void gen_eieio(DisasContext *ctx)
3037 {
3038 }
3039
3040 #if !defined(CONFIG_USER_ONLY)
3041 static inline void gen_check_tlb_flush(DisasContext *ctx)
3042 {
3043 TCGv_i32 t;
3044 TCGLabel *l;
3045
3046 if (!ctx->lazy_tlb_flush) {
3047 return;
3048 }
3049 l = gen_new_label();
3050 t = tcg_temp_new_i32();
3051 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3052 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3053 gen_helper_check_tlb_flush(cpu_env);
3054 gen_set_label(l);
3055 tcg_temp_free_i32(t);
3056 }
3057 #else
3058 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3059 #endif
3060
3061 /* isync */
3062 static void gen_isync(DisasContext *ctx)
3063 {
3064 /*
3065 * We need to check for a pending TLB flush. This can only happen in
3066 * kernel mode however so check MSR_PR
3067 */
3068 if (!ctx->pr) {
3069 gen_check_tlb_flush(ctx);
3070 }
3071 gen_stop_exception(ctx);
3072 }
3073
3074 #define LARX(name, len, loadop) \
3075 static void gen_##name(DisasContext *ctx) \
3076 { \
3077 TCGv t0; \
3078 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3079 gen_set_access_type(ctx, ACCESS_RES); \
3080 t0 = tcg_temp_local_new(); \
3081 gen_addr_reg_index(ctx, t0); \
3082 if ((len) > 1) { \
3083 gen_check_align(ctx, t0, (len)-1); \
3084 } \
3085 gen_qemu_##loadop(ctx, gpr, t0); \
3086 tcg_gen_mov_tl(cpu_reserve, t0); \
3087 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3088 tcg_temp_free(t0); \
3089 }
3090
3091 /* lwarx */
3092 LARX(lbarx, 1, ld8u);
3093 LARX(lharx, 2, ld16u);
3094 LARX(lwarx, 4, ld32u);
3095
3096
3097 #if defined(CONFIG_USER_ONLY)
3098 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3099 int reg, int size)
3100 {
3101 TCGv t0 = tcg_temp_new();
3102
3103 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3104 tcg_gen_movi_tl(t0, (size << 5) | reg);
3105 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3106 tcg_temp_free(t0);
3107 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3108 }
3109 #else
3110 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3111 int reg, int size)
3112 {
3113 TCGLabel *l1;
3114
3115 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3116 l1 = gen_new_label();
3117 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3118 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3119 #if defined(TARGET_PPC64)
3120 if (size == 8) {
3121 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3122 } else
3123 #endif
3124 if (size == 4) {
3125 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3126 } else if (size == 2) {
3127 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3128 #if defined(TARGET_PPC64)
3129 } else if (size == 16) {
3130 TCGv gpr1, gpr2 , EA8;
3131 if (unlikely(ctx->le_mode)) {
3132 gpr1 = cpu_gpr[reg+1];
3133 gpr2 = cpu_gpr[reg];
3134 } else {
3135 gpr1 = cpu_gpr[reg];
3136 gpr2 = cpu_gpr[reg+1];
3137 }
3138 gen_qemu_st64(ctx, gpr1, EA);
3139 EA8 = tcg_temp_local_new();
3140 gen_addr_add(ctx, EA8, EA, 8);
3141 gen_qemu_st64(ctx, gpr2, EA8);
3142 tcg_temp_free(EA8);
3143 #endif
3144 } else {
3145 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3146 }
3147 gen_set_label(l1);
3148 tcg_gen_movi_tl(cpu_reserve, -1);
3149 }
3150 #endif
3151
3152 #define STCX(name, len) \
3153 static void gen_##name(DisasContext *ctx) \
3154 { \
3155 TCGv t0; \
3156 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3157 gen_inval_exception(ctx, \
3158 POWERPC_EXCP_INVAL_INVAL); \
3159 return; \
3160 } \
3161 gen_set_access_type(ctx, ACCESS_RES); \
3162 t0 = tcg_temp_local_new(); \
3163 gen_addr_reg_index(ctx, t0); \
3164 if (len > 1) { \
3165 gen_check_align(ctx, t0, (len)-1); \
3166 } \
3167 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3168 tcg_temp_free(t0); \
3169 }
3170
3171 STCX(stbcx_, 1);
3172 STCX(sthcx_, 2);
3173 STCX(stwcx_, 4);
3174
3175 #if defined(TARGET_PPC64)
3176 /* ldarx */
3177 LARX(ldarx, 8, ld64);
3178
3179 /* lqarx */
3180 static void gen_lqarx(DisasContext *ctx)
3181 {
3182 TCGv EA;
3183 int rd = rD(ctx->opcode);
3184 TCGv gpr1, gpr2;
3185
3186 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3187 (rd == rB(ctx->opcode)))) {
3188 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3189 return;
3190 }
3191
3192 gen_set_access_type(ctx, ACCESS_RES);
3193 EA = tcg_temp_local_new();
3194 gen_addr_reg_index(ctx, EA);
3195 gen_check_align(ctx, EA, 15);
3196 if (unlikely(ctx->le_mode)) {
3197 gpr1 = cpu_gpr[rd+1];
3198 gpr2 = cpu_gpr[rd];
3199 } else {
3200 gpr1 = cpu_gpr[rd];
3201 gpr2 = cpu_gpr[rd+1];
3202 }
3203 gen_qemu_ld64(ctx, gpr1, EA);
3204 tcg_gen_mov_tl(cpu_reserve, EA);
3205
3206 gen_addr_add(ctx, EA, EA, 8);
3207 gen_qemu_ld64(ctx, gpr2, EA);
3208
3209 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3210 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3211
3212 tcg_temp_free(EA);
3213 }
3214
3215 /* stdcx. */
3216 STCX(stdcx_, 8);
3217 STCX(stqcx_, 16);
3218 #endif /* defined(TARGET_PPC64) */
3219
3220 /* sync */
3221 static void gen_sync(DisasContext *ctx)
3222 {
3223 uint32_t l = (ctx->opcode >> 21) & 3;
3224
3225 /*
3226 * We may need to check for a pending TLB flush.
3227 *
3228 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3229 *
3230 * Additionally, this can only happen in kernel mode however so
3231 * check MSR_PR as well.
3232 */
3233 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3234 gen_check_tlb_flush(ctx);
3235 }
3236 }
3237
3238 /* wait */
3239 static void gen_wait(DisasContext *ctx)
3240 {
3241 TCGv_i32 t0 = tcg_const_i32(1);
3242 tcg_gen_st_i32(t0, cpu_env,
3243 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3244 tcg_temp_free_i32(t0);
3245 /* Stop translation, as the CPU is supposed to sleep from now */
3246 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3247 }
3248
3249 #if defined(TARGET_PPC64)
3250 static void gen_doze(DisasContext *ctx)
3251 {
3252 #if defined(CONFIG_USER_ONLY)
3253 GEN_PRIV;
3254 #else
3255 TCGv_i32 t;
3256
3257 CHK_HV;
3258 t = tcg_const_i32(PPC_PM_DOZE);
3259 gen_helper_pminsn(cpu_env, t);
3260 tcg_temp_free_i32(t);
3261 gen_stop_exception(ctx);
3262 #endif /* defined(CONFIG_USER_ONLY) */
3263 }
3264
3265 static void gen_nap(DisasContext *ctx)
3266 {
3267 #if defined(CONFIG_USER_ONLY)
3268 GEN_PRIV;
3269 #else
3270 TCGv_i32 t;
3271
3272 CHK_HV;
3273 t = tcg_const_i32(PPC_PM_NAP);
3274 gen_helper_pminsn(cpu_env, t);
3275 tcg_temp_free_i32(t);
3276 gen_stop_exception(ctx);
3277 #endif /* defined(CONFIG_USER_ONLY) */
3278 }
3279
3280 static void gen_sleep(DisasContext *ctx)
3281 {
3282 #if defined(CONFIG_USER_ONLY)
3283 GEN_PRIV;
3284 #else
3285 TCGv_i32 t;
3286
3287 CHK_HV;
3288 t = tcg_const_i32(PPC_PM_SLEEP);
3289 gen_helper_pminsn(cpu_env, t);
3290 tcg_temp_free_i32(t);
3291 gen_stop_exception(ctx);
3292 #endif /* defined(CONFIG_USER_ONLY) */
3293 }
3294
3295 static void gen_rvwinkle(DisasContext *ctx)
3296 {
3297 #if defined(CONFIG_USER_ONLY)
3298 GEN_PRIV;
3299 #else
3300 TCGv_i32 t;
3301
3302 CHK_HV;
3303 t = tcg_const_i32(PPC_PM_RVWINKLE);
3304 gen_helper_pminsn(cpu_env, t);
3305 tcg_temp_free_i32(t);
3306 gen_stop_exception(ctx);
3307 #endif /* defined(CONFIG_USER_ONLY) */
3308 }
3309 #endif /* #if defined(TARGET_PPC64) */
3310
3311 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3312 {
3313 #if defined(TARGET_PPC64)
3314 if (ctx->has_cfar)
3315 tcg_gen_movi_tl(cpu_cfar, nip);
3316 #endif
3317 }
3318
3319 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3320 {
3321 if (unlikely(ctx->singlestep_enabled)) {
3322 return false;
3323 }
3324
3325 #ifndef CONFIG_USER_ONLY
3326 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3327 #else
3328 return true;
3329 #endif
3330 }
3331
3332 /*** Branch ***/
3333 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3334 {
3335 if (NARROW_MODE(ctx)) {
3336 dest = (uint32_t) dest;
3337 }
3338 if (use_goto_tb(ctx, dest)) {
3339 tcg_gen_goto_tb(n);
3340 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3341 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3342 } else {
3343 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3344 if (unlikely(ctx->singlestep_enabled)) {
3345 if ((ctx->singlestep_enabled &
3346 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3347 (ctx->exception == POWERPC_EXCP_BRANCH ||
3348 ctx->exception == POWERPC_EXCP_TRACE)) {
3349 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3350 }
3351 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3352 gen_debug_exception(ctx);
3353 }
3354 }
3355 tcg_gen_exit_tb(0);
3356 }
3357 }
3358
3359 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3360 {
3361 if (NARROW_MODE(ctx)) {
3362 nip = (uint32_t)nip;
3363 }
3364 tcg_gen_movi_tl(cpu_lr, nip);
3365 }
3366
3367 /* b ba bl bla */
3368 static void gen_b(DisasContext *ctx)
3369 {
3370 target_ulong li, target;
3371
3372 ctx->exception = POWERPC_EXCP_BRANCH;
3373 /* sign extend LI */
3374 li = LI(ctx->opcode);
3375 li = (li ^ 0x02000000) - 0x02000000;
3376 if (likely(AA(ctx->opcode) == 0)) {
3377 target = ctx->nip + li - 4;
3378 } else {
3379 target = li;
3380 }
3381 if (LK(ctx->opcode)) {
3382 gen_setlr(ctx, ctx->nip);
3383 }
3384 gen_update_cfar(ctx, ctx->nip - 4);
3385 gen_goto_tb(ctx, 0, target);
3386 }
3387
3388 #define BCOND_IM 0
3389 #define BCOND_LR 1
3390 #define BCOND_CTR 2
3391 #define BCOND_TAR 3
3392
3393 static inline void gen_bcond(DisasContext *ctx, int type)
3394 {
3395 uint32_t bo = BO(ctx->opcode);
3396 TCGLabel *l1;
3397 TCGv target;
3398
3399 ctx->exception = POWERPC_EXCP_BRANCH;
3400 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3401 target = tcg_temp_local_new();
3402 if (type == BCOND_CTR)
3403 tcg_gen_mov_tl(target, cpu_ctr);
3404 else if (type == BCOND_TAR)
3405 gen_load_spr(target, SPR_TAR);
3406 else
3407 tcg_gen_mov_tl(target, cpu_lr);
3408 } else {
3409 TCGV_UNUSED(target);
3410 }
3411 if (LK(ctx->opcode))
3412 gen_setlr(ctx, ctx->nip);
3413 l1 = gen_new_label();
3414 if ((bo & 0x4) == 0) {
3415 /* Decrement and test CTR */
3416 TCGv temp = tcg_temp_new();
3417 if (unlikely(type == BCOND_CTR)) {
3418 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3419 return;
3420 }
3421 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3422 if (NARROW_MODE(ctx)) {
3423 tcg_gen_ext32u_tl(temp, cpu_ctr);
3424 } else {
3425 tcg_gen_mov_tl(temp, cpu_ctr);
3426 }
3427 if (bo & 0x2) {
3428 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3429 } else {
3430 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3431 }
3432 tcg_temp_free(temp);
3433 }
3434 if ((bo & 0x10) == 0) {
3435 /* Test CR */
3436 uint32_t bi = BI(ctx->opcode);
3437 uint32_t mask = 0x08 >> (bi & 0x03);
3438 TCGv_i32 temp = tcg_temp_new_i32();
3439
3440 if (bo & 0x8) {
3441 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3442 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3443 } else {
3444 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3445 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3446 }
3447 tcg_temp_free_i32(temp);
3448 }
3449 gen_update_cfar(ctx, ctx->nip - 4);
3450 if (type == BCOND_IM) {
3451 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3452 if (likely(AA(ctx->opcode) == 0)) {
3453 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3454 } else {
3455 gen_goto_tb(ctx, 0, li);
3456 }
3457 gen_set_label(l1);
3458 gen_goto_tb(ctx, 1, ctx->nip);
3459 } else {
3460 if (NARROW_MODE(ctx)) {
3461 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3462 } else {
3463 tcg_gen_andi_tl(cpu_nip, target, ~3);
3464 }
3465 tcg_gen_exit_tb(0);
3466 gen_set_label(l1);
3467 gen_update_nip(ctx, ctx->nip);
3468 tcg_gen_exit_tb(0);
3469 }
3470 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3471 tcg_temp_free(target);
3472 }
3473 }
3474
3475 static void gen_bc(DisasContext *ctx)
3476 {
3477 gen_bcond(ctx, BCOND_IM);
3478 }
3479
3480 static void gen_bcctr(DisasContext *ctx)
3481 {
3482 gen_bcond(ctx, BCOND_CTR);
3483 }
3484
3485 static void gen_bclr(DisasContext *ctx)
3486 {
3487 gen_bcond(ctx, BCOND_LR);
3488 }
3489
3490 static void gen_bctar(DisasContext *ctx)
3491 {
3492 gen_bcond(ctx, BCOND_TAR);
3493 }
3494
3495 /*** Condition register logical ***/
3496 #define GEN_CRLOGIC(name, tcg_op, opc) \
3497 static void glue(gen_, name)(DisasContext *ctx) \
3498 { \
3499 uint8_t bitmask; \
3500 int sh; \
3501 TCGv_i32 t0, t1; \
3502 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3503 t0 = tcg_temp_new_i32(); \
3504 if (sh > 0) \
3505 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3506 else if (sh < 0) \
3507 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3508 else \
3509 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3510 t1 = tcg_temp_new_i32(); \
3511 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3512 if (sh > 0) \
3513 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3514 else if (sh < 0) \
3515 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3516 else \
3517 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3518 tcg_op(t0, t0, t1); \
3519 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3520 tcg_gen_andi_i32(t0, t0, bitmask); \
3521 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3522 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3523 tcg_temp_free_i32(t0); \
3524 tcg_temp_free_i32(t1); \
3525 }
3526
3527 /* crand */
3528 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3529 /* crandc */
3530 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3531 /* creqv */
3532 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3533 /* crnand */
3534 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3535 /* crnor */
3536 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3537 /* cror */
3538 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3539 /* crorc */
3540 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3541 /* crxor */
3542 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3543
3544 /* mcrf */
3545 static void gen_mcrf(DisasContext *ctx)
3546 {
3547 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3548 }
3549
3550 /*** System linkage ***/
3551
3552 /* rfi (supervisor only) */
3553 static void gen_rfi(DisasContext *ctx)
3554 {
3555 #if defined(CONFIG_USER_ONLY)
3556 GEN_PRIV;
3557 #else
3558 /* FIXME: This instruction doesn't exist anymore on 64-bit server
3559 * processors compliant with arch 2.x, we should remove it there,
3560 * but we need to fix OpenBIOS not to use it on 970 first
3561 */
3562 /* Restore CPU state */
3563 CHK_SV;
3564 gen_update_cfar(ctx, ctx->nip - 4);
3565 gen_helper_rfi(cpu_env);
3566 gen_sync_exception(ctx);
3567 #endif
3568 }
3569
3570 #if defined(TARGET_PPC64)
3571 static void gen_rfid(DisasContext *ctx)
3572 {
3573 #if defined(CONFIG_USER_ONLY)
3574 GEN_PRIV;
3575 #else
3576 /* Restore CPU state */
3577 CHK_SV;
3578 gen_update_cfar(ctx, ctx->nip - 4);
3579 gen_helper_rfid(cpu_env);
3580 gen_sync_exception(ctx);
3581 #endif
3582 }
3583
3584 static void gen_hrfid(DisasContext *ctx)
3585 {
3586 #if defined(CONFIG_USER_ONLY)
3587 GEN_PRIV;
3588 #else
3589 /* Restore CPU state */
3590 CHK_HV;
3591 gen_helper_hrfid(cpu_env);
3592 gen_sync_exception(ctx);
3593 #endif
3594 }
3595 #endif
3596
3597 /* sc */
3598 #if defined(CONFIG_USER_ONLY)
3599 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3600 #else
3601 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3602 #endif
3603 static void gen_sc(DisasContext *ctx)
3604 {
3605 uint32_t lev;
3606
3607 lev = (ctx->opcode >> 5) & 0x7F;
3608 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3609 }
3610
3611 /*** Trap ***/
3612
3613 /* Check for unconditional traps (always or never) */
3614 static bool check_unconditional_trap(DisasContext *ctx)
3615 {
3616 /* Trap never */
3617 if (TO(ctx->opcode) == 0) {
3618 return true;
3619 }
3620 /* Trap always */
3621 if (TO(ctx->opcode) == 31) {
3622 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3623 return true;
3624 }
3625 return false;
3626 }
3627
3628 /* tw */
3629 static void gen_tw(DisasContext *ctx)
3630 {
3631 TCGv_i32 t0;
3632
3633 if (check_unconditional_trap(ctx)) {
3634 return;
3635 }
3636 t0 = tcg_const_i32(TO(ctx->opcode));
3637 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3638 t0);
3639 tcg_temp_free_i32(t0);
3640 }
3641
3642 /* twi */
3643 static void gen_twi(DisasContext *ctx)
3644 {
3645 TCGv t0;
3646 TCGv_i32 t1;
3647
3648 if (check_unconditional_trap(ctx)) {
3649 return;
3650 }
3651 t0 = tcg_const_tl(SIMM(ctx->opcode));
3652 t1 = tcg_const_i32(TO(ctx->opcode));
3653 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3654 tcg_temp_free(t0);
3655 tcg_temp_free_i32(t1);
3656 }
3657
3658 #if defined(TARGET_PPC64)
3659 /* td */
3660 static void gen_td(DisasContext *ctx)
3661 {
3662 TCGv_i32 t0;
3663
3664 if (check_unconditional_trap(ctx)) {
3665 return;
3666 }
3667 t0 = tcg_const_i32(TO(ctx->opcode));
3668 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3669 t0);
3670 tcg_temp_free_i32(t0);
3671 }
3672
3673 /* tdi */
3674 static void gen_tdi(DisasContext *ctx)
3675 {
3676 TCGv t0;
3677 TCGv_i32 t1;
3678
3679 if (check_unconditional_trap(ctx)) {
3680 return;
3681 }
3682 t0 = tcg_const_tl(SIMM(ctx->opcode));
3683 t1 = tcg_const_i32(TO(ctx->opcode));
3684 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3685 tcg_temp_free(t0);
3686 tcg_temp_free_i32(t1);
3687 }
3688 #endif
3689
3690 /*** Processor control ***/
3691
3692 static void gen_read_xer(TCGv dst)
3693 {
3694 TCGv t0 = tcg_temp_new();
3695 TCGv t1 = tcg_temp_new();
3696 TCGv t2 = tcg_temp_new();
3697 tcg_gen_mov_tl(dst, cpu_xer);
3698 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3699 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3700 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3701 tcg_gen_or_tl(t0, t0, t1);
3702 tcg_gen_or_tl(dst, dst, t2);
3703 tcg_gen_or_tl(dst, dst, t0);
3704 tcg_temp_free(t0);
3705 tcg_temp_free(t1);
3706 tcg_temp_free(t2);
3707 }
3708
3709 static void gen_write_xer(TCGv src)
3710 {
3711 tcg_gen_andi_tl(cpu_xer, src,
3712 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3713 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3714 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3715 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3716 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3717 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3718 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3719 }
3720
3721 /* mcrxr */
3722 static void gen_mcrxr(DisasContext *ctx)
3723 {
3724 TCGv_i32 t0 = tcg_temp_new_i32();
3725 TCGv_i32 t1 = tcg_temp_new_i32();
3726 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3727
3728 tcg_gen_trunc_tl_i32(t0, cpu_so);
3729 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3730 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3731 tcg_gen_shli_i32(t0, t0, 3);
3732 tcg_gen_shli_i32(t1, t1, 2);
3733 tcg_gen_shli_i32(dst, dst, 1);
3734 tcg_gen_or_i32(dst, dst, t0);
3735 tcg_gen_or_i32(dst, dst, t1);
3736 tcg_temp_free_i32(t0);
3737 tcg_temp_free_i32(t1);
3738
3739 tcg_gen_movi_tl(cpu_so, 0);
3740 tcg_gen_movi_tl(cpu_ov, 0);
3741 tcg_gen_movi_tl(cpu_ca, 0);
3742 }
3743
3744 /* mfcr mfocrf */
3745 static void gen_mfcr(DisasContext *ctx)
3746 {
3747 uint32_t crm, crn;
3748
3749 if (likely(ctx->opcode & 0x00100000)) {
3750 crm = CRM(ctx->opcode);
3751 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3752 crn = ctz32 (crm);
3753 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3754 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3755 cpu_gpr[rD(ctx->opcode)], crn * 4);
3756 }
3757 } else {
3758 TCGv_i32 t0 = tcg_temp_new_i32();
3759 tcg_gen_mov_i32(t0, cpu_crf[0]);
3760 tcg_gen_shli_i32(t0, t0, 4);
3761 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3762 tcg_gen_shli_i32(t0, t0, 4);
3763 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3764 tcg_gen_shli_i32(t0, t0, 4);
3765 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3766 tcg_gen_shli_i32(t0, t0, 4);
3767 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3768 tcg_gen_shli_i32(t0, t0, 4);
3769 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3770 tcg_gen_shli_i32(t0, t0, 4);
3771 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3772 tcg_gen_shli_i32(t0, t0, 4);
3773 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3774 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3775 tcg_temp_free_i32(t0);
3776 }
3777 }
3778
3779 /* mfmsr */
3780 static void gen_mfmsr(DisasContext *ctx)
3781 {
3782 CHK_SV;
3783 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3784 }
3785
3786 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3787 {
3788 #if 0
3789 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3790 printf("ERROR: try to access SPR %d !\n", sprn);
3791 #endif
3792 }
3793 #define SPR_NOACCESS (&spr_noaccess)
3794
3795 /* mfspr */
3796 static inline void gen_op_mfspr(DisasContext *ctx)
3797 {
3798 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3799 uint32_t sprn = SPR(ctx->opcode);
3800
3801 #if defined(CONFIG_USER_ONLY)
3802 read_cb = ctx->spr_cb[sprn].uea_read;
3803 #else
3804 if (ctx->pr) {
3805 read_cb = ctx->spr_cb[sprn].uea_read;
3806 } else if (ctx->hv) {
3807 read_cb = ctx->spr_cb[sprn].hea_read;
3808 } else {
3809 read_cb = ctx->spr_cb[sprn].oea_read;
3810 }
3811 #endif
3812 if (likely(read_cb != NULL)) {
3813 if (likely(read_cb != SPR_NOACCESS)) {
3814 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3815 } else {
3816 /* Privilege exception */
3817 /* This is a hack to avoid warnings when running Linux:
3818 * this OS breaks the PowerPC virtualisation model,
3819 * allowing userland application to read the PVR
3820 */
3821 if (sprn != SPR_PVR) {
3822 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3823 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3824 if (qemu_log_separate()) {
3825 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3826 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3827 }
3828 }
3829 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3830 }
3831 } else {
3832 /* ISA 2.07 defines these as no-ops */
3833 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3834 (sprn >= 808 && sprn <= 811)) {
3835 /* This is a nop */
3836 return;
3837 }
3838 /* Not defined */
3839 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3840 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3841 if (qemu_log_separate()) {
3842 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3843 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3844 }
3845
3846 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3847 * it can generate a priv, a hv emu or a no-op
3848 */
3849 if (sprn & 0x10) {
3850 if (ctx->pr) {
3851 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3852 }
3853 } else {
3854 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3855 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3856 }
3857 }
3858 }
3859 }
3860
3861 static void gen_mfspr(DisasContext *ctx)
3862 {
3863 gen_op_mfspr(ctx);
3864 }
3865
3866 /* mftb */
3867 static void gen_mftb(DisasContext *ctx)
3868 {
3869 gen_op_mfspr(ctx);
3870 }
3871
3872 /* mtcrf mtocrf*/
3873 static void gen_mtcrf(DisasContext *ctx)
3874 {
3875 uint32_t crm, crn;
3876
3877 crm = CRM(ctx->opcode);
3878 if (likely((ctx->opcode & 0x00100000))) {
3879 if (crm && ((crm & (crm - 1)) == 0)) {
3880 TCGv_i32 temp = tcg_temp_new_i32();
3881 crn = ctz32 (crm);
3882 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3883 tcg_gen_shri_i32(temp, temp, crn * 4);
3884 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3885 tcg_temp_free_i32(temp);
3886 }
3887 } else {
3888 TCGv_i32 temp = tcg_temp_new_i32();
3889 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3890 for (crn = 0 ; crn < 8 ; crn++) {
3891 if (crm & (1 << crn)) {
3892 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3893 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3894 }
3895 }
3896 tcg_temp_free_i32(temp);
3897 }
3898 }
3899
3900 /* mtmsr */
3901 #if defined(TARGET_PPC64)
3902 static void gen_mtmsrd(DisasContext *ctx)
3903 {
3904 CHK_SV;
3905
3906 #if !defined(CONFIG_USER_ONLY)
3907 if (ctx->opcode & 0x00010000) {
3908 /* Special form that does not need any synchronisation */
3909 TCGv t0 = tcg_temp_new();
3910 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3911 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3912 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3913 tcg_temp_free(t0);
3914 } else {
3915 /* XXX: we need to update nip before the store
3916 * if we enter power saving mode, we will exit the loop
3917 * directly from ppc_store_msr
3918 */
3919 gen_update_nip(ctx, ctx->nip);
3920 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3921 /* Must stop the translation as machine state (may have) changed */
3922 /* Note that mtmsr is not always defined as context-synchronizing */
3923 gen_stop_exception(ctx);
3924 }
3925 #endif /* !defined(CONFIG_USER_ONLY) */
3926 }
3927 #endif /* defined(TARGET_PPC64) */
3928
3929 static void gen_mtmsr(DisasContext *ctx)
3930 {
3931 CHK_SV;
3932
3933 #if !defined(CONFIG_USER_ONLY)
3934 if (ctx->opcode & 0x00010000) {
3935 /* Special form that does not need any synchronisation */
3936 TCGv t0 = tcg_temp_new();
3937 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3938 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3939 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3940 tcg_temp_free(t0);
3941 } else {
3942 TCGv msr = tcg_temp_new();
3943
3944 /* XXX: we need to update nip before the store
3945 * if we enter power saving mode, we will exit the loop
3946 * directly from ppc_store_msr
3947 */
3948 gen_update_nip(ctx, ctx->nip);
3949 #if defined(TARGET_PPC64)
3950 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3951 #else
3952 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3953 #endif
3954 gen_helper_store_msr(cpu_env, msr);
3955 tcg_temp_free(msr);
3956 /* Must stop the translation as machine state (may have) changed */
3957 /* Note that mtmsr is not always defined as context-synchronizing */
3958 gen_stop_exception(ctx);
3959 }
3960 #endif
3961 }
3962
3963 /* mtspr */
3964 static void gen_mtspr(DisasContext *ctx)
3965 {
3966 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
3967 uint32_t sprn = SPR(ctx->opcode);
3968
3969 #if defined(CONFIG_USER_ONLY)
3970 write_cb = ctx->spr_cb[sprn].uea_write;
3971 #else
3972 if (ctx->pr) {
3973 write_cb = ctx->spr_cb[sprn].uea_write;
3974 } else if (ctx->hv) {
3975 write_cb = ctx->spr_cb[sprn].hea_write;
3976 } else {
3977 write_cb = ctx->spr_cb[sprn].oea_write;
3978 }
3979 #endif
3980 if (likely(write_cb != NULL)) {
3981 if (likely(write_cb != SPR_NOACCESS)) {
3982 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3983 } else {
3984 /* Privilege exception */
3985 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
3986 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3987 if (qemu_log_separate()) {
3988 qemu_log("Trying to write privileged spr %d (0x%03x) at "
3989 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3990 }
3991 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3992 }
3993 } else {
3994 /* ISA 2.07 defines these as no-ops */
3995 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3996 (sprn >= 808 && sprn <= 811)) {
3997 /* This is a nop */
3998 return;
3999 }
4000
4001 /* Not defined */
4002 if (qemu_log_separate()) {
4003 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4004 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4005 }
4006 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4007 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4008
4009
4010 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4011 * it can generate a priv, a hv emu or a no-op
4012 */
4013 if (sprn & 0x10) {
4014 if (ctx->pr) {
4015 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4016 }
4017 } else {
4018 if (ctx->pr || sprn == 0) {
4019 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4020 }
4021 }
4022 }
4023 }
4024
4025 #if defined(TARGET_PPC64)
4026 /* setb */
4027 static void gen_setb(DisasContext *ctx)
4028 {
4029 TCGv_i32 t0 = tcg_temp_new_i32();
4030 TCGv_i32 t8 = tcg_temp_new_i32();
4031 TCGv_i32 tm1 = tcg_temp_new_i32();
4032 int crf = crfS(ctx->opcode);
4033
4034 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4035 tcg_gen_movi_i32(t8, 8);
4036 tcg_gen_movi_i32(tm1, -1);
4037 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4038 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4039
4040 tcg_temp_free_i32(t0);
4041 tcg_temp_free_i32(t8);
4042 tcg_temp_free_i32(tm1);
4043 }
4044 #endif
4045
4046 /*** Cache management ***/
4047
4048 /* dcbf */
4049 static void gen_dcbf(DisasContext *ctx)
4050 {
4051 /* XXX: specification says this is treated as a load by the MMU */
4052 TCGv t0;
4053 gen_set_access_type(ctx, ACCESS_CACHE);
4054 t0 = tcg_temp_new();
4055 gen_addr_reg_index(ctx, t0);
4056 gen_qemu_ld8u(ctx, t0, t0);
4057 tcg_temp_free(t0);
4058 }
4059
4060 /* dcbi (Supervisor only) */
4061 static void gen_dcbi(DisasContext *ctx)
4062 {
4063 #if defined(CONFIG_USER_ONLY)
4064 GEN_PRIV;
4065 #else
4066 TCGv EA, val;
4067
4068 CHK_SV;
4069 EA = tcg_temp_new();
4070 gen_set_access_type(ctx, ACCESS_CACHE);
4071 gen_addr_reg_index(ctx, EA);
4072 val = tcg_temp_new();
4073 /* XXX: specification says this should be treated as a store by the MMU */
4074 gen_qemu_ld8u(ctx, val, EA);
4075 gen_qemu_st8(ctx, val, EA);
4076 tcg_temp_free(val);
4077 tcg_temp_free(EA);
4078 #endif /* defined(CONFIG_USER_ONLY) */
4079 }
4080
4081 /* dcdst */
4082 static void gen_dcbst(DisasContext *ctx)
4083 {
4084 /* XXX: specification say this is treated as a load by the MMU */
4085 TCGv t0;
4086 gen_set_access_type(ctx, ACCESS_CACHE);
4087 t0 = tcg_temp_new();
4088 gen_addr_reg_index(ctx, t0);
4089 gen_qemu_ld8u(ctx, t0, t0);
4090 tcg_temp_free(t0);
4091 }
4092
4093 /* dcbt */
4094 static void gen_dcbt(DisasContext *ctx)
4095 {
4096 /* interpreted as no-op */
4097 /* XXX: specification say this is treated as a load by the MMU
4098 * but does not generate any exception
4099 */
4100 }
4101
4102 /* dcbtst */
4103 static void gen_dcbtst(DisasContext *ctx)
4104 {
4105 /* interpreted as no-op */
4106 /* XXX: specification say this is treated as a load by the MMU
4107 * but does not generate any exception
4108 */
4109 }
4110
4111 /* dcbtls */
4112 static void gen_dcbtls(DisasContext *ctx)
4113 {
4114 /* Always fails locking the cache */
4115 TCGv t0 = tcg_temp_new();
4116 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4117 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4118 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4119 tcg_temp_free(t0);
4120 }
4121
4122 /* dcbz */
4123 static void gen_dcbz(DisasContext *ctx)
4124 {
4125 TCGv tcgv_addr;
4126 TCGv_i32 tcgv_op;
4127
4128 gen_set_access_type(ctx, ACCESS_CACHE);
4129 tcgv_addr = tcg_temp_new();
4130 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4131 gen_addr_reg_index(ctx, tcgv_addr);
4132 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4133 tcg_temp_free(tcgv_addr);
4134 tcg_temp_free_i32(tcgv_op);
4135 }
4136
4137 /* dst / dstt */
4138 static void gen_dst(DisasContext *ctx)
4139 {
4140 if (rA(ctx->opcode) == 0) {
4141 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4142 } else {
4143 /* interpreted as no-op */
4144 }
4145 }
4146
4147 /* dstst /dststt */
4148 static void gen_dstst(DisasContext *ctx)
4149 {
4150 if (rA(ctx->opcode) == 0) {
4151 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4152 } else {
4153 /* interpreted as no-op */
4154 }
4155
4156 }
4157
4158 /* dss / dssall */
4159 static void gen_dss(DisasContext *ctx)
4160 {
4161 /* interpreted as no-op */
4162 }
4163
4164 /* icbi */
4165 static void gen_icbi(DisasContext *ctx)
4166 {
4167 TCGv t0;
4168 gen_set_access_type(ctx, ACCESS_CACHE);
4169 t0 = tcg_temp_new();
4170 gen_addr_reg_index(ctx, t0);
4171 gen_helper_icbi(cpu_env, t0);
4172 tcg_temp_free(t0);
4173 }
4174
4175 /* Optional: */
4176 /* dcba */
4177 static void gen_dcba(DisasContext *ctx)
4178 {
4179 /* interpreted as no-op */
4180 /* XXX: specification say this is treated as a store by the MMU
4181 * but does not generate any exception
4182 */
4183 }
4184
4185 /*** Segment register manipulation ***/
4186 /* Supervisor only: */
4187
4188 /* mfsr */
4189 static void gen_mfsr(DisasContext *ctx)
4190 {
4191 #if defined(CONFIG_USER_ONLY)
4192 GEN_PRIV;
4193 #else
4194 TCGv t0;
4195
4196 CHK_SV;
4197 t0 = tcg_const_tl(SR(ctx->opcode));
4198 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4199 tcg_temp_free(t0);
4200 #endif /* defined(CONFIG_USER_ONLY) */
4201 }
4202
4203 /* mfsrin */
4204 static void gen_mfsrin(DisasContext *ctx)
4205 {
4206 #if defined(CONFIG_USER_ONLY)
4207 GEN_PRIV;
4208 #else
4209 TCGv t0;
4210
4211 CHK_SV;
4212 t0 = tcg_temp_new();
4213 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4214 tcg_gen_andi_tl(t0, t0, 0xF);
4215 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4216 tcg_temp_free(t0);
4217 #endif /* defined(CONFIG_USER_ONLY) */
4218 }
4219
4220 /* mtsr */
4221 static void gen_mtsr(DisasContext *ctx)
4222 {
4223 #if defined(CONFIG_USER_ONLY)
4224 GEN_PRIV;
4225 #else
4226 TCGv t0;
4227
4228 CHK_SV;
4229 t0 = tcg_const_tl(SR(ctx->opcode));
4230 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4231 tcg_temp_free(t0);
4232 #endif /* defined(CONFIG_USER_ONLY) */
4233 }
4234
4235 /* mtsrin */
4236 static void gen_mtsrin(DisasContext *ctx)
4237 {
4238 #if defined(CONFIG_USER_ONLY)
4239 GEN_PRIV;
4240 #else
4241 TCGv t0;
4242 CHK_SV;
4243
4244 t0 = tcg_temp_new();
4245 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4246 tcg_gen_andi_tl(t0, t0, 0xF);
4247 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4248 tcg_temp_free(t0);
4249 #endif /* defined(CONFIG_USER_ONLY) */
4250 }
4251
4252 #if defined(TARGET_PPC64)
4253 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4254
4255 /* mfsr */
4256 static void gen_mfsr_64b(DisasContext *ctx)
4257 {
4258 #if defined(CONFIG_USER_ONLY)
4259 GEN_PRIV;
4260 #else
4261 TCGv t0;
4262
4263 CHK_SV;
4264 t0 = tcg_const_tl(SR(ctx->opcode));
4265 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4266 tcg_temp_free(t0);
4267 #endif /* defined(CONFIG_USER_ONLY) */
4268 }
4269
4270 /* mfsrin */
4271 static void gen_mfsrin_64b(DisasContext *ctx)
4272 {
4273 #if defined(CONFIG_USER_ONLY)
4274 GEN_PRIV;
4275 #else
4276 TCGv t0;
4277
4278 CHK_SV;
4279 t0 = tcg_temp_new();
4280 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4281 tcg_gen_andi_tl(t0, t0, 0xF);
4282 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4283 tcg_temp_free(t0);
4284 #endif /* defined(CONFIG_USER_ONLY) */
4285 }
4286
4287 /* mtsr */
4288 static void gen_mtsr_64b(DisasContext *ctx)
4289 {
4290 #if defined(CONFIG_USER_ONLY)
4291 GEN_PRIV;
4292 #else
4293 TCGv t0;
4294
4295 CHK_SV;
4296 t0 = tcg_const_tl(SR(ctx->opcode));
4297 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4298 tcg_temp_free(t0);
4299 #endif /* defined(CONFIG_USER_ONLY) */
4300 }
4301
4302 /* mtsrin */
4303 static void gen_mtsrin_64b(DisasContext *ctx)
4304 {
4305 #if defined(CONFIG_USER_ONLY)
4306 GEN_PRIV;
4307 #else
4308 TCGv t0;
4309
4310 CHK_SV;
4311 t0 = tcg_temp_new();
4312 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4313 tcg_gen_andi_tl(t0, t0, 0xF);
4314 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4315 tcg_temp_free(t0);
4316 #endif /* defined(CONFIG_USER_ONLY) */
4317 }
4318
4319 /* slbmte */
4320 static void gen_slbmte(DisasContext *ctx)
4321 {
4322 #if defined(CONFIG_USER_ONLY)
4323 GEN_PRIV;
4324 #else
4325 CHK_SV;
4326
4327 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4328 cpu_gpr[rS(ctx->opcode)]);
4329 #endif /* defined(CONFIG_USER_ONLY) */
4330 }
4331
4332 static void gen_slbmfee(DisasContext *ctx)
4333 {
4334 #if defined(CONFIG_USER_ONLY)
4335 GEN_PRIV;
4336 #else
4337 CHK_SV;
4338
4339 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4340 cpu_gpr[rB(ctx->opcode)]);
4341 #endif /* defined(CONFIG_USER_ONLY) */
4342 }
4343
4344 static void gen_slbmfev(DisasContext *ctx)
4345 {
4346 #if defined(CONFIG_USER_ONLY)
4347 GEN_PRIV;
4348 #else
4349 CHK_SV;
4350
4351 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4352 cpu_gpr[rB(ctx->opcode)]);
4353 #endif /* defined(CONFIG_USER_ONLY) */
4354 }
4355
4356 static void gen_slbfee_(DisasContext *ctx)
4357 {
4358 #if defined(CONFIG_USER_ONLY)
4359 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4360 #else
4361 TCGLabel *l1, *l2;
4362
4363 if (unlikely(ctx->pr)) {
4364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4365 return;
4366 }
4367 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4368 cpu_gpr[rB(ctx->opcode)]);
4369 l1 = gen_new_label();
4370 l2 = gen_new_label();
4371 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4372 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4373 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4374 tcg_gen_br(l2);
4375 gen_set_label(l1);
4376 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4377 gen_set_label(l2);
4378 #endif
4379 }
4380 #endif /* defined(TARGET_PPC64) */
4381
4382 /*** Lookaside buffer management ***/
4383 /* Optional & supervisor only: */
4384
4385 /* tlbia */
4386 static void gen_tlbia(DisasContext *ctx)
4387 {
4388 #if defined(CONFIG_USER_ONLY)
4389 GEN_PRIV;
4390 #else
4391 CHK_HV;
4392
4393 gen_helper_tlbia(cpu_env);
4394 #endif /* defined(CONFIG_USER_ONLY) */
4395 }
4396
4397 /* tlbiel */
4398 static void gen_tlbiel(DisasContext *ctx)
4399 {
4400 #if defined(CONFIG_USER_ONLY)
4401 GEN_PRIV;
4402 #else
4403 CHK_SV;
4404
4405 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4406 #endif /* defined(CONFIG_USER_ONLY) */
4407 }
4408
4409 /* tlbie */
4410 static void gen_tlbie(DisasContext *ctx)
4411 {
4412 #if defined(CONFIG_USER_ONLY)
4413 GEN_PRIV;
4414 #else
4415 CHK_HV;
4416
4417 if (NARROW_MODE(ctx)) {
4418 TCGv t0 = tcg_temp_new();
4419 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4420 gen_helper_tlbie(cpu_env, t0);
4421 tcg_temp_free(t0);
4422 } else {
4423 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4424 }
4425 #endif /* defined(CONFIG_USER_ONLY) */
4426 }
4427
4428 /* tlbsync */
4429 static void gen_tlbsync(DisasContext *ctx)
4430 {
4431 #if defined(CONFIG_USER_ONLY)
4432 GEN_PRIV;
4433 #else
4434 CHK_HV;
4435
4436 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4437 * embedded however needs to deal with tlbsync. We don't try to be
4438 * fancy and swallow the overhead of checking for both.
4439 */
4440 gen_check_tlb_flush(ctx);
4441 #endif /* defined(CONFIG_USER_ONLY) */
4442 }
4443
4444 #if defined(TARGET_PPC64)
4445 /* slbia */
4446 static void gen_slbia(DisasContext *ctx)
4447 {
4448 #if defined(CONFIG_USER_ONLY)
4449 GEN_PRIV;
4450 #else
4451 CHK_SV;
4452
4453 gen_helper_slbia(cpu_env);
4454 #endif /* defined(CONFIG_USER_ONLY) */
4455 }
4456
4457 /* slbie */
4458 static void gen_slbie(DisasContext *ctx)
4459 {
4460 #if defined(CONFIG_USER_ONLY)
4461 GEN_PRIV;
4462 #else
4463 CHK_SV;
4464
4465 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4466 #endif /* defined(CONFIG_USER_ONLY) */
4467 }
4468 #endif /* defined(TARGET_PPC64) */
4469
4470 /*** External control ***/
4471 /* Optional: */
4472
4473 /* eciwx */
4474 static void gen_eciwx(DisasContext *ctx)
4475 {
4476 TCGv t0;
4477 /* Should check EAR[E] ! */
4478 gen_set_access_type(ctx, ACCESS_EXT);
4479 t0 = tcg_temp_new();
4480 gen_addr_reg_index(ctx, t0);
4481 gen_check_align(ctx, t0, 0x03);
4482 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4483 tcg_temp_free(t0);
4484 }
4485
4486 /* ecowx */
4487 static void gen_ecowx(DisasContext *ctx)
4488 {
4489 TCGv t0;
4490 /* Should check EAR[E] ! */
4491 gen_set_access_type(ctx, ACCESS_EXT);
4492 t0 = tcg_temp_new();
4493 gen_addr_reg_index(ctx, t0);
4494 gen_check_align(ctx, t0, 0x03);
4495 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4496 tcg_temp_free(t0);
4497 }
4498
4499 /* PowerPC 601 specific instructions */
4500
4501 /* abs - abs. */
4502 static void gen_abs(DisasContext *ctx)
4503 {
4504 TCGLabel *l1 = gen_new_label();
4505 TCGLabel *l2 = gen_new_label();
4506 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4507 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4508 tcg_gen_br(l2);
4509 gen_set_label(l1);
4510 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4511 gen_set_label(l2);
4512 if (unlikely(Rc(ctx->opcode) != 0))
4513 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4514 }
4515
4516 /* abso - abso. */
4517 static void gen_abso(DisasContext *ctx)
4518 {
4519 TCGLabel *l1 = gen_new_label();
4520 TCGLabel *l2 = gen_new_label();
4521 TCGLabel *l3 = gen_new_label();
4522 /* Start with XER OV disabled, the most likely case */
4523 tcg_gen_movi_tl(cpu_ov, 0);
4524 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4525 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4526 tcg_gen_movi_tl(cpu_ov, 1);
4527 tcg_gen_movi_tl(cpu_so, 1);
4528 tcg_gen_br(l2);
4529 gen_set_label(l1);
4530 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4531 tcg_gen_br(l3);
4532 gen_set_label(l2);
4533 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4534 gen_set_label(l3);
4535 if (unlikely(Rc(ctx->opcode) != 0))
4536 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4537 }
4538
4539 /* clcs */
4540 static void gen_clcs(DisasContext *ctx)
4541 {
4542 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4543 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4544 tcg_temp_free_i32(t0);
4545 /* Rc=1 sets CR0 to an undefined state */
4546 }
4547
4548 /* div - div. */
4549 static void gen_div(DisasContext *ctx)
4550 {
4551 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4552 cpu_gpr[rB(ctx->opcode)]);
4553 if (unlikely(Rc(ctx->opcode) != 0))
4554 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4555 }
4556
4557 /* divo - divo. */
4558 static void gen_divo(DisasContext *ctx)
4559 {
4560 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4561 cpu_gpr[rB(ctx->opcode)]);
4562 if (unlikely(Rc(ctx->opcode) != 0))
4563 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4564 }
4565
4566 /* divs - divs. */
4567 static void gen_divs(DisasContext *ctx)
4568 {
4569 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4570 cpu_gpr[rB(ctx->opcode)]);
4571 if (unlikely(Rc(ctx->opcode) != 0))
4572 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4573 }
4574
4575 /* divso - divso. */
4576 static void gen_divso(DisasContext *ctx)
4577 {
4578 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4579 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4580 if (unlikely(Rc(ctx->opcode) != 0))
4581 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4582 }
4583
4584 /* doz - doz. */
4585 static void gen_doz(DisasContext *ctx)
4586 {
4587 TCGLabel *l1 = gen_new_label();
4588 TCGLabel *l2 = gen_new_label();
4589 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4590 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4591 tcg_gen_br(l2);
4592 gen_set_label(l1);
4593 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4594 gen_set_label(l2);
4595 if (unlikely(Rc(ctx->opcode) != 0))
4596 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4597 }
4598
4599 /* dozo - dozo. */
4600 static void gen_dozo(DisasContext *ctx)
4601 {
4602 TCGLabel *l1 = gen_new_label();
4603 TCGLabel *l2 = gen_new_label();
4604 TCGv t0 = tcg_temp_new();
4605 TCGv t1 = tcg_temp_new();
4606 TCGv t2 = tcg_temp_new();
4607 /* Start with XER OV disabled, the most likely case */
4608 tcg_gen_movi_tl(cpu_ov, 0);
4609 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4610 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4611 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4612 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4613 tcg_gen_andc_tl(t1, t1, t2);
4614 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4615 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4616 tcg_gen_movi_tl(cpu_ov, 1);
4617 tcg_gen_movi_tl(cpu_so, 1);
4618 tcg_gen_br(l2);
4619 gen_set_label(l1);
4620 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4621 gen_set_label(l2);
4622 tcg_temp_free(t0);
4623 tcg_temp_free(t1);
4624 tcg_temp_free(t2);
4625 if (unlikely(Rc(ctx->opcode) != 0))
4626 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4627 }
4628
4629 /* dozi */
4630 static void gen_dozi(DisasContext *ctx)
4631 {
4632 target_long simm = SIMM(ctx->opcode);
4633 TCGLabel *l1 = gen_new_label();
4634 TCGLabel *l2 = gen_new_label();
4635 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4636 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4637 tcg_gen_br(l2);
4638 gen_set_label(l1);
4639 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4640 gen_set_label(l2);
4641 if (unlikely(Rc(ctx->opcode) != 0))
4642 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4643 }
4644
4645 /* lscbx - lscbx. */
4646 static void gen_lscbx(DisasContext *ctx)
4647 {
4648 TCGv t0 = tcg_temp_new();
4649 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4650 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4651 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4652
4653 gen_addr_reg_index(ctx, t0);
4654 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4655 tcg_temp_free_i32(t1);
4656 tcg_temp_free_i32(t2);
4657 tcg_temp_free_i32(t3);
4658 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4659 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4660 if (unlikely(Rc(ctx->opcode) != 0))
4661 gen_set_Rc0(ctx, t0);
4662 tcg_temp_free(t0);
4663 }
4664
4665 /* maskg - maskg. */
4666 static void gen_maskg(DisasContext *ctx)
4667 {
4668 TCGLabel *l1 = gen_new_label();
4669 TCGv t0 = tcg_temp_new();
4670 TCGv t1 = tcg_temp_new();
4671 TCGv t2 = tcg_temp_new();
4672 TCGv t3 = tcg_temp_new();
4673 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4674 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4675 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4676 tcg_gen_addi_tl(t2, t0, 1);
4677 tcg_gen_shr_tl(t2, t3, t2);
4678 tcg_gen_shr_tl(t3, t3, t1);
4679 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4680 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4681 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4682 gen_set_label(l1);
4683 tcg_temp_free(t0);
4684 tcg_temp_free(t1);
4685 tcg_temp_free(t2);
4686 tcg_temp_free(t3);
4687 if (unlikely(Rc(ctx->opcode) != 0))
4688 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4689 }
4690
4691 /* maskir - maskir. */
4692 static void gen_maskir(DisasContext *ctx)
4693 {
4694 TCGv t0 = tcg_temp_new();
4695 TCGv t1 = tcg_temp_new();
4696 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4697 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4698 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4699 tcg_temp_free(t0);
4700 tcg_temp_free(t1);
4701 if (unlikely(Rc(ctx->opcode) != 0))
4702 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4703 }
4704
4705 /* mul - mul. */
4706 static void gen_mul(DisasContext *ctx)
4707 {
4708 TCGv_i64 t0 = tcg_temp_new_i64();
4709 TCGv_i64 t1 = tcg_temp_new_i64();
4710 TCGv t2 = tcg_temp_new();
4711 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4712 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4713 tcg_gen_mul_i64(t0, t0, t1);
4714 tcg_gen_trunc_i64_tl(t2, t0);
4715 gen_store_spr(SPR_MQ, t2);
4716 tcg_gen_shri_i64(t1, t0, 32);
4717 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4718 tcg_temp_free_i64(t0);
4719 tcg_temp_free_i64(t1);
4720 tcg_temp_free(t2);
4721 if (unlikely(Rc(ctx->opcode) != 0))
4722 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4723 }
4724
4725 /* mulo - mulo. */
4726 static void gen_mulo(DisasContext *ctx)
4727 {
4728 TCGLabel *l1 = gen_new_label();
4729 TCGv_i64 t0 = tcg_temp_new_i64();
4730 TCGv_i64 t1 = tcg_temp_new_i64();
4731 TCGv t2 = tcg_temp_new();
4732 /* Start with XER OV disabled, the most likely case */
4733 tcg_gen_movi_tl(cpu_ov, 0);
4734 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4735 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4736 tcg_gen_mul_i64(t0, t0, t1);
4737 tcg_gen_trunc_i64_tl(t2, t0);
4738 gen_store_spr(SPR_MQ, t2);
4739 tcg_gen_shri_i64(t1, t0, 32);
4740 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4741 tcg_gen_ext32s_i64(t1, t0);
4742 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4743 tcg_gen_movi_tl(cpu_ov, 1);
4744 tcg_gen_movi_tl(cpu_so, 1);
4745 gen_set_label(l1);
4746 tcg_temp_free_i64(t0);
4747 tcg_temp_free_i64(t1);
4748 tcg_temp_free(t2);
4749 if (unlikely(Rc(ctx->opcode) != 0))
4750 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4751 }
4752
4753 /* nabs - nabs. */
4754 static void gen_nabs(DisasContext *ctx)
4755 {
4756 TCGLabel *l1 = gen_new_label();
4757 TCGLabel *l2 = gen_new_label();
4758 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4759 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4760 tcg_gen_br(l2);
4761 gen_set_label(l1);
4762 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4763 gen_set_label(l2);
4764 if (unlikely(Rc(ctx->opcode) != 0))
4765 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4766 }
4767
4768 /* nabso - nabso. */
4769 static void gen_nabso(DisasContext *ctx)
4770 {
4771 TCGLabel *l1 = gen_new_label();
4772 TCGLabel *l2 = gen_new_label();
4773 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4774 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4775 tcg_gen_br(l2);
4776 gen_set_label(l1);
4777 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4778 gen_set_label(l2);
4779 /* nabs never overflows */
4780 tcg_gen_movi_tl(cpu_ov, 0);
4781 if (unlikely(Rc(ctx->opcode) != 0))
4782 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4783 }
4784
4785 /* rlmi - rlmi. */
4786 static void gen_rlmi(DisasContext *ctx)
4787 {
4788 uint32_t mb = MB(ctx->opcode);
4789 uint32_t me = ME(ctx->opcode);
4790 TCGv t0 = tcg_temp_new();
4791 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4792 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4793 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4794 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4795 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4796 tcg_temp_free(t0);
4797 if (unlikely(Rc(ctx->opcode) != 0))
4798 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4799 }
4800
4801 /* rrib - rrib. */
4802 static void gen_rrib(DisasContext *ctx)
4803 {
4804 TCGv t0 = tcg_temp_new();
4805 TCGv t1 = tcg_temp_new();
4806 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4807 tcg_gen_movi_tl(t1, 0x80000000);
4808 tcg_gen_shr_tl(t1, t1, t0);
4809 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4810 tcg_gen_and_tl(t0, t0, t1);
4811 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4812 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4813 tcg_temp_free(t0);
4814 tcg_temp_free(t1);
4815 if (unlikely(Rc(ctx->opcode) != 0))
4816 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4817 }
4818
4819 /* sle - sle. */
4820 static void gen_sle(DisasContext *ctx)
4821 {
4822 TCGv t0 = tcg_temp_new();
4823 TCGv t1 = tcg_temp_new();
4824 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4825 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4826 tcg_gen_subfi_tl(t1, 32, t1);
4827 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4828 tcg_gen_or_tl(t1, t0, t1);
4829 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4830 gen_store_spr(SPR_MQ, t1);
4831 tcg_temp_free(t0);
4832 tcg_temp_free(t1);
4833 if (unlikely(Rc(ctx->opcode) != 0))
4834 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4835 }
4836
4837 /* sleq - sleq. */
4838 static void gen_sleq(DisasContext *ctx)
4839 {
4840 TCGv t0 = tcg_temp_new();
4841 TCGv t1 = tcg_temp_new();
4842 TCGv t2 = tcg_temp_new();
4843 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4844 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4845 tcg_gen_shl_tl(t2, t2, t0);
4846 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4847 gen_load_spr(t1, SPR_MQ);
4848 gen_store_spr(SPR_MQ, t0);
4849 tcg_gen_and_tl(t0, t0, t2);
4850 tcg_gen_andc_tl(t1, t1, t2);
4851 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4852 tcg_temp_free(t0);
4853 tcg_temp_free(t1);
4854 tcg_temp_free(t2);
4855 if (unlikely(Rc(ctx->opcode) != 0))
4856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4857 }
4858
4859 /* sliq - sliq. */
4860 static void gen_sliq(DisasContext *ctx)
4861 {
4862 int sh = SH(ctx->opcode);
4863 TCGv t0 = tcg_temp_new();
4864 TCGv t1 = tcg_temp_new();
4865 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4866 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4867 tcg_gen_or_tl(t1, t0, t1);
4868 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4869 gen_store_spr(SPR_MQ, t1);
4870 tcg_temp_free(t0);
4871 tcg_temp_free(t1);
4872 if (unlikely(Rc(ctx->opcode) != 0))
4873 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4874 }
4875
4876 /* slliq - slliq. */
4877 static void gen_slliq(DisasContext *ctx)
4878 {
4879 int sh = SH(ctx->opcode);
4880 TCGv t0 = tcg_temp_new();
4881 TCGv t1 = tcg_temp_new();
4882 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4883 gen_load_spr(t1, SPR_MQ);
4884 gen_store_spr(SPR_MQ, t0);
4885 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4886 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4887 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4888 tcg_temp_free(t0);
4889 tcg_temp_free(t1);
4890 if (unlikely(Rc(ctx->opcode) != 0))
4891 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4892 }
4893
4894 /* sllq - sllq. */
4895 static void gen_sllq(DisasContext *ctx)
4896 {
4897 TCGLabel *l1 = gen_new_label();
4898 TCGLabel *l2 = gen_new_label();
4899 TCGv t0 = tcg_temp_local_new();
4900 TCGv t1 = tcg_temp_local_new();
4901 TCGv t2 = tcg_temp_local_new();
4902 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4903 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4904 tcg_gen_shl_tl(t1, t1, t2);
4905 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4906 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4907 gen_load_spr(t0, SPR_MQ);
4908 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4909 tcg_gen_br(l2);
4910 gen_set_label(l1);
4911 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4912 gen_load_spr(t2, SPR_MQ);
4913 tcg_gen_andc_tl(t1, t2, t1);
4914 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4915 gen_set_label(l2);
4916 tcg_temp_free(t0);
4917 tcg_temp_free(t1);
4918 tcg_temp_free(t2);
4919 if (unlikely(Rc(ctx->opcode) != 0))
4920 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4921 }
4922
4923 /* slq - slq. */
4924 static void gen_slq(DisasContext *ctx)
4925 {
4926 TCGLabel *l1 = gen_new_label();
4927 TCGv t0 = tcg_temp_new();
4928 TCGv t1 = tcg_temp_new();
4929 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4930 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4931 tcg_gen_subfi_tl(t1, 32, t1);
4932 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4933 tcg_gen_or_tl(t1, t0, t1);
4934 gen_store_spr(SPR_MQ, t1);
4935 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4936 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4937 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4938 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4939 gen_set_label(l1);
4940 tcg_temp_free(t0);
4941 tcg_temp_free(t1);
4942 if (unlikely(Rc(ctx->opcode) != 0))
4943 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4944 }
4945
4946 /* sraiq - sraiq. */
4947 static void gen_sraiq(DisasContext *ctx)
4948 {
4949 int sh = SH(ctx->opcode);
4950 TCGLabel *l1 = gen_new_label();
4951 TCGv t0 = tcg_temp_new();
4952 TCGv t1 = tcg_temp_new();
4953 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4954 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4955 tcg_gen_or_tl(t0, t0, t1);
4956 gen_store_spr(SPR_MQ, t0);
4957 tcg_gen_movi_tl(cpu_ca, 0);
4958 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4959 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4960 tcg_gen_movi_tl(cpu_ca, 1);
4961 gen_set_label(l1);
4962 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4963 tcg_temp_free(t0);
4964 tcg_temp_free(t1);
4965 if (unlikely(Rc(ctx->opcode) != 0))
4966 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4967 }
4968
4969 /* sraq - sraq. */
4970 static void gen_sraq(DisasContext *ctx)
4971 {
4972 TCGLabel *l1 = gen_new_label();
4973 TCGLabel *l2 = gen_new_label();
4974 TCGv t0 = tcg_temp_new();
4975 TCGv t1 = tcg_temp_local_new();
4976 TCGv t2 = tcg_temp_local_new();
4977 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4978 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4979 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4980 tcg_gen_subfi_tl(t2, 32, t2);
4981 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4982 tcg_gen_or_tl(t0, t0, t2);
4983 gen_store_spr(SPR_MQ, t0);
4984 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4985 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4986 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4987 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4988 gen_set_label(l1);
4989 tcg_temp_free(t0);
4990 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4991 tcg_gen_movi_tl(cpu_ca, 0);
4992 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4993 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4994 tcg_gen_movi_tl(cpu_ca, 1);
4995 gen_set_label(l2);
4996 tcg_temp_free(t1);
4997 tcg_temp_free(t2);
4998 if (unlikely(Rc(ctx->opcode) != 0))
4999 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5000 }
5001
5002 /* sre - sre. */
5003 static void gen_sre(DisasContext *ctx)
5004 {
5005 TCGv t0 = tcg_temp_new();
5006 TCGv t1 = tcg_temp_new();
5007 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5008 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5009 tcg_gen_subfi_tl(t1, 32, t1);
5010 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5011 tcg_gen_or_tl(t1, t0, t1);
5012 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5013 gen_store_spr(SPR_MQ, t1);
5014 tcg_temp_free(t0);
5015 tcg_temp_free(t1);
5016 if (unlikely(Rc(ctx->opcode) != 0))
5017 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5018 }
5019
5020 /* srea - srea. */
5021 static void gen_srea(DisasContext *ctx)
5022 {
5023 TCGv t0 = tcg_temp_new();
5024 TCGv t1 = tcg_temp_new();
5025 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5026 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5027 gen_store_spr(SPR_MQ, t0);
5028 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5029 tcg_temp_free(t0);
5030 tcg_temp_free(t1);
5031 if (unlikely(Rc(ctx->opcode) != 0))
5032 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5033 }
5034
5035 /* sreq */
5036 static void gen_sreq(DisasContext *ctx)
5037 {
5038 TCGv t0 = tcg_temp_new();
5039 TCGv t1 = tcg_temp_new();
5040 TCGv t2 = tcg_temp_new();
5041 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5042 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5043 tcg_gen_shr_tl(t1, t1, t0);
5044 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5045 gen_load_spr(t2, SPR_MQ);
5046 gen_store_spr(SPR_MQ, t0);
5047 tcg_gen_and_tl(t0, t0, t1);
5048 tcg_gen_andc_tl(t2, t2, t1);
5049 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5050 tcg_temp_free(t0);
5051 tcg_temp_free(t1);
5052 tcg_temp_free(t2);
5053 if (unlikely(Rc(ctx->opcode) != 0))
5054 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5055 }
5056
5057 /* sriq */
5058 static void gen_sriq(DisasContext *ctx)
5059 {
5060 int sh = SH(ctx->opcode);
5061 TCGv t0 = tcg_temp_new();
5062 TCGv t1 = tcg_temp_new();
5063 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5064 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5065 tcg_gen_or_tl(t1, t0, t1);
5066 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5067 gen_store_spr(SPR_MQ, t1);
5068 tcg_temp_free(t0);
5069 tcg_temp_free(t1);
5070 if (unlikely(Rc(ctx->opcode) != 0))
5071 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5072 }
5073
5074 /* srliq */
5075 static void gen_srliq(DisasContext *ctx)
5076 {
5077 int sh = SH(ctx->opcode);
5078 TCGv t0 = tcg_temp_new();
5079 TCGv t1 = tcg_temp_new();
5080 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5081 gen_load_spr(t1, SPR_MQ);
5082 gen_store_spr(SPR_MQ, t0);
5083 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5084 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5085 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5086 tcg_temp_free(t0);
5087 tcg_temp_free(t1);
5088 if (unlikely(Rc(ctx->opcode) != 0))
5089 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5090 }
5091
5092 /* srlq */
5093 static void gen_srlq(DisasContext *ctx)
5094 {
5095 TCGLabel *l1 = gen_new_label();
5096 TCGLabel *l2 = gen_new_label();
5097 TCGv t0 = tcg_temp_local_new();
5098 TCGv t1 = tcg_temp_local_new();
5099 TCGv t2 = tcg_temp_local_new();
5100 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5101 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5102 tcg_gen_shr_tl(t2, t1, t2);
5103 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5104 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5105 gen_load_spr(t0, SPR_MQ);
5106 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5107 tcg_gen_br(l2);
5108 gen_set_label(l1);
5109 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5110 tcg_gen_and_tl(t0, t0, t2);
5111 gen_load_spr(t1, SPR_MQ);
5112 tcg_gen_andc_tl(t1, t1, t2);
5113 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5114 gen_set_label(l2);
5115 tcg_temp_free(t0);
5116 tcg_temp_free(t1);
5117 tcg_temp_free(t2);
5118 if (unlikely(Rc(ctx->opcode) != 0))
5119 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5120 }
5121
5122 /* srq */
5123 static void gen_srq(DisasContext *ctx)
5124 {
5125 TCGLabel *l1 = gen_new_label();
5126 TCGv t0 = tcg_temp_new();
5127 TCGv t1 = tcg_temp_new();
5128 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5129 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5130 tcg_gen_subfi_tl(t1, 32, t1);
5131 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5132 tcg_gen_or_tl(t1, t0, t1);
5133 gen_store_spr(SPR_MQ, t1);
5134 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5135 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5136 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5137 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5138 gen_set_label(l1);
5139 tcg_temp_free(t0);
5140 tcg_temp_free(t1);
5141 if (unlikely(Rc(ctx->opcode) != 0))
5142 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5143 }
5144
5145 /* PowerPC 602 specific instructions */
5146
5147 /* dsa */
5148 static void gen_dsa(DisasContext *ctx)
5149 {
5150 /* XXX: TODO */
5151 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5152 }
5153
5154 /* esa */
5155 static void gen_esa(DisasContext *ctx)
5156 {
5157 /* XXX: TODO */
5158 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5159 }
5160
5161 /* mfrom */
5162 static void gen_mfrom(DisasContext *ctx)
5163 {
5164 #if defined(CONFIG_USER_ONLY)
5165 GEN_PRIV;
5166 #else
5167 CHK_SV;
5168 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5169 #endif /* defined(CONFIG_USER_ONLY) */
5170 }
5171
5172 /* 602 - 603 - G2 TLB management */
5173
5174 /* tlbld */
5175 static void gen_tlbld_6xx(DisasContext *ctx)
5176 {
5177 #if defined(CONFIG_USER_ONLY)
5178 GEN_PRIV;
5179 #else
5180 CHK_SV;
5181 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5182 #endif /* defined(CONFIG_USER_ONLY) */
5183 }
5184
5185 /* tlbli */
5186 static void gen_tlbli_6xx(DisasContext *ctx)
5187 {
5188 #if defined(CONFIG_USER_ONLY)
5189 GEN_PRIV;
5190 #else
5191 CHK_SV;
5192 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5193 #endif /* defined(CONFIG_USER_ONLY) */
5194 }
5195
5196 /* 74xx TLB management */
5197
5198 /* tlbld */
5199 static void gen_tlbld_74xx(DisasContext *ctx)
5200 {
5201 #if defined(CONFIG_USER_ONLY)
5202 GEN_PRIV;
5203 #else
5204 CHK_SV;
5205 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5206 #endif /* defined(CONFIG_USER_ONLY) */
5207 }
5208
5209 /* tlbli */
5210 static void gen_tlbli_74xx(DisasContext *ctx)
5211 {
5212 #if defined(CONFIG_USER_ONLY)
5213 GEN_PRIV;
5214 #else
5215 CHK_SV;
5216 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5217 #endif /* defined(CONFIG_USER_ONLY) */
5218 }
5219
5220 /* POWER instructions not in PowerPC 601 */
5221
5222 /* clf */
5223 static void gen_clf(DisasContext *ctx)
5224 {
5225 /* Cache line flush: implemented as no-op */
5226 }
5227
5228 /* cli */
5229 static void gen_cli(DisasContext *ctx)
5230 {
5231 #if defined(CONFIG_USER_ONLY)
5232 GEN_PRIV;
5233 #else
5234 /* Cache line invalidate: privileged and treated as no-op */
5235 CHK_SV;
5236 #endif /* defined(CONFIG_USER_ONLY) */
5237 }
5238
5239 /* dclst */
5240 static void gen_dclst(DisasContext *ctx)
5241 {
5242 /* Data cache line store: treated as no-op */
5243 }
5244
5245 static void gen_mfsri(DisasContext *ctx)
5246 {
5247 #if defined(CONFIG_USER_ONLY)
5248 GEN_PRIV;
5249 #else
5250 int ra = rA(ctx->opcode);
5251 int rd = rD(ctx->opcode);
5252 TCGv t0;
5253
5254 CHK_SV;
5255 t0 = tcg_temp_new();
5256 gen_addr_reg_index(ctx, t0);
5257 tcg_gen_shri_tl(t0, t0, 28);
5258 tcg_gen_andi_tl(t0, t0, 0xF);
5259 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5260 tcg_temp_free(t0);
5261 if (ra != 0 && ra != rd)
5262 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5263 #endif /* defined(CONFIG_USER_ONLY) */
5264 }
5265
5266 static void gen_rac(DisasContext *ctx)
5267 {
5268 #if defined(CONFIG_USER_ONLY)
5269 GEN_PRIV;
5270 #else
5271 TCGv t0;
5272
5273 CHK_SV;
5274 t0 = tcg_temp_new();
5275 gen_addr_reg_index(ctx, t0);
5276 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5277 tcg_temp_free(t0);
5278 #endif /* defined(CONFIG_USER_ONLY) */
5279 }
5280
5281 static void gen_rfsvc(DisasContext *ctx)
5282 {
5283 #if defined(CONFIG_USER_ONLY)
5284 GEN_PRIV;
5285 #else
5286 CHK_SV;
5287
5288 gen_helper_rfsvc(cpu_env);
5289 gen_sync_exception(ctx);
5290 #endif /* defined(CONFIG_USER_ONLY) */
5291 }
5292
5293 #include "translate/fp-impl.c"
5294
5295 #include "translate/vmx-impl.c"
5296
5297 #include "translate/vsx-impl.c"
5298
5299 /* svc is not implemented for now */
5300
5301 /* BookE specific instructions */
5302
5303 /* XXX: not implemented on 440 ? */
5304 static void gen_mfapidi(DisasContext *ctx)
5305 {
5306 /* XXX: TODO */
5307 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5308 }
5309
5310 /* XXX: not implemented on 440 ? */
5311 static void gen_tlbiva(DisasContext *ctx)
5312 {
5313 #if defined(CONFIG_USER_ONLY)
5314 GEN_PRIV;
5315 #else
5316 TCGv t0;
5317
5318 CHK_SV;
5319 t0 = tcg_temp_new();
5320 gen_addr_reg_index(ctx, t0);
5321 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5322 tcg_temp_free(t0);
5323 #endif /* defined(CONFIG_USER_ONLY) */
5324 }
5325
5326 /* All 405 MAC instructions are translated here */
5327 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5328 int ra, int rb, int rt, int Rc)
5329 {
5330 TCGv t0, t1;
5331
5332 t0 = tcg_temp_local_new();
5333 t1 = tcg_temp_local_new();
5334
5335 switch (opc3 & 0x0D) {
5336 case 0x05:
5337 /* macchw - macchw. - macchwo - macchwo. */
5338 /* macchws - macchws. - macchwso - macchwso. */
5339 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5340 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5341 /* mulchw - mulchw. */
5342 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5343 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5344 tcg_gen_ext16s_tl(t1, t1);
5345 break;
5346 case 0x04:
5347 /* macchwu - macchwu. - macchwuo - macchwuo. */
5348 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5349 /* mulchwu - mulchwu. */
5350 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5351 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5352 tcg_gen_ext16u_tl(t1, t1);
5353 break;
5354 case 0x01:
5355 /* machhw - machhw. - machhwo - machhwo. */
5356 /* machhws - machhws. - machhwso - machhwso. */
5357 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5358 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5359 /* mulhhw - mulhhw. */
5360 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5361 tcg_gen_ext16s_tl(t0, t0);
5362 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5363 tcg_gen_ext16s_tl(t1, t1);
5364 break;
5365 case 0x00:
5366 /* machhwu - machhwu. - machhwuo - machhwuo. */
5367 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5368 /* mulhhwu - mulhhwu. */
5369 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5370 tcg_gen_ext16u_tl(t0, t0);
5371 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5372 tcg_gen_ext16u_tl(t1, t1);
5373 break;
5374 case 0x0D:
5375 /* maclhw - maclhw. - maclhwo - maclhwo. */
5376 /* maclhws - maclhws. - maclhwso - maclhwso. */
5377 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5378 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5379 /* mullhw - mullhw. */
5380 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5381 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5382 break;
5383 case 0x0C:
5384 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5385 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5386 /* mullhwu - mullhwu. */
5387 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5388 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5389 break;
5390 }
5391 if (opc2 & 0x04) {
5392 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5393 tcg_gen_mul_tl(t1, t0, t1);
5394 if (opc2 & 0x02) {
5395 /* nmultiply-and-accumulate (0x0E) */
5396 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5397 } else {
5398 /* multiply-and-accumulate (0x0C) */
5399 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5400 }
5401
5402 if (opc3 & 0x12) {
5403 /* Check overflow and/or saturate */
5404 TCGLabel *l1 = gen_new_label();
5405
5406 if (opc3 & 0x10) {
5407 /* Start with XER OV disabled, the most likely case */
5408 tcg_gen_movi_tl(cpu_ov, 0);
5409 }
5410 if (opc3 & 0x01) {
5411 /* Signed */
5412 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5413 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5414 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5415 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5416 if (opc3 & 0x02) {
5417 /* Saturate */
5418 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5419 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5420 }
5421 } else {
5422 /* Unsigned */
5423 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5424 if (opc3 & 0x02) {
5425 /* Saturate */
5426 tcg_gen_movi_tl(t0, UINT32_MAX);
5427 }
5428 }
5429 if (opc3 & 0x10) {
5430 /* Check overflow */
5431 tcg_gen_movi_tl(cpu_ov, 1);
5432 tcg_gen_movi_tl(cpu_so, 1);
5433 }
5434 gen_set_label(l1);
5435 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5436 }
5437 } else {
5438 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5439 }
5440 tcg_temp_free(t0);
5441 tcg_temp_free(t1);
5442 if (unlikely(Rc) != 0) {
5443 /* Update Rc0 */
5444 gen_set_Rc0(ctx, cpu_gpr[rt]);
5445 }
5446 }
5447
5448 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5449 static void glue(gen_, name)(DisasContext *ctx) \
5450 { \
5451 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5452 rD(ctx->opcode), Rc(ctx->opcode)); \
5453 }
5454
5455 /* macchw - macchw. */
5456 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5457 /* macchwo - macchwo. */
5458 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5459 /* macchws - macchws. */
5460 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5461 /* macchwso - macchwso. */
5462 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5463 /* macchwsu - macchwsu. */
5464 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5465 /* macchwsuo - macchwsuo. */
5466 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5467 /* macchwu - macchwu. */
5468 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5469 /* macchwuo - macchwuo. */
5470 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5471 /* machhw - machhw. */
5472 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5473 /* machhwo - machhwo. */
5474 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5475 /* machhws - machhws. */
5476 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5477 /* machhwso - machhwso. */
5478 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5479 /* machhwsu - machhwsu. */
5480 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5481 /* machhwsuo - machhwsuo. */
5482 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5483 /* machhwu - machhwu. */
5484 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5485 /* machhwuo - machhwuo. */
5486 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5487 /* maclhw - maclhw. */
5488 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5489 /* maclhwo - maclhwo. */
5490 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5491 /* maclhws - maclhws. */
5492 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5493 /* maclhwso - maclhwso. */
5494 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5495 /* maclhwu - maclhwu. */
5496 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5497 /* maclhwuo - maclhwuo. */
5498 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5499 /* maclhwsu - maclhwsu. */
5500 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5501 /* maclhwsuo - maclhwsuo. */
5502 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5503 /* nmacchw - nmacchw. */
5504 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5505 /* nmacchwo - nmacchwo. */
5506 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5507 /* nmacchws - nmacchws. */
5508 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5509 /* nmacchwso - nmacchwso. */
5510 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5511 /* nmachhw - nmachhw. */
5512 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5513 /* nmachhwo - nmachhwo. */
5514 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5515 /* nmachhws - nmachhws. */
5516 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5517 /* nmachhwso - nmachhwso. */
5518 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5519 /* nmaclhw - nmaclhw. */
5520 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5521 /* nmaclhwo - nmaclhwo. */
5522 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5523 /* nmaclhws - nmaclhws. */
5524 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5525 /* nmaclhwso - nmaclhwso. */
5526 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5527
5528 /* mulchw - mulchw. */
5529 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5530 /* mulchwu - mulchwu. */
5531 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5532 /* mulhhw - mulhhw. */
5533 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5534 /* mulhhwu - mulhhwu. */
5535 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5536 /* mullhw - mullhw. */
5537 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5538 /* mullhwu - mullhwu. */
5539 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5540
5541 /* mfdcr */
5542 static void gen_mfdcr(DisasContext *ctx)
5543 {
5544 #if defined(CONFIG_USER_ONLY)
5545 GEN_PRIV;
5546 #else
5547 TCGv dcrn;
5548
5549 CHK_SV;
5550 dcrn = tcg_const_tl(SPR(ctx->opcode));
5551 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5552 tcg_temp_free(dcrn);
5553 #endif /* defined(CONFIG_USER_ONLY) */
5554 }
5555
5556 /* mtdcr */
5557 static void gen_mtdcr(DisasContext *ctx)
5558 {
5559 #if defined(CONFIG_USER_ONLY)
5560 GEN_PRIV;
5561 #else
5562 TCGv dcrn;
5563
5564 CHK_SV;
5565 dcrn = tcg_const_tl(SPR(ctx->opcode));
5566 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5567 tcg_temp_free(dcrn);
5568 #endif /* defined(CONFIG_USER_ONLY) */
5569 }
5570
5571 /* mfdcrx */
5572 /* XXX: not implemented on 440 ? */
5573 static void gen_mfdcrx(DisasContext *ctx)
5574 {
5575 #if defined(CONFIG_USER_ONLY)
5576 GEN_PRIV;
5577 #else
5578 CHK_SV;
5579 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5580 cpu_gpr[rA(ctx->opcode)]);
5581 /* Note: Rc update flag set leads to undefined state of Rc0 */
5582 #endif /* defined(CONFIG_USER_ONLY) */
5583 }
5584
5585 /* mtdcrx */
5586 /* XXX: not implemented on 440 ? */
5587 static void gen_mtdcrx(DisasContext *ctx)
5588 {
5589 #if defined(CONFIG_USER_ONLY)
5590 GEN_PRIV;
5591 #else
5592 CHK_SV;
5593 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5594 cpu_gpr[rS(ctx->opcode)]);
5595 /* Note: Rc update flag set leads to undefined state of Rc0 */
5596 #endif /* defined(CONFIG_USER_ONLY) */
5597 }
5598
5599 /* mfdcrux (PPC 460) : user-mode access to DCR */
5600 static void gen_mfdcrux(DisasContext *ctx)
5601 {
5602 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5603 cpu_gpr[rA(ctx->opcode)]);
5604 /* Note: Rc update flag set leads to undefined state of Rc0 */
5605 }
5606
5607 /* mtdcrux (PPC 460) : user-mode access to DCR */
5608 static void gen_mtdcrux(DisasContext *ctx)
5609 {
5610 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5611 cpu_gpr[rS(ctx->opcode)]);
5612 /* Note: Rc update flag set leads to undefined state of Rc0 */
5613 }
5614
5615 /* dccci */
5616 static void gen_dccci(DisasContext *ctx)
5617 {
5618 CHK_SV;
5619 /* interpreted as no-op */
5620 }
5621
5622 /* dcread */
5623 static void gen_dcread(DisasContext *ctx)
5624 {
5625 #if defined(CONFIG_USER_ONLY)
5626 GEN_PRIV;
5627 #else
5628 TCGv EA, val;
5629
5630 CHK_SV;
5631 gen_set_access_type(ctx, ACCESS_CACHE);
5632 EA = tcg_temp_new();
5633 gen_addr_reg_index(ctx, EA);
5634 val = tcg_temp_new();
5635 gen_qemu_ld32u(ctx, val, EA);
5636 tcg_temp_free(val);
5637 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5638 tcg_temp_free(EA);
5639 #endif /* defined(CONFIG_USER_ONLY) */
5640 }
5641
5642 /* icbt */
5643 static void gen_icbt_40x(DisasContext *ctx)
5644 {
5645 /* interpreted as no-op */
5646 /* XXX: specification say this is treated as a load by the MMU
5647 * but does not generate any exception
5648 */
5649 }
5650
5651 /* iccci */
5652 static void gen_iccci(DisasContext *ctx)
5653 {
5654 CHK_SV;
5655 /* interpreted as no-op */
5656 }
5657
5658 /* icread */
5659 static void gen_icread(DisasContext *ctx)
5660 {
5661 CHK_SV;
5662 /* interpreted as no-op */
5663 }
5664
5665 /* rfci (supervisor only) */
5666 static void gen_rfci_40x(DisasContext *ctx)
5667 {
5668 #if defined(CONFIG_USER_ONLY)
5669 GEN_PRIV;
5670 #else
5671 CHK_SV;
5672 /* Restore CPU state */
5673 gen_helper_40x_rfci(cpu_env);
5674 gen_sync_exception(ctx);
5675 #endif /* defined(CONFIG_USER_ONLY) */
5676 }
5677
5678 static void gen_rfci(DisasContext *ctx)
5679 {
5680 #if defined(CONFIG_USER_ONLY)
5681 GEN_PRIV;
5682 #else
5683 CHK_SV;
5684 /* Restore CPU state */
5685 gen_helper_rfci(cpu_env);
5686 gen_sync_exception(ctx);
5687 #endif /* defined(CONFIG_USER_ONLY) */
5688 }
5689
5690 /* BookE specific */
5691
5692 /* XXX: not implemented on 440 ? */
5693 static void gen_rfdi(DisasContext *ctx)
5694 {
5695 #if defined(CONFIG_USER_ONLY)
5696 GEN_PRIV;
5697 #else
5698 CHK_SV;
5699 /* Restore CPU state */
5700 gen_helper_rfdi(cpu_env);
5701 gen_sync_exception(ctx);
5702 #endif /* defined(CONFIG_USER_ONLY) */
5703 }
5704
5705 /* XXX: not implemented on 440 ? */
5706 static void gen_rfmci(DisasContext *ctx)
5707 {
5708 #if defined(CONFIG_USER_ONLY)
5709 GEN_PRIV;
5710 #else
5711 CHK_SV;
5712 /* Restore CPU state */
5713 gen_helper_rfmci(cpu_env);
5714 gen_sync_exception(ctx);
5715 #endif /* defined(CONFIG_USER_ONLY) */
5716 }
5717
5718 /* TLB management - PowerPC 405 implementation */
5719
5720 /* tlbre */
5721 static void gen_tlbre_40x(DisasContext *ctx)
5722 {
5723 #if defined(CONFIG_USER_ONLY)
5724 GEN_PRIV;
5725 #else
5726 CHK_SV;
5727 switch (rB(ctx->opcode)) {
5728 case 0:
5729 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5730 cpu_gpr[rA(ctx->opcode)]);
5731 break;
5732 case 1:
5733 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5734 cpu_gpr[rA(ctx->opcode)]);
5735 break;
5736 default:
5737 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5738 break;
5739 }
5740 #endif /* defined(CONFIG_USER_ONLY) */
5741 }
5742
5743 /* tlbsx - tlbsx. */
5744 static void gen_tlbsx_40x(DisasContext *ctx)
5745 {
5746 #if defined(CONFIG_USER_ONLY)
5747 GEN_PRIV;
5748 #else
5749 TCGv t0;
5750
5751 CHK_SV;
5752 t0 = tcg_temp_new();
5753 gen_addr_reg_index(ctx, t0);
5754 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5755 tcg_temp_free(t0);
5756 if (Rc(ctx->opcode)) {
5757 TCGLabel *l1 = gen_new_label();
5758 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5759 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5760 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5761 gen_set_label(l1);
5762 }
5763 #endif /* defined(CONFIG_USER_ONLY) */
5764 }
5765
5766 /* tlbwe */
5767 static void gen_tlbwe_40x(DisasContext *ctx)
5768 {
5769 #if defined(CONFIG_USER_ONLY)
5770 GEN_PRIV;
5771 #else
5772 CHK_SV;
5773
5774 switch (rB(ctx->opcode)) {
5775 case 0:
5776 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5777 cpu_gpr[rS(ctx->opcode)]);
5778 break;
5779 case 1:
5780 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5781 cpu_gpr[rS(ctx->opcode)]);
5782 break;
5783 default:
5784 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5785 break;
5786 }
5787 #endif /* defined(CONFIG_USER_ONLY) */
5788 }
5789
5790 /* TLB management - PowerPC 440 implementation */
5791
5792 /* tlbre */
5793 static void gen_tlbre_440(DisasContext *ctx)
5794 {
5795 #if defined(CONFIG_USER_ONLY)
5796 GEN_PRIV;
5797 #else
5798 CHK_SV;
5799
5800 switch (rB(ctx->opcode)) {
5801 case 0:
5802 case 1:
5803 case 2:
5804 {
5805 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5806 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5807 t0, cpu_gpr[rA(ctx->opcode)]);
5808 tcg_temp_free_i32(t0);
5809 }
5810 break;
5811 default:
5812 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5813 break;
5814 }
5815 #endif /* defined(CONFIG_USER_ONLY) */
5816 }
5817
5818 /* tlbsx - tlbsx. */
5819 static void gen_tlbsx_440(DisasContext *ctx)
5820 {
5821 #if defined(CONFIG_USER_ONLY)
5822 GEN_PRIV;
5823 #else
5824 TCGv t0;
5825
5826 CHK_SV;
5827 t0 = tcg_temp_new();
5828 gen_addr_reg_index(ctx, t0);
5829 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5830 tcg_temp_free(t0);
5831 if (Rc(ctx->opcode)) {
5832 TCGLabel *l1 = gen_new_label();
5833 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5834 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5835 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5836 gen_set_label(l1);
5837 }
5838 #endif /* defined(CONFIG_USER_ONLY) */
5839 }
5840
5841 /* tlbwe */
5842 static void gen_tlbwe_440(DisasContext *ctx)
5843 {
5844 #if defined(CONFIG_USER_ONLY)
5845 GEN_PRIV;
5846 #else
5847 CHK_SV;
5848 switch (rB(ctx->opcode)) {
5849 case 0:
5850 case 1:
5851 case 2:
5852 {
5853 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5854 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5855 cpu_gpr[rS(ctx->opcode)]);
5856 tcg_temp_free_i32(t0);
5857 }
5858 break;
5859 default:
5860 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5861 break;
5862 }
5863 #endif /* defined(CONFIG_USER_ONLY) */
5864 }
5865
5866 /* TLB management - PowerPC BookE 2.06 implementation */
5867
5868 /* tlbre */
5869 static void gen_tlbre_booke206(DisasContext *ctx)
5870 {
5871 #if defined(CONFIG_USER_ONLY)
5872 GEN_PRIV;
5873 #else
5874 CHK_SV;
5875 gen_helper_booke206_tlbre(cpu_env);
5876 #endif /* defined(CONFIG_USER_ONLY) */
5877 }
5878
5879 /* tlbsx - tlbsx. */
5880 static void gen_tlbsx_booke206(DisasContext *ctx)
5881 {
5882 #if defined(CONFIG_USER_ONLY)
5883 GEN_PRIV;
5884 #else
5885 TCGv t0;
5886
5887 CHK_SV;
5888 if (rA(ctx->opcode)) {
5889 t0 = tcg_temp_new();
5890 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
5891 } else {
5892 t0 = tcg_const_tl(0);
5893 }
5894
5895 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
5896 gen_helper_booke206_tlbsx(cpu_env, t0);
5897 tcg_temp_free(t0);
5898 #endif /* defined(CONFIG_USER_ONLY) */
5899 }
5900
5901 /* tlbwe */
5902 static void gen_tlbwe_booke206(DisasContext *ctx)
5903 {
5904 #if defined(CONFIG_USER_ONLY)
5905 GEN_PRIV;
5906 #else
5907 CHK_SV;
5908 gen_helper_booke206_tlbwe(cpu_env);
5909 #endif /* defined(CONFIG_USER_ONLY) */
5910 }
5911
5912 static void gen_tlbivax_booke206(DisasContext *ctx)
5913 {
5914 #if defined(CONFIG_USER_ONLY)
5915 GEN_PRIV;
5916 #else
5917 TCGv t0;
5918
5919 CHK_SV;
5920 t0 = tcg_temp_new();
5921 gen_addr_reg_index(ctx, t0);
5922 gen_helper_booke206_tlbivax(cpu_env, t0);
5923 tcg_temp_free(t0);
5924 #endif /* defined(CONFIG_USER_ONLY) */
5925 }
5926
5927 static void gen_tlbilx_booke206(DisasContext *ctx)
5928 {
5929 #if defined(CONFIG_USER_ONLY)
5930 GEN_PRIV;
5931 #else
5932 TCGv t0;
5933
5934 CHK_SV;
5935 t0 = tcg_temp_new();
5936 gen_addr_reg_index(ctx, t0);
5937
5938 switch((ctx->opcode >> 21) & 0x3) {
5939 case 0:
5940 gen_helper_booke206_tlbilx0(cpu_env, t0);
5941 break;
5942 case 1:
5943 gen_helper_booke206_tlbilx1(cpu_env, t0);
5944 break;
5945 case 3:
5946 gen_helper_booke206_tlbilx3(cpu_env, t0);
5947 break;
5948 default:
5949 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5950 break;
5951 }
5952
5953 tcg_temp_free(t0);
5954 #endif /* defined(CONFIG_USER_ONLY) */
5955 }
5956
5957
5958 /* wrtee */
5959 static void gen_wrtee(DisasContext *ctx)
5960 {
5961 #if defined(CONFIG_USER_ONLY)
5962 GEN_PRIV;
5963 #else
5964 TCGv t0;
5965
5966 CHK_SV;
5967 t0 = tcg_temp_new();
5968 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
5969 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5970 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
5971 tcg_temp_free(t0);
5972 /* Stop translation to have a chance to raise an exception
5973 * if we just set msr_ee to 1
5974 */
5975 gen_stop_exception(ctx);
5976 #endif /* defined(CONFIG_USER_ONLY) */
5977 }
5978
5979 /* wrteei */
5980 static void gen_wrteei(DisasContext *ctx)
5981 {
5982 #if defined(CONFIG_USER_ONLY)
5983 GEN_PRIV;
5984 #else
5985 CHK_SV;
5986 if (ctx->opcode & 0x00008000) {
5987 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
5988 /* Stop translation to have a chance to raise an exception */
5989 gen_stop_exception(ctx);
5990 } else {
5991 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5992 }
5993 #endif /* defined(CONFIG_USER_ONLY) */
5994 }
5995
5996 /* PowerPC 440 specific instructions */
5997
5998 /* dlmzb */
5999 static void gen_dlmzb(DisasContext *ctx)
6000 {
6001 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6002 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6003 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6004 tcg_temp_free_i32(t0);
6005 }
6006
6007 /* mbar replaces eieio on 440 */
6008 static void gen_mbar(DisasContext *ctx)
6009 {
6010 /* interpreted as no-op */
6011 }
6012
6013 /* msync replaces sync on 440 */
6014 static void gen_msync_4xx(DisasContext *ctx)
6015 {
6016 /* interpreted as no-op */
6017 }
6018
6019 /* icbt */
6020 static void gen_icbt_440(DisasContext *ctx)
6021 {
6022 /* interpreted as no-op */
6023 /* XXX: specification say this is treated as a load by the MMU
6024 * but does not generate any exception
6025 */
6026 }
6027
6028 /* Embedded.Processor Control */
6029
6030 static void gen_msgclr(DisasContext *ctx)
6031 {
6032 #if defined(CONFIG_USER_ONLY)
6033 GEN_PRIV;
6034 #else
6035 CHK_SV;
6036 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6037 #endif /* defined(CONFIG_USER_ONLY) */
6038 }
6039
6040 static void gen_msgsnd(DisasContext *ctx)
6041 {
6042 #if defined(CONFIG_USER_ONLY)
6043 GEN_PRIV;
6044 #else
6045 CHK_SV;
6046 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6047 #endif /* defined(CONFIG_USER_ONLY) */
6048 }
6049
6050
6051 #if defined(TARGET_PPC64)
6052 static void gen_maddld(DisasContext *ctx)
6053 {
6054 TCGv_i64 t1 = tcg_temp_new_i64();
6055
6056 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6057 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6058 tcg_temp_free_i64(t1);
6059 }
6060
6061 /* maddhd maddhdu */
6062 static void gen_maddhd_maddhdu(DisasContext *ctx)
6063 {
6064 TCGv_i64 lo = tcg_temp_new_i64();
6065 TCGv_i64 hi = tcg_temp_new_i64();
6066 TCGv_i64 t1 = tcg_temp_new_i64();
6067
6068 if (Rc(ctx->opcode)) {
6069 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6070 cpu_gpr[rB(ctx->opcode)]);
6071 tcg_gen_movi_i64(t1, 0);
6072 } else {
6073 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6074 cpu_gpr[rB(ctx->opcode)]);
6075 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6076 }
6077 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6078 cpu_gpr[rC(ctx->opcode)], t1);
6079 tcg_temp_free_i64(lo);
6080 tcg_temp_free_i64(hi);
6081 tcg_temp_free_i64(t1);
6082 }
6083 #endif /* defined(TARGET_PPC64) */
6084
6085 #include "translate/dfp-impl.c"
6086
6087 #include "translate/spe-impl.c"
6088
6089 static void gen_tbegin(DisasContext *ctx)
6090 {
6091 if (unlikely(!ctx->tm_enabled)) {
6092 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6093 return;
6094 }
6095 gen_helper_tbegin(cpu_env);
6096 }
6097
6098 #define GEN_TM_NOOP(name) \
6099 static inline void gen_##name(DisasContext *ctx) \
6100 { \
6101 if (unlikely(!ctx->tm_enabled)) { \
6102 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6103 return; \
6104 } \
6105 /* Because tbegin always fails in QEMU, these user \
6106 * space instructions all have a simple implementation: \
6107 * \
6108 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6109 * = 0b0 || 0b00 || 0b0 \
6110 */ \
6111 tcg_gen_movi_i32(cpu_crf[0], 0); \
6112 }
6113
6114 GEN_TM_NOOP(tend);
6115 GEN_TM_NOOP(tabort);
6116 GEN_TM_NOOP(tabortwc);
6117 GEN_TM_NOOP(tabortwci);
6118 GEN_TM_NOOP(tabortdc);
6119 GEN_TM_NOOP(tabortdci);
6120 GEN_TM_NOOP(tsr);
6121
6122 static void gen_tcheck(DisasContext *ctx)
6123 {
6124 if (unlikely(!ctx->tm_enabled)) {
6125 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6126 return;
6127 }
6128 /* Because tbegin always fails, the tcheck implementation
6129 * is simple:
6130 *
6131 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6132 * = 0b1 || 0b00 || 0b0
6133 */
6134 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6135 }
6136
6137 #if defined(CONFIG_USER_ONLY)
6138 #define GEN_TM_PRIV_NOOP(name) \
6139 static inline void gen_##name(DisasContext *ctx) \
6140 { \
6141 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6142 }
6143
6144 #else
6145
6146 #define GEN_TM_PRIV_NOOP(name) \
6147 static inline void gen_##name(DisasContext *ctx) \
6148 { \
6149 CHK_SV; \
6150 if (unlikely(!ctx->tm_enabled)) { \
6151 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6152 return; \
6153 } \
6154 /* Because tbegin always fails, the implementation is \
6155 * simple: \
6156 * \
6157 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6158 * = 0b0 || 0b00 | 0b0 \
6159 */ \
6160 tcg_gen_movi_i32(cpu_crf[0], 0); \
6161 }
6162
6163 #endif
6164
6165 GEN_TM_PRIV_NOOP(treclaim);
6166 GEN_TM_PRIV_NOOP(trechkpt);
6167
6168 static opcode_t opcodes[] = {
6169 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6170 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6171 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6172 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
6173 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6174 #if defined(TARGET_PPC64)
6175 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6176 #endif
6177 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6178 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6179 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6180 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6181 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6182 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6183 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6184 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6185 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6186 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6187 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6188 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6189 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6190 #if defined(TARGET_PPC64)
6191 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6192 #endif
6193 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6194 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6195 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6196 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6197 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6198 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6199 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6200 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6201 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6202 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6203 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6204 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6205 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6206 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6207 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6208 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6209 #if defined(TARGET_PPC64)
6210 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6211 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6212 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6213 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6214 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6215 #endif
6216 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6217 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6218 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6219 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6220 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6221 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6222 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6223 #if defined(TARGET_PPC64)
6224 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6225 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6226 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6227 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6228 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6229 #endif
6230 #if defined(TARGET_PPC64)
6231 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6232 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6233 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6234 #endif
6235 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6236 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6237 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6238 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6239 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6240 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6241 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6242 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6243 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6244 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6245 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6246 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6247 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6248 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6249 #if defined(TARGET_PPC64)
6250 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6251 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6252 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6253 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6254 #endif
6255 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6256 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6257 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6258 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6259 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6260 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6261 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
6262 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6263 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6264 #if defined(TARGET_PPC64)
6265 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6266 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6267 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6268 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6269 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6270 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6271 #endif
6272 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6273 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6274 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6275 #if defined(TARGET_PPC64)
6276 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6277 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6278 #endif
6279 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6280 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6281 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6282 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6283 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6284 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6285 #if defined(TARGET_PPC64)
6286 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6287 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6288 #endif
6289 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6290 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6291 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6292 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6293 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6294 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6295 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6296 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6297 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6298 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6299 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6300 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6301 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6302 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6303 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6304 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6305 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6306 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6307 #if defined(TARGET_PPC64)
6308 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6309 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6310 PPC_SEGMENT_64B),
6311 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6312 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6313 PPC_SEGMENT_64B),
6314 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6315 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6316 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6317 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6318 #endif
6319 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6320 /* XXX Those instructions will need to be handled differently for
6321 * different ISA versions */
6322 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6323 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6324 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6325 #if defined(TARGET_PPC64)
6326 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6327 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6328 #endif
6329 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6330 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6331 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6332 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6333 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6334 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6335 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6336 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6337 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6338 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6339 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6340 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6341 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6342 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6343 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6344 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6345 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6346 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6347 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6348 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6349 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6350 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6351 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6352 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6353 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6354 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6355 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6356 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6357 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6358 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6359 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6360 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6361 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6362 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6363 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6364 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6365 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6366 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6367 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6368 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6369 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6370 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6371 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6372 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6373 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6374 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6375 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6376 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6377 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6378 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6379 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6380 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6381 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6382 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6383 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6384 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6385 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6386 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6387 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6388 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6389 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6390 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6391 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6392 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6393 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6394 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6395 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6396 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6397 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6398 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6399 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6400 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6401 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6402 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6403 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6404 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6405 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6406 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6407 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6408 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6409 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6410 PPC_NONE, PPC2_BOOKE206),
6411 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6412 PPC_NONE, PPC2_BOOKE206),
6413 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6414 PPC_NONE, PPC2_BOOKE206),
6415 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6416 PPC_NONE, PPC2_BOOKE206),
6417 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6418 PPC_NONE, PPC2_BOOKE206),
6419 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6420 PPC_NONE, PPC2_PRCNTL),
6421 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6422 PPC_NONE, PPC2_PRCNTL),
6423 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6424 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6425 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6426 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6427 PPC_BOOKE, PPC2_BOOKE206),
6428 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6429 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6430 PPC_BOOKE, PPC2_BOOKE206),
6431 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6432 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6433 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6434 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6435 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6436 #if defined(TARGET_PPC64)
6437 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6438 PPC2_ISA300),
6439 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6440 #endif
6441
6442 #undef GEN_INT_ARITH_ADD
6443 #undef GEN_INT_ARITH_ADD_CONST
6444 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6445 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6446 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6447 add_ca, compute_ca, compute_ov) \
6448 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6449 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6450 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6451 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6452 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6453 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6454 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6455 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6456 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6457 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6458 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6459
6460 #undef GEN_INT_ARITH_DIVW
6461 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6462 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6463 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6464 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6465 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6466 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6467 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6468 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6469 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6470 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6471 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6472 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6473
6474 #if defined(TARGET_PPC64)
6475 #undef GEN_INT_ARITH_DIVD
6476 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6477 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6478 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6479 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6480 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6481 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6482
6483 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6484 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6485 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6486 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6487 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6488 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6489
6490 #undef GEN_INT_ARITH_MUL_HELPER
6491 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6492 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6493 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6494 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6495 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6496 #endif
6497
6498 #undef GEN_INT_ARITH_SUBF
6499 #undef GEN_INT_ARITH_SUBF_CONST
6500 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6501 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6502 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6503 add_ca, compute_ca, compute_ov) \
6504 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6505 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6506 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6507 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6508 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6509 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6510 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6511 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6512 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6513 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6514 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6515
6516 #undef GEN_LOGICAL1
6517 #undef GEN_LOGICAL2
6518 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6519 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6520 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6521 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6522 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6523 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6524 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6525 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6526 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6527 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6528 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6529 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6530 #if defined(TARGET_PPC64)
6531 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6532 #endif
6533
6534 #if defined(TARGET_PPC64)
6535 #undef GEN_PPC64_R2
6536 #undef GEN_PPC64_R4
6537 #define GEN_PPC64_R2(name, opc1, opc2) \
6538 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6539 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6540 PPC_64B)
6541 #define GEN_PPC64_R4(name, opc1, opc2) \
6542 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6543 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6544 PPC_64B), \
6545 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6546 PPC_64B), \
6547 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6548 PPC_64B)
6549 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6550 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6551 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6552 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6553 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6554 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6555 #endif
6556
6557 #undef GEN_LD
6558 #undef GEN_LDU
6559 #undef GEN_LDUX
6560 #undef GEN_LDX_E
6561 #undef GEN_LDS
6562 #define GEN_LD(name, ldop, opc, type) \
6563 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6564 #define GEN_LDU(name, ldop, opc, type) \
6565 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6566 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6567 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6568 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6569 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6570 #define GEN_LDS(name, ldop, op, type) \
6571 GEN_LD(name, ldop, op | 0x20, type) \
6572 GEN_LDU(name, ldop, op | 0x21, type) \
6573 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6574 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6575
6576 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6577 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6578 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6579 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6580 #if defined(TARGET_PPC64)
6581 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6582 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6583 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
6584 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
6585 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6586
6587 /* HV/P7 and later only */
6588 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
6589 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6590 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6591 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6592 #endif
6593 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6594 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6595
6596 #undef GEN_ST
6597 #undef GEN_STU
6598 #undef GEN_STUX
6599 #undef GEN_STX_E
6600 #undef GEN_STS
6601 #define GEN_ST(name, stop, opc, type) \
6602 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6603 #define GEN_STU(name, stop, opc, type) \
6604 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6605 #define GEN_STUX(name, stop, opc2, opc3, type) \
6606 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6607 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6608 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6609 #define GEN_STS(name, stop, op, type) \
6610 GEN_ST(name, stop, op | 0x20, type) \
6611 GEN_STU(name, stop, op | 0x21, type) \
6612 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6613 GEN_STX(name, stop, 0x17, op | 0x00, type)
6614
6615 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6616 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6617 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6618 #if defined(TARGET_PPC64)
6619 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
6620 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
6621 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6622 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
6623 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6624 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6625 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6626 #endif
6627 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6628 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6629
6630 #undef GEN_CRLOGIC
6631 #define GEN_CRLOGIC(name, tcg_op, opc) \
6632 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6633 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6634 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6635 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6636 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6637 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6638 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6639 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6640 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6641
6642 #undef GEN_MAC_HANDLER
6643 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6644 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6645 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6646 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6647 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6648 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6649 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6650 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6651 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6652 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6653 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6654 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6655 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6656 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6657 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6658 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6659 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6660 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6661 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6662 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6663 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6664 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6665 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6666 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6667 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6668 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6669 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6670 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6671 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6672 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6673 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6674 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6675 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6676 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6677 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6678 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6679 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6680 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6681 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6682 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6683 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6684 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6685 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6686 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6687
6688 #include "translate/fp-ops.c"
6689
6690 #include "translate/vmx-ops.c"
6691
6692 #include "translate/vsx-ops.c"
6693
6694 #include "translate/dfp-ops.c"
6695
6696 #include "translate/spe-ops.c"
6697
6698 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6699 PPC_NONE, PPC2_TM),
6700 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6701 PPC_NONE, PPC2_TM),
6702 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6703 PPC_NONE, PPC2_TM),
6704 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6705 PPC_NONE, PPC2_TM),
6706 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6707 PPC_NONE, PPC2_TM),
6708 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6709 PPC_NONE, PPC2_TM),
6710 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6711 PPC_NONE, PPC2_TM),
6712 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6713 PPC_NONE, PPC2_TM),
6714 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6715 PPC_NONE, PPC2_TM),
6716 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6717 PPC_NONE, PPC2_TM),
6718 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6719 PPC_NONE, PPC2_TM),
6720 };
6721
6722 #include "helper_regs.h"
6723 #include "translate_init.c"
6724
6725 /*****************************************************************************/
6726 /* Misc PowerPC helpers */
6727 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6728 int flags)
6729 {
6730 #define RGPL 4
6731 #define RFPL 4
6732
6733 PowerPCCPU *cpu = POWERPC_CPU(cs);
6734 CPUPPCState *env = &cpu->env;
6735 int i;
6736
6737 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6738 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6739 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6740 cs->cpu_index);
6741 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
6742 TARGET_FMT_lx " iidx %d didx %d\n",
6743 env->msr, env->spr[SPR_HID0],
6744 env->hflags, env->immu_idx, env->dmmu_idx);
6745 #if !defined(NO_TIMER_DUMP)
6746 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
6747 #if !defined(CONFIG_USER_ONLY)
6748 " DECR %08" PRIu32
6749 #endif
6750 "\n",
6751 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6752 #if !defined(CONFIG_USER_ONLY)
6753 , cpu_ppc_load_decr(env)
6754 #endif
6755 );
6756 #endif
6757 for (i = 0; i < 32; i++) {
6758 if ((i & (RGPL - 1)) == 0)
6759 cpu_fprintf(f, "GPR%02d", i);
6760 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
6761 if ((i & (RGPL - 1)) == (RGPL - 1))
6762 cpu_fprintf(f, "\n");
6763 }
6764 cpu_fprintf(f, "CR ");
6765 for (i = 0; i < 8; i++)
6766 cpu_fprintf(f, "%01x", env->crf[i]);
6767 cpu_fprintf(f, " [");
6768 for (i = 0; i < 8; i++) {
6769 char a = '-';
6770 if (env->crf[i] & 0x08)
6771 a = 'L';
6772 else if (env->crf[i] & 0x04)
6773 a = 'G';
6774 else if (env->crf[i] & 0x02)
6775 a = 'E';
6776 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6777 }
6778 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
6779 env->reserve_addr);
6780 for (i = 0; i < 32; i++) {
6781 if ((i & (RFPL - 1)) == 0)
6782 cpu_fprintf(f, "FPR%02d", i);
6783 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6784 if ((i & (RFPL - 1)) == (RFPL - 1))
6785 cpu_fprintf(f, "\n");
6786 }
6787 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
6788 #if !defined(CONFIG_USER_ONLY)
6789 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
6790 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
6791 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
6792 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
6793
6794 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
6795 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
6796 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
6797 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
6798
6799 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
6800 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
6801 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
6802 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
6803
6804 #if defined(TARGET_PPC64)
6805 if (env->excp_model == POWERPC_EXCP_POWER7 ||
6806 env->excp_model == POWERPC_EXCP_POWER8) {
6807 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
6808 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
6809 }
6810 #endif
6811 if (env->excp_model == POWERPC_EXCP_BOOKE) {
6812 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
6813 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
6814 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
6815 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
6816
6817 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
6818 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
6819 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
6820 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
6821
6822 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
6823 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
6824 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
6825 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
6826
6827 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
6828 " EPR " TARGET_FMT_lx "\n",
6829 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
6830 env->spr[SPR_BOOKE_EPR]);
6831
6832 /* FSL-specific */
6833 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
6834 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
6835 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
6836 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
6837
6838 /*
6839 * IVORs are left out as they are large and do not change often --
6840 * they can be read with "p $ivor0", "p $ivor1", etc.
6841 */
6842 }
6843
6844 #if defined(TARGET_PPC64)
6845 if (env->flags & POWERPC_FLAG_CFAR) {
6846 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
6847 }
6848 #endif
6849
6850 switch (env->mmu_model) {
6851 case POWERPC_MMU_32B:
6852 case POWERPC_MMU_601:
6853 case POWERPC_MMU_SOFT_6xx:
6854 case POWERPC_MMU_SOFT_74xx:
6855 #if defined(TARGET_PPC64)
6856 case POWERPC_MMU_64B:
6857 case POWERPC_MMU_2_03:
6858 case POWERPC_MMU_2_06:
6859 case POWERPC_MMU_2_06a:
6860 case POWERPC_MMU_2_07:
6861 case POWERPC_MMU_2_07a:
6862 #endif
6863 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
6864 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
6865 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
6866 break;
6867 case POWERPC_MMU_BOOKE206:
6868 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
6869 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
6870 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
6871 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
6872
6873 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
6874 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
6875 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
6876 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
6877
6878 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
6879 " TLB1CFG " TARGET_FMT_lx "\n",
6880 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
6881 env->spr[SPR_BOOKE_TLB1CFG]);
6882 break;
6883 default:
6884 break;
6885 }
6886 #endif
6887
6888 #undef RGPL
6889 #undef RFPL
6890 }
6891
6892 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
6893 fprintf_function cpu_fprintf, int flags)
6894 {
6895 #if defined(DO_PPC_STATISTICS)
6896 PowerPCCPU *cpu = POWERPC_CPU(cs);
6897 opc_handler_t **t1, **t2, **t3, *handler;
6898 int op1, op2, op3;
6899
6900 t1 = cpu->env.opcodes;
6901 for (op1 = 0; op1 < 64; op1++) {
6902 handler = t1[op1];
6903 if (is_indirect_opcode(handler)) {
6904 t2 = ind_table(handler);
6905 for (op2 = 0; op2 < 32; op2++) {
6906 handler = t2[op2];
6907 if (is_indirect_opcode(handler)) {
6908 t3 = ind_table(handler);
6909 for (op3 = 0; op3 < 32; op3++) {
6910 handler = t3[op3];
6911 if (handler->count == 0)
6912 continue;
6913 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6914 "%016" PRIx64 " %" PRId64 "\n",
6915 op1, op2, op3, op1, (op3 << 5) | op2,
6916 handler->oname,
6917 handler->count, handler->count);
6918 }
6919 } else {
6920 if (handler->count == 0)
6921 continue;
6922 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6923 "%016" PRIx64 " %" PRId64 "\n",
6924 op1, op2, op1, op2, handler->oname,
6925 handler->count, handler->count);
6926 }
6927 }
6928 } else {
6929 if (handler->count == 0)
6930 continue;
6931 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
6932 " %" PRId64 "\n",
6933 op1, op1, handler->oname,
6934 handler->count, handler->count);
6935 }
6936 }
6937 #endif
6938 }
6939
6940 /*****************************************************************************/
6941 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
6942 {
6943 PowerPCCPU *cpu = ppc_env_get_cpu(env);
6944 CPUState *cs = CPU(cpu);
6945 DisasContext ctx, *ctxp = &ctx;
6946 opc_handler_t **table, *handler;
6947 target_ulong pc_start;
6948 int num_insns;
6949 int max_insns;
6950
6951 pc_start = tb->pc;
6952 ctx.nip = pc_start;
6953 ctx.tb = tb;
6954 ctx.exception = POWERPC_EXCP_NONE;
6955 ctx.spr_cb = env->spr_cb;
6956 ctx.pr = msr_pr;
6957 ctx.mem_idx = env->dmmu_idx;
6958 ctx.dr = msr_dr;
6959 #if !defined(CONFIG_USER_ONLY)
6960 ctx.hv = msr_hv || !env->has_hv_mode;
6961 #endif
6962 ctx.insns_flags = env->insns_flags;
6963 ctx.insns_flags2 = env->insns_flags2;
6964 ctx.access_type = -1;
6965 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
6966 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
6967 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
6968 #if defined(TARGET_PPC64)
6969 ctx.sf_mode = msr_is_64bit(env, env->msr);
6970 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
6971 #endif
6972 if (env->mmu_model == POWERPC_MMU_32B ||
6973 env->mmu_model == POWERPC_MMU_601 ||
6974 (env->mmu_model & POWERPC_MMU_64B))
6975 ctx.lazy_tlb_flush = true;
6976
6977 ctx.fpu_enabled = !!msr_fp;
6978 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6979 ctx.spe_enabled = !!msr_spe;
6980 else
6981 ctx.spe_enabled = false;
6982 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6983 ctx.altivec_enabled = !!msr_vr;
6984 else
6985 ctx.altivec_enabled = false;
6986 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
6987 ctx.vsx_enabled = !!msr_vsx;
6988 } else {
6989 ctx.vsx_enabled = false;
6990 }
6991 #if defined(TARGET_PPC64)
6992 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
6993 ctx.tm_enabled = !!msr_tm;
6994 } else {
6995 ctx.tm_enabled = false;
6996 }
6997 #endif
6998 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6999 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7000 else
7001 ctx.singlestep_enabled = 0;
7002 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7003 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7004 if (unlikely(cs->singlestep_enabled)) {
7005 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7006 }
7007 #if defined (DO_SINGLE_STEP) && 0
7008 /* Single step trace mode */
7009 msr_se = 1;
7010 #endif
7011 num_insns = 0;
7012 max_insns = tb->cflags & CF_COUNT_MASK;
7013 if (max_insns == 0) {
7014 max_insns = CF_COUNT_MASK;
7015 }
7016 if (max_insns > TCG_MAX_INSNS) {
7017 max_insns = TCG_MAX_INSNS;
7018 }
7019
7020 gen_tb_start(tb);
7021 tcg_clear_temp_count();
7022 /* Set env in case of segfault during code fetch */
7023 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
7024 tcg_gen_insn_start(ctx.nip);
7025 num_insns++;
7026
7027 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
7028 gen_debug_exception(ctxp);
7029 /* The address covered by the breakpoint must be included in
7030 [tb->pc, tb->pc + tb->size) in order to for it to be
7031 properly cleared -- thus we increment the PC here so that
7032 the logic setting tb->size below does the right thing. */
7033 ctx.nip += 4;
7034 break;
7035 }
7036
7037 LOG_DISAS("----------------\n");
7038 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7039 ctx.nip, ctx.mem_idx, (int)msr_ir);
7040 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7041 gen_io_start();
7042 if (unlikely(need_byteswap(&ctx))) {
7043 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7044 } else {
7045 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7046 }
7047 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7048 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7049 opc3(ctx.opcode), opc4(ctx.opcode),
7050 ctx.le_mode ? "little" : "big");
7051 ctx.nip += 4;
7052 table = env->opcodes;
7053 handler = table[opc1(ctx.opcode)];
7054 if (is_indirect_opcode(handler)) {
7055 table = ind_table(handler);
7056 handler = table[opc2(ctx.opcode)];
7057 if (is_indirect_opcode(handler)) {
7058 table = ind_table(handler);
7059 handler = table[opc3(ctx.opcode)];
7060 if (is_indirect_opcode(handler)) {
7061 table = ind_table(handler);
7062 handler = table[opc4(ctx.opcode)];
7063 }
7064 }
7065 }
7066 /* Is opcode *REALLY* valid ? */
7067 if (unlikely(handler->handler == &gen_invalid)) {
7068 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7069 "%02x - %02x - %02x - %02x (%08x) "
7070 TARGET_FMT_lx " %d\n",
7071 opc1(ctx.opcode), opc2(ctx.opcode),
7072 opc3(ctx.opcode), opc4(ctx.opcode),
7073 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7074 } else {
7075 uint32_t inval;
7076
7077 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7078 inval = handler->inval2;
7079 } else {
7080 inval = handler->inval1;
7081 }
7082
7083 if (unlikely((ctx.opcode & inval) != 0)) {
7084 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7085 "%02x - %02x - %02x - %02x (%08x) "
7086 TARGET_FMT_lx "\n", ctx.opcode & inval,
7087 opc1(ctx.opcode), opc2(ctx.opcode),
7088 opc3(ctx.opcode), opc4(ctx.opcode),
7089 ctx.opcode, ctx.nip - 4);
7090 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7091 break;
7092 }
7093 }
7094 (*(handler->handler))(&ctx);
7095 #if defined(DO_PPC_STATISTICS)
7096 handler->count++;
7097 #endif
7098 /* Check trace mode exceptions */
7099 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7100 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7101 ctx.exception != POWERPC_SYSCALL &&
7102 ctx.exception != POWERPC_EXCP_TRAP &&
7103 ctx.exception != POWERPC_EXCP_BRANCH)) {
7104 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7105 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7106 (cs->singlestep_enabled) ||
7107 singlestep ||
7108 num_insns >= max_insns)) {
7109 /* if we reach a page boundary or are single stepping, stop
7110 * generation
7111 */
7112 break;
7113 }
7114 if (tcg_check_temp_count()) {
7115 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7116 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7117 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7118 exit(1);
7119 }
7120 }
7121 if (tb->cflags & CF_LAST_IO)
7122 gen_io_end();
7123 if (ctx.exception == POWERPC_EXCP_NONE) {
7124 gen_goto_tb(&ctx, 0, ctx.nip);
7125 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7126 if (unlikely(cs->singlestep_enabled)) {
7127 gen_debug_exception(ctxp);
7128 }
7129 /* Generate the return instruction */
7130 tcg_gen_exit_tb(0);
7131 }
7132 gen_tb_end(tb, num_insns);
7133
7134 tb->size = ctx.nip - pc_start;
7135 tb->icount = num_insns;
7136
7137 #if defined(DEBUG_DISAS)
7138 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7139 && qemu_log_in_addr_range(pc_start)) {
7140 int flags;
7141 flags = env->bfd_mach;
7142 flags |= ctx.le_mode << 16;
7143 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7144 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7145 qemu_log("\n");
7146 }
7147 #endif
7148 }
7149
7150 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7151 target_ulong *data)
7152 {
7153 env->nip = data[0];
7154 }
Random patches