tcg/tci/tcg-target.inc.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2009, 2011 Stefan Weil
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "tcg-be-null.h"
  26
  27 /* TODO list:
  28  * - See TODO comments in code.
  29  */
  30
  31 /* Marker for missing code. */
  32 #define TODO() \
  33     do { \
  34         fprintf(stderr, "TODO %s:%u: %s()\n", \
  35                 __FILE__, __LINE__, __func__); \
  36         tcg_abort(); \
  37     } while (0)
  38
  39 /* Bitfield n...m (in 32 bit value). */
  40 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
  41
  42 /* Macros used in tcg_target_op_defs. */
  43 #define R       "r"
  44 #define RI      "ri"
  45 #if TCG_TARGET_REG_BITS == 32
  46 # define R64    "r", "r"
  47 #else
  48 # define R64    "r"
  49 #endif
  50 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  51 # define L      "L", "L"
  52 # define S      "S", "S"
  53 #else
  54 # define L      "L"
  55 # define S      "S"
  56 #endif
  57
  58 /* TODO: documentation. */
  59 static const TCGTargetOpDef tcg_target_op_defs[] = {
  60     { INDEX_op_exit_tb, { NULL } },
  61     { INDEX_op_goto_tb, { NULL } },
  62     { INDEX_op_br, { NULL } },
  63
  64     { INDEX_op_ld8u_i32, { R, R } },
  65     { INDEX_op_ld8s_i32, { R, R } },
  66     { INDEX_op_ld16u_i32, { R, R } },
  67     { INDEX_op_ld16s_i32, { R, R } },
  68     { INDEX_op_ld_i32, { R, R } },
  69     { INDEX_op_st8_i32, { R, R } },
  70     { INDEX_op_st16_i32, { R, R } },
  71     { INDEX_op_st_i32, { R, R } },
  72
  73     { INDEX_op_add_i32, { R, RI, RI } },
  74     { INDEX_op_sub_i32, { R, RI, RI } },
  75     { INDEX_op_mul_i32, { R, RI, RI } },
  76 #if TCG_TARGET_HAS_div_i32
  77     { INDEX_op_div_i32, { R, R, R } },
  78     { INDEX_op_divu_i32, { R, R, R } },
  79     { INDEX_op_rem_i32, { R, R, R } },
  80     { INDEX_op_remu_i32, { R, R, R } },
  81 #elif TCG_TARGET_HAS_div2_i32
  82     { INDEX_op_div2_i32, { R, R, "0", "1", R } },
  83     { INDEX_op_divu2_i32, { R, R, "0", "1", R } },
  84 #endif
  85     /* TODO: Does R, RI, RI result in faster code than R, R, RI?
  86        If both operands are constants, we can optimize. */
  87     { INDEX_op_and_i32, { R, RI, RI } },
  88 #if TCG_TARGET_HAS_andc_i32
  89     { INDEX_op_andc_i32, { R, RI, RI } },
  90 #endif
  91 #if TCG_TARGET_HAS_eqv_i32
  92     { INDEX_op_eqv_i32, { R, RI, RI } },
  93 #endif
  94 #if TCG_TARGET_HAS_nand_i32
  95     { INDEX_op_nand_i32, { R, RI, RI } },
  96 #endif
  97 #if TCG_TARGET_HAS_nor_i32
  98     { INDEX_op_nor_i32, { R, RI, RI } },
  99 #endif
 100     { INDEX_op_or_i32, { R, RI, RI } },
 101 #if TCG_TARGET_HAS_orc_i32
 102     { INDEX_op_orc_i32, { R, RI, RI } },
 103 #endif
 104     { INDEX_op_xor_i32, { R, RI, RI } },
 105     { INDEX_op_shl_i32, { R, RI, RI } },
 106     { INDEX_op_shr_i32, { R, RI, RI } },
 107     { INDEX_op_sar_i32, { R, RI, RI } },
 108 #if TCG_TARGET_HAS_rot_i32
 109     { INDEX_op_rotl_i32, { R, RI, RI } },
 110     { INDEX_op_rotr_i32, { R, RI, RI } },
 111 #endif
 112 #if TCG_TARGET_HAS_deposit_i32
 113     { INDEX_op_deposit_i32, { R, "0", R } },
 114 #endif
 115
 116     { INDEX_op_brcond_i32, { R, RI } },
 117
 118     { INDEX_op_setcond_i32, { R, R, RI } },
 119 #if TCG_TARGET_REG_BITS == 64
 120     { INDEX_op_setcond_i64, { R, R, RI } },
 121 #endif /* TCG_TARGET_REG_BITS == 64 */
 122
 123 #if TCG_TARGET_REG_BITS == 32
 124     /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
 125     { INDEX_op_add2_i32, { R, R, R, R, R, R } },
 126     { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
 127     { INDEX_op_brcond2_i32, { R, R, RI, RI } },
 128     { INDEX_op_mulu2_i32, { R, R, R, R } },
 129     { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
 130 #endif
 131
 132 #if TCG_TARGET_HAS_not_i32
 133     { INDEX_op_not_i32, { R, R } },
 134 #endif
 135 #if TCG_TARGET_HAS_neg_i32
 136     { INDEX_op_neg_i32, { R, R } },
 137 #endif
 138
 139 #if TCG_TARGET_REG_BITS == 64
 140     { INDEX_op_ld8u_i64, { R, R } },
 141     { INDEX_op_ld8s_i64, { R, R } },
 142     { INDEX_op_ld16u_i64, { R, R } },
 143     { INDEX_op_ld16s_i64, { R, R } },
 144     { INDEX_op_ld32u_i64, { R, R } },
 145     { INDEX_op_ld32s_i64, { R, R } },
 146     { INDEX_op_ld_i64, { R, R } },
 147
 148     { INDEX_op_st8_i64, { R, R } },
 149     { INDEX_op_st16_i64, { R, R } },
 150     { INDEX_op_st32_i64, { R, R } },
 151     { INDEX_op_st_i64, { R, R } },
 152
 153     { INDEX_op_add_i64, { R, RI, RI } },
 154     { INDEX_op_sub_i64, { R, RI, RI } },
 155     { INDEX_op_mul_i64, { R, RI, RI } },
 156 #if TCG_TARGET_HAS_div_i64
 157     { INDEX_op_div_i64, { R, R, R } },
 158     { INDEX_op_divu_i64, { R, R, R } },
 159     { INDEX_op_rem_i64, { R, R, R } },
 160     { INDEX_op_remu_i64, { R, R, R } },
 161 #elif TCG_TARGET_HAS_div2_i64
 162     { INDEX_op_div2_i64, { R, R, "0", "1", R } },
 163     { INDEX_op_divu2_i64, { R, R, "0", "1", R } },
 164 #endif
 165     { INDEX_op_and_i64, { R, RI, RI } },
 166 #if TCG_TARGET_HAS_andc_i64
 167     { INDEX_op_andc_i64, { R, RI, RI } },
 168 #endif
 169 #if TCG_TARGET_HAS_eqv_i64
 170     { INDEX_op_eqv_i64, { R, RI, RI } },
 171 #endif
 172 #if TCG_TARGET_HAS_nand_i64
 173     { INDEX_op_nand_i64, { R, RI, RI } },
 174 #endif
 175 #if TCG_TARGET_HAS_nor_i64
 176     { INDEX_op_nor_i64, { R, RI, RI } },
 177 #endif
 178     { INDEX_op_or_i64, { R, RI, RI } },
 179 #if TCG_TARGET_HAS_orc_i64
 180     { INDEX_op_orc_i64, { R, RI, RI } },
 181 #endif
 182     { INDEX_op_xor_i64, { R, RI, RI } },
 183     { INDEX_op_shl_i64, { R, RI, RI } },
 184     { INDEX_op_shr_i64, { R, RI, RI } },
 185     { INDEX_op_sar_i64, { R, RI, RI } },
 186 #if TCG_TARGET_HAS_rot_i64
 187     { INDEX_op_rotl_i64, { R, RI, RI } },
 188     { INDEX_op_rotr_i64, { R, RI, RI } },
 189 #endif
 190 #if TCG_TARGET_HAS_deposit_i64
 191     { INDEX_op_deposit_i64, { R, "0", R } },
 192 #endif
 193     { INDEX_op_brcond_i64, { R, RI } },
 194
 195 #if TCG_TARGET_HAS_ext8s_i64
 196     { INDEX_op_ext8s_i64, { R, R } },
 197 #endif
 198 #if TCG_TARGET_HAS_ext16s_i64
 199     { INDEX_op_ext16s_i64, { R, R } },
 200 #endif
 201 #if TCG_TARGET_HAS_ext32s_i64
 202     { INDEX_op_ext32s_i64, { R, R } },
 203 #endif
 204 #if TCG_TARGET_HAS_ext8u_i64
 205     { INDEX_op_ext8u_i64, { R, R } },
 206 #endif
 207 #if TCG_TARGET_HAS_ext16u_i64
 208     { INDEX_op_ext16u_i64, { R, R } },
 209 #endif
 210 #if TCG_TARGET_HAS_ext32u_i64
 211     { INDEX_op_ext32u_i64, { R, R } },
 212 #endif
 213     { INDEX_op_ext_i32_i64, { R, R } },
 214     { INDEX_op_extu_i32_i64, { R, R } },
 215 #if TCG_TARGET_HAS_bswap16_i64
 216     { INDEX_op_bswap16_i64, { R, R } },
 217 #endif
 218 #if TCG_TARGET_HAS_bswap32_i64
 219     { INDEX_op_bswap32_i64, { R, R } },
 220 #endif
 221 #if TCG_TARGET_HAS_bswap64_i64
 222     { INDEX_op_bswap64_i64, { R, R } },
 223 #endif
 224 #if TCG_TARGET_HAS_not_i64
 225     { INDEX_op_not_i64, { R, R } },
 226 #endif
 227 #if TCG_TARGET_HAS_neg_i64
 228     { INDEX_op_neg_i64, { R, R } },
 229 #endif
 230 #endif /* TCG_TARGET_REG_BITS == 64 */
 231
 232     { INDEX_op_qemu_ld_i32, { R, L } },
 233     { INDEX_op_qemu_ld_i64, { R64, L } },
 234
 235     { INDEX_op_qemu_st_i32, { R, S } },
 236     { INDEX_op_qemu_st_i64, { R64, S } },
 237
 238 #if TCG_TARGET_HAS_ext8s_i32
 239     { INDEX_op_ext8s_i32, { R, R } },
 240 #endif
 241 #if TCG_TARGET_HAS_ext16s_i32
 242     { INDEX_op_ext16s_i32, { R, R } },
 243 #endif
 244 #if TCG_TARGET_HAS_ext8u_i32
 245     { INDEX_op_ext8u_i32, { R, R } },
 246 #endif
 247 #if TCG_TARGET_HAS_ext16u_i32
 248     { INDEX_op_ext16u_i32, { R, R } },
 249 #endif
 250
 251 #if TCG_TARGET_HAS_bswap16_i32
 252     { INDEX_op_bswap16_i32, { R, R } },
 253 #endif
 254 #if TCG_TARGET_HAS_bswap32_i32
 255     { INDEX_op_bswap32_i32, { R, R } },
 256 #endif
 257
 258     { INDEX_op_mb, { } },
 259     { -1 },
 260 };
 261
 262 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
 263 {
 264     int i, n = ARRAY_SIZE(tcg_target_op_defs);
 265
 266     for (i = 0; i < n; ++i) {
 267         if (tcg_target_op_defs[i].op == op) {
 268             return &tcg_target_op_defs[i];
 269         }
 270     }
 271     return NULL;
 272 }
 273
 274 static const int tcg_target_reg_alloc_order[] = {
 275     TCG_REG_R0,
 276     TCG_REG_R1,
 277     TCG_REG_R2,
 278     TCG_REG_R3,
 279 #if 0 /* used for TCG_REG_CALL_STACK */
 280     TCG_REG_R4,
 281 #endif
 282     TCG_REG_R5,
 283     TCG_REG_R6,
 284     TCG_REG_R7,
 285 #if TCG_TARGET_NB_REGS >= 16
 286     TCG_REG_R8,
 287     TCG_REG_R9,
 288     TCG_REG_R10,
 289     TCG_REG_R11,
 290     TCG_REG_R12,
 291     TCG_REG_R13,
 292     TCG_REG_R14,
 293     TCG_REG_R15,
 294 #endif
 295 };
 296
 297 #if MAX_OPC_PARAM_IARGS != 5
 298 # error Fix needed, number of supported input arguments changed!
 299 #endif
 300
 301 static const int tcg_target_call_iarg_regs[] = {
 302     TCG_REG_R0,
 303     TCG_REG_R1,
 304     TCG_REG_R2,
 305     TCG_REG_R3,
 306 #if 0 /* used for TCG_REG_CALL_STACK */
 307     TCG_REG_R4,
 308 #endif
 309     TCG_REG_R5,
 310 #if TCG_TARGET_REG_BITS == 32
 311     /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
 312     TCG_REG_R6,
 313     TCG_REG_R7,
 314 #if TCG_TARGET_NB_REGS >= 16
 315     TCG_REG_R8,
 316     TCG_REG_R9,
 317     TCG_REG_R10,
 318 #else
 319 # error Too few input registers available
 320 #endif
 321 #endif
 322 };
 323
 324 static const int tcg_target_call_oarg_regs[] = {
 325     TCG_REG_R0,
 326 #if TCG_TARGET_REG_BITS == 32
 327     TCG_REG_R1
 328 #endif
 329 };
 330
 331 #ifdef CONFIG_DEBUG_TCG
 332 static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
 333     "r00",
 334     "r01",
 335     "r02",
 336     "r03",
 337     "r04",
 338     "r05",
 339     "r06",
 340     "r07",
 341 #if TCG_TARGET_NB_REGS >= 16
 342     "r08",
 343     "r09",
 344     "r10",
 345     "r11",
 346     "r12",
 347     "r13",
 348     "r14",
 349     "r15",
 350 #if TCG_TARGET_NB_REGS >= 32
 351     "r16",
 352     "r17",
 353     "r18",
 354     "r19",
 355     "r20",
 356     "r21",
 357     "r22",
 358     "r23",
 359     "r24",
 360     "r25",
 361     "r26",
 362     "r27",
 363     "r28",
 364     "r29",
 365     "r30",
 366     "r31"
 367 #endif
 368 #endif
 369 };
 370 #endif
 371
 372 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
 373                         intptr_t value, intptr_t addend)
 374 {
 375     /* tcg_out_reloc always uses the same type, addend. */
 376     tcg_debug_assert(type == sizeof(tcg_target_long));
 377     tcg_debug_assert(addend == 0);
 378     tcg_debug_assert(value != 0);
 379     if (TCG_TARGET_REG_BITS == 32) {
 380         tcg_patch32(code_ptr, value);
 381     } else {
 382         tcg_patch64(code_ptr, value);
 383     }
 384 }
 385
 386 /* Parse target specific constraints. */
 387 static const char *target_parse_constraint(TCGArgConstraint *ct,
 388                                            const char *ct_str, TCGType type)
 389 {
 390     switch (*ct_str++) {
 391     case 'r':
 392     case 'L':                   /* qemu_ld constraint */
 393     case 'S':                   /* qemu_st constraint */
 394         ct->ct |= TCG_CT_REG;
 395         tcg_regset_set32(ct->u.regs, 0, BIT(TCG_TARGET_NB_REGS) - 1);
 396         break;
 397     default:
 398         return NULL;
 399     }
 400     return ct_str;
 401 }
 402
 403 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
 404 /* Show current bytecode. Used by tcg interpreter. */
 405 void tci_disas(uint8_t opc)
 406 {
 407     const TCGOpDef *def = &tcg_op_defs[opc];
 408     fprintf(stderr, "TCG %s %u, %u, %u\n",
 409             def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs);
 410 }
 411 #endif
 412
 413 /* Write value (native size). */
 414 static void tcg_out_i(TCGContext *s, tcg_target_ulong v)
 415 {
 416     if (TCG_TARGET_REG_BITS == 32) {
 417         tcg_out32(s, v);
 418     } else {
 419         tcg_out64(s, v);
 420     }
 421 }
 422
 423 /* Write opcode. */
 424 static void tcg_out_op_t(TCGContext *s, TCGOpcode op)
 425 {
 426     tcg_out8(s, op);
 427     tcg_out8(s, 0);
 428 }
 429
 430 /* Write register. */
 431 static void tcg_out_r(TCGContext *s, TCGArg t0)
 432 {
 433     tcg_debug_assert(t0 < TCG_TARGET_NB_REGS);
 434     tcg_out8(s, t0);
 435 }
 436
 437 /* Write register or constant (native size). */
 438 static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg)
 439 {
 440     if (const_arg) {
 441         tcg_debug_assert(const_arg == 1);
 442         tcg_out8(s, TCG_CONST);
 443         tcg_out_i(s, arg);
 444     } else {
 445         tcg_out_r(s, arg);
 446     }
 447 }
 448
 449 /* Write register or constant (32 bit). */
 450 static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg)
 451 {
 452     if (const_arg) {
 453         tcg_debug_assert(const_arg == 1);
 454         tcg_out8(s, TCG_CONST);
 455         tcg_out32(s, arg);
 456     } else {
 457         tcg_out_r(s, arg);
 458     }
 459 }
 460
 461 #if TCG_TARGET_REG_BITS == 64
 462 /* Write register or constant (64 bit). */
 463 static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg)
 464 {
 465     if (const_arg) {
 466         tcg_debug_assert(const_arg == 1);
 467         tcg_out8(s, TCG_CONST);
 468         tcg_out64(s, arg);
 469     } else {
 470         tcg_out_r(s, arg);
 471     }
 472 }
 473 #endif
 474
 475 /* Write label. */
 476 static void tci_out_label(TCGContext *s, TCGLabel *label)
 477 {
 478     if (label->has_value) {
 479         tcg_out_i(s, label->u.value);
 480         tcg_debug_assert(label->u.value);
 481     } else {
 482         tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0);
 483         s->code_ptr += sizeof(tcg_target_ulong);
 484     }
 485 }
 486
 487 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
 488                        intptr_t arg2)
 489 {
 490     uint8_t *old_code_ptr = s->code_ptr;
 491     if (type == TCG_TYPE_I32) {
 492         tcg_out_op_t(s, INDEX_op_ld_i32);
 493         tcg_out_r(s, ret);
 494         tcg_out_r(s, arg1);
 495         tcg_out32(s, arg2);
 496     } else {
 497         tcg_debug_assert(type == TCG_TYPE_I64);
 498 #if TCG_TARGET_REG_BITS == 64
 499         tcg_out_op_t(s, INDEX_op_ld_i64);
 500         tcg_out_r(s, ret);
 501         tcg_out_r(s, arg1);
 502         tcg_debug_assert(arg2 == (int32_t)arg2);
 503         tcg_out32(s, arg2);
 504 #else
 505         TODO();
 506 #endif
 507     }
 508     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 509 }
 510
 511 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
 512 {
 513     uint8_t *old_code_ptr = s->code_ptr;
 514     tcg_debug_assert(ret != arg);
 515 #if TCG_TARGET_REG_BITS == 32
 516     tcg_out_op_t(s, INDEX_op_mov_i32);
 517 #else
 518     tcg_out_op_t(s, INDEX_op_mov_i64);
 519 #endif
 520     tcg_out_r(s, ret);
 521     tcg_out_r(s, arg);
 522     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 523 }
 524
 525 static void tcg_out_movi(TCGContext *s, TCGType type,
 526                          TCGReg t0, tcg_target_long arg)
 527 {
 528     uint8_t *old_code_ptr = s->code_ptr;
 529     uint32_t arg32 = arg;
 530     if (type == TCG_TYPE_I32 || arg == arg32) {
 531         tcg_out_op_t(s, INDEX_op_movi_i32);
 532         tcg_out_r(s, t0);
 533         tcg_out32(s, arg32);
 534     } else {
 535         tcg_debug_assert(type == TCG_TYPE_I64);
 536 #if TCG_TARGET_REG_BITS == 64
 537         tcg_out_op_t(s, INDEX_op_movi_i64);
 538         tcg_out_r(s, t0);
 539         tcg_out64(s, arg);
 540 #else
 541         TODO();
 542 #endif
 543     }
 544     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 545 }
 546
 547 static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
 548 {
 549     uint8_t *old_code_ptr = s->code_ptr;
 550     tcg_out_op_t(s, INDEX_op_call);
 551     tcg_out_ri(s, 1, (uintptr_t)arg);
 552     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 553 }
 554
 555 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
 556                        const int *const_args)
 557 {
 558     uint8_t *old_code_ptr = s->code_ptr;
 559
 560     tcg_out_op_t(s, opc);
 561
 562     switch (opc) {
 563     case INDEX_op_exit_tb:
 564         tcg_out64(s, args[0]);
 565         break;
 566     case INDEX_op_goto_tb:
 567         if (s->tb_jmp_insn_offset) {
 568             /* Direct jump method. */
 569             /* Align for atomic patching and thread safety */
 570             s->code_ptr = QEMU_ALIGN_PTR_UP(s->code_ptr, 4);
 571             s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
 572             tcg_out32(s, 0);
 573         } else {
 574             /* Indirect jump method. */
 575             TODO();
 576         }
 577         s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
 578         break;
 579     case INDEX_op_br:
 580         tci_out_label(s, arg_label(args[0]));
 581         break;
 582     case INDEX_op_setcond_i32:
 583         tcg_out_r(s, args[0]);
 584         tcg_out_r(s, args[1]);
 585         tcg_out_ri32(s, const_args[2], args[2]);
 586         tcg_out8(s, args[3]);   /* condition */
 587         break;
 588 #if TCG_TARGET_REG_BITS == 32
 589     case INDEX_op_setcond2_i32:
 590         /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
 591         tcg_out_r(s, args[0]);
 592         tcg_out_r(s, args[1]);
 593         tcg_out_r(s, args[2]);
 594         tcg_out_ri32(s, const_args[3], args[3]);
 595         tcg_out_ri32(s, const_args[4], args[4]);
 596         tcg_out8(s, args[5]);   /* condition */
 597         break;
 598 #elif TCG_TARGET_REG_BITS == 64
 599     case INDEX_op_setcond_i64:
 600         tcg_out_r(s, args[0]);
 601         tcg_out_r(s, args[1]);
 602         tcg_out_ri64(s, const_args[2], args[2]);
 603         tcg_out8(s, args[3]);   /* condition */
 604         break;
 605 #endif
 606     case INDEX_op_ld8u_i32:
 607     case INDEX_op_ld8s_i32:
 608     case INDEX_op_ld16u_i32:
 609     case INDEX_op_ld16s_i32:
 610     case INDEX_op_ld_i32:
 611     case INDEX_op_st8_i32:
 612     case INDEX_op_st16_i32:
 613     case INDEX_op_st_i32:
 614     case INDEX_op_ld8u_i64:
 615     case INDEX_op_ld8s_i64:
 616     case INDEX_op_ld16u_i64:
 617     case INDEX_op_ld16s_i64:
 618     case INDEX_op_ld32u_i64:
 619     case INDEX_op_ld32s_i64:
 620     case INDEX_op_ld_i64:
 621     case INDEX_op_st8_i64:
 622     case INDEX_op_st16_i64:
 623     case INDEX_op_st32_i64:
 624     case INDEX_op_st_i64:
 625         tcg_out_r(s, args[0]);
 626         tcg_out_r(s, args[1]);
 627         tcg_debug_assert(args[2] == (int32_t)args[2]);
 628         tcg_out32(s, args[2]);
 629         break;
 630     case INDEX_op_add_i32:
 631     case INDEX_op_sub_i32:
 632     case INDEX_op_mul_i32:
 633     case INDEX_op_and_i32:
 634     case INDEX_op_andc_i32:     /* Optional (TCG_TARGET_HAS_andc_i32). */
 635     case INDEX_op_eqv_i32:      /* Optional (TCG_TARGET_HAS_eqv_i32). */
 636     case INDEX_op_nand_i32:     /* Optional (TCG_TARGET_HAS_nand_i32). */
 637     case INDEX_op_nor_i32:      /* Optional (TCG_TARGET_HAS_nor_i32). */
 638     case INDEX_op_or_i32:
 639     case INDEX_op_orc_i32:      /* Optional (TCG_TARGET_HAS_orc_i32). */
 640     case INDEX_op_xor_i32:
 641     case INDEX_op_shl_i32:
 642     case INDEX_op_shr_i32:
 643     case INDEX_op_sar_i32:
 644     case INDEX_op_rotl_i32:     /* Optional (TCG_TARGET_HAS_rot_i32). */
 645     case INDEX_op_rotr_i32:     /* Optional (TCG_TARGET_HAS_rot_i32). */
 646         tcg_out_r(s, args[0]);
 647         tcg_out_ri32(s, const_args[1], args[1]);
 648         tcg_out_ri32(s, const_args[2], args[2]);
 649         break;
 650     case INDEX_op_deposit_i32:  /* Optional (TCG_TARGET_HAS_deposit_i32). */
 651         tcg_out_r(s, args[0]);
 652         tcg_out_r(s, args[1]);
 653         tcg_out_r(s, args[2]);
 654         tcg_debug_assert(args[3] <= UINT8_MAX);
 655         tcg_out8(s, args[3]);
 656         tcg_debug_assert(args[4] <= UINT8_MAX);
 657         tcg_out8(s, args[4]);
 658         break;
 659
 660 #if TCG_TARGET_REG_BITS == 64
 661     case INDEX_op_add_i64:
 662     case INDEX_op_sub_i64:
 663     case INDEX_op_mul_i64:
 664     case INDEX_op_and_i64:
 665     case INDEX_op_andc_i64:     /* Optional (TCG_TARGET_HAS_andc_i64). */
 666     case INDEX_op_eqv_i64:      /* Optional (TCG_TARGET_HAS_eqv_i64). */
 667     case INDEX_op_nand_i64:     /* Optional (TCG_TARGET_HAS_nand_i64). */
 668     case INDEX_op_nor_i64:      /* Optional (TCG_TARGET_HAS_nor_i64). */
 669     case INDEX_op_or_i64:
 670     case INDEX_op_orc_i64:      /* Optional (TCG_TARGET_HAS_orc_i64). */
 671     case INDEX_op_xor_i64:
 672     case INDEX_op_shl_i64:
 673     case INDEX_op_shr_i64:
 674     case INDEX_op_sar_i64:
 675     case INDEX_op_rotl_i64:     /* Optional (TCG_TARGET_HAS_rot_i64). */
 676     case INDEX_op_rotr_i64:     /* Optional (TCG_TARGET_HAS_rot_i64). */
 677         tcg_out_r(s, args[0]);
 678         tcg_out_ri64(s, const_args[1], args[1]);
 679         tcg_out_ri64(s, const_args[2], args[2]);
 680         break;
 681     case INDEX_op_deposit_i64:  /* Optional (TCG_TARGET_HAS_deposit_i64). */
 682         tcg_out_r(s, args[0]);
 683         tcg_out_r(s, args[1]);
 684         tcg_out_r(s, args[2]);
 685         tcg_debug_assert(args[3] <= UINT8_MAX);
 686         tcg_out8(s, args[3]);
 687         tcg_debug_assert(args[4] <= UINT8_MAX);
 688         tcg_out8(s, args[4]);
 689         break;
 690     case INDEX_op_div_i64:      /* Optional (TCG_TARGET_HAS_div_i64). */
 691     case INDEX_op_divu_i64:     /* Optional (TCG_TARGET_HAS_div_i64). */
 692     case INDEX_op_rem_i64:      /* Optional (TCG_TARGET_HAS_div_i64). */
 693     case INDEX_op_remu_i64:     /* Optional (TCG_TARGET_HAS_div_i64). */
 694         TODO();
 695         break;
 696     case INDEX_op_div2_i64:     /* Optional (TCG_TARGET_HAS_div2_i64). */
 697     case INDEX_op_divu2_i64:    /* Optional (TCG_TARGET_HAS_div2_i64). */
 698         TODO();
 699         break;
 700     case INDEX_op_brcond_i64:
 701         tcg_out_r(s, args[0]);
 702         tcg_out_ri64(s, const_args[1], args[1]);
 703         tcg_out8(s, args[2]);           /* condition */
 704         tci_out_label(s, arg_label(args[3]));
 705         break;
 706     case INDEX_op_bswap16_i64:  /* Optional (TCG_TARGET_HAS_bswap16_i64). */
 707     case INDEX_op_bswap32_i64:  /* Optional (TCG_TARGET_HAS_bswap32_i64). */
 708     case INDEX_op_bswap64_i64:  /* Optional (TCG_TARGET_HAS_bswap64_i64). */
 709     case INDEX_op_not_i64:      /* Optional (TCG_TARGET_HAS_not_i64). */
 710     case INDEX_op_neg_i64:      /* Optional (TCG_TARGET_HAS_neg_i64). */
 711     case INDEX_op_ext8s_i64:    /* Optional (TCG_TARGET_HAS_ext8s_i64). */
 712     case INDEX_op_ext8u_i64:    /* Optional (TCG_TARGET_HAS_ext8u_i64). */
 713     case INDEX_op_ext16s_i64:   /* Optional (TCG_TARGET_HAS_ext16s_i64). */
 714     case INDEX_op_ext16u_i64:   /* Optional (TCG_TARGET_HAS_ext16u_i64). */
 715     case INDEX_op_ext32s_i64:   /* Optional (TCG_TARGET_HAS_ext32s_i64). */
 716     case INDEX_op_ext32u_i64:   /* Optional (TCG_TARGET_HAS_ext32u_i64). */
 717     case INDEX_op_ext_i32_i64:
 718     case INDEX_op_extu_i32_i64:
 719 #endif /* TCG_TARGET_REG_BITS == 64 */
 720     case INDEX_op_neg_i32:      /* Optional (TCG_TARGET_HAS_neg_i32). */
 721     case INDEX_op_not_i32:      /* Optional (TCG_TARGET_HAS_not_i32). */
 722     case INDEX_op_ext8s_i32:    /* Optional (TCG_TARGET_HAS_ext8s_i32). */
 723     case INDEX_op_ext16s_i32:   /* Optional (TCG_TARGET_HAS_ext16s_i32). */
 724     case INDEX_op_ext8u_i32:    /* Optional (TCG_TARGET_HAS_ext8u_i32). */
 725     case INDEX_op_ext16u_i32:   /* Optional (TCG_TARGET_HAS_ext16u_i32). */
 726     case INDEX_op_bswap16_i32:  /* Optional (TCG_TARGET_HAS_bswap16_i32). */
 727     case INDEX_op_bswap32_i32:  /* Optional (TCG_TARGET_HAS_bswap32_i32). */
 728         tcg_out_r(s, args[0]);
 729         tcg_out_r(s, args[1]);
 730         break;
 731     case INDEX_op_div_i32:      /* Optional (TCG_TARGET_HAS_div_i32). */
 732     case INDEX_op_divu_i32:     /* Optional (TCG_TARGET_HAS_div_i32). */
 733     case INDEX_op_rem_i32:      /* Optional (TCG_TARGET_HAS_div_i32). */
 734     case INDEX_op_remu_i32:     /* Optional (TCG_TARGET_HAS_div_i32). */
 735         tcg_out_r(s, args[0]);
 736         tcg_out_ri32(s, const_args[1], args[1]);
 737         tcg_out_ri32(s, const_args[2], args[2]);
 738         break;
 739     case INDEX_op_div2_i32:     /* Optional (TCG_TARGET_HAS_div2_i32). */
 740     case INDEX_op_divu2_i32:    /* Optional (TCG_TARGET_HAS_div2_i32). */
 741         TODO();
 742         break;
 743 #if TCG_TARGET_REG_BITS == 32
 744     case INDEX_op_add2_i32:
 745     case INDEX_op_sub2_i32:
 746         tcg_out_r(s, args[0]);
 747         tcg_out_r(s, args[1]);
 748         tcg_out_r(s, args[2]);
 749         tcg_out_r(s, args[3]);
 750         tcg_out_r(s, args[4]);
 751         tcg_out_r(s, args[5]);
 752         break;
 753     case INDEX_op_brcond2_i32:
 754         tcg_out_r(s, args[0]);
 755         tcg_out_r(s, args[1]);
 756         tcg_out_ri32(s, const_args[2], args[2]);
 757         tcg_out_ri32(s, const_args[3], args[3]);
 758         tcg_out8(s, args[4]);           /* condition */
 759         tci_out_label(s, arg_label(args[5]));
 760         break;
 761     case INDEX_op_mulu2_i32:
 762         tcg_out_r(s, args[0]);
 763         tcg_out_r(s, args[1]);
 764         tcg_out_r(s, args[2]);
 765         tcg_out_r(s, args[3]);
 766         break;
 767 #endif
 768     case INDEX_op_brcond_i32:
 769         tcg_out_r(s, args[0]);
 770         tcg_out_ri32(s, const_args[1], args[1]);
 771         tcg_out8(s, args[2]);           /* condition */
 772         tci_out_label(s, arg_label(args[3]));
 773         break;
 774     case INDEX_op_qemu_ld_i32:
 775         tcg_out_r(s, *args++);
 776         tcg_out_r(s, *args++);
 777         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 778             tcg_out_r(s, *args++);
 779         }
 780         tcg_out_i(s, *args++);
 781         break;
 782     case INDEX_op_qemu_ld_i64:
 783         tcg_out_r(s, *args++);
 784         if (TCG_TARGET_REG_BITS == 32) {
 785             tcg_out_r(s, *args++);
 786         }
 787         tcg_out_r(s, *args++);
 788         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 789             tcg_out_r(s, *args++);
 790         }
 791         tcg_out_i(s, *args++);
 792         break;
 793     case INDEX_op_qemu_st_i32:
 794         tcg_out_r(s, *args++);
 795         tcg_out_r(s, *args++);
 796         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 797             tcg_out_r(s, *args++);
 798         }
 799         tcg_out_i(s, *args++);
 800         break;
 801     case INDEX_op_qemu_st_i64:
 802         tcg_out_r(s, *args++);
 803         if (TCG_TARGET_REG_BITS == 32) {
 804             tcg_out_r(s, *args++);
 805         }
 806         tcg_out_r(s, *args++);
 807         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 808             tcg_out_r(s, *args++);
 809         }
 810         tcg_out_i(s, *args++);
 811         break;
 812     case INDEX_op_mb:
 813         break;
 814     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
 815     case INDEX_op_mov_i64:
 816     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
 817     case INDEX_op_movi_i64:
 818     case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
 819     default:
 820         tcg_abort();
 821     }
 822     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 823 }
 824
 825 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
 826                        intptr_t arg2)
 827 {
 828     uint8_t *old_code_ptr = s->code_ptr;
 829     if (type == TCG_TYPE_I32) {
 830         tcg_out_op_t(s, INDEX_op_st_i32);
 831         tcg_out_r(s, arg);
 832         tcg_out_r(s, arg1);
 833         tcg_out32(s, arg2);
 834     } else {
 835         tcg_debug_assert(type == TCG_TYPE_I64);
 836 #if TCG_TARGET_REG_BITS == 64
 837         tcg_out_op_t(s, INDEX_op_st_i64);
 838         tcg_out_r(s, arg);
 839         tcg_out_r(s, arg1);
 840         tcg_out32(s, arg2);
 841 #else
 842         TODO();
 843 #endif
 844     }
 845     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 846 }
 847
 848 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
 849                                TCGReg base, intptr_t ofs)
 850 {
 851     return false;
 852 }
 853
 854 /* Test if a constant matches the constraint. */
 855 static int tcg_target_const_match(tcg_target_long val, TCGType type,
 856                                   const TCGArgConstraint *arg_ct)
 857 {
 858     /* No need to return 0 or 1, 0 or != 0 is good enough. */
 859     return arg_ct->ct & TCG_CT_CONST;
 860 }
 861
 862 static void tcg_target_init(TCGContext *s)
 863 {
 864 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
 865     const char *envval = getenv("DEBUG_TCG");
 866     if (envval) {
 867         qemu_set_log(strtol(envval, NULL, 0));
 868     }
 869 #endif
 870
 871     /* The current code uses uint8_t for tcg operations. */
 872     tcg_debug_assert(tcg_op_defs_max <= UINT8_MAX);
 873
 874     /* Registers available for 32 bit operations. */
 875     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
 876                      BIT(TCG_TARGET_NB_REGS) - 1);
 877     /* Registers available for 64 bit operations. */
 878     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0,
 879                      BIT(TCG_TARGET_NB_REGS) - 1);
 880     /* TODO: Which registers should be set here? */
 881     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
 882                      BIT(TCG_TARGET_NB_REGS) - 1);
 883
 884     tcg_regset_clear(s->reserved_regs);
 885     tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
 886
 887     /* We use negative offsets from "sp" so that we can distinguish
 888        stores that might pretend to be call arguments.  */
 889     tcg_set_frame(s, TCG_REG_CALL_STACK,
 890                   -CPU_TEMP_BUF_NLONGS * sizeof(long),
 891                   CPU_TEMP_BUF_NLONGS * sizeof(long));
 892 }
 893
 894 /* Generate global QEMU prologue and epilogue code. */
 895 static inline void tcg_target_qemu_prologue(TCGContext *s)
 896 {
 897 }