ppc/xive: Introduce a new XiveRouter end_notify() handler
[qemu/kevin.git] / include / hw / ppc / xive2_regs.h
blobb7adbdb7b98057bc95fbd6c7aff46380e074a240
1 /*
2 * QEMU PowerPC XIVE2 internal structure definitions (POWER10)
4 * Copyright (c) 2019-2022, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */
10 #ifndef PPC_XIVE2_REGS_H
11 #define PPC_XIVE2_REGS_H
13 #include "cpu.h"
16 * Thread Interrupt Management Area (TIMA)
18 * In Gen1 mode (P9 compat mode) word 2 is the same. However in Gen2
19 * mode (P10), the CAM line is slightly different as the VP space was
20 * increased.
22 #define TM2_QW0W2_VU PPC_BIT32(0)
23 #define TM2_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31)
24 #define TM2_QW1W2_VO PPC_BIT32(0)
25 #define TM2_QW1W2_HO PPC_BIT32(1)
26 #define TM2_QW1W2_OS_CAM PPC_BITMASK32(4, 31)
27 #define TM2_QW2W2_VP PPC_BIT32(0)
28 #define TM2_QW2W2_HP PPC_BIT32(1)
29 #define TM2_QW2W2_POOL_CAM PPC_BITMASK32(4, 31)
30 #define TM2_QW3W2_VT PPC_BIT32(0)
31 #define TM2_QW3W2_HT PPC_BIT32(1)
32 #define TM2_QW3W2_LP PPC_BIT32(6)
33 #define TM2_QW3W2_LE PPC_BIT32(7)
36 * Event Assignment Structure (EAS)
39 typedef struct Xive2Eas {
40 uint64_t w;
41 #define EAS2_VALID PPC_BIT(0)
42 #define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ block# */
43 #define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ index */
44 #define EAS2_MASKED PPC_BIT(32) /* Masked */
45 #define EAS2_END_DATA PPC_BITMASK(33, 63) /* written to the EQ */
46 } Xive2Eas;
48 #define xive2_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS2_VALID)
49 #define xive2_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS2_MASKED)
51 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon);
54 * Event Notifification Descriptor (END)
57 typedef struct Xive2End {
58 uint32_t w0;
59 #define END2_W0_VALID PPC_BIT32(0) /* "v" bit */
60 #define END2_W0_ENQUEUE PPC_BIT32(5) /* "q" bit */
61 #define END2_W0_UCOND_NOTIFY PPC_BIT32(6) /* "n" bit */
62 #define END2_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit */
63 #define END2_W0_BACKLOG PPC_BIT32(8) /* "b" bit */
64 #define END2_W0_PRECL_ESC_CTL PPC_BIT32(9) /* "p" bit */
65 #define END2_W0_UNCOND_ESCALATE PPC_BIT32(10) /* "u" bit */
66 #define END2_W0_ESCALATE_CTL PPC_BIT32(11) /* "e" bit */
67 #define END2_W0_ADAPTIVE_ESC PPC_BIT32(12) /* "a" bit */
68 #define END2_W0_ESCALATE_END PPC_BIT32(13) /* "N" bit */
69 #define END2_W0_FIRMWARE1 PPC_BIT32(16) /* Owned by FW */
70 #define END2_W0_FIRMWARE2 PPC_BIT32(17) /* Owned by FW */
71 #define END2_W0_AEC_SIZE PPC_BITMASK32(18, 19)
72 #define END2_W0_AEG_SIZE PPC_BITMASK32(20, 23)
73 #define END2_W0_EQ_VG_PREDICT PPC_BITMASK32(24, 31) /* Owned by HW */
74 uint32_t w1;
75 #define END2_W1_ESn PPC_BITMASK32(0, 1)
76 #define END2_W1_ESn_P PPC_BIT32(0)
77 #define END2_W1_ESn_Q PPC_BIT32(1)
78 #define END2_W1_ESe PPC_BITMASK32(2, 3)
79 #define END2_W1_ESe_P PPC_BIT32(2)
80 #define END2_W1_ESe_Q PPC_BIT32(3)
81 #define END2_W1_GEN_FLIPPED PPC_BIT32(8)
82 #define END2_W1_GENERATION PPC_BIT32(9)
83 #define END2_W1_PAGE_OFF PPC_BITMASK32(10, 31)
84 uint32_t w2;
85 #define END2_W2_RESERVED PPC_BITMASK32(4, 7)
86 #define END2_W2_EQ_ADDR_HI PPC_BITMASK32(8, 31)
87 uint32_t w3;
88 #define END2_W3_EQ_ADDR_LO PPC_BITMASK32(0, 24)
89 #define END2_W3_QSIZE PPC_BITMASK32(28, 31)
90 uint32_t w4;
91 #define END2_W4_END_BLOCK PPC_BITMASK32(4, 7)
92 #define END2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31)
93 #define END2_W4_ESB_BLOCK PPC_BITMASK32(0, 3)
94 #define END2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31)
95 uint32_t w5;
96 #define END2_W5_ESC_END_DATA PPC_BITMASK32(1, 31)
97 uint32_t w6;
98 #define END2_W6_FORMAT_BIT PPC_BIT32(0)
99 #define END2_W6_IGNORE PPC_BIT32(1)
100 #define END2_W6_VP_BLOCK PPC_BITMASK32(4, 7)
101 #define END2_W6_VP_OFFSET PPC_BITMASK32(8, 31)
102 #define END2_W6_VP_OFFSET_GEN1 PPC_BITMASK32(13, 31)
103 uint32_t w7;
104 #define END2_W7_TOPO PPC_BITMASK32(0, 3) /* Owned by HW */
105 #define END2_W7_F0_PRIORITY PPC_BITMASK32(8, 15)
106 #define END2_W7_F1_LOG_SERVER_ID PPC_BITMASK32(4, 31)
107 } Xive2End;
109 #define xive2_end_is_valid(end) (be32_to_cpu((end)->w0) & END2_W0_VALID)
110 #define xive2_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END2_W0_ENQUEUE)
111 #define xive2_end_is_notify(end) \
112 (be32_to_cpu((end)->w0) & END2_W0_UCOND_NOTIFY)
113 #define xive2_end_is_backlog(end) (be32_to_cpu((end)->w0) & END2_W0_BACKLOG)
114 #define xive2_end_is_escalate(end) \
115 (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_CTL)
116 #define xive2_end_is_uncond_escalation(end) \
117 (be32_to_cpu((end)->w0) & END2_W0_UNCOND_ESCALATE)
118 #define xive2_end_is_silent_escalation(end) \
119 (be32_to_cpu((end)->w0) & END2_W0_SILENT_ESCALATE)
120 #define xive2_end_is_escalate_end(end) \
121 (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_END)
122 #define xive2_end_is_firmware1(end) \
123 (be32_to_cpu((end)->w0) & END2_W0_FIRMWARE1)
124 #define xive2_end_is_firmware2(end) \
125 (be32_to_cpu((end)->w0) & END2_W0_FIRMWARE2)
127 static inline uint64_t xive2_end_qaddr(Xive2End *end)
129 return ((uint64_t) be32_to_cpu(end->w2) & END2_W2_EQ_ADDR_HI) << 32 |
130 (be32_to_cpu(end->w3) & END2_W3_EQ_ADDR_LO);
133 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon);
134 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width,
135 Monitor *mon);
136 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,
137 Monitor *mon);
140 * Notification Virtual Processor (NVP)
142 typedef struct Xive2Nvp {
143 uint32_t w0;
144 #define NVP2_W0_VALID PPC_BIT32(0)
145 #define NVP2_W0_HW PPC_BIT32(7)
146 #define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */
147 uint32_t w1;
148 #define NVP2_W1_CO PPC_BIT32(13)
149 #define NVP2_W1_CO_PRIV PPC_BITMASK32(14, 15)
150 #define NVP2_W1_CO_THRID_VALID PPC_BIT32(16)
151 #define NVP2_W1_CO_THRID PPC_BITMASK32(17, 31)
152 uint32_t w2;
153 #define NVP2_W2_CPPR PPC_BITMASK32(0, 7)
154 #define NVP2_W2_IPB PPC_BITMASK32(8, 15)
155 #define NVP2_W2_LSMFB PPC_BITMASK32(16, 23)
156 uint32_t w3;
157 uint32_t w4;
158 #define NVP2_W4_ESC_ESB_BLOCK PPC_BITMASK32(0, 3) /* N:0 */
159 #define NVP2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31) /* N:0 */
160 #define NVP2_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7) /* N:1 */
161 #define NVP2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31) /* N:1 */
162 uint32_t w5;
163 #define NVP2_W5_PSIZE PPC_BITMASK32(0, 1)
164 #define NVP2_W5_VP_END_BLOCK PPC_BITMASK32(4, 7)
165 #define NVP2_W5_VP_END_INDEX PPC_BITMASK32(8, 31)
166 uint32_t w6;
167 uint32_t w7;
168 } Xive2Nvp;
170 #define xive2_nvp_is_valid(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_VALID)
171 #define xive2_nvp_is_hw(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_HW)
172 #define xive2_nvp_is_co(nvp) (be32_to_cpu((nvp)->w1) & NVP2_W1_CO)
175 * The VP number space in a block is defined by the END2_W6_VP_OFFSET
176 * field of the XIVE END. When running in Gen1 mode (P9 compat mode),
177 * the VP space is reduced to (1 << 19) VPs per block
179 #define XIVE2_NVP_SHIFT 24
180 #define XIVE2_NVP_COUNT (1 << XIVE2_NVP_SHIFT)
182 static inline uint32_t xive2_nvp_cam_line(uint8_t nvp_blk, uint32_t nvp_idx)
184 return (nvp_blk << XIVE2_NVP_SHIFT) | nvp_idx;
187 static inline uint32_t xive2_nvp_idx(uint32_t cam_line)
189 return cam_line & ((1 << XIVE2_NVP_SHIFT) - 1);
192 static inline uint32_t xive2_nvp_blk(uint32_t cam_line)
194 return (cam_line >> XIVE2_NVP_SHIFT) & 0xf;
198 * Notification Virtual Group or Crowd (NVG/NVC)
200 typedef struct Xive2Nvgc {
201 uint32_t w0;
202 #define NVGC2_W0_VALID PPC_BIT32(0)
203 uint32_t w1;
204 uint32_t w2;
205 uint32_t w3;
206 uint32_t w4;
207 uint32_t w5;
208 uint32_t w6;
209 uint32_t w7;
210 } Xive2Nvgc;
212 #endif /* PPC_XIVE2_REGS_H */