include/hw/ppc/pnv_chip.h

   1 #ifndef PPC_PNV_CHIP_H
   2 #define PPC_PNV_CHIP_H
   3
   4 #include "hw/pci-host/pnv_phb4.h"
   5 #include "hw/ppc/pnv_core.h"
   6 #include "hw/ppc/pnv_homer.h"
   7 #include "hw/ppc/pnv_lpc.h"
   8 #include "hw/ppc/pnv_occ.h"
   9 #include "hw/ppc/pnv_psi.h"
  10 #include "hw/ppc/pnv_sbe.h"
  11 #include "hw/ppc/pnv_xive.h"
  12 #include "hw/sysbus.h"
  13
  14 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
  15                     PNV_CHIP)
  16
  17 struct PnvChip {
  18     /*< private >*/
  19     SysBusDevice parent_obj;
  20
  21     /*< public >*/
  22     uint32_t     chip_id;
  23     uint64_t     ram_start;
  24     uint64_t     ram_size;
  25
  26     uint32_t     nr_cores;
  27     uint32_t     nr_threads;
  28     uint64_t     cores_mask;
  29     PnvCore      **cores;
  30
  31     uint32_t     num_pecs;
  32
  33     MemoryRegion xscom_mmio;
  34     MemoryRegion xscom;
  35     AddressSpace xscom_as;
  36
  37     MemoryRegion *fw_mr;
  38     gchar        *dt_isa_nodename;
  39 };
  40
  41 #define TYPE_PNV8_CHIP "pnv8-chip"
  42 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
  43                          TYPE_PNV8_CHIP)
  44
  45 struct Pnv8Chip {
  46     /*< private >*/
  47     PnvChip      parent_obj;
  48
  49     /*< public >*/
  50     MemoryRegion icp_mmio;
  51
  52     PnvLpcController lpc;
  53     Pnv8Psi      psi;
  54     PnvOCC       occ;
  55     PnvHomer     homer;
  56
  57 #define PNV8_CHIP_PHB3_MAX 4
  58     /*
  59      * The array is used to allow quick access to the phbs by
  60      * pnv_ics_get_child() and pnv_ics_resend_child().
  61      */
  62     PnvPHB       *phbs[PNV8_CHIP_PHB3_MAX];
  63     uint32_t     num_phbs;
  64
  65     XICSFabric    *xics;
  66 };
  67
  68 #define TYPE_PNV9_CHIP "pnv9-chip"
  69 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
  70                          TYPE_PNV9_CHIP)
  71
  72 struct Pnv9Chip {
  73     /*< private >*/
  74     PnvChip      parent_obj;
  75
  76     /*< public >*/
  77     PnvXive      xive;
  78     Pnv9Psi      psi;
  79     PnvLpcController lpc;
  80     PnvOCC       occ;
  81     PnvSBE       sbe;
  82     PnvHomer     homer;
  83
  84     uint32_t     nr_quads;
  85     PnvQuad      *quads;
  86
  87 #define PNV9_CHIP_MAX_PEC 3
  88     PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
  89 };
  90
  91 /*
  92  * A SMT8 fused core is a pair of SMT4 cores.
  93  */
  94 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
  95 #define PNV9_PIR2CHIP(pir)      (((pir) >> 8) & 0x7f)
  96
  97 #define TYPE_PNV10_CHIP "pnv10-chip"
  98 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
  99                          TYPE_PNV10_CHIP)
 100
 101 struct Pnv10Chip {
 102     /*< private >*/
 103     PnvChip      parent_obj;
 104
 105     /*< public >*/
 106     PnvXive2     xive;
 107     Pnv9Psi      psi;
 108     PnvLpcController lpc;
 109     PnvOCC       occ;
 110     PnvSBE       sbe;
 111     PnvHomer     homer;
 112
 113     uint32_t     nr_quads;
 114     PnvQuad      *quads;
 115
 116 #define PNV10_CHIP_MAX_PEC 2
 117     PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];
 118 };
 119
 120 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
 121 #define PNV10_PIR2CHIP(pir)      (((pir) >> 8) & 0x7f)
 122
 123 struct PnvChipClass {
 124     /*< private >*/
 125     SysBusDeviceClass parent_class;
 126
 127     /*< public >*/
 128     uint64_t     chip_cfam_id;
 129     uint64_t     cores_mask;
 130     uint32_t     num_pecs;
 131     uint32_t     num_phbs;
 132
 133     DeviceRealize parent_realize;
 134
 135     uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
 136     void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
 137     void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
 138     void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
 139     void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
 140     ISABus *(*isa_create)(PnvChip *chip, Error **errp);
 141     void (*dt_populate)(PnvChip *chip, void *fdt);
 142     void (*pic_print_info)(PnvChip *chip, Monitor *mon);
 143     uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
 144     uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
 145 };
 146
 147 #endif