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prep: qdev'ify Raven host bridge (PCIDevice)
[qemu/kevin.git] / hw / eepro100.c
blob6a162f607f1ddb9665c9cf695236c5713d535a38
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2011 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * Windows networking
28 *
29 * References:
30 *
31 * Intel 8255x 10/100 Mbps Ethernet Controller Family
32 * Open Source Software Developer Manual
33 *
34 * TODO:
35 * * PHY emulation should be separated from nic emulation.
36 * Most nic emulations could share the same phy code.
37 * * i82550 is untested. It is programmed like the i82559.
38 * * i82562 is untested. It is programmed like the i82559.
39 * * Power management (i82558 and later) is not implemented.
40 * * Wake-on-LAN is not implemented.
41 */
42
43 #include <stddef.h> /* offsetof */
44 #include "hw.h"
45 #include "pci.h"
46 #include "net.h"
47 #include "eeprom93xx.h"
48 #include "sysemu.h"
49 #include "dma.h"
50
51 /* QEMU sends frames smaller than 60 bytes to ethernet nics.
52 * Such frames are rejected by real nics and their emulations.
53 * To avoid this behaviour, other nic emulations pad received
54 * frames. The following definition enables this padding for
55 * eepro100, too. We keep the define around in case it might
56 * become useful the future if the core networking is ever
57 * changed to pad short packets itself. */
58 #define CONFIG_PAD_RECEIVED_FRAMES
59
60 #define KiB 1024
61
62 /* Debug EEPRO100 card. */
63 #if 0
64 # define DEBUG_EEPRO100
65 #endif
66
67 #ifdef DEBUG_EEPRO100
68 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
69 #else
70 #define logout(fmt, ...) ((void)0)
71 #endif
72
73 /* Set flags to 0 to disable debug output. */
74 #define INT 1 /* interrupt related actions */
75 #define MDI 1 /* mdi related actions */
76 #define OTHER 1
77 #define RXTX 1
78 #define EEPROM 1 /* eeprom related actions */
79
80 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
81
82 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
83
84 #define MAX_ETH_FRAME_SIZE 1514
85
86 /* This driver supports several different devices which are declared here. */
87 #define i82550 0x82550
88 #define i82551 0x82551
89 #define i82557A 0x82557a
90 #define i82557B 0x82557b
91 #define i82557C 0x82557c
92 #define i82558A 0x82558a
93 #define i82558B 0x82558b
94 #define i82559A 0x82559a
95 #define i82559B 0x82559b
96 #define i82559C 0x82559c
97 #define i82559ER 0x82559e
98 #define i82562 0x82562
99 #define i82801 0x82801
100
101 /* Use 64 word EEPROM. TODO: could be a runtime option. */
102 #define EEPROM_SIZE 64
103
104 #define PCI_MEM_SIZE (4 * KiB)
105 #define PCI_IO_SIZE 64
106 #define PCI_FLASH_SIZE (128 * KiB)
107
108 #define BIT(n) (1 << (n))
109 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
110
111 /* The SCB accepts the following controls for the Tx and Rx units: */
112 #define CU_NOP 0x0000 /* No operation. */
113 #define CU_START 0x0010 /* CU start. */
114 #define CU_RESUME 0x0020 /* CU resume. */
115 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
116 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
117 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
118 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
119 #define CU_SRESUME 0x00a0 /* CU static resume. */
120
121 #define RU_NOP 0x0000
122 #define RX_START 0x0001
123 #define RX_RESUME 0x0002
124 #define RU_ABORT 0x0004
125 #define RX_ADDR_LOAD 0x0006
126 #define RX_RESUMENR 0x0007
127 #define INT_MASK 0x0100
128 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
129
130 typedef struct {
131 PCIDeviceInfo pci;
132 uint32_t device;
133 uint8_t stats_size;
134 bool has_extended_tcb_support;
135 bool power_management;
136 } E100PCIDeviceInfo;
137
138 /* Offsets to the various registers.
139 All accesses need not be longword aligned. */
140 typedef enum {
141 SCBStatus = 0, /* Status Word. */
142 SCBAck = 1,
143 SCBCmd = 2, /* Rx/Command Unit command and status. */
144 SCBIntmask = 3,
145 SCBPointer = 4, /* General purpose pointer. */
146 SCBPort = 8, /* Misc. commands and operands. */
147 SCBflash = 12, /* Flash memory control. */
148 SCBeeprom = 14, /* EEPROM control. */
149 SCBCtrlMDI = 16, /* MDI interface control. */
150 SCBEarlyRx = 20, /* Early receive byte count. */
151 SCBFlow = 24, /* Flow Control. */
152 SCBpmdr = 27, /* Power Management Driver. */
153 SCBgctrl = 28, /* General Control. */
154 SCBgstat = 29, /* General Status. */
155 } E100RegisterOffset;
156
157 /* A speedo3 transmit buffer descriptor with two buffers... */
158 typedef struct {
159 uint16_t status;
160 uint16_t command;
161 uint32_t link; /* void * */
162 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
163 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
164 uint8_t tx_threshold; /* transmit threshold */
165 uint8_t tbd_count; /* TBD number */
166 #if 0
167 /* This constitutes two "TBD" entries: hdr and data */
168 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
169 int32_t tx_buf_size0; /* Length of Tx hdr. */
170 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
171 int32_t tx_buf_size1; /* Length of Tx data. */
172 #endif
173 } eepro100_tx_t;
174
175 /* Receive frame descriptor. */
176 typedef struct {
177 int16_t status;
178 uint16_t command;
179 uint32_t link; /* struct RxFD * */
180 uint32_t rx_buf_addr; /* void * */
181 uint16_t count;
182 uint16_t size;
183 /* Ethernet frame data follows. */
184 } eepro100_rx_t;
185
186 typedef enum {
187 COMMAND_EL = BIT(15),
188 COMMAND_S = BIT(14),
189 COMMAND_I = BIT(13),
190 COMMAND_NC = BIT(4),
191 COMMAND_SF = BIT(3),
192 COMMAND_CMD = BITS(2, 0),
193 } scb_command_bit;
194
195 typedef enum {
196 STATUS_C = BIT(15),
197 STATUS_OK = BIT(13),
198 } scb_status_bit;
199
200 typedef struct {
201 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
202 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
203 tx_multiple_collisions, tx_total_collisions;
204 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
205 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
206 rx_short_frame_errors;
207 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
208 uint16_t xmt_tco_frames, rcv_tco_frames;
209 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
210 uint32_t reserved[4];
211 } eepro100_stats_t;
212
213 typedef enum {
214 cu_idle = 0,
215 cu_suspended = 1,
216 cu_active = 2,
217 cu_lpq_active = 2,
218 cu_hqp_active = 3
219 } cu_state_t;
220
221 typedef enum {
222 ru_idle = 0,
223 ru_suspended = 1,
224 ru_no_resources = 2,
225 ru_ready = 4
226 } ru_state_t;
227
228 typedef struct {
229 PCIDevice dev;
230 /* Hash register (multicast mask array, multiple individual addresses). */
231 uint8_t mult[8];
232 MemoryRegion mmio_bar;
233 MemoryRegion io_bar;
234 MemoryRegion flash_bar;
235 NICState *nic;
236 NICConf conf;
237 uint8_t scb_stat; /* SCB stat/ack byte */
238 uint8_t int_stat; /* PCI interrupt status */
239 /* region must not be saved by nic_save. */
240 uint16_t mdimem[32];
241 eeprom_t *eeprom;
242 uint32_t device; /* device variant */
243 /* (cu_base + cu_offset) address the next command block in the command block list. */
244 uint32_t cu_base; /* CU base address */
245 uint32_t cu_offset; /* CU address offset */
246 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
247 uint32_t ru_base; /* RU base address */
248 uint32_t ru_offset; /* RU address offset */
249 uint32_t statsaddr; /* pointer to eepro100_stats_t */
250
251 /* Temporary status information (no need to save these values),
252 * used while processing CU commands. */
253 eepro100_tx_t tx; /* transmit buffer descriptor */
254 uint32_t cb_address; /* = cu_base + cu_offset */
255
256 /* Statistical counters. Also used for wake-up packet (i82559). */
257 eepro100_stats_t statistics;
258
259 /* Data in mem is always in the byte order of the controller (le).
260 * It must be dword aligned to allow direct access to 32 bit values. */
261 uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));
262
263 /* Configuration bytes. */
264 uint8_t configuration[22];
265
266 /* vmstate for each particular nic */
267 VMStateDescription *vmstate;
268
269 /* Quasi static device properties (no need to save them). */
270 uint16_t stats_size;
271 bool has_extended_tcb_support;
272 } EEPRO100State;
273
274 /* Word indices in EEPROM. */
275 typedef enum {
276 EEPROM_CNFG_MDIX = 0x03,
277 EEPROM_ID = 0x05,
278 EEPROM_PHY_ID = 0x06,
279 EEPROM_VENDOR_ID = 0x0c,
280 EEPROM_CONFIG_ASF = 0x0d,
281 EEPROM_DEVICE_ID = 0x23,
282 EEPROM_SMBUS_ADDR = 0x90,
283 } EEPROMOffset;
284
285 /* Bit values for EEPROM ID word. */
286 typedef enum {
287 EEPROM_ID_MDM = BIT(0), /* Modem */
288 EEPROM_ID_STB = BIT(1), /* Standby Enable */
289 EEPROM_ID_WMR = BIT(2), /* ??? */
290 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
291 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
292 EEPROM_ID_ALT = BIT(7), /* */
293 /* BITS(10, 8) device revision */
294 EEPROM_ID_BD = BIT(11), /* boot disable */
295 EEPROM_ID_ID = BIT(13), /* id bit */
296 /* BITS(15, 14) signature */
297 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
298 } eeprom_id_bit;
299
300 /* Default values for MDI (PHY) registers */
301 static const uint16_t eepro100_mdi_default[] = {
302 /* MDI Registers 0 - 6, 7 */
303 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
304 /* MDI Registers 8 - 15 */
305 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
306 /* MDI Registers 16 - 31 */
307 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
308 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
309 };
310
311 /* Readonly mask for MDI (PHY) registers */
312 static const uint16_t eepro100_mdi_mask[] = {
313 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
314 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
315 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
316 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
317 };
318
319 #define POLYNOMIAL 0x04c11db6
320
321 /* From FreeBSD */
322 /* XXX: optimize */
323 static unsigned compute_mcast_idx(const uint8_t * ep)
324 {
325 uint32_t crc;
326 int carry, i, j;
327 uint8_t b;
328
329 crc = 0xffffffff;
330 for (i = 0; i < 6; i++) {
331 b = *ep++;
332 for (j = 0; j < 8; j++) {
333 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
334 crc <<= 1;
335 b >>= 1;
336 if (carry) {
337 crc = ((crc ^ POLYNOMIAL) | carry);
338 }
339 }
340 }
341 return (crc & BITS(7, 2)) >> 2;
342 }
343
344 /* Read a 16 bit control/status (CSR) register. */
345 static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
346 {
347 assert(!((uintptr_t)&s->mem[addr] & 1));
348 return le16_to_cpup((uint16_t *)&s->mem[addr]);
349 }
350
351 /* Read a 32 bit control/status (CSR) register. */
352 static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
353 {
354 assert(!((uintptr_t)&s->mem[addr] & 3));
355 return le32_to_cpup((uint32_t *)&s->mem[addr]);
356 }
357
358 /* Write a 16 bit control/status (CSR) register. */
359 static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr,
360 uint16_t val)
361 {
362 assert(!((uintptr_t)&s->mem[addr] & 1));
363 cpu_to_le16w((uint16_t *)&s->mem[addr], val);
364 }
365
366 /* Read a 32 bit control/status (CSR) register. */
367 static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr,
368 uint32_t val)
369 {
370 assert(!((uintptr_t)&s->mem[addr] & 3));
371 cpu_to_le32w((uint32_t *)&s->mem[addr], val);
372 }
373
374 #if defined(DEBUG_EEPRO100)
375 static const char *nic_dump(const uint8_t * buf, unsigned size)
376 {
377 static char dump[3 * 16 + 1];
378 char *p = &dump[0];
379 if (size > 16) {
380 size = 16;
381 }
382 while (size-- > 0) {
383 p += sprintf(p, " %02x", *buf++);
384 }
385 return dump;
386 }
387 #endif /* DEBUG_EEPRO100 */
388
389 enum scb_stat_ack {
390 stat_ack_not_ours = 0x00,
391 stat_ack_sw_gen = 0x04,
392 stat_ack_rnr = 0x10,
393 stat_ack_cu_idle = 0x20,
394 stat_ack_frame_rx = 0x40,
395 stat_ack_cu_cmd_done = 0x80,
396 stat_ack_not_present = 0xFF,
397 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
398 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
399 };
400
401 static void disable_interrupt(EEPRO100State * s)
402 {
403 if (s->int_stat) {
404 TRACE(INT, logout("interrupt disabled\n"));
405 qemu_irq_lower(s->dev.irq[0]);
406 s->int_stat = 0;
407 }
408 }
409
410 static void enable_interrupt(EEPRO100State * s)
411 {
412 if (!s->int_stat) {
413 TRACE(INT, logout("interrupt enabled\n"));
414 qemu_irq_raise(s->dev.irq[0]);
415 s->int_stat = 1;
416 }
417 }
418
419 static void eepro100_acknowledge(EEPRO100State * s)
420 {
421 s->scb_stat &= ~s->mem[SCBAck];
422 s->mem[SCBAck] = s->scb_stat;
423 if (s->scb_stat == 0) {
424 disable_interrupt(s);
425 }
426 }
427
428 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
429 {
430 uint8_t mask = ~s->mem[SCBIntmask];
431 s->mem[SCBAck] |= status;
432 status = s->scb_stat = s->mem[SCBAck];
433 status &= (mask | 0x0f);
434 #if 0
435 status &= (~s->mem[SCBIntmask] | 0x0xf);
436 #endif
437 if (status && (mask & 0x01)) {
438 /* SCB mask and SCB Bit M do not disable interrupt. */
439 enable_interrupt(s);
440 } else if (s->int_stat) {
441 disable_interrupt(s);
442 }
443 }
444
445 static void eepro100_cx_interrupt(EEPRO100State * s)
446 {
447 /* CU completed action command. */
448 /* Transmit not ok (82557 only, not in emulation). */
449 eepro100_interrupt(s, 0x80);
450 }
451
452 static void eepro100_cna_interrupt(EEPRO100State * s)
453 {
454 /* CU left the active state. */
455 eepro100_interrupt(s, 0x20);
456 }
457
458 static void eepro100_fr_interrupt(EEPRO100State * s)
459 {
460 /* RU received a complete frame. */
461 eepro100_interrupt(s, 0x40);
462 }
463
464 static void eepro100_rnr_interrupt(EEPRO100State * s)
465 {
466 /* RU is not ready. */
467 eepro100_interrupt(s, 0x10);
468 }
469
470 static void eepro100_mdi_interrupt(EEPRO100State * s)
471 {
472 /* MDI completed read or write cycle. */
473 eepro100_interrupt(s, 0x08);
474 }
475
476 static void eepro100_swi_interrupt(EEPRO100State * s)
477 {
478 /* Software has requested an interrupt. */
479 eepro100_interrupt(s, 0x04);
480 }
481
482 #if 0
483 static void eepro100_fcp_interrupt(EEPRO100State * s)
484 {
485 /* Flow control pause interrupt (82558 and later). */
486 eepro100_interrupt(s, 0x01);
487 }
488 #endif
489
490 static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device)
491 {
492 uint32_t device = s->device;
493 uint8_t *pci_conf = s->dev.config;
494
495 TRACE(OTHER, logout("%p\n", s));
496
497 /* PCI Status */
498 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
499 PCI_STATUS_FAST_BACK);
500 /* PCI Latency Timer */
501 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
502 /* Capability Pointer is set by PCI framework. */
503 /* Interrupt Line */
504 /* Interrupt Pin */
505 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
506 /* Minimum Grant */
507 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
508 /* Maximum Latency */
509 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
510
511 s->stats_size = e100_device->stats_size;
512 s->has_extended_tcb_support = e100_device->has_extended_tcb_support;
513
514 switch (device) {
515 case i82550:
516 case i82551:
517 case i82557A:
518 case i82557B:
519 case i82557C:
520 case i82558A:
521 case i82558B:
522 case i82559A:
523 case i82559B:
524 case i82559ER:
525 case i82562:
526 case i82801:
527 case i82559C:
528 break;
529 default:
530 logout("Device %X is undefined!\n", device);
531 }
532
533 /* Standard TxCB. */
534 s->configuration[6] |= BIT(4);
535
536 /* Standard statistical counters. */
537 s->configuration[6] |= BIT(5);
538
539 if (s->stats_size == 80) {
540 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
541 if (s->configuration[6] & BIT(2)) {
542 /* TCO statistical counters. */
543 assert(s->configuration[6] & BIT(5));
544 } else {
545 if (s->configuration[6] & BIT(5)) {
546 /* No extended statistical counters, i82557 compatible. */
547 s->stats_size = 64;
548 } else {
549 /* i82558 compatible. */
550 s->stats_size = 76;
551 }
552 }
553 } else {
554 if (s->configuration[6] & BIT(5)) {
555 /* No extended statistical counters. */
556 s->stats_size = 64;
557 }
558 }
559 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
560
561 if (e100_device->power_management) {
562 /* Power Management Capabilities */
563 int cfg_offset = 0xdc;
564 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
565 cfg_offset, PCI_PM_SIZEOF);
566 assert(r >= 0);
567 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
568 #if 0 /* TODO: replace dummy code for power management emulation. */
569 /* TODO: Power Management Control / Status. */
570 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
571 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
572 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
573 #endif
574 }
575
576 #if EEPROM_SIZE > 0
577 if (device == i82557C || device == i82558B || device == i82559C) {
578 /*
579 TODO: get vendor id from EEPROM for i82557C or later.
580 TODO: get device id from EEPROM for i82557C or later.
581 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
582 TODO: header type is determined by EEPROM for i82559.
583 TODO: get subsystem id from EEPROM for i82557C or later.
584 TODO: get subsystem vendor id from EEPROM for i82557C or later.
585 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
586 TODO: capability pointer depends on EEPROM for i82558.
587 */
588 logout("Get device id and revision from EEPROM!!!\n");
589 }
590 #endif /* EEPROM_SIZE > 0 */
591 }
592
593 static void nic_selective_reset(EEPRO100State * s)
594 {
595 size_t i;
596 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
597 #if 0
598 eeprom93xx_reset(s->eeprom);
599 #endif
600 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
601 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
602 if (s->device == i82557B || s->device == i82557C)
603 eeprom_contents[5] = 0x0100;
604 eeprom_contents[EEPROM_PHY_ID] = 1;
605 uint16_t sum = 0;
606 for (i = 0; i < EEPROM_SIZE - 1; i++) {
607 sum += eeprom_contents[i];
608 }
609 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
610 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
611
612 memset(s->mem, 0, sizeof(s->mem));
613 e100_write_reg4(s, SCBCtrlMDI, BIT(21));
614
615 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
616 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
617 }
618
619 static void nic_reset(void *opaque)
620 {
621 EEPRO100State *s = opaque;
622 TRACE(OTHER, logout("%p\n", s));
623 /* TODO: Clearing of hash register for selective reset, too? */
624 memset(&s->mult[0], 0, sizeof(s->mult));
625 nic_selective_reset(s);
626 }
627
628 #if defined(DEBUG_EEPRO100)
629 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
630 "Command/Status",
631 "General Pointer",
632 "Port",
633 "EEPROM/Flash Control",
634 "MDI Control",
635 "Receive DMA Byte Count",
636 "Flow Control",
637 "General Status/Control"
638 };
639
640 static char *regname(uint32_t addr)
641 {
642 static char buf[32];
643 if (addr < PCI_IO_SIZE) {
644 const char *r = e100_reg[addr / 4];
645 if (r != 0) {
646 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
647 } else {
648 snprintf(buf, sizeof(buf), "0x%02x", addr);
649 }
650 } else {
651 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
652 }
653 return buf;
654 }
655 #endif /* DEBUG_EEPRO100 */
656
657 /*****************************************************************************
658 *
659 * Command emulation.
660 *
661 ****************************************************************************/
662
663 #if 0
664 static uint16_t eepro100_read_command(EEPRO100State * s)
665 {
666 uint16_t val = 0xffff;
667 TRACE(OTHER, logout("val=0x%04x\n", val));
668 return val;
669 }
670 #endif
671
672 /* Commands that can be put in a command list entry. */
673 enum commands {
674 CmdNOp = 0,
675 CmdIASetup = 1,
676 CmdConfigure = 2,
677 CmdMulticastList = 3,
678 CmdTx = 4,
679 CmdTDR = 5, /* load microcode */
680 CmdDump = 6,
681 CmdDiagnose = 7,
682
683 /* And some extra flags: */
684 CmdSuspend = 0x4000, /* Suspend after completion. */
685 CmdIntr = 0x2000, /* Interrupt after completion. */
686 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
687 };
688
689 static cu_state_t get_cu_state(EEPRO100State * s)
690 {
691 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
692 }
693
694 static void set_cu_state(EEPRO100State * s, cu_state_t state)
695 {
696 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
697 }
698
699 static ru_state_t get_ru_state(EEPRO100State * s)
700 {
701 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
702 }
703
704 static void set_ru_state(EEPRO100State * s, ru_state_t state)
705 {
706 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
707 }
708
709 static void dump_statistics(EEPRO100State * s)
710 {
711 /* Dump statistical data. Most data is never changed by the emulation
712 * and always 0, so we first just copy the whole block and then those
713 * values which really matter.
714 * Number of data should check configuration!!!
715 */
716 pci_dma_write(&s->dev, s->statsaddr, &s->statistics, s->stats_size);
717 stl_le_pci_dma(&s->dev, s->statsaddr + 0,
718 s->statistics.tx_good_frames);
719 stl_le_pci_dma(&s->dev, s->statsaddr + 36,
720 s->statistics.rx_good_frames);
721 stl_le_pci_dma(&s->dev, s->statsaddr + 48,
722 s->statistics.rx_resource_errors);
723 stl_le_pci_dma(&s->dev, s->statsaddr + 60,
724 s->statistics.rx_short_frame_errors);
725 #if 0
726 stw_le_pci_dma(&s->dev, s->statsaddr + 76, s->statistics.xmt_tco_frames);
727 stw_le_pci_dma(&s->dev, s->statsaddr + 78, s->statistics.rcv_tco_frames);
728 missing("CU dump statistical counters");
729 #endif
730 }
731
732 static void read_cb(EEPRO100State *s)
733 {
734 pci_dma_read(&s->dev, s->cb_address, &s->tx, sizeof(s->tx));
735 s->tx.status = le16_to_cpu(s->tx.status);
736 s->tx.command = le16_to_cpu(s->tx.command);
737 s->tx.link = le32_to_cpu(s->tx.link);
738 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
739 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
740 }
741
742 static void tx_command(EEPRO100State *s)
743 {
744 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
745 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
746 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
747 uint8_t buf[2600];
748 uint16_t size = 0;
749 uint32_t tbd_address = s->cb_address + 0x10;
750 TRACE(RXTX, logout
751 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
752 tbd_array, tcb_bytes, s->tx.tbd_count));
753
754 if (tcb_bytes > 2600) {
755 logout("TCB byte count too large, using 2600\n");
756 tcb_bytes = 2600;
757 }
758 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
759 logout
760 ("illegal values of TBD array address and TCB byte count!\n");
761 }
762 assert(tcb_bytes <= sizeof(buf));
763 while (size < tcb_bytes) {
764 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
765 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
766 #if 0
767 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
768 #endif
769 tbd_address += 8;
770 TRACE(RXTX, logout
771 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
772 tx_buffer_address, tx_buffer_size));
773 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
774 pci_dma_read(&s->dev, tx_buffer_address, &buf[size], tx_buffer_size);
775 size += tx_buffer_size;
776 }
777 if (tbd_array == 0xffffffff) {
778 /* Simplified mode. Was already handled by code above. */
779 } else {
780 /* Flexible mode. */
781 uint8_t tbd_count = 0;
782 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
783 /* Extended Flexible TCB. */
784 for (; tbd_count < 2; tbd_count++) {
785 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev,
786 tbd_address);
787 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev,
788 tbd_address + 4);
789 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev,
790 tbd_address + 6);
791 tbd_address += 8;
792 TRACE(RXTX, logout
793 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
794 tx_buffer_address, tx_buffer_size));
795 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
796 pci_dma_read(&s->dev, tx_buffer_address,
797 &buf[size], tx_buffer_size);
798 size += tx_buffer_size;
799 if (tx_buffer_el & 1) {
800 break;
801 }
802 }
803 }
804 tbd_address = tbd_array;
805 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
806 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
807 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
808 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
809 tbd_address += 8;
810 TRACE(RXTX, logout
811 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
812 tx_buffer_address, tx_buffer_size));
813 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
814 pci_dma_read(&s->dev, tx_buffer_address,
815 &buf[size], tx_buffer_size);
816 size += tx_buffer_size;
817 if (tx_buffer_el & 1) {
818 break;
819 }
820 }
821 }
822 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
823 qemu_send_packet(&s->nic->nc, buf, size);
824 s->statistics.tx_good_frames++;
825 /* Transmit with bad status would raise an CX/TNO interrupt.
826 * (82557 only). Emulation never has bad status. */
827 #if 0
828 eepro100_cx_interrupt(s);
829 #endif
830 }
831
832 static void set_multicast_list(EEPRO100State *s)
833 {
834 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
835 uint16_t i;
836 memset(&s->mult[0], 0, sizeof(s->mult));
837 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
838 for (i = 0; i < multicast_count; i += 6) {
839 uint8_t multicast_addr[6];
840 pci_dma_read(&s->dev, s->cb_address + 10 + i, multicast_addr, 6);
841 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
842 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
843 assert(mcast_idx < 64);
844 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
845 }
846 }
847
848 static void action_command(EEPRO100State *s)
849 {
850 for (;;) {
851 bool bit_el;
852 bool bit_s;
853 bool bit_i;
854 bool bit_nc;
855 uint16_t ok_status = STATUS_OK;
856 s->cb_address = s->cu_base + s->cu_offset;
857 read_cb(s);
858 bit_el = ((s->tx.command & COMMAND_EL) != 0);
859 bit_s = ((s->tx.command & COMMAND_S) != 0);
860 bit_i = ((s->tx.command & COMMAND_I) != 0);
861 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
862 #if 0
863 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
864 #endif
865 s->cu_offset = s->tx.link;
866 TRACE(OTHER,
867 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
868 s->tx.status, s->tx.command, s->tx.link));
869 switch (s->tx.command & COMMAND_CMD) {
870 case CmdNOp:
871 /* Do nothing. */
872 break;
873 case CmdIASetup:
874 pci_dma_read(&s->dev, s->cb_address + 8, &s->conf.macaddr.a[0], 6);
875 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
876 break;
877 case CmdConfigure:
878 pci_dma_read(&s->dev, s->cb_address + 8,
879 &s->configuration[0], sizeof(s->configuration));
880 TRACE(OTHER, logout("configuration: %s\n",
881 nic_dump(&s->configuration[0], 16)));
882 TRACE(OTHER, logout("configuration: %s\n",
883 nic_dump(&s->configuration[16],
884 ARRAY_SIZE(s->configuration) - 16)));
885 if (s->configuration[20] & BIT(6)) {
886 TRACE(OTHER, logout("Multiple IA bit\n"));
887 }
888 break;
889 case CmdMulticastList:
890 set_multicast_list(s);
891 break;
892 case CmdTx:
893 if (bit_nc) {
894 missing("CmdTx: NC = 0");
895 ok_status = 0;
896 break;
897 }
898 tx_command(s);
899 break;
900 case CmdTDR:
901 TRACE(OTHER, logout("load microcode\n"));
902 /* Starting with offset 8, the command contains
903 * 64 dwords microcode which we just ignore here. */
904 break;
905 case CmdDiagnose:
906 TRACE(OTHER, logout("diagnose\n"));
907 /* Make sure error flag is not set. */
908 s->tx.status = 0;
909 break;
910 default:
911 missing("undefined command");
912 ok_status = 0;
913 break;
914 }
915 /* Write new status. */
916 stw_le_pci_dma(&s->dev, s->cb_address,
917 s->tx.status | ok_status | STATUS_C);
918 if (bit_i) {
919 /* CU completed action. */
920 eepro100_cx_interrupt(s);
921 }
922 if (bit_el) {
923 /* CU becomes idle. Terminate command loop. */
924 set_cu_state(s, cu_idle);
925 eepro100_cna_interrupt(s);
926 break;
927 } else if (bit_s) {
928 /* CU becomes suspended. Terminate command loop. */
929 set_cu_state(s, cu_suspended);
930 eepro100_cna_interrupt(s);
931 break;
932 } else {
933 /* More entries in list. */
934 TRACE(OTHER, logout("CU list with at least one more entry\n"));
935 }
936 }
937 TRACE(OTHER, logout("CU list empty\n"));
938 /* List is empty. Now CU is idle or suspended. */
939 }
940
941 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
942 {
943 cu_state_t cu_state;
944 switch (val) {
945 case CU_NOP:
946 /* No operation. */
947 break;
948 case CU_START:
949 cu_state = get_cu_state(s);
950 if (cu_state != cu_idle && cu_state != cu_suspended) {
951 /* Intel documentation says that CU must be idle or suspended
952 * for the CU start command. */
953 logout("unexpected CU state is %u\n", cu_state);
954 }
955 set_cu_state(s, cu_active);
956 s->cu_offset = e100_read_reg4(s, SCBPointer);
957 action_command(s);
958 break;
959 case CU_RESUME:
960 if (get_cu_state(s) != cu_suspended) {
961 logout("bad CU resume from CU state %u\n", get_cu_state(s));
962 /* Workaround for bad Linux eepro100 driver which resumes
963 * from idle state. */
964 #if 0
965 missing("cu resume");
966 #endif
967 set_cu_state(s, cu_suspended);
968 }
969 if (get_cu_state(s) == cu_suspended) {
970 TRACE(OTHER, logout("CU resuming\n"));
971 set_cu_state(s, cu_active);
972 action_command(s);
973 }
974 break;
975 case CU_STATSADDR:
976 /* Load dump counters address. */
977 s->statsaddr = e100_read_reg4(s, SCBPointer);
978 TRACE(OTHER, logout("val=0x%02x (dump counters address)\n", val));
979 if (s->statsaddr & 3) {
980 /* Memory must be Dword aligned. */
981 logout("unaligned dump counters address\n");
982 /* Handling of misaligned addresses is undefined.
983 * Here we align the address by ignoring the lower bits. */
984 /* TODO: Test unaligned dump counter address on real hardware. */
985 s->statsaddr &= ~3;
986 }
987 break;
988 case CU_SHOWSTATS:
989 /* Dump statistical counters. */
990 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
991 dump_statistics(s);
992 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa005);
993 break;
994 case CU_CMD_BASE:
995 /* Load CU base. */
996 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
997 s->cu_base = e100_read_reg4(s, SCBPointer);
998 break;
999 case CU_DUMPSTATS:
1000 /* Dump and reset statistical counters. */
1001 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
1002 dump_statistics(s);
1003 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa007);
1004 memset(&s->statistics, 0, sizeof(s->statistics));
1005 break;
1006 case CU_SRESUME:
1007 /* CU static resume. */
1008 missing("CU static resume");
1009 break;
1010 default:
1011 missing("Undefined CU command");
1012 }
1013 }
1014
1015 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1016 {
1017 switch (val) {
1018 case RU_NOP:
1019 /* No operation. */
1020 break;
1021 case RX_START:
1022 /* RU start. */
1023 if (get_ru_state(s) != ru_idle) {
1024 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1025 #if 0
1026 assert(!"wrong RU state");
1027 #endif
1028 }
1029 set_ru_state(s, ru_ready);
1030 s->ru_offset = e100_read_reg4(s, SCBPointer);
1031 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1032 break;
1033 case RX_RESUME:
1034 /* Restart RU. */
1035 if (get_ru_state(s) != ru_suspended) {
1036 logout("RU state is %u, should be %u\n", get_ru_state(s),
1037 ru_suspended);
1038 #if 0
1039 assert(!"wrong RU state");
1040 #endif
1041 }
1042 set_ru_state(s, ru_ready);
1043 break;
1044 case RU_ABORT:
1045 /* RU abort. */
1046 if (get_ru_state(s) == ru_ready) {
1047 eepro100_rnr_interrupt(s);
1048 }
1049 set_ru_state(s, ru_idle);
1050 break;
1051 case RX_ADDR_LOAD:
1052 /* Load RU base. */
1053 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1054 s->ru_base = e100_read_reg4(s, SCBPointer);
1055 break;
1056 default:
1057 logout("val=0x%02x (undefined RU command)\n", val);
1058 missing("Undefined SU command");
1059 }
1060 }
1061
1062 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1063 {
1064 eepro100_ru_command(s, val & 0x0f);
1065 eepro100_cu_command(s, val & 0xf0);
1066 if ((val) == 0) {
1067 TRACE(OTHER, logout("val=0x%02x\n", val));
1068 }
1069 /* Clear command byte after command was accepted. */
1070 s->mem[SCBCmd] = 0;
1071 }
1072
1073 /*****************************************************************************
1074 *
1075 * EEPROM emulation.
1076 *
1077 ****************************************************************************/
1078
1079 #define EEPROM_CS 0x02
1080 #define EEPROM_SK 0x01
1081 #define EEPROM_DI 0x04
1082 #define EEPROM_DO 0x08
1083
1084 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1085 {
1086 uint16_t val = e100_read_reg2(s, SCBeeprom);
1087 if (eeprom93xx_read(s->eeprom)) {
1088 val |= EEPROM_DO;
1089 } else {
1090 val &= ~EEPROM_DO;
1091 }
1092 TRACE(EEPROM, logout("val=0x%04x\n", val));
1093 return val;
1094 }
1095
1096 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1097 {
1098 TRACE(EEPROM, logout("val=0x%02x\n", val));
1099
1100 /* mask unwritable bits */
1101 #if 0
1102 val = SET_MASKED(val, 0x31, eeprom->value);
1103 #endif
1104
1105 int eecs = ((val & EEPROM_CS) != 0);
1106 int eesk = ((val & EEPROM_SK) != 0);
1107 int eedi = ((val & EEPROM_DI) != 0);
1108 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1109 }
1110
1111 /*****************************************************************************
1112 *
1113 * MDI emulation.
1114 *
1115 ****************************************************************************/
1116
1117 #if defined(DEBUG_EEPRO100)
1118 static const char * const mdi_op_name[] = {
1119 "opcode 0",
1120 "write",
1121 "read",
1122 "opcode 3"
1123 };
1124
1125 static const char * const mdi_reg_name[] = {
1126 "Control",
1127 "Status",
1128 "PHY Identification (Word 1)",
1129 "PHY Identification (Word 2)",
1130 "Auto-Negotiation Advertisement",
1131 "Auto-Negotiation Link Partner Ability",
1132 "Auto-Negotiation Expansion"
1133 };
1134
1135 static const char *reg2name(uint8_t reg)
1136 {
1137 static char buffer[10];
1138 const char *p = buffer;
1139 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1140 p = mdi_reg_name[reg];
1141 } else {
1142 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1143 }
1144 return p;
1145 }
1146 #endif /* DEBUG_EEPRO100 */
1147
1148 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1149 {
1150 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
1151
1152 #ifdef DEBUG_EEPRO100
1153 uint8_t raiseint = (val & BIT(29)) >> 29;
1154 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1155 uint8_t phy = (val & BITS(25, 21)) >> 21;
1156 uint8_t reg = (val & BITS(20, 16)) >> 16;
1157 uint16_t data = (val & BITS(15, 0));
1158 #endif
1159 /* Emulation takes no time to finish MDI transaction. */
1160 val |= BIT(28);
1161 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1162 val, raiseint, mdi_op_name[opcode], phy,
1163 reg2name(reg), data));
1164 return val;
1165 }
1166
1167 static void eepro100_write_mdi(EEPRO100State *s)
1168 {
1169 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
1170 uint8_t raiseint = (val & BIT(29)) >> 29;
1171 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1172 uint8_t phy = (val & BITS(25, 21)) >> 21;
1173 uint8_t reg = (val & BITS(20, 16)) >> 16;
1174 uint16_t data = (val & BITS(15, 0));
1175 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1176 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1177 if (phy != 1) {
1178 /* Unsupported PHY address. */
1179 #if 0
1180 logout("phy must be 1 but is %u\n", phy);
1181 #endif
1182 data = 0;
1183 } else if (opcode != 1 && opcode != 2) {
1184 /* Unsupported opcode. */
1185 logout("opcode must be 1 or 2 but is %u\n", opcode);
1186 data = 0;
1187 } else if (reg > 6) {
1188 /* Unsupported register. */
1189 logout("register must be 0...6 but is %u\n", reg);
1190 data = 0;
1191 } else {
1192 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1193 val, raiseint, mdi_op_name[opcode], phy,
1194 reg2name(reg), data));
1195 if (opcode == 1) {
1196 /* MDI write */
1197 switch (reg) {
1198 case 0: /* Control Register */
1199 if (data & 0x8000) {
1200 /* Reset status and control registers to default. */
1201 s->mdimem[0] = eepro100_mdi_default[0];
1202 s->mdimem[1] = eepro100_mdi_default[1];
1203 data = s->mdimem[reg];
1204 } else {
1205 /* Restart Auto Configuration = Normal Operation */
1206 data &= ~0x0200;
1207 }
1208 break;
1209 case 1: /* Status Register */
1210 missing("not writable");
1211 data = s->mdimem[reg];
1212 break;
1213 case 2: /* PHY Identification Register (Word 1) */
1214 case 3: /* PHY Identification Register (Word 2) */
1215 missing("not implemented");
1216 break;
1217 case 4: /* Auto-Negotiation Advertisement Register */
1218 case 5: /* Auto-Negotiation Link Partner Ability Register */
1219 break;
1220 case 6: /* Auto-Negotiation Expansion Register */
1221 default:
1222 missing("not implemented");
1223 }
1224 s->mdimem[reg] = data;
1225 } else if (opcode == 2) {
1226 /* MDI read */
1227 switch (reg) {
1228 case 0: /* Control Register */
1229 if (data & 0x8000) {
1230 /* Reset status and control registers to default. */
1231 s->mdimem[0] = eepro100_mdi_default[0];
1232 s->mdimem[1] = eepro100_mdi_default[1];
1233 }
1234 break;
1235 case 1: /* Status Register */
1236 s->mdimem[reg] |= 0x0020;
1237 break;
1238 case 2: /* PHY Identification Register (Word 1) */
1239 case 3: /* PHY Identification Register (Word 2) */
1240 case 4: /* Auto-Negotiation Advertisement Register */
1241 break;
1242 case 5: /* Auto-Negotiation Link Partner Ability Register */
1243 s->mdimem[reg] = 0x41fe;
1244 break;
1245 case 6: /* Auto-Negotiation Expansion Register */
1246 s->mdimem[reg] = 0x0001;
1247 break;
1248 }
1249 data = s->mdimem[reg];
1250 }
1251 /* Emulation takes no time to finish MDI transaction.
1252 * Set MDI bit in SCB status register. */
1253 s->mem[SCBAck] |= 0x08;
1254 val |= BIT(28);
1255 if (raiseint) {
1256 eepro100_mdi_interrupt(s);
1257 }
1258 }
1259 val = (val & 0xffff0000) + data;
1260 e100_write_reg4(s, SCBCtrlMDI, val);
1261 }
1262
1263 /*****************************************************************************
1264 *
1265 * Port emulation.
1266 *
1267 ****************************************************************************/
1268
1269 #define PORT_SOFTWARE_RESET 0
1270 #define PORT_SELFTEST 1
1271 #define PORT_SELECTIVE_RESET 2
1272 #define PORT_DUMP 3
1273 #define PORT_SELECTION_MASK 3
1274
1275 typedef struct {
1276 uint32_t st_sign; /* Self Test Signature */
1277 uint32_t st_result; /* Self Test Results */
1278 } eepro100_selftest_t;
1279
1280 static uint32_t eepro100_read_port(EEPRO100State * s)
1281 {
1282 return 0;
1283 }
1284
1285 static void eepro100_write_port(EEPRO100State *s)
1286 {
1287 uint32_t val = e100_read_reg4(s, SCBPort);
1288 uint32_t address = (val & ~PORT_SELECTION_MASK);
1289 uint8_t selection = (val & PORT_SELECTION_MASK);
1290 switch (selection) {
1291 case PORT_SOFTWARE_RESET:
1292 nic_reset(s);
1293 break;
1294 case PORT_SELFTEST:
1295 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1296 eepro100_selftest_t data;
1297 pci_dma_read(&s->dev, address, (uint8_t *) &data, sizeof(data));
1298 data.st_sign = 0xffffffff;
1299 data.st_result = 0;
1300 pci_dma_write(&s->dev, address, (uint8_t *) &data, sizeof(data));
1301 break;
1302 case PORT_SELECTIVE_RESET:
1303 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1304 nic_selective_reset(s);
1305 break;
1306 default:
1307 logout("val=0x%08x\n", val);
1308 missing("unknown port selection");
1309 }
1310 }
1311
1312 /*****************************************************************************
1313 *
1314 * General hardware emulation.
1315 *
1316 ****************************************************************************/
1317
1318 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1319 {
1320 uint8_t val = 0;
1321 if (addr <= sizeof(s->mem) - sizeof(val)) {
1322 val = s->mem[addr];
1323 }
1324
1325 switch (addr) {
1326 case SCBStatus:
1327 case SCBAck:
1328 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1329 break;
1330 case SCBCmd:
1331 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1332 #if 0
1333 val = eepro100_read_command(s);
1334 #endif
1335 break;
1336 case SCBIntmask:
1337 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1338 break;
1339 case SCBPort + 3:
1340 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1341 break;
1342 case SCBeeprom:
1343 val = eepro100_read_eeprom(s);
1344 break;
1345 case SCBCtrlMDI:
1346 case SCBCtrlMDI + 1:
1347 case SCBCtrlMDI + 2:
1348 case SCBCtrlMDI + 3:
1349 val = (uint8_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1350 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1351 break;
1352 case SCBpmdr: /* Power Management Driver Register */
1353 val = 0;
1354 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1355 break;
1356 case SCBgctrl: /* General Control Register */
1357 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1358 break;
1359 case SCBgstat: /* General Status Register */
1360 /* 100 Mbps full duplex, valid link */
1361 val = 0x07;
1362 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1363 break;
1364 default:
1365 logout("addr=%s val=0x%02x\n", regname(addr), val);
1366 missing("unknown byte read");
1367 }
1368 return val;
1369 }
1370
1371 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1372 {
1373 uint16_t val = 0;
1374 if (addr <= sizeof(s->mem) - sizeof(val)) {
1375 val = e100_read_reg2(s, addr);
1376 }
1377
1378 switch (addr) {
1379 case SCBStatus:
1380 case SCBCmd:
1381 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1382 break;
1383 case SCBeeprom:
1384 val = eepro100_read_eeprom(s);
1385 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1386 break;
1387 case SCBCtrlMDI:
1388 case SCBCtrlMDI + 2:
1389 val = (uint16_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1390 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1391 break;
1392 default:
1393 logout("addr=%s val=0x%04x\n", regname(addr), val);
1394 missing("unknown word read");
1395 }
1396 return val;
1397 }
1398
1399 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1400 {
1401 uint32_t val = 0;
1402 if (addr <= sizeof(s->mem) - sizeof(val)) {
1403 val = e100_read_reg4(s, addr);
1404 }
1405
1406 switch (addr) {
1407 case SCBStatus:
1408 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1409 break;
1410 case SCBPointer:
1411 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1412 break;
1413 case SCBPort:
1414 val = eepro100_read_port(s);
1415 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1416 break;
1417 case SCBflash:
1418 val = eepro100_read_eeprom(s);
1419 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1420 break;
1421 case SCBCtrlMDI:
1422 val = eepro100_read_mdi(s);
1423 break;
1424 default:
1425 logout("addr=%s val=0x%08x\n", regname(addr), val);
1426 missing("unknown longword read");
1427 }
1428 return val;
1429 }
1430
1431 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1432 {
1433 /* SCBStatus is readonly. */
1434 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1435 s->mem[addr] = val;
1436 }
1437
1438 switch (addr) {
1439 case SCBStatus:
1440 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1441 break;
1442 case SCBAck:
1443 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1444 eepro100_acknowledge(s);
1445 break;
1446 case SCBCmd:
1447 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1448 eepro100_write_command(s, val);
1449 break;
1450 case SCBIntmask:
1451 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1452 if (val & BIT(1)) {
1453 eepro100_swi_interrupt(s);
1454 }
1455 eepro100_interrupt(s, 0);
1456 break;
1457 case SCBPointer:
1458 case SCBPointer + 1:
1459 case SCBPointer + 2:
1460 case SCBPointer + 3:
1461 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1462 break;
1463 case SCBPort:
1464 case SCBPort + 1:
1465 case SCBPort + 2:
1466 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1467 break;
1468 case SCBPort + 3:
1469 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1470 eepro100_write_port(s);
1471 break;
1472 case SCBFlow: /* does not exist on 82557 */
1473 case SCBFlow + 1:
1474 case SCBFlow + 2:
1475 case SCBpmdr: /* does not exist on 82557 */
1476 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1477 break;
1478 case SCBeeprom:
1479 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1480 eepro100_write_eeprom(s->eeprom, val);
1481 break;
1482 case SCBCtrlMDI:
1483 case SCBCtrlMDI + 1:
1484 case SCBCtrlMDI + 2:
1485 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1486 break;
1487 case SCBCtrlMDI + 3:
1488 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1489 eepro100_write_mdi(s);
1490 break;
1491 default:
1492 logout("addr=%s val=0x%02x\n", regname(addr), val);
1493 missing("unknown byte write");
1494 }
1495 }
1496
1497 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1498 {
1499 /* SCBStatus is readonly. */
1500 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1501 e100_write_reg2(s, addr, val);
1502 }
1503
1504 switch (addr) {
1505 case SCBStatus:
1506 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1507 s->mem[SCBAck] = (val >> 8);
1508 eepro100_acknowledge(s);
1509 break;
1510 case SCBCmd:
1511 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1512 eepro100_write_command(s, val);
1513 eepro100_write1(s, SCBIntmask, val >> 8);
1514 break;
1515 case SCBPointer:
1516 case SCBPointer + 2:
1517 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1518 break;
1519 case SCBPort:
1520 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1521 break;
1522 case SCBPort + 2:
1523 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1524 eepro100_write_port(s);
1525 break;
1526 case SCBeeprom:
1527 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1528 eepro100_write_eeprom(s->eeprom, val);
1529 break;
1530 case SCBCtrlMDI:
1531 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1532 break;
1533 case SCBCtrlMDI + 2:
1534 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1535 eepro100_write_mdi(s);
1536 break;
1537 default:
1538 logout("addr=%s val=0x%04x\n", regname(addr), val);
1539 missing("unknown word write");
1540 }
1541 }
1542
1543 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1544 {
1545 if (addr <= sizeof(s->mem) - sizeof(val)) {
1546 e100_write_reg4(s, addr, val);
1547 }
1548
1549 switch (addr) {
1550 case SCBPointer:
1551 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1552 break;
1553 case SCBPort:
1554 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1555 eepro100_write_port(s);
1556 break;
1557 case SCBflash:
1558 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1559 val = val >> 16;
1560 eepro100_write_eeprom(s->eeprom, val);
1561 break;
1562 case SCBCtrlMDI:
1563 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1564 eepro100_write_mdi(s);
1565 break;
1566 default:
1567 logout("addr=%s val=0x%08x\n", regname(addr), val);
1568 missing("unknown longword write");
1569 }
1570 }
1571
1572 static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
1573 unsigned size)
1574 {
1575 EEPRO100State *s = opaque;
1576
1577 switch (size) {
1578 case 1: return eepro100_read1(s, addr);
1579 case 2: return eepro100_read2(s, addr);
1580 case 4: return eepro100_read4(s, addr);
1581 default: abort();
1582 }
1583 }
1584
1585 static void eepro100_write(void *opaque, target_phys_addr_t addr,
1586 uint64_t data, unsigned size)
1587 {
1588 EEPRO100State *s = opaque;
1589
1590 switch (size) {
1591 case 1: return eepro100_write1(s, addr, data);
1592 case 2: return eepro100_write2(s, addr, data);
1593 case 4: return eepro100_write4(s, addr, data);
1594 default: abort();
1595 }
1596 }
1597
1598 static const MemoryRegionOps eepro100_ops = {
1599 .read = eepro100_read,
1600 .write = eepro100_write,
1601 .endianness = DEVICE_LITTLE_ENDIAN,
1602 };
1603
1604 static int nic_can_receive(VLANClientState *nc)
1605 {
1606 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1607 TRACE(RXTX, logout("%p\n", s));
1608 return get_ru_state(s) == ru_ready;
1609 #if 0
1610 return !eepro100_buffer_full(s);
1611 #endif
1612 }
1613
1614 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1615 {
1616 /* TODO:
1617 * - Magic packets should set bit 30 in power management driver register.
1618 * - Interesting packets should set bit 29 in power management driver register.
1619 */
1620 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1621 uint16_t rfd_status = 0xa000;
1622 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1623 uint8_t min_buf[60];
1624 #endif
1625 static const uint8_t broadcast_macaddr[6] =
1626 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1627
1628 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1629 /* Pad to minimum Ethernet frame length */
1630 if (size < sizeof(min_buf)) {
1631 memcpy(min_buf, buf, size);
1632 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1633 buf = min_buf;
1634 size = sizeof(min_buf);
1635 }
1636 #endif
1637
1638 if (s->configuration[8] & 0x80) {
1639 /* CSMA is disabled. */
1640 logout("%p received while CSMA is disabled\n", s);
1641 return -1;
1642 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1643 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1644 /* Short frame and configuration byte 7/0 (discard short receive) set:
1645 * Short frame is discarded */
1646 logout("%p received short frame (%zu byte)\n", s, size);
1647 s->statistics.rx_short_frame_errors++;
1648 return -1;
1649 #endif
1650 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1651 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1652 * Long frames are discarded. */
1653 logout("%p received long frame (%zu byte), ignored\n", s, size);
1654 return -1;
1655 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1656 /* Frame matches individual address. */
1657 /* TODO: check configuration byte 15/4 (ignore U/L). */
1658 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1659 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1660 /* Broadcast frame. */
1661 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1662 rfd_status |= 0x0002;
1663 } else if (buf[0] & 0x01) {
1664 /* Multicast frame. */
1665 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1666 if (s->configuration[21] & BIT(3)) {
1667 /* Multicast all bit is set, receive all multicast frames. */
1668 } else {
1669 unsigned mcast_idx = compute_mcast_idx(buf);
1670 assert(mcast_idx < 64);
1671 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1672 /* Multicast frame is allowed in hash table. */
1673 } else if (s->configuration[15] & BIT(0)) {
1674 /* Promiscuous: receive all. */
1675 rfd_status |= 0x0004;
1676 } else {
1677 TRACE(RXTX, logout("%p multicast ignored\n", s));
1678 return -1;
1679 }
1680 }
1681 /* TODO: Next not for promiscuous mode? */
1682 rfd_status |= 0x0002;
1683 } else if (s->configuration[15] & BIT(0)) {
1684 /* Promiscuous: receive all. */
1685 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1686 rfd_status |= 0x0004;
1687 } else if (s->configuration[20] & BIT(6)) {
1688 /* Multiple IA bit set. */
1689 unsigned mcast_idx = compute_mcast_idx(buf);
1690 assert(mcast_idx < 64);
1691 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1692 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
1693 } else {
1694 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
1695 return -1;
1696 }
1697 } else {
1698 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1699 nic_dump(buf, size)));
1700 return size;
1701 }
1702
1703 if (get_ru_state(s) != ru_ready) {
1704 /* No resources available. */
1705 logout("no resources, state=%u\n", get_ru_state(s));
1706 /* TODO: RNR interrupt only at first failed frame? */
1707 eepro100_rnr_interrupt(s);
1708 s->statistics.rx_resource_errors++;
1709 #if 0
1710 assert(!"no resources");
1711 #endif
1712 return -1;
1713 }
1714 /* !!! */
1715 eepro100_rx_t rx;
1716 pci_dma_read(&s->dev, s->ru_base + s->ru_offset,
1717 &rx, sizeof(eepro100_rx_t));
1718 uint16_t rfd_command = le16_to_cpu(rx.command);
1719 uint16_t rfd_size = le16_to_cpu(rx.size);
1720
1721 if (size > rfd_size) {
1722 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1723 "(%zu bytes); data truncated\n", rfd_size, size);
1724 size = rfd_size;
1725 }
1726 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1727 if (size < 64) {
1728 rfd_status |= 0x0080;
1729 }
1730 #endif
1731 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1732 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1733 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1734 offsetof(eepro100_rx_t, status), rfd_status);
1735 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1736 offsetof(eepro100_rx_t, count), size);
1737 /* Early receive interrupt not supported. */
1738 #if 0
1739 eepro100_er_interrupt(s);
1740 #endif
1741 /* Receive CRC Transfer not supported. */
1742 if (s->configuration[18] & BIT(2)) {
1743 missing("Receive CRC Transfer");
1744 return -1;
1745 }
1746 /* TODO: check stripping enable bit. */
1747 #if 0
1748 assert(!(s->configuration[17] & BIT(0)));
1749 #endif
1750 pci_dma_write(&s->dev, s->ru_base + s->ru_offset +
1751 sizeof(eepro100_rx_t), buf, size);
1752 s->statistics.rx_good_frames++;
1753 eepro100_fr_interrupt(s);
1754 s->ru_offset = le32_to_cpu(rx.link);
1755 if (rfd_command & COMMAND_EL) {
1756 /* EL bit is set, so this was the last frame. */
1757 logout("receive: Running out of frames\n");
1758 set_ru_state(s, ru_suspended);
1759 }
1760 if (rfd_command & COMMAND_S) {
1761 /* S bit is set. */
1762 set_ru_state(s, ru_suspended);
1763 }
1764 return size;
1765 }
1766
1767 static const VMStateDescription vmstate_eepro100 = {
1768 .version_id = 3,
1769 .minimum_version_id = 2,
1770 .minimum_version_id_old = 2,
1771 .fields = (VMStateField []) {
1772 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1773 VMSTATE_UNUSED(32),
1774 VMSTATE_BUFFER(mult, EEPRO100State),
1775 VMSTATE_BUFFER(mem, EEPRO100State),
1776 /* Save all members of struct between scb_stat and mem. */
1777 VMSTATE_UINT8(scb_stat, EEPRO100State),
1778 VMSTATE_UINT8(int_stat, EEPRO100State),
1779 VMSTATE_UNUSED(3*4),
1780 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1781 VMSTATE_UNUSED(19*4),
1782 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1783 /* The eeprom should be saved and restored by its own routines. */
1784 VMSTATE_UINT32(device, EEPRO100State),
1785 /* TODO check device. */
1786 VMSTATE_UINT32(cu_base, EEPRO100State),
1787 VMSTATE_UINT32(cu_offset, EEPRO100State),
1788 VMSTATE_UINT32(ru_base, EEPRO100State),
1789 VMSTATE_UINT32(ru_offset, EEPRO100State),
1790 VMSTATE_UINT32(statsaddr, EEPRO100State),
1791 /* Save eepro100_stats_t statistics. */
1792 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1793 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1794 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1795 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1796 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1797 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1798 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1799 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1800 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1801 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1802 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1803 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1804 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1805 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1806 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1807 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1808 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1809 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1810 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1811 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1812 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1813 /* Configuration bytes. */
1814 VMSTATE_BUFFER(configuration, EEPRO100State),
1815 VMSTATE_END_OF_LIST()
1816 }
1817 };
1818
1819 static void nic_cleanup(VLANClientState *nc)
1820 {
1821 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1822
1823 s->nic = NULL;
1824 }
1825
1826 static int pci_nic_uninit(PCIDevice *pci_dev)
1827 {
1828 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1829
1830 memory_region_destroy(&s->mmio_bar);
1831 memory_region_destroy(&s->io_bar);
1832 memory_region_destroy(&s->flash_bar);
1833 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
1834 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
1835 qemu_del_vlan_client(&s->nic->nc);
1836 return 0;
1837 }
1838
1839 static NetClientInfo net_eepro100_info = {
1840 .type = NET_CLIENT_TYPE_NIC,
1841 .size = sizeof(NICState),
1842 .can_receive = nic_can_receive,
1843 .receive = nic_receive,
1844 .cleanup = nic_cleanup,
1845 };
1846
1847 static int e100_nic_init(PCIDevice *pci_dev)
1848 {
1849 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1850 E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev,
1851 pci_dev->qdev.info);
1852
1853 TRACE(OTHER, logout("\n"));
1854
1855 s->device = e100_device->device;
1856
1857 e100_pci_reset(s, e100_device);
1858
1859 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1860 * i82559 and later support 64 or 256 word EEPROM. */
1861 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
1862
1863 /* Handler for memory-mapped I/O */
1864 memory_region_init_io(&s->mmio_bar, &eepro100_ops, s, "eepro100-mmio",
1865 PCI_MEM_SIZE);
1866 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->mmio_bar);
1867 memory_region_init_io(&s->io_bar, &eepro100_ops, s, "eepro100-io",
1868 PCI_IO_SIZE);
1869 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1870 /* FIXME: flash aliases to mmio?! */
1871 memory_region_init_io(&s->flash_bar, &eepro100_ops, s, "eepro100-flash",
1872 PCI_FLASH_SIZE);
1873 pci_register_bar(&s->dev, 2, 0, &s->flash_bar);
1874
1875 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1876 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1877
1878 nic_reset(s);
1879
1880 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1881 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1882
1883 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1884 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1885
1886 qemu_register_reset(nic_reset, s);
1887
1888 s->vmstate = g_malloc(sizeof(vmstate_eepro100));
1889 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1890 s->vmstate->name = s->nic->nc.model;
1891 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
1892
1893 add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1894
1895 return 0;
1896 }
1897
1898 static E100PCIDeviceInfo e100_devices[] = {
1899 {
1900 .pci.qdev.name = "i82550",
1901 .pci.qdev.desc = "Intel i82550 Ethernet",
1902 .device = i82550,
1903 /* TODO: check device id. */
1904 .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
1905 /* Revision ID: 0x0c, 0x0d, 0x0e. */
1906 .pci.revision = 0x0e,
1907 /* TODO: check size of statistical counters. */
1908 .stats_size = 80,
1909 /* TODO: check extended tcb support. */
1910 .has_extended_tcb_support = true,
1911 .power_management = true,
1912 },{
1913 .pci.qdev.name = "i82551",
1914 .pci.qdev.desc = "Intel i82551 Ethernet",
1915 .device = i82551,
1916 .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
1917 /* Revision ID: 0x0f, 0x10. */
1918 .pci.revision = 0x0f,
1919 /* TODO: check size of statistical counters. */
1920 .stats_size = 80,
1921 .has_extended_tcb_support = true,
1922 .power_management = true,
1923 },{
1924 .pci.qdev.name = "i82557a",
1925 .pci.qdev.desc = "Intel i82557A Ethernet",
1926 .device = i82557A,
1927 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1928 .pci.revision = 0x01,
1929 .power_management = false,
1930 },{
1931 .pci.qdev.name = "i82557b",
1932 .pci.qdev.desc = "Intel i82557B Ethernet",
1933 .device = i82557B,
1934 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1935 .pci.revision = 0x02,
1936 .power_management = false,
1937 },{
1938 .pci.qdev.name = "i82557c",
1939 .pci.qdev.desc = "Intel i82557C Ethernet",
1940 .device = i82557C,
1941 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1942 .pci.revision = 0x03,
1943 .power_management = false,
1944 },{
1945 .pci.qdev.name = "i82558a",
1946 .pci.qdev.desc = "Intel i82558A Ethernet",
1947 .device = i82558A,
1948 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1949 .pci.revision = 0x04,
1950 .stats_size = 76,
1951 .has_extended_tcb_support = true,
1952 .power_management = true,
1953 },{
1954 .pci.qdev.name = "i82558b",
1955 .pci.qdev.desc = "Intel i82558B Ethernet",
1956 .device = i82558B,
1957 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1958 .pci.revision = 0x05,
1959 .stats_size = 76,
1960 .has_extended_tcb_support = true,
1961 .power_management = true,
1962 },{
1963 .pci.qdev.name = "i82559a",
1964 .pci.qdev.desc = "Intel i82559A Ethernet",
1965 .device = i82559A,
1966 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1967 .pci.revision = 0x06,
1968 .stats_size = 80,
1969 .has_extended_tcb_support = true,
1970 .power_management = true,
1971 },{
1972 .pci.qdev.name = "i82559b",
1973 .pci.qdev.desc = "Intel i82559B Ethernet",
1974 .device = i82559B,
1975 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1976 .pci.revision = 0x07,
1977 .stats_size = 80,
1978 .has_extended_tcb_support = true,
1979 .power_management = true,
1980 },{
1981 .pci.qdev.name = "i82559c",
1982 .pci.qdev.desc = "Intel i82559C Ethernet",
1983 .device = i82559C,
1984 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1985 #if 0
1986 .pci.revision = 0x08,
1987 #endif
1988 /* TODO: Windows wants revision id 0x0c. */
1989 .pci.revision = 0x0c,
1990 #if EEPROM_SIZE > 0
1991 .pci.subsystem_vendor_id = PCI_VENDOR_ID_INTEL,
1992 .pci.subsystem_id = 0x0040,
1993 #endif
1994 .stats_size = 80,
1995 .has_extended_tcb_support = true,
1996 .power_management = true,
1997 },{
1998 .pci.qdev.name = "i82559er",
1999 .pci.qdev.desc = "Intel i82559ER Ethernet",
2000 .device = i82559ER,
2001 .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
2002 .pci.revision = 0x09,
2003 .stats_size = 80,
2004 .has_extended_tcb_support = true,
2005 .power_management = true,
2006 },{
2007 .pci.qdev.name = "i82562",
2008 .pci.qdev.desc = "Intel i82562 Ethernet",
2009 .device = i82562,
2010 /* TODO: check device id. */
2011 .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
2012 /* TODO: wrong revision id. */
2013 .pci.revision = 0x0e,
2014 .stats_size = 80,
2015 .has_extended_tcb_support = true,
2016 .power_management = true,
2017 },{
2018 /* Toshiba Tecra 8200. */
2019 .pci.qdev.name = "i82801",
2020 .pci.qdev.desc = "Intel i82801 Ethernet",
2021 .device = i82801,
2022 .pci.device_id = 0x2449,
2023 .pci.revision = 0x03,
2024 .stats_size = 80,
2025 .has_extended_tcb_support = true,
2026 .power_management = true,
2027 }
2028 };
2029
2030 static Property e100_properties[] = {
2031 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2032 DEFINE_PROP_END_OF_LIST(),
2033 };
2034
2035 static void eepro100_register_devices(void)
2036 {
2037 size_t i;
2038 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2039 PCIDeviceInfo *pci_dev = &e100_devices[i].pci;
2040 /* We use the same rom file for all device ids.
2041 QEMU fixes the device id during rom load. */
2042 pci_dev->vendor_id = PCI_VENDOR_ID_INTEL;
2043 pci_dev->class_id = PCI_CLASS_NETWORK_ETHERNET;
2044 pci_dev->romfile = "pxe-eepro100.rom";
2045 pci_dev->init = e100_nic_init;
2046 pci_dev->exit = pci_nic_uninit;
2047 pci_dev->qdev.props = e100_properties;
2048 pci_dev->qdev.size = sizeof(EEPRO100State);
2049 pci_qdev_register(pci_dev);
2050 }
2051 }
2052
2053 device_init(eepro100_register_devices)
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