hw/ppc/spapr_pci_vfio.c

   1 /*
   2  * QEMU sPAPR PCI host for VFIO
   3  *
   4  * Copyright (c) 2011-2014 Alexey Kardashevskiy, IBM Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License,
   9  *  or (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/ppc/spapr.h"
  22 #include "hw/pci-host/spapr.h"
  23 #include "hw/pci/msix.h"
  24 #include "linux/vfio.h"
  25 #include "hw/vfio/vfio.h"
  26 #include "qemu/error-report.h"
  27
  28 #define TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE "spapr-pci-vfio-host-bridge"
  29
  30 #define SPAPR_PCI_VFIO_HOST_BRIDGE(obj) \
  31     OBJECT_CHECK(sPAPRPHBVFIOState, (obj), TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE)
  32
  33 typedef struct sPAPRPHBVFIOState sPAPRPHBVFIOState;
  34
  35 struct sPAPRPHBVFIOState {
  36     sPAPRPHBState phb;
  37
  38     int32_t iommugroupid;
  39 };
  40
  41 static Property spapr_phb_vfio_properties[] = {
  42     DEFINE_PROP_INT32("iommu", sPAPRPHBVFIOState, iommugroupid, -1),
  43     DEFINE_PROP_END_OF_LIST(),
  44 };
  45
  46 static void spapr_phb_vfio_instance_init(Object *obj)
  47 {
  48     error_report("spapr-pci-vfio-host-bridge is deprecated");
  49 }
  50
  51 bool spapr_phb_eeh_available(sPAPRPHBState *sphb)
  52 {
  53     return vfio_eeh_as_ok(&sphb->iommu_as);
  54 }
  55
  56 static void spapr_phb_vfio_eeh_reenable(sPAPRPHBState *sphb)
  57 {
  58     vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_ENABLE);
  59 }
  60
  61 void spapr_phb_vfio_reset(DeviceState *qdev)
  62 {
  63     /*
  64      * The PE might be in frozen state. To reenable the EEH
  65      * functionality on it will clean the frozen state, which
  66      * ensures that the contained PCI devices will work properly
  67      * after reboot.
  68      */
  69     spapr_phb_vfio_eeh_reenable(SPAPR_PCI_HOST_BRIDGE(qdev));
  70 }
  71
  72 int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
  73                                   unsigned int addr, int option)
  74 {
  75     uint32_t op;
  76     int ret;
  77
  78     switch (option) {
  79     case RTAS_EEH_DISABLE:
  80         op = VFIO_EEH_PE_DISABLE;
  81         break;
  82     case RTAS_EEH_ENABLE: {
  83         PCIHostState *phb;
  84         PCIDevice *pdev;
  85
  86         /*
  87          * The EEH functionality is enabled on basis of PCI device,
  88          * instead of PE. We need check the validity of the PCI
  89          * device address.
  90          */
  91         phb = PCI_HOST_BRIDGE(sphb);
  92         pdev = pci_find_device(phb->bus,
  93                                (addr >> 16) & 0xFF, (addr >> 8) & 0xFF);
  94         if (!pdev || !object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
  95             return RTAS_OUT_PARAM_ERROR;
  96         }
  97
  98         op = VFIO_EEH_PE_ENABLE;
  99         break;
 100     }
 101     case RTAS_EEH_THAW_IO:
 102         op = VFIO_EEH_PE_UNFREEZE_IO;
 103         break;
 104     case RTAS_EEH_THAW_DMA:
 105         op = VFIO_EEH_PE_UNFREEZE_DMA;
 106         break;
 107     default:
 108         return RTAS_OUT_PARAM_ERROR;
 109     }
 110
 111     ret = vfio_eeh_as_op(&sphb->iommu_as, op);
 112     if (ret < 0) {
 113         return RTAS_OUT_HW_ERROR;
 114     }
 115
 116     return RTAS_OUT_SUCCESS;
 117 }
 118
 119 int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state)
 120 {
 121     int ret;
 122
 123     ret = vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_GET_STATE);
 124     if (ret < 0) {
 125         return RTAS_OUT_PARAM_ERROR;
 126     }
 127
 128     *state = ret;
 129     return RTAS_OUT_SUCCESS;
 130 }
 131
 132 static void spapr_phb_vfio_eeh_clear_dev_msix(PCIBus *bus,
 133                                               PCIDevice *pdev,
 134                                               void *opaque)
 135 {
 136     /* Check if the device is VFIO PCI device */
 137     if (!object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
 138         return;
 139     }
 140
 141     /*
 142      * The MSIx table will be cleaned out by reset. We need
 143      * disable it so that it can be reenabled properly. Also,
 144      * the cached MSIx table should be cleared as it's not
 145      * reflecting the contents in hardware.
 146      */
 147     if (msix_enabled(pdev)) {
 148         uint16_t flags;
 149
 150         flags = pci_host_config_read_common(pdev,
 151                                             pdev->msix_cap + PCI_MSIX_FLAGS,
 152                                             pci_config_size(pdev), 2);
 153         flags &= ~PCI_MSIX_FLAGS_ENABLE;
 154         pci_host_config_write_common(pdev,
 155                                      pdev->msix_cap + PCI_MSIX_FLAGS,
 156                                      pci_config_size(pdev), flags, 2);
 157     }
 158
 159     msix_reset(pdev);
 160 }
 161
 162 static void spapr_phb_vfio_eeh_clear_bus_msix(PCIBus *bus, void *opaque)
 163 {
 164        pci_for_each_device(bus, pci_bus_num(bus),
 165                            spapr_phb_vfio_eeh_clear_dev_msix, NULL);
 166 }
 167
 168 static void spapr_phb_vfio_eeh_pre_reset(sPAPRPHBState *sphb)
 169 {
 170        PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
 171
 172        pci_for_each_bus(phb->bus, spapr_phb_vfio_eeh_clear_bus_msix, NULL);
 173 }
 174
 175 int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
 176 {
 177     uint32_t op;
 178     int ret;
 179
 180     switch (option) {
 181     case RTAS_SLOT_RESET_DEACTIVATE:
 182         op = VFIO_EEH_PE_RESET_DEACTIVATE;
 183         break;
 184     case RTAS_SLOT_RESET_HOT:
 185         spapr_phb_vfio_eeh_pre_reset(sphb);
 186         op = VFIO_EEH_PE_RESET_HOT;
 187         break;
 188     case RTAS_SLOT_RESET_FUNDAMENTAL:
 189         spapr_phb_vfio_eeh_pre_reset(sphb);
 190         op = VFIO_EEH_PE_RESET_FUNDAMENTAL;
 191         break;
 192     default:
 193         return RTAS_OUT_PARAM_ERROR;
 194     }
 195
 196     ret = vfio_eeh_as_op(&sphb->iommu_as, op);
 197     if (ret < 0) {
 198         return RTAS_OUT_HW_ERROR;
 199     }
 200
 201     return RTAS_OUT_SUCCESS;
 202 }
 203
 204 int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb)
 205 {
 206     int ret;
 207
 208     ret = vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_CONFIGURE);
 209     if (ret < 0) {
 210         return RTAS_OUT_PARAM_ERROR;
 211     }
 212
 213     return RTAS_OUT_SUCCESS;
 214 }
 215
 216 static void spapr_phb_vfio_class_init(ObjectClass *klass, void *data)
 217 {
 218     DeviceClass *dc = DEVICE_CLASS(klass);
 219
 220     dc->props = spapr_phb_vfio_properties;
 221 }
 222
 223 static const TypeInfo spapr_phb_vfio_info = {
 224     .name          = TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE,
 225     .parent        = TYPE_SPAPR_PCI_HOST_BRIDGE,
 226     .instance_size = sizeof(sPAPRPHBVFIOState),
 227     .instance_init = spapr_phb_vfio_instance_init,
 228     .class_init    = spapr_phb_vfio_class_init,
 229 };
 230
 231 static void spapr_pci_vfio_register_types(void)
 232 {
 233     type_register_static(&spapr_phb_vfio_info);
 234 }
 235
 236 type_init(spapr_pci_vfio_register_types)