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ivshmem: Implement shm=... with a memory backend
[qemu/kevin.git] / hw / net / vmxnet3.c
blob093a71e12e3dbf0deb368bfd3c1f53fcaeb34f5b
1 /*
2 * QEMU VMWARE VMXNET3 paravirtual NIC
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Authors:
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "qemu/osdep.h"
19 #include "hw/hw.h"
20 #include "hw/pci/pci.h"
21 #include "net/net.h"
22 #include "net/tap.h"
23 #include "net/checksum.h"
24 #include "sysemu/sysemu.h"
25 #include "qemu-common.h"
26 #include "qemu/bswap.h"
27 #include "hw/pci/msix.h"
28 #include "hw/pci/msi.h"
29
30 #include "vmxnet3.h"
31 #include "vmxnet_debug.h"
32 #include "vmware_utils.h"
33 #include "vmxnet_tx_pkt.h"
34 #include "vmxnet_rx_pkt.h"
35
36 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
37 #define VMXNET3_MSIX_BAR_SIZE 0x2000
38 #define MIN_BUF_SIZE 60
39
40 /* Compatability flags for migration */
41 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
42 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \
43 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT)
44 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1
45 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \
46 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT)
47
48 #define VMXNET3_EXP_EP_OFFSET (0x48)
49 #define VMXNET3_MSI_OFFSET(s) \
50 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84)
51 #define VMXNET3_MSIX_OFFSET(s) \
52 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c)
53 #define VMXNET3_DSN_OFFSET (0x100)
54
55 #define VMXNET3_BAR0_IDX (0)
56 #define VMXNET3_BAR1_IDX (1)
57 #define VMXNET3_MSIX_BAR_IDX (2)
58
59 #define VMXNET3_OFF_MSIX_TABLE (0x000)
60 #define VMXNET3_OFF_MSIX_PBA(s) \
61 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000)
62
63 /* Link speed in Mbps should be shifted by 16 */
64 #define VMXNET3_LINK_SPEED (1000 << 16)
65
66 /* Link status: 1 - up, 0 - down. */
67 #define VMXNET3_LINK_STATUS_UP 0x1
68
69 /* Least significant bit should be set for revision and version */
70 #define VMXNET3_UPT_REVISION 0x1
71 #define VMXNET3_DEVICE_REVISION 0x1
72
73 /* Number of interrupt vectors for non-MSIx modes */
74 #define VMXNET3_MAX_NMSIX_INTRS (1)
75
76 /* Macros for rings descriptors access */
77 #define VMXNET3_READ_TX_QUEUE_DESCR8(dpa, field) \
78 (vmw_shmem_ld8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
79
80 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(dpa, field, value) \
81 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
82
83 #define VMXNET3_READ_TX_QUEUE_DESCR32(dpa, field) \
84 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
85
86 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(dpa, field, value) \
87 (vmw_shmem_st32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
88
89 #define VMXNET3_READ_TX_QUEUE_DESCR64(dpa, field) \
90 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
91
92 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(dpa, field, value) \
93 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
94
95 #define VMXNET3_READ_RX_QUEUE_DESCR64(dpa, field) \
96 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
97
98 #define VMXNET3_READ_RX_QUEUE_DESCR32(dpa, field) \
99 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
100
101 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(dpa, field, value) \
102 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
103
104 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(dpa, field, value) \
105 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
106
107 /* Macros for guest driver shared area access */
108 #define VMXNET3_READ_DRV_SHARED64(shpa, field) \
109 (vmw_shmem_ld64(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
110
111 #define VMXNET3_READ_DRV_SHARED32(shpa, field) \
112 (vmw_shmem_ld32(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
113
114 #define VMXNET3_WRITE_DRV_SHARED32(shpa, field, val) \
115 (vmw_shmem_st32(shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
116
117 #define VMXNET3_READ_DRV_SHARED16(shpa, field) \
118 (vmw_shmem_ld16(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
119
120 #define VMXNET3_READ_DRV_SHARED8(shpa, field) \
121 (vmw_shmem_ld8(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
122
123 #define VMXNET3_READ_DRV_SHARED(shpa, field, b, l) \
124 (vmw_shmem_read(shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
125
126 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
127
128 typedef struct VMXNET3Class {
129 PCIDeviceClass parent_class;
130 DeviceRealize parent_dc_realize;
131 } VMXNET3Class;
132
133 #define TYPE_VMXNET3 "vmxnet3"
134 #define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)
135
136 #define VMXNET3_DEVICE_CLASS(klass) \
137 OBJECT_CLASS_CHECK(VMXNET3Class, (klass), TYPE_VMXNET3)
138 #define VMXNET3_DEVICE_GET_CLASS(obj) \
139 OBJECT_GET_CLASS(VMXNET3Class, (obj), TYPE_VMXNET3)
140
141 /* Cyclic ring abstraction */
142 typedef struct {
143 hwaddr pa;
144 size_t size;
145 size_t cell_size;
146 size_t next;
147 uint8_t gen;
148 } Vmxnet3Ring;
149
150 static inline void vmxnet3_ring_init(Vmxnet3Ring *ring,
151 hwaddr pa,
152 size_t size,
153 size_t cell_size,
154 bool zero_region)
155 {
156 ring->pa = pa;
157 ring->size = size;
158 ring->cell_size = cell_size;
159 ring->gen = VMXNET3_INIT_GEN;
160 ring->next = 0;
161
162 if (zero_region) {
163 vmw_shmem_set(pa, 0, size * cell_size);
164 }
165 }
166
167 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
168 macro("%s#%d: base %" PRIx64 " size %zu cell_size %zu gen %d next %zu", \
169 (ring_name), (ridx), \
170 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
171
172 static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring)
173 {
174 if (++ring->next >= ring->size) {
175 ring->next = 0;
176 ring->gen ^= 1;
177 }
178 }
179
180 static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring)
181 {
182 if (ring->next-- == 0) {
183 ring->next = ring->size - 1;
184 ring->gen ^= 1;
185 }
186 }
187
188 static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring)
189 {
190 return ring->pa + ring->next * ring->cell_size;
191 }
192
193 static inline void vmxnet3_ring_read_curr_cell(Vmxnet3Ring *ring, void *buff)
194 {
195 vmw_shmem_read(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
196 }
197
198 static inline void vmxnet3_ring_write_curr_cell(Vmxnet3Ring *ring, void *buff)
199 {
200 vmw_shmem_write(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
201 }
202
203 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring)
204 {
205 return ring->next;
206 }
207
208 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring)
209 {
210 return ring->gen;
211 }
212
213 /* Debug trace-related functions */
214 static inline void
215 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr)
216 {
217 VMW_PKPRN("TX DESCR: "
218 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
219 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
220 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
221 le64_to_cpu(descr->addr), descr->len, descr->gen, descr->rsvd,
222 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om,
223 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci);
224 }
225
226 static inline void
227 vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr)
228 {
229 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
230 "csum_start: %d, csum_offset: %d",
231 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size,
232 vhdr->csum_start, vhdr->csum_offset);
233 }
234
235 static inline void
236 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr)
237 {
238 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
239 "dtype: %d, ext1: %d, btype: %d",
240 le64_to_cpu(descr->addr), descr->len, descr->gen,
241 descr->rsvd, descr->dtype, descr->ext1, descr->btype);
242 }
243
244 /* Device state and helper functions */
245 #define VMXNET3_RX_RINGS_PER_QUEUE (2)
246
247 typedef struct {
248 Vmxnet3Ring tx_ring;
249 Vmxnet3Ring comp_ring;
250
251 uint8_t intr_idx;
252 hwaddr tx_stats_pa;
253 struct UPT1_TxStats txq_stats;
254 } Vmxnet3TxqDescr;
255
256 typedef struct {
257 Vmxnet3Ring rx_ring[VMXNET3_RX_RINGS_PER_QUEUE];
258 Vmxnet3Ring comp_ring;
259 uint8_t intr_idx;
260 hwaddr rx_stats_pa;
261 struct UPT1_RxStats rxq_stats;
262 } Vmxnet3RxqDescr;
263
264 typedef struct {
265 bool is_masked;
266 bool is_pending;
267 bool is_asserted;
268 } Vmxnet3IntState;
269
270 typedef struct {
271 PCIDevice parent_obj;
272 NICState *nic;
273 NICConf conf;
274 MemoryRegion bar0;
275 MemoryRegion bar1;
276 MemoryRegion msix_bar;
277
278 Vmxnet3RxqDescr rxq_descr[VMXNET3_DEVICE_MAX_RX_QUEUES];
279 Vmxnet3TxqDescr txq_descr[VMXNET3_DEVICE_MAX_TX_QUEUES];
280
281 /* Whether MSI-X support was installed successfully */
282 bool msix_used;
283 /* Whether MSI support was installed successfully */
284 bool msi_used;
285 hwaddr drv_shmem;
286 hwaddr temp_shared_guest_driver_memory;
287
288 uint8_t txq_num;
289
290 /* This boolean tells whether RX packet being indicated has to */
291 /* be split into head and body chunks from different RX rings */
292 bool rx_packets_compound;
293
294 bool rx_vlan_stripping;
295 bool lro_supported;
296
297 uint8_t rxq_num;
298
299 /* Network MTU */
300 uint32_t mtu;
301
302 /* Maximum number of fragments for indicated TX packets */
303 uint32_t max_tx_frags;
304
305 /* Maximum number of fragments for indicated RX packets */
306 uint16_t max_rx_frags;
307
308 /* Index for events interrupt */
309 uint8_t event_int_idx;
310
311 /* Whether automatic interrupts masking enabled */
312 bool auto_int_masking;
313
314 bool peer_has_vhdr;
315
316 /* TX packets to QEMU interface */
317 struct VmxnetTxPkt *tx_pkt;
318 uint32_t offload_mode;
319 uint32_t cso_or_gso_size;
320 uint16_t tci;
321 bool needs_vlan;
322
323 struct VmxnetRxPkt *rx_pkt;
324
325 bool tx_sop;
326 bool skip_current_tx_pkt;
327
328 uint32_t device_active;
329 uint32_t last_command;
330
331 uint32_t link_status_and_speed;
332
333 Vmxnet3IntState interrupt_states[VMXNET3_MAX_INTRS];
334
335 uint32_t temp_mac; /* To store the low part first */
336
337 MACAddr perm_mac;
338 uint32_t vlan_table[VMXNET3_VFT_SIZE];
339 uint32_t rx_mode;
340 MACAddr *mcast_list;
341 uint32_t mcast_list_len;
342 uint32_t mcast_list_buff_size; /* needed for live migration. */
343
344 /* Compatability flags for migration */
345 uint32_t compat_flags;
346 } VMXNET3State;
347
348 /* Interrupt management */
349
350 /*
351 *This function returns sign whether interrupt line is in asserted state
352 * This depends on the type of interrupt used. For INTX interrupt line will
353 * be asserted until explicit deassertion, for MSI(X) interrupt line will
354 * be deasserted automatically due to notification semantics of the MSI(X)
355 * interrupts
356 */
357 static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx)
358 {
359 PCIDevice *d = PCI_DEVICE(s);
360
361 if (s->msix_used && msix_enabled(d)) {
362 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx);
363 msix_notify(d, int_idx);
364 return false;
365 }
366 if (s->msi_used && msi_enabled(d)) {
367 VMW_IRPRN("Sending MSI notification for vector %u", int_idx);
368 msi_notify(d, int_idx);
369 return false;
370 }
371
372 VMW_IRPRN("Asserting line for interrupt %u", int_idx);
373 pci_irq_assert(d);
374 return true;
375 }
376
377 static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx)
378 {
379 PCIDevice *d = PCI_DEVICE(s);
380
381 /*
382 * This function should never be called for MSI(X) interrupts
383 * because deassertion never required for message interrupts
384 */
385 assert(!s->msix_used || !msix_enabled(d));
386 /*
387 * This function should never be called for MSI(X) interrupts
388 * because deassertion never required for message interrupts
389 */
390 assert(!s->msi_used || !msi_enabled(d));
391
392 VMW_IRPRN("Deasserting line for interrupt %u", lidx);
393 pci_irq_deassert(d);
394 }
395
396 static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx)
397 {
398 if (!s->interrupt_states[lidx].is_pending &&
399 s->interrupt_states[lidx].is_asserted) {
400 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx);
401 _vmxnet3_deassert_interrupt_line(s, lidx);
402 s->interrupt_states[lidx].is_asserted = false;
403 return;
404 }
405
406 if (s->interrupt_states[lidx].is_pending &&
407 !s->interrupt_states[lidx].is_masked &&
408 !s->interrupt_states[lidx].is_asserted) {
409 VMW_IRPRN("New interrupt line state for index %d is UP", lidx);
410 s->interrupt_states[lidx].is_asserted =
411 _vmxnet3_assert_interrupt_line(s, lidx);
412 s->interrupt_states[lidx].is_pending = false;
413 return;
414 }
415 }
416
417 static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx)
418 {
419 PCIDevice *d = PCI_DEVICE(s);
420 s->interrupt_states[lidx].is_pending = true;
421 vmxnet3_update_interrupt_line_state(s, lidx);
422
423 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) {
424 goto do_automask;
425 }
426
427 if (s->msi_used && msi_enabled(d) && s->auto_int_masking) {
428 goto do_automask;
429 }
430
431 return;
432
433 do_automask:
434 s->interrupt_states[lidx].is_masked = true;
435 vmxnet3_update_interrupt_line_state(s, lidx);
436 }
437
438 static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx)
439 {
440 return s->interrupt_states[lidx].is_asserted;
441 }
442
443 static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx)
444 {
445 s->interrupt_states[int_idx].is_pending = false;
446 if (s->auto_int_masking) {
447 s->interrupt_states[int_idx].is_masked = true;
448 }
449 vmxnet3_update_interrupt_line_state(s, int_idx);
450 }
451
452 static void
453 vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked)
454 {
455 s->interrupt_states[lidx].is_masked = is_masked;
456 vmxnet3_update_interrupt_line_state(s, lidx);
457 }
458
459 static bool vmxnet3_verify_driver_magic(hwaddr dshmem)
460 {
461 return (VMXNET3_READ_DRV_SHARED32(dshmem, magic) == VMXNET3_REV1_MAGIC);
462 }
463
464 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
465 #define VMXNET3_MAKE_BYTE(byte_num, val) \
466 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
467
468 static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l)
469 {
470 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0);
471 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1);
472 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2);
473 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3);
474 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0);
475 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1);
476
477 VMW_CFPRN("Variable MAC: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));
478
479 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
480 }
481
482 static uint64_t vmxnet3_get_mac_low(MACAddr *addr)
483 {
484 return VMXNET3_MAKE_BYTE(0, addr->a[0]) |
485 VMXNET3_MAKE_BYTE(1, addr->a[1]) |
486 VMXNET3_MAKE_BYTE(2, addr->a[2]) |
487 VMXNET3_MAKE_BYTE(3, addr->a[3]);
488 }
489
490 static uint64_t vmxnet3_get_mac_high(MACAddr *addr)
491 {
492 return VMXNET3_MAKE_BYTE(0, addr->a[4]) |
493 VMXNET3_MAKE_BYTE(1, addr->a[5]);
494 }
495
496 static void
497 vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx)
498 {
499 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring);
500 }
501
502 static inline void
503 vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx)
504 {
505 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]);
506 }
507
508 static inline void
509 vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx)
510 {
511 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring);
512 }
513
514 static void
515 vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx)
516 {
517 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring);
518 }
519
520 static void
521 vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx)
522 {
523 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring);
524 }
525
526 static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32_t tx_ridx)
527 {
528 struct Vmxnet3_TxCompDesc txcq_descr;
529
530 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring);
531
532 txcq_descr.txdIdx = tx_ridx;
533 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring);
534
535 vmxnet3_ring_write_curr_cell(&s->txq_descr[qidx].comp_ring, &txcq_descr);
536
537 /* Flush changes in TX descriptor before changing the counter value */
538 smp_wmb();
539
540 vmxnet3_inc_tx_completion_counter(s, qidx);
541 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx);
542 }
543
544 static bool
545 vmxnet3_setup_tx_offloads(VMXNET3State *s)
546 {
547 switch (s->offload_mode) {
548 case VMXNET3_OM_NONE:
549 vmxnet_tx_pkt_build_vheader(s->tx_pkt, false, false, 0);
550 break;
551
552 case VMXNET3_OM_CSUM:
553 vmxnet_tx_pkt_build_vheader(s->tx_pkt, false, true, 0);
554 VMW_PKPRN("L4 CSO requested\n");
555 break;
556
557 case VMXNET3_OM_TSO:
558 vmxnet_tx_pkt_build_vheader(s->tx_pkt, true, true,
559 s->cso_or_gso_size);
560 vmxnet_tx_pkt_update_ip_checksums(s->tx_pkt);
561 VMW_PKPRN("GSO offload requested.");
562 break;
563
564 default:
565 g_assert_not_reached();
566 return false;
567 }
568
569 return true;
570 }
571
572 static void
573 vmxnet3_tx_retrieve_metadata(VMXNET3State *s,
574 const struct Vmxnet3_TxDesc *txd)
575 {
576 s->offload_mode = txd->om;
577 s->cso_or_gso_size = txd->msscof;
578 s->tci = txd->tci;
579 s->needs_vlan = txd->ti;
580 }
581
582 typedef enum {
583 VMXNET3_PKT_STATUS_OK,
584 VMXNET3_PKT_STATUS_ERROR,
585 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */
586 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */
587 } Vmxnet3PktStatus;
588
589 static void
590 vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx,
591 Vmxnet3PktStatus status)
592 {
593 size_t tot_len = vmxnet_tx_pkt_get_total_len(s->tx_pkt);
594 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats;
595
596 switch (status) {
597 case VMXNET3_PKT_STATUS_OK:
598 switch (vmxnet_tx_pkt_get_packet_type(s->tx_pkt)) {
599 case ETH_PKT_BCAST:
600 stats->bcastPktsTxOK++;
601 stats->bcastBytesTxOK += tot_len;
602 break;
603 case ETH_PKT_MCAST:
604 stats->mcastPktsTxOK++;
605 stats->mcastBytesTxOK += tot_len;
606 break;
607 case ETH_PKT_UCAST:
608 stats->ucastPktsTxOK++;
609 stats->ucastBytesTxOK += tot_len;
610 break;
611 default:
612 g_assert_not_reached();
613 }
614
615 if (s->offload_mode == VMXNET3_OM_TSO) {
616 /*
617 * According to VMWARE headers this statistic is a number
618 * of packets after segmentation but since we don't have
619 * this information in QEMU model, the best we can do is to
620 * provide number of non-segmented packets
621 */
622 stats->TSOPktsTxOK++;
623 stats->TSOBytesTxOK += tot_len;
624 }
625 break;
626
627 case VMXNET3_PKT_STATUS_DISCARD:
628 stats->pktsTxDiscard++;
629 break;
630
631 case VMXNET3_PKT_STATUS_ERROR:
632 stats->pktsTxError++;
633 break;
634
635 default:
636 g_assert_not_reached();
637 }
638 }
639
640 static void
641 vmxnet3_on_rx_done_update_stats(VMXNET3State *s,
642 int qidx,
643 Vmxnet3PktStatus status)
644 {
645 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats;
646 size_t tot_len = vmxnet_rx_pkt_get_total_len(s->rx_pkt);
647
648 switch (status) {
649 case VMXNET3_PKT_STATUS_OUT_OF_BUF:
650 stats->pktsRxOutOfBuf++;
651 break;
652
653 case VMXNET3_PKT_STATUS_ERROR:
654 stats->pktsRxError++;
655 break;
656 case VMXNET3_PKT_STATUS_OK:
657 switch (vmxnet_rx_pkt_get_packet_type(s->rx_pkt)) {
658 case ETH_PKT_BCAST:
659 stats->bcastPktsRxOK++;
660 stats->bcastBytesRxOK += tot_len;
661 break;
662 case ETH_PKT_MCAST:
663 stats->mcastPktsRxOK++;
664 stats->mcastBytesRxOK += tot_len;
665 break;
666 case ETH_PKT_UCAST:
667 stats->ucastPktsRxOK++;
668 stats->ucastBytesRxOK += tot_len;
669 break;
670 default:
671 g_assert_not_reached();
672 }
673
674 if (tot_len > s->mtu) {
675 stats->LROPktsRxOK++;
676 stats->LROBytesRxOK += tot_len;
677 }
678 break;
679 default:
680 g_assert_not_reached();
681 }
682 }
683
684 static inline bool
685 vmxnet3_pop_next_tx_descr(VMXNET3State *s,
686 int qidx,
687 struct Vmxnet3_TxDesc *txd,
688 uint32_t *descr_idx)
689 {
690 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring;
691
692 vmxnet3_ring_read_curr_cell(ring, txd);
693 if (txd->gen == vmxnet3_ring_curr_gen(ring)) {
694 /* Only read after generation field verification */
695 smp_rmb();
696 /* Re-read to be sure we got the latest version */
697 vmxnet3_ring_read_curr_cell(ring, txd);
698 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring);
699 *descr_idx = vmxnet3_ring_curr_cell_idx(ring);
700 vmxnet3_inc_tx_consumption_counter(s, qidx);
701 return true;
702 }
703
704 return false;
705 }
706
707 static bool
708 vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx)
709 {
710 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK;
711
712 if (!vmxnet3_setup_tx_offloads(s)) {
713 status = VMXNET3_PKT_STATUS_ERROR;
714 goto func_exit;
715 }
716
717 /* debug prints */
718 vmxnet3_dump_virt_hdr(vmxnet_tx_pkt_get_vhdr(s->tx_pkt));
719 vmxnet_tx_pkt_dump(s->tx_pkt);
720
721 if (!vmxnet_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) {
722 status = VMXNET3_PKT_STATUS_DISCARD;
723 goto func_exit;
724 }
725
726 func_exit:
727 vmxnet3_on_tx_done_update_stats(s, qidx, status);
728 return (status == VMXNET3_PKT_STATUS_OK);
729 }
730
731 static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx)
732 {
733 struct Vmxnet3_TxDesc txd;
734 uint32_t txd_idx;
735 uint32_t data_len;
736 hwaddr data_pa;
737
738 for (;;) {
739 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) {
740 break;
741 }
742
743 vmxnet3_dump_tx_descr(&txd);
744
745 if (!s->skip_current_tx_pkt) {
746 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
747 data_pa = le64_to_cpu(txd.addr);
748
749 if (!vmxnet_tx_pkt_add_raw_fragment(s->tx_pkt,
750 data_pa,
751 data_len)) {
752 s->skip_current_tx_pkt = true;
753 }
754 }
755
756 if (s->tx_sop) {
757 vmxnet3_tx_retrieve_metadata(s, &txd);
758 s->tx_sop = false;
759 }
760
761 if (txd.eop) {
762 if (!s->skip_current_tx_pkt && vmxnet_tx_pkt_parse(s->tx_pkt)) {
763 if (s->needs_vlan) {
764 vmxnet_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci);
765 }
766
767 vmxnet3_send_packet(s, qidx);
768 } else {
769 vmxnet3_on_tx_done_update_stats(s, qidx,
770 VMXNET3_PKT_STATUS_ERROR);
771 }
772
773 vmxnet3_complete_packet(s, qidx, txd_idx);
774 s->tx_sop = true;
775 s->skip_current_tx_pkt = false;
776 vmxnet_tx_pkt_reset(s->tx_pkt);
777 }
778 }
779 }
780
781 static inline void
782 vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
783 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
784 {
785 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx];
786 *didx = vmxnet3_ring_curr_cell_idx(ring);
787 vmxnet3_ring_read_curr_cell(ring, dbuf);
788 }
789
790 static inline uint8_t
791 vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx)
792 {
793 return s->rxq_descr[qidx].rx_ring[ridx].gen;
794 }
795
796 static inline hwaddr
797 vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen)
798 {
799 uint8_t ring_gen;
800 struct Vmxnet3_RxCompDesc rxcd;
801
802 hwaddr daddr =
803 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring);
804
805 cpu_physical_memory_read(daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc));
806 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring);
807
808 if (rxcd.gen != ring_gen) {
809 *descr_gen = ring_gen;
810 vmxnet3_inc_rx_completion_counter(s, qidx);
811 return daddr;
812 }
813
814 return 0;
815 }
816
817 static inline void
818 vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx)
819 {
820 vmxnet3_dec_rx_completion_counter(s, qidx);
821 }
822
823 #define RXQ_IDX (0)
824 #define RX_HEAD_BODY_RING (0)
825 #define RX_BODY_ONLY_RING (1)
826
827 static bool
828 vmxnet3_get_next_head_rx_descr(VMXNET3State *s,
829 struct Vmxnet3_RxDesc *descr_buf,
830 uint32_t *descr_idx,
831 uint32_t *ridx)
832 {
833 for (;;) {
834 uint32_t ring_gen;
835 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
836 descr_buf, descr_idx);
837
838 /* If no more free descriptors - return */
839 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING);
840 if (descr_buf->gen != ring_gen) {
841 return false;
842 }
843
844 /* Only read after generation field verification */
845 smp_rmb();
846 /* Re-read to be sure we got the latest version */
847 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
848 descr_buf, descr_idx);
849
850 /* Mark current descriptor as used/skipped */
851 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
852
853 /* If this is what we are looking for - return */
854 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) {
855 *ridx = RX_HEAD_BODY_RING;
856 return true;
857 }
858 }
859 }
860
861 static bool
862 vmxnet3_get_next_body_rx_descr(VMXNET3State *s,
863 struct Vmxnet3_RxDesc *d,
864 uint32_t *didx,
865 uint32_t *ridx)
866 {
867 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
868
869 /* Try to find corresponding descriptor in head/body ring */
870 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) {
871 /* Only read after generation field verification */
872 smp_rmb();
873 /* Re-read to be sure we got the latest version */
874 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
875 if (d->btype == VMXNET3_RXD_BTYPE_BODY) {
876 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
877 *ridx = RX_HEAD_BODY_RING;
878 return true;
879 }
880 }
881
882 /*
883 * If there is no free descriptors on head/body ring or next free
884 * descriptor is a head descriptor switch to body only ring
885 */
886 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
887
888 /* If no more free descriptors - return */
889 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) {
890 /* Only read after generation field verification */
891 smp_rmb();
892 /* Re-read to be sure we got the latest version */
893 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
894 assert(d->btype == VMXNET3_RXD_BTYPE_BODY);
895 *ridx = RX_BODY_ONLY_RING;
896 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING);
897 return true;
898 }
899
900 return false;
901 }
902
903 static inline bool
904 vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head,
905 struct Vmxnet3_RxDesc *descr_buf,
906 uint32_t *descr_idx,
907 uint32_t *ridx)
908 {
909 if (is_head || !s->rx_packets_compound) {
910 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx);
911 } else {
912 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx);
913 }
914 }
915
916 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID),
917 * the implementation always passes an RxCompDesc with a "Checksum
918 * calculated and found correct" to the OS (cnc=0 and tuc=1, see
919 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior.
920 *
921 * Therefore, if packet has the NEEDS_CSUM set, we must calculate
922 * and place a fully computed checksum into the tcp/udp header.
923 * Otherwise, the OS driver will receive a checksum-correct indication
924 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field
925 * having just the pseudo header csum value.
926 *
927 * While this is not a problem if packet is destined for local delivery,
928 * in the case the host OS performs forwarding, it will forward an
929 * incorrectly checksummed packet.
930 */
931 static void vmxnet3_rx_need_csum_calculate(struct VmxnetRxPkt *pkt,
932 const void *pkt_data,
933 size_t pkt_len)
934 {
935 struct virtio_net_hdr *vhdr;
936 bool isip4, isip6, istcp, isudp;
937 uint8_t *data;
938 int len;
939
940 if (!vmxnet_rx_pkt_has_virt_hdr(pkt)) {
941 return;
942 }
943
944 vhdr = vmxnet_rx_pkt_get_vhdr(pkt);
945 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
946 return;
947 }
948
949 vmxnet_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
950 if (!(isip4 || isip6) || !(istcp || isudp)) {
951 return;
952 }
953
954 vmxnet3_dump_virt_hdr(vhdr);
955
956 /* Validate packet len: csum_start + scum_offset + length of csum field */
957 if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) {
958 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, "
959 "cannot calculate checksum",
960 pkt_len, vhdr->csum_start, vhdr->csum_offset);
961 return;
962 }
963
964 data = (uint8_t *)pkt_data + vhdr->csum_start;
965 len = pkt_len - vhdr->csum_start;
966 /* Put the checksum obtained into the packet */
967 stw_be_p(data + vhdr->csum_offset, net_raw_checksum(data, len));
968
969 vhdr->flags &= ~VIRTIO_NET_HDR_F_NEEDS_CSUM;
970 vhdr->flags |= VIRTIO_NET_HDR_F_DATA_VALID;
971 }
972
973 static void vmxnet3_rx_update_descr(struct VmxnetRxPkt *pkt,
974 struct Vmxnet3_RxCompDesc *rxcd)
975 {
976 int csum_ok, is_gso;
977 bool isip4, isip6, istcp, isudp;
978 struct virtio_net_hdr *vhdr;
979 uint8_t offload_type;
980
981 if (vmxnet_rx_pkt_is_vlan_stripped(pkt)) {
982 rxcd->ts = 1;
983 rxcd->tci = vmxnet_rx_pkt_get_vlan_tag(pkt);
984 }
985
986 if (!vmxnet_rx_pkt_has_virt_hdr(pkt)) {
987 goto nocsum;
988 }
989
990 vhdr = vmxnet_rx_pkt_get_vhdr(pkt);
991 /*
992 * Checksum is valid when lower level tell so or when lower level
993 * requires checksum offload telling that packet produced/bridged
994 * locally and did travel over network after last checksum calculation
995 * or production
996 */
997 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) ||
998 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM);
999
1000 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN;
1001 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0;
1002
1003 if (!csum_ok && !is_gso) {
1004 goto nocsum;
1005 }
1006
1007 vmxnet_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
1008 if ((!istcp && !isudp) || (!isip4 && !isip6)) {
1009 goto nocsum;
1010 }
1011
1012 rxcd->cnc = 0;
1013 rxcd->v4 = isip4 ? 1 : 0;
1014 rxcd->v6 = isip6 ? 1 : 0;
1015 rxcd->tcp = istcp ? 1 : 0;
1016 rxcd->udp = isudp ? 1 : 0;
1017 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1;
1018 return;
1019
1020 nocsum:
1021 rxcd->cnc = 1;
1022 return;
1023 }
1024
1025 static void
1026 vmxnet3_physical_memory_writev(const struct iovec *iov,
1027 size_t start_iov_off,
1028 hwaddr target_addr,
1029 size_t bytes_to_copy)
1030 {
1031 size_t curr_off = 0;
1032 size_t copied = 0;
1033
1034 while (bytes_to_copy) {
1035 if (start_iov_off < (curr_off + iov->iov_len)) {
1036 size_t chunk_len =
1037 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy);
1038
1039 cpu_physical_memory_write(target_addr + copied,
1040 iov->iov_base + start_iov_off - curr_off,
1041 chunk_len);
1042
1043 copied += chunk_len;
1044 start_iov_off += chunk_len;
1045 curr_off = start_iov_off;
1046 bytes_to_copy -= chunk_len;
1047 } else {
1048 curr_off += iov->iov_len;
1049 }
1050 iov++;
1051 }
1052 }
1053
1054 static bool
1055 vmxnet3_indicate_packet(VMXNET3State *s)
1056 {
1057 struct Vmxnet3_RxDesc rxd;
1058 bool is_head = true;
1059 uint32_t rxd_idx;
1060 uint32_t rx_ridx = 0;
1061
1062 struct Vmxnet3_RxCompDesc rxcd;
1063 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN;
1064 hwaddr new_rxcd_pa = 0;
1065 hwaddr ready_rxcd_pa = 0;
1066 struct iovec *data = vmxnet_rx_pkt_get_iovec(s->rx_pkt);
1067 size_t bytes_copied = 0;
1068 size_t bytes_left = vmxnet_rx_pkt_get_total_len(s->rx_pkt);
1069 uint16_t num_frags = 0;
1070 size_t chunk_size;
1071
1072 vmxnet_rx_pkt_dump(s->rx_pkt);
1073
1074 while (bytes_left > 0) {
1075
1076 /* cannot add more frags to packet */
1077 if (num_frags == s->max_rx_frags) {
1078 break;
1079 }
1080
1081 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen);
1082 if (!new_rxcd_pa) {
1083 break;
1084 }
1085
1086 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) {
1087 break;
1088 }
1089
1090 chunk_size = MIN(bytes_left, rxd.len);
1091 vmxnet3_physical_memory_writev(data, bytes_copied,
1092 le64_to_cpu(rxd.addr), chunk_size);
1093 bytes_copied += chunk_size;
1094 bytes_left -= chunk_size;
1095
1096 vmxnet3_dump_rx_descr(&rxd);
1097
1098 if (ready_rxcd_pa != 0) {
1099 cpu_physical_memory_write(ready_rxcd_pa, &rxcd, sizeof(rxcd));
1100 }
1101
1102 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc));
1103 rxcd.rxdIdx = rxd_idx;
1104 rxcd.len = chunk_size;
1105 rxcd.sop = is_head;
1106 rxcd.gen = new_rxcd_gen;
1107 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num;
1108
1109 if (bytes_left == 0) {
1110 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd);
1111 }
1112
1113 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1114 "sop %d csum_correct %lu",
1115 (unsigned long) rx_ridx,
1116 (unsigned long) rxcd.rxdIdx,
1117 (unsigned long) rxcd.len,
1118 (int) rxcd.sop,
1119 (unsigned long) rxcd.tuc);
1120
1121 is_head = false;
1122 ready_rxcd_pa = new_rxcd_pa;
1123 new_rxcd_pa = 0;
1124 num_frags++;
1125 }
1126
1127 if (ready_rxcd_pa != 0) {
1128 rxcd.eop = 1;
1129 rxcd.err = (bytes_left != 0);
1130 cpu_physical_memory_write(ready_rxcd_pa, &rxcd, sizeof(rxcd));
1131
1132 /* Flush RX descriptor changes */
1133 smp_wmb();
1134 }
1135
1136 if (new_rxcd_pa != 0) {
1137 vmxnet3_revert_rxc_descr(s, RXQ_IDX);
1138 }
1139
1140 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx);
1141
1142 if (bytes_left == 0) {
1143 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK);
1144 return true;
1145 } else if (num_frags == s->max_rx_frags) {
1146 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR);
1147 return false;
1148 } else {
1149 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX,
1150 VMXNET3_PKT_STATUS_OUT_OF_BUF);
1151 return false;
1152 }
1153 }
1154
1155 static void
1156 vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
1157 uint64_t val, unsigned size)
1158 {
1159 VMXNET3State *s = opaque;
1160
1161 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD,
1162 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) {
1163 int tx_queue_idx =
1164 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD,
1165 VMXNET3_REG_ALIGN);
1166 assert(tx_queue_idx <= s->txq_num);
1167 vmxnet3_process_tx_queue(s, tx_queue_idx);
1168 return;
1169 }
1170
1171 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1172 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1173 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1174 VMXNET3_REG_ALIGN);
1175
1176 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val);
1177
1178 vmxnet3_on_interrupt_mask_changed(s, l, val);
1179 return;
1180 }
1181
1182 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD,
1183 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) ||
1184 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2,
1185 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) {
1186 return;
1187 }
1188
1189 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d",
1190 (uint64_t) addr, val, size);
1191 }
1192
1193 static uint64_t
1194 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
1195 {
1196 VMXNET3State *s = opaque;
1197
1198 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1199 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1200 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1201 VMXNET3_REG_ALIGN);
1202 return s->interrupt_states[l].is_masked;
1203 }
1204
1205 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
1206 return 0;
1207 }
1208
1209 static void vmxnet3_reset_interrupt_states(VMXNET3State *s)
1210 {
1211 int i;
1212 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) {
1213 s->interrupt_states[i].is_asserted = false;
1214 s->interrupt_states[i].is_pending = false;
1215 s->interrupt_states[i].is_masked = true;
1216 }
1217 }
1218
1219 static void vmxnet3_reset_mac(VMXNET3State *s)
1220 {
1221 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
1222 VMW_CFPRN("MAC address set to: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));
1223 }
1224
1225 static void vmxnet3_deactivate_device(VMXNET3State *s)
1226 {
1227 if (s->device_active) {
1228 VMW_CBPRN("Deactivating vmxnet3...");
1229 vmxnet_tx_pkt_reset(s->tx_pkt);
1230 vmxnet_tx_pkt_uninit(s->tx_pkt);
1231 vmxnet_rx_pkt_uninit(s->rx_pkt);
1232 s->device_active = false;
1233 }
1234 }
1235
1236 static void vmxnet3_reset(VMXNET3State *s)
1237 {
1238 VMW_CBPRN("Resetting vmxnet3...");
1239
1240 vmxnet3_deactivate_device(s);
1241 vmxnet3_reset_interrupt_states(s);
1242 s->drv_shmem = 0;
1243 s->tx_sop = true;
1244 s->skip_current_tx_pkt = false;
1245 }
1246
1247 static void vmxnet3_update_rx_mode(VMXNET3State *s)
1248 {
1249 s->rx_mode = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
1250 devRead.rxFilterConf.rxMode);
1251 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode);
1252 }
1253
1254 static void vmxnet3_update_vlan_filters(VMXNET3State *s)
1255 {
1256 int i;
1257
1258 /* Copy configuration from shared memory */
1259 VMXNET3_READ_DRV_SHARED(s->drv_shmem,
1260 devRead.rxFilterConf.vfTable,
1261 s->vlan_table,
1262 sizeof(s->vlan_table));
1263
1264 /* Invert byte order when needed */
1265 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) {
1266 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]);
1267 }
1268
1269 /* Dump configuration for debugging purposes */
1270 VMW_CFPRN("Configured VLANs:");
1271 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) {
1272 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) {
1273 VMW_CFPRN("\tVLAN %d is present", i);
1274 }
1275 }
1276 }
1277
1278 static void vmxnet3_update_mcast_filters(VMXNET3State *s)
1279 {
1280 uint16_t list_bytes =
1281 VMXNET3_READ_DRV_SHARED16(s->drv_shmem,
1282 devRead.rxFilterConf.mfTableLen);
1283
1284 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]);
1285
1286 s->mcast_list = g_realloc(s->mcast_list, list_bytes);
1287 if (!s->mcast_list) {
1288 if (s->mcast_list_len == 0) {
1289 VMW_CFPRN("Current multicast list is empty");
1290 } else {
1291 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1292 s->mcast_list_len);
1293 }
1294 s->mcast_list_len = 0;
1295 } else {
1296 int i;
1297 hwaddr mcast_list_pa =
1298 VMXNET3_READ_DRV_SHARED64(s->drv_shmem,
1299 devRead.rxFilterConf.mfTablePA);
1300
1301 cpu_physical_memory_read(mcast_list_pa, s->mcast_list, list_bytes);
1302 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len);
1303 for (i = 0; i < s->mcast_list_len; i++) {
1304 VMW_CFPRN("\t" VMXNET_MF, VMXNET_MA(s->mcast_list[i].a));
1305 }
1306 }
1307 }
1308
1309 static void vmxnet3_setup_rx_filtering(VMXNET3State *s)
1310 {
1311 vmxnet3_update_rx_mode(s);
1312 vmxnet3_update_vlan_filters(s);
1313 vmxnet3_update_mcast_filters(s);
1314 }
1315
1316 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s)
1317 {
1318 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2);
1319 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode);
1320 return interrupt_mode;
1321 }
1322
1323 static void vmxnet3_fill_stats(VMXNET3State *s)
1324 {
1325 int i;
1326
1327 if (!s->device_active)
1328 return;
1329
1330 for (i = 0; i < s->txq_num; i++) {
1331 cpu_physical_memory_write(s->txq_descr[i].tx_stats_pa,
1332 &s->txq_descr[i].txq_stats,
1333 sizeof(s->txq_descr[i].txq_stats));
1334 }
1335
1336 for (i = 0; i < s->rxq_num; i++) {
1337 cpu_physical_memory_write(s->rxq_descr[i].rx_stats_pa,
1338 &s->rxq_descr[i].rxq_stats,
1339 sizeof(s->rxq_descr[i].rxq_stats));
1340 }
1341 }
1342
1343 static void vmxnet3_adjust_by_guest_type(VMXNET3State *s)
1344 {
1345 struct Vmxnet3_GOSInfo gos;
1346
1347 VMXNET3_READ_DRV_SHARED(s->drv_shmem, devRead.misc.driverInfo.gos,
1348 &gos, sizeof(gos));
1349 s->rx_packets_compound =
1350 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true;
1351
1352 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound);
1353 }
1354
1355 static void
1356 vmxnet3_dump_conf_descr(const char *name,
1357 struct Vmxnet3_VariableLenConfDesc *pm_descr)
1358 {
1359 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1360 name, pm_descr->confVer, pm_descr->confLen);
1361
1362 };
1363
1364 static void vmxnet3_update_pm_state(VMXNET3State *s)
1365 {
1366 struct Vmxnet3_VariableLenConfDesc pm_descr;
1367
1368 pm_descr.confLen =
1369 VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confLen);
1370 pm_descr.confVer =
1371 VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confVer);
1372 pm_descr.confPA =
1373 VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.pmConfDesc.confPA);
1374
1375 vmxnet3_dump_conf_descr("PM State", &pm_descr);
1376 }
1377
1378 static void vmxnet3_update_features(VMXNET3State *s)
1379 {
1380 uint32_t guest_features;
1381 int rxcso_supported;
1382
1383 guest_features = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
1384 devRead.misc.uptFeatures);
1385
1386 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM);
1387 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN);
1388 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO);
1389
1390 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1391 s->lro_supported, rxcso_supported,
1392 s->rx_vlan_stripping);
1393 if (s->peer_has_vhdr) {
1394 qemu_set_offload(qemu_get_queue(s->nic)->peer,
1395 rxcso_supported,
1396 s->lro_supported,
1397 s->lro_supported,
1398 0,
1399 0);
1400 }
1401 }
1402
1403 static bool vmxnet3_verify_intx(VMXNET3State *s, int intx)
1404 {
1405 return s->msix_used || s->msi_used || (intx ==
1406 (pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1));
1407 }
1408
1409 static void vmxnet3_validate_interrupt_idx(bool is_msix, int idx)
1410 {
1411 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS;
1412 if (idx >= max_ints) {
1413 hw_error("Bad interrupt index: %d\n", idx);
1414 }
1415 }
1416
1417 static void vmxnet3_validate_interrupts(VMXNET3State *s)
1418 {
1419 int i;
1420
1421 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx);
1422 vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx);
1423
1424 for (i = 0; i < s->txq_num; i++) {
1425 int idx = s->txq_descr[i].intr_idx;
1426 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx);
1427 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1428 }
1429
1430 for (i = 0; i < s->rxq_num; i++) {
1431 int idx = s->rxq_descr[i].intr_idx;
1432 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx);
1433 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1434 }
1435 }
1436
1437 static void vmxnet3_validate_queues(VMXNET3State *s)
1438 {
1439 /*
1440 * txq_num and rxq_num are total number of queues
1441 * configured by guest. These numbers must not
1442 * exceed corresponding maximal values.
1443 */
1444
1445 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) {
1446 hw_error("Bad TX queues number: %d\n", s->txq_num);
1447 }
1448
1449 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) {
1450 hw_error("Bad RX queues number: %d\n", s->rxq_num);
1451 }
1452 }
1453
1454 static void vmxnet3_activate_device(VMXNET3State *s)
1455 {
1456 int i;
1457 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1;
1458 hwaddr qdescr_table_pa;
1459 uint64_t pa;
1460 uint32_t size;
1461
1462 /* Verify configuration consistency */
1463 if (!vmxnet3_verify_driver_magic(s->drv_shmem)) {
1464 VMW_ERPRN("Device configuration received from driver is invalid");
1465 return;
1466 }
1467
1468 /* Verify if device is active */
1469 if (s->device_active) {
1470 VMW_CFPRN("Vmxnet3 device is active");
1471 return;
1472 }
1473
1474 vmxnet3_adjust_by_guest_type(s);
1475 vmxnet3_update_features(s);
1476 vmxnet3_update_pm_state(s);
1477 vmxnet3_setup_rx_filtering(s);
1478 /* Cache fields from shared memory */
1479 s->mtu = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.misc.mtu);
1480 VMW_CFPRN("MTU is %u", s->mtu);
1481
1482 s->max_rx_frags =
1483 VMXNET3_READ_DRV_SHARED16(s->drv_shmem, devRead.misc.maxNumRxSG);
1484
1485 if (s->max_rx_frags == 0) {
1486 s->max_rx_frags = 1;
1487 }
1488
1489 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags);
1490
1491 s->event_int_idx =
1492 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.eventIntrIdx);
1493 assert(vmxnet3_verify_intx(s, s->event_int_idx));
1494 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx);
1495
1496 s->auto_int_masking =
1497 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.autoMask);
1498 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking);
1499
1500 s->txq_num =
1501 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numTxQueues);
1502 s->rxq_num =
1503 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numRxQueues);
1504
1505 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num);
1506 vmxnet3_validate_queues(s);
1507
1508 qdescr_table_pa =
1509 VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.misc.queueDescPA);
1510 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa);
1511
1512 /*
1513 * Worst-case scenario is a packet that holds all TX rings space so
1514 * we calculate total size of all TX rings for max TX fragments number
1515 */
1516 s->max_tx_frags = 0;
1517
1518 /* TX queues */
1519 for (i = 0; i < s->txq_num; i++) {
1520 hwaddr qdescr_pa =
1521 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc);
1522
1523 /* Read interrupt number for this TX queue */
1524 s->txq_descr[i].intr_idx =
1525 VMXNET3_READ_TX_QUEUE_DESCR8(qdescr_pa, conf.intrIdx);
1526 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx));
1527
1528 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx);
1529
1530 /* Read rings memory locations for TX queues */
1531 pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.txRingBasePA);
1532 size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.txRingSize);
1533
1534 vmxnet3_ring_init(&s->txq_descr[i].tx_ring, pa, size,
1535 sizeof(struct Vmxnet3_TxDesc), false);
1536 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring);
1537
1538 s->max_tx_frags += size;
1539
1540 /* TXC ring */
1541 pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.compRingBasePA);
1542 size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.compRingSize);
1543 vmxnet3_ring_init(&s->txq_descr[i].comp_ring, pa, size,
1544 sizeof(struct Vmxnet3_TxCompDesc), true);
1545 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring);
1546
1547 s->txq_descr[i].tx_stats_pa =
1548 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats);
1549
1550 memset(&s->txq_descr[i].txq_stats, 0,
1551 sizeof(s->txq_descr[i].txq_stats));
1552
1553 /* Fill device-managed parameters for queues */
1554 VMXNET3_WRITE_TX_QUEUE_DESCR32(qdescr_pa,
1555 ctrl.txThreshold,
1556 VMXNET3_DEF_TX_THRESHOLD);
1557 }
1558
1559 /* Preallocate TX packet wrapper */
1560 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags);
1561 vmxnet_tx_pkt_init(&s->tx_pkt, s->max_tx_frags, s->peer_has_vhdr);
1562 vmxnet_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
1563
1564 /* Read rings memory locations for RX queues */
1565 for (i = 0; i < s->rxq_num; i++) {
1566 int j;
1567 hwaddr qd_pa =
1568 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) +
1569 i * sizeof(struct Vmxnet3_RxQueueDesc);
1570
1571 /* Read interrupt number for this RX queue */
1572 s->rxq_descr[i].intr_idx =
1573 VMXNET3_READ_TX_QUEUE_DESCR8(qd_pa, conf.intrIdx);
1574 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx));
1575
1576 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx);
1577
1578 /* Read rings memory locations */
1579 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) {
1580 /* RX rings */
1581 pa = VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa, conf.rxRingBasePA[j]);
1582 size = VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa, conf.rxRingSize[j]);
1583 vmxnet3_ring_init(&s->rxq_descr[i].rx_ring[j], pa, size,
1584 sizeof(struct Vmxnet3_RxDesc), false);
1585 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d",
1586 i, j, pa, size);
1587 }
1588
1589 /* RXC ring */
1590 pa = VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa, conf.compRingBasePA);
1591 size = VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa, conf.compRingSize);
1592 vmxnet3_ring_init(&s->rxq_descr[i].comp_ring, pa, size,
1593 sizeof(struct Vmxnet3_RxCompDesc), true);
1594 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size);
1595
1596 s->rxq_descr[i].rx_stats_pa =
1597 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats);
1598 memset(&s->rxq_descr[i].rxq_stats, 0,
1599 sizeof(s->rxq_descr[i].rxq_stats));
1600 }
1601
1602 vmxnet3_validate_interrupts(s);
1603
1604 /* Make sure everything is in place before device activation */
1605 smp_wmb();
1606
1607 vmxnet3_reset_mac(s);
1608
1609 s->device_active = true;
1610 }
1611
1612 static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd)
1613 {
1614 s->last_command = cmd;
1615
1616 switch (cmd) {
1617 case VMXNET3_CMD_GET_PERM_MAC_HI:
1618 VMW_CBPRN("Set: Get upper part of permanent MAC");
1619 break;
1620
1621 case VMXNET3_CMD_GET_PERM_MAC_LO:
1622 VMW_CBPRN("Set: Get lower part of permanent MAC");
1623 break;
1624
1625 case VMXNET3_CMD_GET_STATS:
1626 VMW_CBPRN("Set: Get device statistics");
1627 vmxnet3_fill_stats(s);
1628 break;
1629
1630 case VMXNET3_CMD_ACTIVATE_DEV:
1631 VMW_CBPRN("Set: Activating vmxnet3 device");
1632 vmxnet3_activate_device(s);
1633 break;
1634
1635 case VMXNET3_CMD_UPDATE_RX_MODE:
1636 VMW_CBPRN("Set: Update rx mode");
1637 vmxnet3_update_rx_mode(s);
1638 break;
1639
1640 case VMXNET3_CMD_UPDATE_VLAN_FILTERS:
1641 VMW_CBPRN("Set: Update VLAN filters");
1642 vmxnet3_update_vlan_filters(s);
1643 break;
1644
1645 case VMXNET3_CMD_UPDATE_MAC_FILTERS:
1646 VMW_CBPRN("Set: Update MAC filters");
1647 vmxnet3_update_mcast_filters(s);
1648 break;
1649
1650 case VMXNET3_CMD_UPDATE_FEATURE:
1651 VMW_CBPRN("Set: Update features");
1652 vmxnet3_update_features(s);
1653 break;
1654
1655 case VMXNET3_CMD_UPDATE_PMCFG:
1656 VMW_CBPRN("Set: Update power management config");
1657 vmxnet3_update_pm_state(s);
1658 break;
1659
1660 case VMXNET3_CMD_GET_LINK:
1661 VMW_CBPRN("Set: Get link");
1662 break;
1663
1664 case VMXNET3_CMD_RESET_DEV:
1665 VMW_CBPRN("Set: Reset device");
1666 vmxnet3_reset(s);
1667 break;
1668
1669 case VMXNET3_CMD_QUIESCE_DEV:
1670 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device");
1671 vmxnet3_deactivate_device(s);
1672 break;
1673
1674 case VMXNET3_CMD_GET_CONF_INTR:
1675 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1676 break;
1677
1678 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO:
1679 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - "
1680 "adaptive ring info flags");
1681 break;
1682
1683 case VMXNET3_CMD_GET_DID_LO:
1684 VMW_CBPRN("Set: Get lower part of device ID");
1685 break;
1686
1687 case VMXNET3_CMD_GET_DID_HI:
1688 VMW_CBPRN("Set: Get upper part of device ID");
1689 break;
1690
1691 case VMXNET3_CMD_GET_DEV_EXTRA_INFO:
1692 VMW_CBPRN("Set: Get device extra info");
1693 break;
1694
1695 default:
1696 VMW_CBPRN("Received unknown command: %" PRIx64, cmd);
1697 break;
1698 }
1699 }
1700
1701 static uint64_t vmxnet3_get_command_status(VMXNET3State *s)
1702 {
1703 uint64_t ret;
1704
1705 switch (s->last_command) {
1706 case VMXNET3_CMD_ACTIVATE_DEV:
1707 ret = (s->device_active) ? 0 : 1;
1708 VMW_CFPRN("Device active: %" PRIx64, ret);
1709 break;
1710
1711 case VMXNET3_CMD_RESET_DEV:
1712 case VMXNET3_CMD_QUIESCE_DEV:
1713 case VMXNET3_CMD_GET_QUEUE_STATUS:
1714 case VMXNET3_CMD_GET_DEV_EXTRA_INFO:
1715 ret = 0;
1716 break;
1717
1718 case VMXNET3_CMD_GET_LINK:
1719 ret = s->link_status_and_speed;
1720 VMW_CFPRN("Link and speed: %" PRIx64, ret);
1721 break;
1722
1723 case VMXNET3_CMD_GET_PERM_MAC_LO:
1724 ret = vmxnet3_get_mac_low(&s->perm_mac);
1725 break;
1726
1727 case VMXNET3_CMD_GET_PERM_MAC_HI:
1728 ret = vmxnet3_get_mac_high(&s->perm_mac);
1729 break;
1730
1731 case VMXNET3_CMD_GET_CONF_INTR:
1732 ret = vmxnet3_get_interrupt_config(s);
1733 break;
1734
1735 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO:
1736 ret = VMXNET3_DISABLE_ADAPTIVE_RING;
1737 break;
1738
1739 case VMXNET3_CMD_GET_DID_LO:
1740 ret = PCI_DEVICE_ID_VMWARE_VMXNET3;
1741 break;
1742
1743 case VMXNET3_CMD_GET_DID_HI:
1744 ret = VMXNET3_DEVICE_REVISION;
1745 break;
1746
1747 default:
1748 VMW_WRPRN("Received request for unknown command: %x", s->last_command);
1749 ret = 0;
1750 break;
1751 }
1752
1753 return ret;
1754 }
1755
1756 static void vmxnet3_set_events(VMXNET3State *s, uint32_t val)
1757 {
1758 uint32_t events;
1759
1760 VMW_CBPRN("Setting events: 0x%x", val);
1761 events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) | val;
1762 VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
1763 }
1764
1765 static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val)
1766 {
1767 uint32_t events;
1768
1769 VMW_CBPRN("Clearing events: 0x%x", val);
1770 events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) & ~val;
1771 VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
1772 }
1773
1774 static void
1775 vmxnet3_io_bar1_write(void *opaque,
1776 hwaddr addr,
1777 uint64_t val,
1778 unsigned size)
1779 {
1780 VMXNET3State *s = opaque;
1781
1782 switch (addr) {
1783 /* Vmxnet3 Revision Report Selection */
1784 case VMXNET3_REG_VRRS:
1785 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d",
1786 val, size);
1787 break;
1788
1789 /* UPT Version Report Selection */
1790 case VMXNET3_REG_UVRS:
1791 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d",
1792 val, size);
1793 break;
1794
1795 /* Driver Shared Address Low */
1796 case VMXNET3_REG_DSAL:
1797 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d",
1798 val, size);
1799 /*
1800 * Guest driver will first write the low part of the shared
1801 * memory address. We save it to temp variable and set the
1802 * shared address only after we get the high part
1803 */
1804 if (val == 0) {
1805 vmxnet3_deactivate_device(s);
1806 }
1807 s->temp_shared_guest_driver_memory = val;
1808 s->drv_shmem = 0;
1809 break;
1810
1811 /* Driver Shared Address High */
1812 case VMXNET3_REG_DSAH:
1813 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d",
1814 val, size);
1815 /*
1816 * Set the shared memory between guest driver and device.
1817 * We already should have low address part.
1818 */
1819 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32);
1820 break;
1821
1822 /* Command */
1823 case VMXNET3_REG_CMD:
1824 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d",
1825 val, size);
1826 vmxnet3_handle_command(s, val);
1827 break;
1828
1829 /* MAC Address Low */
1830 case VMXNET3_REG_MACL:
1831 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d",
1832 val, size);
1833 s->temp_mac = val;
1834 break;
1835
1836 /* MAC Address High */
1837 case VMXNET3_REG_MACH:
1838 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d",
1839 val, size);
1840 vmxnet3_set_variable_mac(s, val, s->temp_mac);
1841 break;
1842
1843 /* Interrupt Cause Register */
1844 case VMXNET3_REG_ICR:
1845 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d",
1846 val, size);
1847 g_assert_not_reached();
1848 break;
1849
1850 /* Event Cause Register */
1851 case VMXNET3_REG_ECR:
1852 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d",
1853 val, size);
1854 vmxnet3_ack_events(s, val);
1855 break;
1856
1857 default:
1858 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d",
1859 addr, val, size);
1860 break;
1861 }
1862 }
1863
1864 static uint64_t
1865 vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size)
1866 {
1867 VMXNET3State *s = opaque;
1868 uint64_t ret = 0;
1869
1870 switch (addr) {
1871 /* Vmxnet3 Revision Report Selection */
1872 case VMXNET3_REG_VRRS:
1873 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size);
1874 ret = VMXNET3_DEVICE_REVISION;
1875 break;
1876
1877 /* UPT Version Report Selection */
1878 case VMXNET3_REG_UVRS:
1879 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size);
1880 ret = VMXNET3_UPT_REVISION;
1881 break;
1882
1883 /* Command */
1884 case VMXNET3_REG_CMD:
1885 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size);
1886 ret = vmxnet3_get_command_status(s);
1887 break;
1888
1889 /* MAC Address Low */
1890 case VMXNET3_REG_MACL:
1891 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size);
1892 ret = vmxnet3_get_mac_low(&s->conf.macaddr);
1893 break;
1894
1895 /* MAC Address High */
1896 case VMXNET3_REG_MACH:
1897 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size);
1898 ret = vmxnet3_get_mac_high(&s->conf.macaddr);
1899 break;
1900
1901 /*
1902 * Interrupt Cause Register
1903 * Used for legacy interrupts only so interrupt index always 0
1904 */
1905 case VMXNET3_REG_ICR:
1906 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size);
1907 if (vmxnet3_interrupt_asserted(s, 0)) {
1908 vmxnet3_clear_interrupt(s, 0);
1909 ret = true;
1910 } else {
1911 ret = false;
1912 }
1913 break;
1914
1915 default:
1916 VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size);
1917 break;
1918 }
1919
1920 return ret;
1921 }
1922
1923 static int
1924 vmxnet3_can_receive(NetClientState *nc)
1925 {
1926 VMXNET3State *s = qemu_get_nic_opaque(nc);
1927 return s->device_active &&
1928 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP);
1929 }
1930
1931 static inline bool
1932 vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data)
1933 {
1934 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK;
1935 if (IS_SPECIAL_VLAN_ID(vlan_tag)) {
1936 return true;
1937 }
1938
1939 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag);
1940 }
1941
1942 static bool
1943 vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac)
1944 {
1945 int i;
1946 for (i = 0; i < s->mcast_list_len; i++) {
1947 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) {
1948 return true;
1949 }
1950 }
1951 return false;
1952 }
1953
1954 static bool
1955 vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data,
1956 size_t size)
1957 {
1958 struct eth_header *ehdr = PKT_GET_ETH_HDR(data);
1959
1960 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) {
1961 return true;
1962 }
1963
1964 if (!vmxnet3_is_registered_vlan(s, data)) {
1965 return false;
1966 }
1967
1968 switch (vmxnet_rx_pkt_get_packet_type(s->rx_pkt)) {
1969 case ETH_PKT_UCAST:
1970 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) {
1971 return false;
1972 }
1973 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) {
1974 return false;
1975 }
1976 break;
1977
1978 case ETH_PKT_BCAST:
1979 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) {
1980 return false;
1981 }
1982 break;
1983
1984 case ETH_PKT_MCAST:
1985 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) {
1986 return true;
1987 }
1988 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) {
1989 return false;
1990 }
1991 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) {
1992 return false;
1993 }
1994 break;
1995
1996 default:
1997 g_assert_not_reached();
1998 }
1999
2000 return true;
2001 }
2002
2003 static ssize_t
2004 vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size)
2005 {
2006 VMXNET3State *s = qemu_get_nic_opaque(nc);
2007 size_t bytes_indicated;
2008 uint8_t min_buf[MIN_BUF_SIZE];
2009
2010 if (!vmxnet3_can_receive(nc)) {
2011 VMW_PKPRN("Cannot receive now");
2012 return -1;
2013 }
2014
2015 if (s->peer_has_vhdr) {
2016 vmxnet_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf);
2017 buf += sizeof(struct virtio_net_hdr);
2018 size -= sizeof(struct virtio_net_hdr);
2019 }
2020
2021 /* Pad to minimum Ethernet frame length */
2022 if (size < sizeof(min_buf)) {
2023 memcpy(min_buf, buf, size);
2024 memset(&min_buf[size], 0, sizeof(min_buf) - size);
2025 buf = min_buf;
2026 size = sizeof(min_buf);
2027 }
2028
2029 vmxnet_rx_pkt_set_packet_type(s->rx_pkt,
2030 get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
2031
2032 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) {
2033 vmxnet_rx_pkt_set_protocols(s->rx_pkt, buf, size);
2034 vmxnet3_rx_need_csum_calculate(s->rx_pkt, buf, size);
2035 vmxnet_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping);
2036 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1;
2037 if (bytes_indicated < size) {
2038 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated, size);
2039 }
2040 } else {
2041 VMW_PKPRN("Packet dropped by RX filter");
2042 bytes_indicated = size;
2043 }
2044
2045 assert(size > 0);
2046 assert(bytes_indicated != 0);
2047 return bytes_indicated;
2048 }
2049
2050 static void vmxnet3_set_link_status(NetClientState *nc)
2051 {
2052 VMXNET3State *s = qemu_get_nic_opaque(nc);
2053
2054 if (nc->link_down) {
2055 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP;
2056 } else {
2057 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP;
2058 }
2059
2060 vmxnet3_set_events(s, VMXNET3_ECR_LINK);
2061 vmxnet3_trigger_interrupt(s, s->event_int_idx);
2062 }
2063
2064 static NetClientInfo net_vmxnet3_info = {
2065 .type = NET_CLIENT_OPTIONS_KIND_NIC,
2066 .size = sizeof(NICState),
2067 .receive = vmxnet3_receive,
2068 .link_status_changed = vmxnet3_set_link_status,
2069 };
2070
2071 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s)
2072 {
2073 NetClientState *nc = qemu_get_queue(s->nic);
2074
2075 if (qemu_has_vnet_hdr(nc->peer)) {
2076 return true;
2077 }
2078
2079 return false;
2080 }
2081
2082 static void vmxnet3_net_uninit(VMXNET3State *s)
2083 {
2084 g_free(s->mcast_list);
2085 vmxnet3_deactivate_device(s);
2086 qemu_del_nic(s->nic);
2087 }
2088
2089 static void vmxnet3_net_init(VMXNET3State *s)
2090 {
2091 DeviceState *d = DEVICE(s);
2092
2093 VMW_CBPRN("vmxnet3_net_init called...");
2094
2095 qemu_macaddr_default_if_unset(&s->conf.macaddr);
2096
2097 /* Windows guest will query the address that was set on init */
2098 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a));
2099
2100 s->mcast_list = NULL;
2101 s->mcast_list_len = 0;
2102
2103 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP;
2104
2105 VMW_CFPRN("Permanent MAC: " VMXNET_MF, VMXNET_MA(s->perm_mac.a));
2106
2107 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf,
2108 object_get_typename(OBJECT(s)),
2109 d->id, s);
2110
2111 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s);
2112 s->tx_sop = true;
2113 s->skip_current_tx_pkt = false;
2114 s->tx_pkt = NULL;
2115 s->rx_pkt = NULL;
2116 s->rx_vlan_stripping = false;
2117 s->lro_supported = false;
2118
2119 if (s->peer_has_vhdr) {
2120 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer,
2121 sizeof(struct virtio_net_hdr));
2122
2123 qemu_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1);
2124 }
2125
2126 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
2127 }
2128
2129 static void
2130 vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors)
2131 {
2132 PCIDevice *d = PCI_DEVICE(s);
2133 int i;
2134 for (i = 0; i < num_vectors; i++) {
2135 msix_vector_unuse(d, i);
2136 }
2137 }
2138
2139 static bool
2140 vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors)
2141 {
2142 PCIDevice *d = PCI_DEVICE(s);
2143 int i;
2144 for (i = 0; i < num_vectors; i++) {
2145 int res = msix_vector_use(d, i);
2146 if (0 > res) {
2147 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i, res);
2148 vmxnet3_unuse_msix_vectors(s, i);
2149 return false;
2150 }
2151 }
2152 return true;
2153 }
2154
2155 static bool
2156 vmxnet3_init_msix(VMXNET3State *s)
2157 {
2158 PCIDevice *d = PCI_DEVICE(s);
2159 int res = msix_init(d, VMXNET3_MAX_INTRS,
2160 &s->msix_bar,
2161 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
2162 &s->msix_bar,
2163 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s),
2164 VMXNET3_MSIX_OFFSET(s));
2165
2166 if (0 > res) {
2167 VMW_WRPRN("Failed to initialize MSI-X, error %d", res);
2168 s->msix_used = false;
2169 } else {
2170 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2171 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res);
2172 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2173 s->msix_used = false;
2174 } else {
2175 s->msix_used = true;
2176 }
2177 }
2178 return s->msix_used;
2179 }
2180
2181 static void
2182 vmxnet3_cleanup_msix(VMXNET3State *s)
2183 {
2184 PCIDevice *d = PCI_DEVICE(s);
2185
2186 if (s->msix_used) {
2187 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS);
2188 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2189 }
2190 }
2191
2192 #define VMXNET3_USE_64BIT (true)
2193 #define VMXNET3_PER_VECTOR_MASK (false)
2194
2195 static bool
2196 vmxnet3_init_msi(VMXNET3State *s)
2197 {
2198 PCIDevice *d = PCI_DEVICE(s);
2199 int res;
2200
2201 res = msi_init(d, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS,
2202 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK);
2203 if (0 > res) {
2204 VMW_WRPRN("Failed to initialize MSI, error %d", res);
2205 s->msi_used = false;
2206 } else {
2207 s->msi_used = true;
2208 }
2209
2210 return s->msi_used;
2211 }
2212
2213 static void
2214 vmxnet3_cleanup_msi(VMXNET3State *s)
2215 {
2216 PCIDevice *d = PCI_DEVICE(s);
2217
2218 if (s->msi_used) {
2219 msi_uninit(d);
2220 }
2221 }
2222
2223 static void
2224 vmxnet3_msix_save(QEMUFile *f, void *opaque)
2225 {
2226 PCIDevice *d = PCI_DEVICE(opaque);
2227 msix_save(d, f);
2228 }
2229
2230 static int
2231 vmxnet3_msix_load(QEMUFile *f, void *opaque, int version_id)
2232 {
2233 PCIDevice *d = PCI_DEVICE(opaque);
2234 msix_load(d, f);
2235 return 0;
2236 }
2237
2238 static const MemoryRegionOps b0_ops = {
2239 .read = vmxnet3_io_bar0_read,
2240 .write = vmxnet3_io_bar0_write,
2241 .endianness = DEVICE_LITTLE_ENDIAN,
2242 .impl = {
2243 .min_access_size = 4,
2244 .max_access_size = 4,
2245 },
2246 };
2247
2248 static const MemoryRegionOps b1_ops = {
2249 .read = vmxnet3_io_bar1_read,
2250 .write = vmxnet3_io_bar1_write,
2251 .endianness = DEVICE_LITTLE_ENDIAN,
2252 .impl = {
2253 .min_access_size = 4,
2254 .max_access_size = 4,
2255 },
2256 };
2257
2258 static uint8_t *vmxnet3_device_serial_num(VMXNET3State *s)
2259 {
2260 static uint64_t dsn_payload;
2261 uint8_t *dsnp = (uint8_t *)&dsn_payload;
2262
2263 dsnp[0] = 0xfe;
2264 dsnp[1] = s->conf.macaddr.a[3];
2265 dsnp[2] = s->conf.macaddr.a[4];
2266 dsnp[3] = s->conf.macaddr.a[5];
2267 dsnp[4] = s->conf.macaddr.a[0];
2268 dsnp[5] = s->conf.macaddr.a[1];
2269 dsnp[6] = s->conf.macaddr.a[2];
2270 dsnp[7] = 0xff;
2271 return dsnp;
2272 }
2273
2274 static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
2275 {
2276 DeviceState *dev = DEVICE(pci_dev);
2277 VMXNET3State *s = VMXNET3(pci_dev);
2278
2279 VMW_CBPRN("Starting init...");
2280
2281 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s,
2282 "vmxnet3-b0", VMXNET3_PT_REG_SIZE);
2283 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
2284 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
2285
2286 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s,
2287 "vmxnet3-b1", VMXNET3_VD_REG_SIZE);
2288 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
2289 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
2290
2291 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar",
2292 VMXNET3_MSIX_BAR_SIZE);
2293 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
2294 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
2295
2296 vmxnet3_reset_interrupt_states(s);
2297
2298 /* Interrupt pin A */
2299 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
2300
2301 if (!vmxnet3_init_msix(s)) {
2302 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2303 }
2304
2305 if (!vmxnet3_init_msi(s)) {
2306 VMW_WRPRN("Failed to initialize MSI, configuration is inconsistent.");
2307 }
2308
2309 vmxnet3_net_init(s);
2310
2311 if (pci_is_express(pci_dev)) {
2312 if (pci_bus_is_express(pci_dev->bus)) {
2313 pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET);
2314 }
2315
2316 pcie_add_capability(pci_dev, PCI_EXT_CAP_ID_DSN, 0x1,
2317 VMXNET3_DSN_OFFSET, PCI_EXT_CAP_DSN_SIZEOF);
2318 memcpy(pci_dev->config + VMXNET3_DSN_OFFSET + 4,
2319 vmxnet3_device_serial_num(s), sizeof(uint64_t));
2320 }
2321
2322 register_savevm(dev, "vmxnet3-msix", -1, 1,
2323 vmxnet3_msix_save, vmxnet3_msix_load, s);
2324 }
2325
2326 static void vmxnet3_instance_init(Object *obj)
2327 {
2328 VMXNET3State *s = VMXNET3(obj);
2329 device_add_bootindex_property(obj, &s->conf.bootindex,
2330 "bootindex", "/ethernet-phy@0",
2331 DEVICE(obj), NULL);
2332 }
2333
2334 static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
2335 {
2336 DeviceState *dev = DEVICE(pci_dev);
2337 VMXNET3State *s = VMXNET3(pci_dev);
2338
2339 VMW_CBPRN("Starting uninit...");
2340
2341 unregister_savevm(dev, "vmxnet3-msix", s);
2342
2343 vmxnet3_net_uninit(s);
2344
2345 vmxnet3_cleanup_msix(s);
2346
2347 vmxnet3_cleanup_msi(s);
2348 }
2349
2350 static void vmxnet3_qdev_reset(DeviceState *dev)
2351 {
2352 PCIDevice *d = PCI_DEVICE(dev);
2353 VMXNET3State *s = VMXNET3(d);
2354
2355 VMW_CBPRN("Starting QDEV reset...");
2356 vmxnet3_reset(s);
2357 }
2358
2359 static bool vmxnet3_mc_list_needed(void *opaque)
2360 {
2361 return true;
2362 }
2363
2364 static int vmxnet3_mcast_list_pre_load(void *opaque)
2365 {
2366 VMXNET3State *s = opaque;
2367
2368 s->mcast_list = g_malloc(s->mcast_list_buff_size);
2369
2370 return 0;
2371 }
2372
2373
2374 static void vmxnet3_pre_save(void *opaque)
2375 {
2376 VMXNET3State *s = opaque;
2377
2378 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr);
2379 }
2380
2381 static const VMStateDescription vmxstate_vmxnet3_mcast_list = {
2382 .name = "vmxnet3/mcast_list",
2383 .version_id = 1,
2384 .minimum_version_id = 1,
2385 .pre_load = vmxnet3_mcast_list_pre_load,
2386 .needed = vmxnet3_mc_list_needed,
2387 .fields = (VMStateField[]) {
2388 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL, 0,
2389 mcast_list_buff_size),
2390 VMSTATE_END_OF_LIST()
2391 }
2392 };
2393
2394 static void vmxnet3_get_ring_from_file(QEMUFile *f, Vmxnet3Ring *r)
2395 {
2396 r->pa = qemu_get_be64(f);
2397 r->size = qemu_get_be32(f);
2398 r->cell_size = qemu_get_be32(f);
2399 r->next = qemu_get_be32(f);
2400 r->gen = qemu_get_byte(f);
2401 }
2402
2403 static void vmxnet3_put_ring_to_file(QEMUFile *f, Vmxnet3Ring *r)
2404 {
2405 qemu_put_be64(f, r->pa);
2406 qemu_put_be32(f, r->size);
2407 qemu_put_be32(f, r->cell_size);
2408 qemu_put_be32(f, r->next);
2409 qemu_put_byte(f, r->gen);
2410 }
2411
2412 static void vmxnet3_get_tx_stats_from_file(QEMUFile *f,
2413 struct UPT1_TxStats *tx_stat)
2414 {
2415 tx_stat->TSOPktsTxOK = qemu_get_be64(f);
2416 tx_stat->TSOBytesTxOK = qemu_get_be64(f);
2417 tx_stat->ucastPktsTxOK = qemu_get_be64(f);
2418 tx_stat->ucastBytesTxOK = qemu_get_be64(f);
2419 tx_stat->mcastPktsTxOK = qemu_get_be64(f);
2420 tx_stat->mcastBytesTxOK = qemu_get_be64(f);
2421 tx_stat->bcastPktsTxOK = qemu_get_be64(f);
2422 tx_stat->bcastBytesTxOK = qemu_get_be64(f);
2423 tx_stat->pktsTxError = qemu_get_be64(f);
2424 tx_stat->pktsTxDiscard = qemu_get_be64(f);
2425 }
2426
2427 static void vmxnet3_put_tx_stats_to_file(QEMUFile *f,
2428 struct UPT1_TxStats *tx_stat)
2429 {
2430 qemu_put_be64(f, tx_stat->TSOPktsTxOK);
2431 qemu_put_be64(f, tx_stat->TSOBytesTxOK);
2432 qemu_put_be64(f, tx_stat->ucastPktsTxOK);
2433 qemu_put_be64(f, tx_stat->ucastBytesTxOK);
2434 qemu_put_be64(f, tx_stat->mcastPktsTxOK);
2435 qemu_put_be64(f, tx_stat->mcastBytesTxOK);
2436 qemu_put_be64(f, tx_stat->bcastPktsTxOK);
2437 qemu_put_be64(f, tx_stat->bcastBytesTxOK);
2438 qemu_put_be64(f, tx_stat->pktsTxError);
2439 qemu_put_be64(f, tx_stat->pktsTxDiscard);
2440 }
2441
2442 static int vmxnet3_get_txq_descr(QEMUFile *f, void *pv, size_t size)
2443 {
2444 Vmxnet3TxqDescr *r = pv;
2445
2446 vmxnet3_get_ring_from_file(f, &r->tx_ring);
2447 vmxnet3_get_ring_from_file(f, &r->comp_ring);
2448 r->intr_idx = qemu_get_byte(f);
2449 r->tx_stats_pa = qemu_get_be64(f);
2450
2451 vmxnet3_get_tx_stats_from_file(f, &r->txq_stats);
2452
2453 return 0;
2454 }
2455
2456 static void vmxnet3_put_txq_descr(QEMUFile *f, void *pv, size_t size)
2457 {
2458 Vmxnet3TxqDescr *r = pv;
2459
2460 vmxnet3_put_ring_to_file(f, &r->tx_ring);
2461 vmxnet3_put_ring_to_file(f, &r->comp_ring);
2462 qemu_put_byte(f, r->intr_idx);
2463 qemu_put_be64(f, r->tx_stats_pa);
2464 vmxnet3_put_tx_stats_to_file(f, &r->txq_stats);
2465 }
2466
2467 static const VMStateInfo txq_descr_info = {
2468 .name = "txq_descr",
2469 .get = vmxnet3_get_txq_descr,
2470 .put = vmxnet3_put_txq_descr
2471 };
2472
2473 static void vmxnet3_get_rx_stats_from_file(QEMUFile *f,
2474 struct UPT1_RxStats *rx_stat)
2475 {
2476 rx_stat->LROPktsRxOK = qemu_get_be64(f);
2477 rx_stat->LROBytesRxOK = qemu_get_be64(f);
2478 rx_stat->ucastPktsRxOK = qemu_get_be64(f);
2479 rx_stat->ucastBytesRxOK = qemu_get_be64(f);
2480 rx_stat->mcastPktsRxOK = qemu_get_be64(f);
2481 rx_stat->mcastBytesRxOK = qemu_get_be64(f);
2482 rx_stat->bcastPktsRxOK = qemu_get_be64(f);
2483 rx_stat->bcastBytesRxOK = qemu_get_be64(f);
2484 rx_stat->pktsRxOutOfBuf = qemu_get_be64(f);
2485 rx_stat->pktsRxError = qemu_get_be64(f);
2486 }
2487
2488 static void vmxnet3_put_rx_stats_to_file(QEMUFile *f,
2489 struct UPT1_RxStats *rx_stat)
2490 {
2491 qemu_put_be64(f, rx_stat->LROPktsRxOK);
2492 qemu_put_be64(f, rx_stat->LROBytesRxOK);
2493 qemu_put_be64(f, rx_stat->ucastPktsRxOK);
2494 qemu_put_be64(f, rx_stat->ucastBytesRxOK);
2495 qemu_put_be64(f, rx_stat->mcastPktsRxOK);
2496 qemu_put_be64(f, rx_stat->mcastBytesRxOK);
2497 qemu_put_be64(f, rx_stat->bcastPktsRxOK);
2498 qemu_put_be64(f, rx_stat->bcastBytesRxOK);
2499 qemu_put_be64(f, rx_stat->pktsRxOutOfBuf);
2500 qemu_put_be64(f, rx_stat->pktsRxError);
2501 }
2502
2503 static int vmxnet3_get_rxq_descr(QEMUFile *f, void *pv, size_t size)
2504 {
2505 Vmxnet3RxqDescr *r = pv;
2506 int i;
2507
2508 for (i = 0; i < VMXNET3_RX_RINGS_PER_QUEUE; i++) {
2509 vmxnet3_get_ring_from_file(f, &r->rx_ring[i]);
2510 }
2511
2512 vmxnet3_get_ring_from_file(f, &r->comp_ring);
2513 r->intr_idx = qemu_get_byte(f);
2514 r->rx_stats_pa = qemu_get_be64(f);
2515
2516 vmxnet3_get_rx_stats_from_file(f, &r->rxq_stats);
2517
2518 return 0;
2519 }
2520
2521 static void vmxnet3_put_rxq_descr(QEMUFile *f, void *pv, size_t size)
2522 {
2523 Vmxnet3RxqDescr *r = pv;
2524 int i;
2525
2526 for (i = 0; i < VMXNET3_RX_RINGS_PER_QUEUE; i++) {
2527 vmxnet3_put_ring_to_file(f, &r->rx_ring[i]);
2528 }
2529
2530 vmxnet3_put_ring_to_file(f, &r->comp_ring);
2531 qemu_put_byte(f, r->intr_idx);
2532 qemu_put_be64(f, r->rx_stats_pa);
2533 vmxnet3_put_rx_stats_to_file(f, &r->rxq_stats);
2534 }
2535
2536 static int vmxnet3_post_load(void *opaque, int version_id)
2537 {
2538 VMXNET3State *s = opaque;
2539 PCIDevice *d = PCI_DEVICE(s);
2540
2541 vmxnet_tx_pkt_init(&s->tx_pkt, s->max_tx_frags, s->peer_has_vhdr);
2542 vmxnet_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
2543
2544 if (s->msix_used) {
2545 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2546 VMW_WRPRN("Failed to re-use MSI-X vectors");
2547 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2548 s->msix_used = false;
2549 return -1;
2550 }
2551 }
2552
2553 vmxnet3_validate_queues(s);
2554 vmxnet3_validate_interrupts(s);
2555
2556 return 0;
2557 }
2558
2559 static const VMStateInfo rxq_descr_info = {
2560 .name = "rxq_descr",
2561 .get = vmxnet3_get_rxq_descr,
2562 .put = vmxnet3_put_rxq_descr
2563 };
2564
2565 static int vmxnet3_get_int_state(QEMUFile *f, void *pv, size_t size)
2566 {
2567 Vmxnet3IntState *r = pv;
2568
2569 r->is_masked = qemu_get_byte(f);
2570 r->is_pending = qemu_get_byte(f);
2571 r->is_asserted = qemu_get_byte(f);
2572
2573 return 0;
2574 }
2575
2576 static void vmxnet3_put_int_state(QEMUFile *f, void *pv, size_t size)
2577 {
2578 Vmxnet3IntState *r = pv;
2579
2580 qemu_put_byte(f, r->is_masked);
2581 qemu_put_byte(f, r->is_pending);
2582 qemu_put_byte(f, r->is_asserted);
2583 }
2584
2585 static const VMStateInfo int_state_info = {
2586 .name = "int_state",
2587 .get = vmxnet3_get_int_state,
2588 .put = vmxnet3_put_int_state
2589 };
2590
2591 static bool vmxnet3_vmstate_need_pcie_device(void *opaque)
2592 {
2593 VMXNET3State *s = VMXNET3(opaque);
2594
2595 return !(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE);
2596 }
2597
2598 static bool vmxnet3_vmstate_test_pci_device(void *opaque, int version_id)
2599 {
2600 return !vmxnet3_vmstate_need_pcie_device(opaque);
2601 }
2602
2603 static const VMStateDescription vmstate_vmxnet3_pcie_device = {
2604 .name = "vmxnet3/pcie",
2605 .version_id = 1,
2606 .minimum_version_id = 1,
2607 .needed = vmxnet3_vmstate_need_pcie_device,
2608 .fields = (VMStateField[]) {
2609 VMSTATE_PCIE_DEVICE(parent_obj, VMXNET3State),
2610 VMSTATE_END_OF_LIST()
2611 }
2612 };
2613
2614 static const VMStateDescription vmstate_vmxnet3 = {
2615 .name = "vmxnet3",
2616 .version_id = 1,
2617 .minimum_version_id = 1,
2618 .pre_save = vmxnet3_pre_save,
2619 .post_load = vmxnet3_post_load,
2620 .fields = (VMStateField[]) {
2621 VMSTATE_STRUCT_TEST(parent_obj, VMXNET3State,
2622 vmxnet3_vmstate_test_pci_device, 0,
2623 vmstate_pci_device, PCIDevice),
2624 VMSTATE_BOOL(rx_packets_compound, VMXNET3State),
2625 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State),
2626 VMSTATE_BOOL(lro_supported, VMXNET3State),
2627 VMSTATE_UINT32(rx_mode, VMXNET3State),
2628 VMSTATE_UINT32(mcast_list_len, VMXNET3State),
2629 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State),
2630 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE),
2631 VMSTATE_UINT32(mtu, VMXNET3State),
2632 VMSTATE_UINT16(max_rx_frags, VMXNET3State),
2633 VMSTATE_UINT32(max_tx_frags, VMXNET3State),
2634 VMSTATE_UINT8(event_int_idx, VMXNET3State),
2635 VMSTATE_BOOL(auto_int_masking, VMXNET3State),
2636 VMSTATE_UINT8(txq_num, VMXNET3State),
2637 VMSTATE_UINT8(rxq_num, VMXNET3State),
2638 VMSTATE_UINT32(device_active, VMXNET3State),
2639 VMSTATE_UINT32(last_command, VMXNET3State),
2640 VMSTATE_UINT32(link_status_and_speed, VMXNET3State),
2641 VMSTATE_UINT32(temp_mac, VMXNET3State),
2642 VMSTATE_UINT64(drv_shmem, VMXNET3State),
2643 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State),
2644
2645 VMSTATE_ARRAY(txq_descr, VMXNET3State,
2646 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, txq_descr_info,
2647 Vmxnet3TxqDescr),
2648 VMSTATE_ARRAY(rxq_descr, VMXNET3State,
2649 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, rxq_descr_info,
2650 Vmxnet3RxqDescr),
2651 VMSTATE_ARRAY(interrupt_states, VMXNET3State, VMXNET3_MAX_INTRS,
2652 0, int_state_info, Vmxnet3IntState),
2653
2654 VMSTATE_END_OF_LIST()
2655 },
2656 .subsections = (const VMStateDescription*[]) {
2657 &vmxstate_vmxnet3_mcast_list,
2658 &vmstate_vmxnet3_pcie_device,
2659 NULL
2660 }
2661 };
2662
2663 static Property vmxnet3_properties[] = {
2664 DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
2665 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags,
2666 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false),
2667 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags,
2668 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false),
2669 DEFINE_PROP_END_OF_LIST(),
2670 };
2671
2672 static void vmxnet3_realize(DeviceState *qdev, Error **errp)
2673 {
2674 VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev);
2675 PCIDevice *pci_dev = PCI_DEVICE(qdev);
2676 VMXNET3State *s = VMXNET3(qdev);
2677
2678 if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) {
2679 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2680 }
2681
2682 vc->parent_dc_realize(qdev, errp);
2683 }
2684
2685 static void vmxnet3_class_init(ObjectClass *class, void *data)
2686 {
2687 DeviceClass *dc = DEVICE_CLASS(class);
2688 PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
2689 VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class);
2690
2691 c->realize = vmxnet3_pci_realize;
2692 c->exit = vmxnet3_pci_uninit;
2693 c->vendor_id = PCI_VENDOR_ID_VMWARE;
2694 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2695 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION;
2696 c->class_id = PCI_CLASS_NETWORK_ETHERNET;
2697 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
2698 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2699 vc->parent_dc_realize = dc->realize;
2700 dc->realize = vmxnet3_realize;
2701 dc->desc = "VMWare Paravirtualized Ethernet v3";
2702 dc->reset = vmxnet3_qdev_reset;
2703 dc->vmsd = &vmstate_vmxnet3;
2704 dc->props = vmxnet3_properties;
2705 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
2706 }
2707
2708 static const TypeInfo vmxnet3_info = {
2709 .name = TYPE_VMXNET3,
2710 .parent = TYPE_PCI_DEVICE,
2711 .class_size = sizeof(VMXNET3Class),
2712 .instance_size = sizeof(VMXNET3State),
2713 .class_init = vmxnet3_class_init,
2714 .instance_init = vmxnet3_instance_init,
2715 };
2716
2717 static void vmxnet3_register_types(void)
2718 {
2719 VMW_CBPRN("vmxnet3_register_types called...");
2720 type_register_static(&vmxnet3_info);
2721 }
2722
2723 type_init(vmxnet3_register_types)
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