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ivshmem: Implement shm=... with a memory backend
[qemu/kevin.git] / hw / net / dp8393x.c
blobe847b77cf4e8385a8608ab1f11585f8200164f01
1 /*
2 * QEMU NS SONIC DP8393x netcard
3 *
4 * Copyright (c) 2008-2009 Herve Poussineau
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/sysbus.h"
22 #include "hw/devices.h"
23 #include "net/net.h"
24 #include "qemu/timer.h"
25 #include <zlib.h>
26
27 //#define DEBUG_SONIC
28
29 #define SONIC_PROM_SIZE 0x1000
30
31 #ifdef DEBUG_SONIC
32 #define DPRINTF(fmt, ...) \
33 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0)
34 static const char* reg_names[] = {
35 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA",
36 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0",
37 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP",
38 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA",
39 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC",
40 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT",
41 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37",
42 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" };
43 #else
44 #define DPRINTF(fmt, ...) do {} while (0)
45 #endif
46
47 #define SONIC_ERROR(fmt, ...) \
48 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
49
50 #define SONIC_CR 0x00
51 #define SONIC_DCR 0x01
52 #define SONIC_RCR 0x02
53 #define SONIC_TCR 0x03
54 #define SONIC_IMR 0x04
55 #define SONIC_ISR 0x05
56 #define SONIC_UTDA 0x06
57 #define SONIC_CTDA 0x07
58 #define SONIC_TPS 0x08
59 #define SONIC_TFC 0x09
60 #define SONIC_TSA0 0x0a
61 #define SONIC_TSA1 0x0b
62 #define SONIC_TFS 0x0c
63 #define SONIC_URDA 0x0d
64 #define SONIC_CRDA 0x0e
65 #define SONIC_CRBA0 0x0f
66 #define SONIC_CRBA1 0x10
67 #define SONIC_RBWC0 0x11
68 #define SONIC_RBWC1 0x12
69 #define SONIC_EOBC 0x13
70 #define SONIC_URRA 0x14
71 #define SONIC_RSA 0x15
72 #define SONIC_REA 0x16
73 #define SONIC_RRP 0x17
74 #define SONIC_RWP 0x18
75 #define SONIC_TRBA0 0x19
76 #define SONIC_TRBA1 0x1a
77 #define SONIC_LLFA 0x1f
78 #define SONIC_TTDA 0x20
79 #define SONIC_CEP 0x21
80 #define SONIC_CAP2 0x22
81 #define SONIC_CAP1 0x23
82 #define SONIC_CAP0 0x24
83 #define SONIC_CE 0x25
84 #define SONIC_CDP 0x26
85 #define SONIC_CDC 0x27
86 #define SONIC_SR 0x28
87 #define SONIC_WT0 0x29
88 #define SONIC_WT1 0x2a
89 #define SONIC_RSC 0x2b
90 #define SONIC_CRCT 0x2c
91 #define SONIC_FAET 0x2d
92 #define SONIC_MPT 0x2e
93 #define SONIC_MDT 0x2f
94 #define SONIC_DCR2 0x3f
95
96 #define SONIC_CR_HTX 0x0001
97 #define SONIC_CR_TXP 0x0002
98 #define SONIC_CR_RXDIS 0x0004
99 #define SONIC_CR_RXEN 0x0008
100 #define SONIC_CR_STP 0x0010
101 #define SONIC_CR_ST 0x0020
102 #define SONIC_CR_RST 0x0080
103 #define SONIC_CR_RRRA 0x0100
104 #define SONIC_CR_LCAM 0x0200
105 #define SONIC_CR_MASK 0x03bf
106
107 #define SONIC_DCR_DW 0x0020
108 #define SONIC_DCR_LBR 0x2000
109 #define SONIC_DCR_EXBUS 0x8000
110
111 #define SONIC_RCR_PRX 0x0001
112 #define SONIC_RCR_LBK 0x0002
113 #define SONIC_RCR_FAER 0x0004
114 #define SONIC_RCR_CRCR 0x0008
115 #define SONIC_RCR_CRS 0x0020
116 #define SONIC_RCR_LPKT 0x0040
117 #define SONIC_RCR_BC 0x0080
118 #define SONIC_RCR_MC 0x0100
119 #define SONIC_RCR_LB0 0x0200
120 #define SONIC_RCR_LB1 0x0400
121 #define SONIC_RCR_AMC 0x0800
122 #define SONIC_RCR_PRO 0x1000
123 #define SONIC_RCR_BRD 0x2000
124 #define SONIC_RCR_RNT 0x4000
125
126 #define SONIC_TCR_PTX 0x0001
127 #define SONIC_TCR_BCM 0x0002
128 #define SONIC_TCR_FU 0x0004
129 #define SONIC_TCR_EXC 0x0040
130 #define SONIC_TCR_CRSL 0x0080
131 #define SONIC_TCR_NCRS 0x0100
132 #define SONIC_TCR_EXD 0x0400
133 #define SONIC_TCR_CRCI 0x2000
134 #define SONIC_TCR_PINT 0x8000
135
136 #define SONIC_ISR_RBE 0x0020
137 #define SONIC_ISR_RDE 0x0040
138 #define SONIC_ISR_TC 0x0080
139 #define SONIC_ISR_TXDN 0x0200
140 #define SONIC_ISR_PKTRX 0x0400
141 #define SONIC_ISR_PINT 0x0800
142 #define SONIC_ISR_LCD 0x1000
143
144 #define TYPE_DP8393X "dp8393x"
145 #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X)
146
147 typedef struct dp8393xState {
148 SysBusDevice parent_obj;
149
150 /* Hardware */
151 uint8_t it_shift;
152 qemu_irq irq;
153 #ifdef DEBUG_SONIC
154 int irq_level;
155 #endif
156 QEMUTimer *watchdog;
157 int64_t wt_last_update;
158 NICConf conf;
159 NICState *nic;
160 MemoryRegion mmio;
161 MemoryRegion prom;
162
163 /* Registers */
164 uint8_t cam[16][6];
165 uint16_t regs[0x40];
166
167 /* Temporaries */
168 uint8_t tx_buffer[0x10000];
169 int loopback_packet;
170
171 /* Memory access */
172 void *dma_mr;
173 AddressSpace as;
174 } dp8393xState;
175
176 static void dp8393x_update_irq(dp8393xState *s)
177 {
178 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0;
179
180 #ifdef DEBUG_SONIC
181 if (level != s->irq_level) {
182 s->irq_level = level;
183 if (level) {
184 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]);
185 } else {
186 DPRINTF("lower irq\n");
187 }
188 }
189 #endif
190
191 qemu_set_irq(s->irq, level);
192 }
193
194 static void dp8393x_do_load_cam(dp8393xState *s)
195 {
196 uint16_t data[8];
197 int width, size;
198 uint16_t index = 0;
199
200 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
201 size = sizeof(uint16_t) * 4 * width;
202
203 while (s->regs[SONIC_CDC] & 0x1f) {
204 /* Fill current entry */
205 address_space_rw(&s->as,
206 (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP],
207 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
208 s->cam[index][0] = data[1 * width] & 0xff;
209 s->cam[index][1] = data[1 * width] >> 8;
210 s->cam[index][2] = data[2 * width] & 0xff;
211 s->cam[index][3] = data[2 * width] >> 8;
212 s->cam[index][4] = data[3 * width] & 0xff;
213 s->cam[index][5] = data[3 * width] >> 8;
214 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index,
215 s->cam[index][0], s->cam[index][1], s->cam[index][2],
216 s->cam[index][3], s->cam[index][4], s->cam[index][5]);
217 /* Move to next entry */
218 s->regs[SONIC_CDC]--;
219 s->regs[SONIC_CDP] += size;
220 index++;
221 }
222
223 /* Read CAM enable */
224 address_space_rw(&s->as,
225 (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP],
226 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
227 s->regs[SONIC_CE] = data[0 * width];
228 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
229
230 /* Done */
231 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM;
232 s->regs[SONIC_ISR] |= SONIC_ISR_LCD;
233 dp8393x_update_irq(s);
234 }
235
236 static void dp8393x_do_read_rra(dp8393xState *s)
237 {
238 uint16_t data[8];
239 int width, size;
240
241 /* Read memory */
242 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
243 size = sizeof(uint16_t) * 4 * width;
244 address_space_rw(&s->as,
245 (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP],
246 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
247
248 /* Update SONIC registers */
249 s->regs[SONIC_CRBA0] = data[0 * width];
250 s->regs[SONIC_CRBA1] = data[1 * width];
251 s->regs[SONIC_RBWC0] = data[2 * width];
252 s->regs[SONIC_RBWC1] = data[3 * width];
253 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n",
254 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
255 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
256
257 /* Go to next entry */
258 s->regs[SONIC_RRP] += size;
259
260 /* Handle wrap */
261 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) {
262 s->regs[SONIC_RRP] = s->regs[SONIC_RSA];
263 }
264
265 /* Check resource exhaustion */
266 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP])
267 {
268 s->regs[SONIC_ISR] |= SONIC_ISR_RBE;
269 dp8393x_update_irq(s);
270 }
271
272 /* Done */
273 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA;
274 }
275
276 static void dp8393x_do_software_reset(dp8393xState *s)
277 {
278 timer_del(s->watchdog);
279
280 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX);
281 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS;
282 }
283
284 static void dp8393x_set_next_tick(dp8393xState *s)
285 {
286 uint32_t ticks;
287 int64_t delay;
288
289 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
290 timer_del(s->watchdog);
291 return;
292 }
293
294 ticks = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
295 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
296 delay = get_ticks_per_sec() * ticks / 5000000;
297 timer_mod(s->watchdog, s->wt_last_update + delay);
298 }
299
300 static void dp8393x_update_wt_regs(dp8393xState *s)
301 {
302 int64_t elapsed;
303 uint32_t val;
304
305 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
306 timer_del(s->watchdog);
307 return;
308 }
309
310 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
311 val = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
312 val -= elapsed / 5000000;
313 s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
314 s->regs[SONIC_WT0] = (val >> 0) & 0xffff;
315 dp8393x_set_next_tick(s);
316
317 }
318
319 static void dp8393x_do_start_timer(dp8393xState *s)
320 {
321 s->regs[SONIC_CR] &= ~SONIC_CR_STP;
322 dp8393x_set_next_tick(s);
323 }
324
325 static void dp8393x_do_stop_timer(dp8393xState *s)
326 {
327 s->regs[SONIC_CR] &= ~SONIC_CR_ST;
328 dp8393x_update_wt_regs(s);
329 }
330
331 static int dp8393x_can_receive(NetClientState *nc);
332
333 static void dp8393x_do_receiver_enable(dp8393xState *s)
334 {
335 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS;
336 if (dp8393x_can_receive(s->nic->ncs)) {
337 qemu_flush_queued_packets(qemu_get_queue(s->nic));
338 }
339 }
340
341 static void dp8393x_do_receiver_disable(dp8393xState *s)
342 {
343 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN;
344 }
345
346 static void dp8393x_do_transmit_packets(dp8393xState *s)
347 {
348 NetClientState *nc = qemu_get_queue(s->nic);
349 uint16_t data[12];
350 int width, size;
351 int tx_len, len;
352 uint16_t i;
353
354 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
355
356 while (1) {
357 /* Read memory */
358 DPRINTF("Transmit packet at %08x\n",
359 (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_CTDA]);
360 size = sizeof(uint16_t) * 6 * width;
361 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
362 address_space_rw(&s->as,
363 ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * width,
364 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
365 tx_len = 0;
366
367 /* Update registers */
368 s->regs[SONIC_TCR] = data[0 * width] & 0xf000;
369 s->regs[SONIC_TPS] = data[1 * width];
370 s->regs[SONIC_TFC] = data[2 * width];
371 s->regs[SONIC_TSA0] = data[3 * width];
372 s->regs[SONIC_TSA1] = data[4 * width];
373 s->regs[SONIC_TFS] = data[5 * width];
374
375 /* Handle programmable interrupt */
376 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
377 s->regs[SONIC_ISR] |= SONIC_ISR_PINT;
378 } else {
379 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT;
380 }
381
382 for (i = 0; i < s->regs[SONIC_TFC]; ) {
383 /* Append fragment */
384 len = s->regs[SONIC_TFS];
385 if (tx_len + len > sizeof(s->tx_buffer)) {
386 len = sizeof(s->tx_buffer) - tx_len;
387 }
388 address_space_rw(&s->as,
389 (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0],
390 MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0);
391 tx_len += len;
392
393 i++;
394 if (i != s->regs[SONIC_TFC]) {
395 /* Read next fragment details */
396 size = sizeof(uint16_t) * 3 * width;
397 address_space_rw(&s->as,
398 ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * (4 + 3 * i) * width,
399 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
400 s->regs[SONIC_TSA0] = data[0 * width];
401 s->regs[SONIC_TSA1] = data[1 * width];
402 s->regs[SONIC_TFS] = data[2 * width];
403 }
404 }
405
406 /* Handle Ethernet checksum */
407 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) {
408 /* Don't append FCS there, to look like slirp packets
409 * which don't have one */
410 } else {
411 /* Remove existing FCS */
412 tx_len -= 4;
413 }
414
415 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) {
416 /* Loopback */
417 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL;
418 if (nc->info->can_receive(nc)) {
419 s->loopback_packet = 1;
420 nc->info->receive(nc, s->tx_buffer, tx_len);
421 }
422 } else {
423 /* Transmit packet */
424 qemu_send_packet(nc, s->tx_buffer, tx_len);
425 }
426 s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
427
428 /* Write status */
429 data[0 * width] = s->regs[SONIC_TCR] & 0x0fff; /* status */
430 size = sizeof(uint16_t) * width;
431 address_space_rw(&s->as,
432 (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA],
433 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
434
435 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
436 /* Read footer of packet */
437 size = sizeof(uint16_t) * width;
438 address_space_rw(&s->as,
439 ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * (4 + 3 * s->regs[SONIC_TFC]) * width,
440 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
441 s->regs[SONIC_CTDA] = data[0 * width] & ~0x1;
442 if (data[0 * width] & 0x1) {
443 /* EOL detected */
444 break;
445 }
446 }
447 }
448
449 /* Done */
450 s->regs[SONIC_CR] &= ~SONIC_CR_TXP;
451 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN;
452 dp8393x_update_irq(s);
453 }
454
455 static void dp8393x_do_halt_transmission(dp8393xState *s)
456 {
457 /* Nothing to do */
458 }
459
460 static void dp8393x_do_command(dp8393xState *s, uint16_t command)
461 {
462 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) {
463 s->regs[SONIC_CR] &= ~SONIC_CR_RST;
464 return;
465 }
466
467 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK);
468
469 if (command & SONIC_CR_HTX)
470 dp8393x_do_halt_transmission(s);
471 if (command & SONIC_CR_TXP)
472 dp8393x_do_transmit_packets(s);
473 if (command & SONIC_CR_RXDIS)
474 dp8393x_do_receiver_disable(s);
475 if (command & SONIC_CR_RXEN)
476 dp8393x_do_receiver_enable(s);
477 if (command & SONIC_CR_STP)
478 dp8393x_do_stop_timer(s);
479 if (command & SONIC_CR_ST)
480 dp8393x_do_start_timer(s);
481 if (command & SONIC_CR_RST)
482 dp8393x_do_software_reset(s);
483 if (command & SONIC_CR_RRRA)
484 dp8393x_do_read_rra(s);
485 if (command & SONIC_CR_LCAM)
486 dp8393x_do_load_cam(s);
487 }
488
489 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
490 {
491 dp8393xState *s = opaque;
492 int reg = addr >> s->it_shift;
493 uint16_t val = 0;
494
495 switch (reg) {
496 /* Update data before reading it */
497 case SONIC_WT0:
498 case SONIC_WT1:
499 dp8393x_update_wt_regs(s);
500 val = s->regs[reg];
501 break;
502 /* Accept read to some registers only when in reset mode */
503 case SONIC_CAP2:
504 case SONIC_CAP1:
505 case SONIC_CAP0:
506 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
507 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8;
508 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)];
509 }
510 break;
511 /* All other registers have no special contrainst */
512 default:
513 val = s->regs[reg];
514 }
515
516 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]);
517
518 return val;
519 }
520
521 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
522 unsigned int size)
523 {
524 dp8393xState *s = opaque;
525 int reg = addr >> s->it_shift;
526
527 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)data, reg_names[reg]);
528
529 switch (reg) {
530 /* Command register */
531 case SONIC_CR:
532 dp8393x_do_command(s, data);
533 break;
534 /* Prevent write to read-only registers */
535 case SONIC_CAP2:
536 case SONIC_CAP1:
537 case SONIC_CAP0:
538 case SONIC_SR:
539 case SONIC_MDT:
540 DPRINTF("writing to reg %d invalid\n", reg);
541 break;
542 /* Accept write to some registers only when in reset mode */
543 case SONIC_DCR:
544 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
545 s->regs[reg] = data & 0xbfff;
546 } else {
547 DPRINTF("writing to DCR invalid\n");
548 }
549 break;
550 case SONIC_DCR2:
551 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
552 s->regs[reg] = data & 0xf017;
553 } else {
554 DPRINTF("writing to DCR2 invalid\n");
555 }
556 break;
557 /* 12 lower bytes are Read Only */
558 case SONIC_TCR:
559 s->regs[reg] = data & 0xf000;
560 break;
561 /* 9 lower bytes are Read Only */
562 case SONIC_RCR:
563 s->regs[reg] = data & 0xffe0;
564 break;
565 /* Ignore most significant bit */
566 case SONIC_IMR:
567 s->regs[reg] = data & 0x7fff;
568 dp8393x_update_irq(s);
569 break;
570 /* Clear bits by writing 1 to them */
571 case SONIC_ISR:
572 data &= s->regs[reg];
573 s->regs[reg] &= ~data;
574 if (data & SONIC_ISR_RBE) {
575 dp8393x_do_read_rra(s);
576 }
577 dp8393x_update_irq(s);
578 if (dp8393x_can_receive(s->nic->ncs)) {
579 qemu_flush_queued_packets(qemu_get_queue(s->nic));
580 }
581 break;
582 /* Ignore least significant bit */
583 case SONIC_RSA:
584 case SONIC_REA:
585 case SONIC_RRP:
586 case SONIC_RWP:
587 s->regs[reg] = data & 0xfffe;
588 break;
589 /* Invert written value for some registers */
590 case SONIC_CRCT:
591 case SONIC_FAET:
592 case SONIC_MPT:
593 s->regs[reg] = data ^ 0xffff;
594 break;
595 /* All other registers have no special contrainst */
596 default:
597 s->regs[reg] = data;
598 }
599
600 if (reg == SONIC_WT0 || reg == SONIC_WT1) {
601 dp8393x_set_next_tick(s);
602 }
603 }
604
605 static const MemoryRegionOps dp8393x_ops = {
606 .read = dp8393x_read,
607 .write = dp8393x_write,
608 .impl.min_access_size = 2,
609 .impl.max_access_size = 2,
610 .endianness = DEVICE_NATIVE_ENDIAN,
611 };
612
613 static void dp8393x_watchdog(void *opaque)
614 {
615 dp8393xState *s = opaque;
616
617 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
618 return;
619 }
620
621 s->regs[SONIC_WT1] = 0xffff;
622 s->regs[SONIC_WT0] = 0xffff;
623 dp8393x_set_next_tick(s);
624
625 /* Signal underflow */
626 s->regs[SONIC_ISR] |= SONIC_ISR_TC;
627 dp8393x_update_irq(s);
628 }
629
630 static int dp8393x_can_receive(NetClientState *nc)
631 {
632 dp8393xState *s = qemu_get_nic_opaque(nc);
633
634 if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN))
635 return 0;
636 if (s->regs[SONIC_ISR] & SONIC_ISR_RBE)
637 return 0;
638 return 1;
639 }
640
641 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf,
642 int size)
643 {
644 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
645 int i;
646
647 /* Check promiscuous mode */
648 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) {
649 return 0;
650 }
651
652 /* Check multicast packets */
653 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) {
654 return SONIC_RCR_MC;
655 }
656
657 /* Check broadcast */
658 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) {
659 return SONIC_RCR_BC;
660 }
661
662 /* Check CAM */
663 for (i = 0; i < 16; i++) {
664 if (s->regs[SONIC_CE] & (1 << i)) {
665 /* Entry enabled */
666 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) {
667 return 0;
668 }
669 }
670 }
671
672 return -1;
673 }
674
675 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
676 size_t size)
677 {
678 dp8393xState *s = qemu_get_nic_opaque(nc);
679 uint16_t data[10];
680 int packet_type;
681 uint32_t available, address;
682 int width, rx_len = size;
683 uint32_t checksum;
684
685 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
686
687 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER |
688 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC);
689
690 packet_type = dp8393x_receive_filter(s, buf, size);
691 if (packet_type < 0) {
692 DPRINTF("packet not for netcard\n");
693 return -1;
694 }
695
696 /* XXX: Check byte ordering */
697
698 /* Check for EOL */
699 if (s->regs[SONIC_LLFA] & 0x1) {
700 /* Are we still in resource exhaustion? */
701 size = sizeof(uint16_t) * 1 * width;
702 address = ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 5 * width;
703 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
704 (uint8_t *)data, size, 0);
705 if (data[0 * width] & 0x1) {
706 /* Still EOL ; stop reception */
707 return -1;
708 } else {
709 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
710 }
711 }
712
713 /* Save current position */
714 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1];
715 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0];
716
717 /* Calculate the ethernet checksum */
718 checksum = cpu_to_le32(crc32(0, buf, rx_len));
719
720 /* Put packet into RBA */
721 DPRINTF("Receive packet at %08x\n", (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]);
722 address = (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0];
723 address_space_rw(&s->as, address,
724 MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len, 1);
725 address += rx_len;
726 address_space_rw(&s->as, address,
727 MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1);
728 rx_len += 4;
729 s->regs[SONIC_CRBA1] = address >> 16;
730 s->regs[SONIC_CRBA0] = address & 0xffff;
731 available = (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0];
732 available -= rx_len / 2;
733 s->regs[SONIC_RBWC1] = available >> 16;
734 s->regs[SONIC_RBWC0] = available & 0xffff;
735
736 /* Update status */
737 if (((s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]) < s->regs[SONIC_EOBC]) {
738 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
739 }
740 s->regs[SONIC_RCR] |= packet_type;
741 s->regs[SONIC_RCR] |= SONIC_RCR_PRX;
742 if (s->loopback_packet) {
743 s->regs[SONIC_RCR] |= SONIC_RCR_LBK;
744 s->loopback_packet = 0;
745 }
746
747 /* Write status to memory */
748 DPRINTF("Write status at %08x\n", (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]);
749 data[0 * width] = s->regs[SONIC_RCR]; /* status */
750 data[1 * width] = rx_len; /* byte count */
751 data[2 * width] = s->regs[SONIC_TRBA0]; /* pkt_ptr0 */
752 data[3 * width] = s->regs[SONIC_TRBA1]; /* pkt_ptr1 */
753 data[4 * width] = s->regs[SONIC_RSC]; /* seq_no */
754 size = sizeof(uint16_t) * 5 * width;
755 address_space_rw(&s->as, (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA],
756 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
757
758 /* Move to next descriptor */
759 size = sizeof(uint16_t) * width;
760 address_space_rw(&s->as,
761 ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 5 * width,
762 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
763 s->regs[SONIC_LLFA] = data[0 * width];
764 if (s->regs[SONIC_LLFA] & 0x1) {
765 /* EOL detected */
766 s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
767 } else {
768 data[0 * width] = 0; /* in_use */
769 address_space_rw(&s->as,
770 ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 6 * width,
771 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1);
772 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
773 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
774 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);
775
776 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {
777 /* Read next RRA */
778 dp8393x_do_read_rra(s);
779 }
780 }
781
782 /* Done */
783 dp8393x_update_irq(s);
784
785 return size;
786 }
787
788 static void dp8393x_reset(DeviceState *dev)
789 {
790 dp8393xState *s = DP8393X(dev);
791 timer_del(s->watchdog);
792
793 memset(s->regs, 0, sizeof(s->regs));
794 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
795 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
796 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT);
797 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX;
798 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM;
799 s->regs[SONIC_IMR] = 0;
800 s->regs[SONIC_ISR] = 0;
801 s->regs[SONIC_DCR2] = 0;
802 s->regs[SONIC_EOBC] = 0x02F8;
803 s->regs[SONIC_RSC] = 0;
804 s->regs[SONIC_CE] = 0;
805 s->regs[SONIC_RSC] = 0;
806
807 /* Network cable is connected */
808 s->regs[SONIC_RCR] |= SONIC_RCR_CRS;
809
810 dp8393x_update_irq(s);
811 }
812
813 static NetClientInfo net_dp83932_info = {
814 .type = NET_CLIENT_OPTIONS_KIND_NIC,
815 .size = sizeof(NICState),
816 .can_receive = dp8393x_can_receive,
817 .receive = dp8393x_receive,
818 };
819
820 static void dp8393x_instance_init(Object *obj)
821 {
822 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
823 dp8393xState *s = DP8393X(obj);
824
825 sysbus_init_mmio(sbd, &s->mmio);
826 sysbus_init_mmio(sbd, &s->prom);
827 sysbus_init_irq(sbd, &s->irq);
828 }
829
830 static void dp8393x_realize(DeviceState *dev, Error **errp)
831 {
832 dp8393xState *s = DP8393X(dev);
833 int i, checksum;
834 uint8_t *prom;
835 Error *local_err = NULL;
836
837 address_space_init(&s->as, s->dma_mr, "dp8393x");
838 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s,
839 "dp8393x-regs", 0x40 << s->it_shift);
840
841 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf,
842 object_get_typename(OBJECT(dev)), dev->id, s);
843 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
844
845 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
846 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
847
848 memory_region_init_ram(&s->prom, OBJECT(dev),
849 "dp8393x-prom", SONIC_PROM_SIZE, &local_err);
850 if (local_err) {
851 error_propagate(errp, local_err);
852 return;
853 }
854 memory_region_set_readonly(&s->prom, true);
855 prom = memory_region_get_ram_ptr(&s->prom);
856 checksum = 0;
857 for (i = 0; i < 6; i++) {
858 prom[i] = s->conf.macaddr.a[i];
859 checksum += prom[i];
860 if (checksum > 0xff) {
861 checksum = (checksum + 1) & 0xff;
862 }
863 }
864 prom[7] = 0xff - checksum;
865 }
866
867 static const VMStateDescription vmstate_dp8393x = {
868 .name = "dp8393x",
869 .version_id = 0,
870 .minimum_version_id = 0,
871 .fields = (VMStateField []) {
872 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6),
873 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40),
874 VMSTATE_END_OF_LIST()
875 }
876 };
877
878 static Property dp8393x_properties[] = {
879 DEFINE_NIC_PROPERTIES(dp8393xState, conf),
880 DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr),
881 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0),
882 DEFINE_PROP_END_OF_LIST(),
883 };
884
885 static void dp8393x_class_init(ObjectClass *klass, void *data)
886 {
887 DeviceClass *dc = DEVICE_CLASS(klass);
888
889 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
890 dc->realize = dp8393x_realize;
891 dc->reset = dp8393x_reset;
892 dc->vmsd = &vmstate_dp8393x;
893 dc->props = dp8393x_properties;
894 /* Reason: dma_mr property can't be set */
895 dc->cannot_instantiate_with_device_add_yet = true;
896 }
897
898 static const TypeInfo dp8393x_info = {
899 .name = TYPE_DP8393X,
900 .parent = TYPE_SYS_BUS_DEVICE,
901 .instance_size = sizeof(dp8393xState),
902 .instance_init = dp8393x_instance_init,
903 .class_init = dp8393x_class_init,
904 };
905
906 static void dp8393x_register_types(void)
907 {
908 type_register_static(&dp8393x_info);
909 }
910
911 type_init(dp8393x_register_types)
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