2 * QEMU GRLIB IRQMP Emulator
4 * (Multiprocessor and extended interrupt not supported)
6 * Copyright (c) 2010-2011 AdaCore
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "hw/sysbus.h"
31 #include "hw/sparc/grlib.h"
35 #define IRQMP_MAX_CPU 16
36 #define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */
38 /* Memory mapped register offsets */
39 #define LEVEL_OFFSET 0x00
40 #define PENDING_OFFSET 0x04
41 #define FORCE0_OFFSET 0x08
42 #define CLEAR_OFFSET 0x0C
43 #define MP_STATUS_OFFSET 0x10
44 #define BROADCAST_OFFSET 0x14
45 #define MASK_OFFSET 0x40
46 #define FORCE_OFFSET 0x80
47 #define EXTENDED_OFFSET 0xC0
49 #define TYPE_GRLIB_IRQMP "grlib,irqmp"
50 #define GRLIB_IRQMP(obj) OBJECT_CHECK(IRQMP, (obj), TYPE_GRLIB_IRQMP)
52 typedef struct IRQMPState IRQMPState
;
54 typedef struct IRQMP
{
55 SysBusDevice parent_obj
;
60 void *set_pil_in_opaque
;
71 uint32_t mask
[IRQMP_MAX_CPU
];
72 uint32_t force
[IRQMP_MAX_CPU
];
73 uint32_t extended
[IRQMP_MAX_CPU
];
78 static void grlib_irqmp_check_irqs(IRQMPState
*state
)
83 set_pil_in_fn set_pil_in
;
85 assert(state
!= NULL
);
86 assert(state
->parent
!= NULL
);
88 /* IRQ for CPU 0 (no SMP support) */
89 pend
= (state
->pending
| state
->force
[0])
92 level0
= pend
& ~state
->level
;
93 level1
= pend
& state
->level
;
95 trace_grlib_irqmp_check_irqs(state
->pending
, state
->force
[0],
96 state
->mask
[0], level1
, level0
);
98 set_pil_in
= (set_pil_in_fn
)state
->parent
->set_pil_in
;
100 /* Trigger level1 interrupt first and level0 if there is no level1 */
102 set_pil_in(state
->parent
->set_pil_in_opaque
, level1
);
104 set_pil_in(state
->parent
->set_pil_in_opaque
, level0
);
108 void grlib_irqmp_ack(DeviceState
*dev
, int intno
)
110 IRQMP
*irqmp
= GRLIB_IRQMP(dev
);
114 state
= irqmp
->state
;
115 assert(state
!= NULL
);
120 trace_grlib_irqmp_ack(intno
);
122 /* Clear registers */
123 state
->pending
&= ~mask
;
124 state
->force
[0] &= ~mask
; /* Only CPU 0 (No SMP support) */
126 grlib_irqmp_check_irqs(state
);
129 void grlib_irqmp_set_irq(void *opaque
, int irq
, int level
)
131 IRQMP
*irqmp
= GRLIB_IRQMP(opaque
);
137 assert(s
->parent
!= NULL
);
141 trace_grlib_irqmp_set_irq(irq
);
143 if (s
->broadcast
& 1 << irq
) {
144 /* Broadcasted IRQ */
145 for (i
= 0; i
< IRQMP_MAX_CPU
; i
++) {
146 s
->force
[i
] |= 1 << irq
;
149 s
->pending
|= 1 << irq
;
151 grlib_irqmp_check_irqs(s
);
156 static uint64_t grlib_irqmp_read(void *opaque
, hwaddr addr
,
159 IRQMP
*irqmp
= opaque
;
162 assert(irqmp
!= NULL
);
163 state
= irqmp
->state
;
164 assert(state
!= NULL
);
168 /* global registers */
174 return state
->pending
;
177 /* This register is an "alias" for the force register of CPU 0 */
178 return state
->force
[0];
181 case MP_STATUS_OFFSET
:
182 /* Always read as 0 */
185 case BROADCAST_OFFSET
:
186 return state
->broadcast
;
193 if (addr
>= MASK_OFFSET
&& addr
< FORCE_OFFSET
) {
194 int cpu
= (addr
- MASK_OFFSET
) / 4;
195 assert(cpu
>= 0 && cpu
< IRQMP_MAX_CPU
);
197 return state
->mask
[cpu
];
200 /* force registers */
201 if (addr
>= FORCE_OFFSET
&& addr
< EXTENDED_OFFSET
) {
202 int cpu
= (addr
- FORCE_OFFSET
) / 4;
203 assert(cpu
>= 0 && cpu
< IRQMP_MAX_CPU
);
205 return state
->force
[cpu
];
208 /* extended (not supported) */
209 if (addr
>= EXTENDED_OFFSET
&& addr
< IRQMP_REG_SIZE
) {
210 int cpu
= (addr
- EXTENDED_OFFSET
) / 4;
211 assert(cpu
>= 0 && cpu
< IRQMP_MAX_CPU
);
213 return state
->extended
[cpu
];
216 trace_grlib_irqmp_readl_unknown(addr
);
220 static void grlib_irqmp_write(void *opaque
, hwaddr addr
,
221 uint64_t value
, unsigned size
)
223 IRQMP
*irqmp
= opaque
;
226 assert(irqmp
!= NULL
);
227 state
= irqmp
->state
;
228 assert(state
!= NULL
);
232 /* global registers */
235 value
&= 0xFFFF << 1; /* clean up the value */
236 state
->level
= value
;
244 /* This register is an "alias" for the force register of CPU 0 */
246 value
&= 0xFFFE; /* clean up the value */
247 state
->force
[0] = value
;
248 grlib_irqmp_check_irqs(irqmp
->state
);
252 value
&= ~1; /* clean up the value */
253 state
->pending
&= ~value
;
256 case MP_STATUS_OFFSET
:
257 /* Read Only (no SMP support) */
260 case BROADCAST_OFFSET
:
261 value
&= 0xFFFE; /* clean up the value */
262 state
->broadcast
= value
;
270 if (addr
>= MASK_OFFSET
&& addr
< FORCE_OFFSET
) {
271 int cpu
= (addr
- MASK_OFFSET
) / 4;
272 assert(cpu
>= 0 && cpu
< IRQMP_MAX_CPU
);
274 value
&= ~1; /* clean up the value */
275 state
->mask
[cpu
] = value
;
276 grlib_irqmp_check_irqs(irqmp
->state
);
280 /* force registers */
281 if (addr
>= FORCE_OFFSET
&& addr
< EXTENDED_OFFSET
) {
282 int cpu
= (addr
- FORCE_OFFSET
) / 4;
283 assert(cpu
>= 0 && cpu
< IRQMP_MAX_CPU
);
285 uint32_t force
= value
& 0xFFFE;
286 uint32_t clear
= (value
>> 16) & 0xFFFE;
287 uint32_t old
= state
->force
[cpu
];
289 state
->force
[cpu
] = (old
| force
) & ~clear
;
290 grlib_irqmp_check_irqs(irqmp
->state
);
294 /* extended (not supported) */
295 if (addr
>= EXTENDED_OFFSET
&& addr
< IRQMP_REG_SIZE
) {
296 int cpu
= (addr
- EXTENDED_OFFSET
) / 4;
297 assert(cpu
>= 0 && cpu
< IRQMP_MAX_CPU
);
299 value
&= 0xF; /* clean up the value */
300 state
->extended
[cpu
] = value
;
304 trace_grlib_irqmp_writel_unknown(addr
, value
);
307 static const MemoryRegionOps grlib_irqmp_ops
= {
308 .read
= grlib_irqmp_read
,
309 .write
= grlib_irqmp_write
,
310 .endianness
= DEVICE_NATIVE_ENDIAN
,
312 .min_access_size
= 4,
313 .max_access_size
= 4,
317 static void grlib_irqmp_reset(DeviceState
*d
)
319 IRQMP
*irqmp
= GRLIB_IRQMP(d
);
320 assert(irqmp
->state
!= NULL
);
322 memset(irqmp
->state
, 0, sizeof *irqmp
->state
);
323 irqmp
->state
->parent
= irqmp
;
326 static int grlib_irqmp_init(SysBusDevice
*dev
)
328 IRQMP
*irqmp
= GRLIB_IRQMP(dev
);
330 /* Check parameters */
331 if (irqmp
->set_pil_in
== NULL
) {
335 memory_region_init_io(&irqmp
->iomem
, OBJECT(dev
), &grlib_irqmp_ops
, irqmp
,
336 "irqmp", IRQMP_REG_SIZE
);
338 irqmp
->state
= g_malloc0(sizeof *irqmp
->state
);
340 sysbus_init_mmio(dev
, &irqmp
->iomem
);
345 static Property grlib_irqmp_properties
[] = {
346 DEFINE_PROP_PTR("set_pil_in", IRQMP
, set_pil_in
),
347 DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP
, set_pil_in_opaque
),
348 DEFINE_PROP_END_OF_LIST(),
351 static void grlib_irqmp_class_init(ObjectClass
*klass
, void *data
)
353 DeviceClass
*dc
= DEVICE_CLASS(klass
);
354 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
356 k
->init
= grlib_irqmp_init
;
357 dc
->reset
= grlib_irqmp_reset
;
358 dc
->props
= grlib_irqmp_properties
;
359 /* Reason: pointer properties "set_pil_in", "set_pil_in_opaque" */
360 dc
->cannot_instantiate_with_device_add_yet
= true;
363 static const TypeInfo grlib_irqmp_info
= {
364 .name
= TYPE_GRLIB_IRQMP
,
365 .parent
= TYPE_SYS_BUS_DEVICE
,
366 .instance_size
= sizeof(IRQMP
),
367 .class_init
= grlib_irqmp_class_init
,
370 static void grlib_irqmp_register_types(void)
372 type_register_static(&grlib_irqmp_info
);
375 type_init(grlib_irqmp_register_types
)