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ivshmem: Implement shm=... with a memory backend
[qemu/kevin.git] / hw / arm / strongarm.c
blob3b17a2126a7168e698f0d56a5416f8630c3fb232
1 /*
2 * StrongARM SA-1100/SA-1110 emulation
3 *
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
5 *
6 * Largely based on StrongARM emulation:
7 * Copyright (c) 2006 Openedhand Ltd.
8 * Written by Andrzej Zaborowski <balrog@zabor.org>
9 *
10 * UART code based on QEMU 16550A UART emulation
11 * Copyright (c) 2003-2004 Fabrice Bellard
12 * Copyright (c) 2008 Citrix Systems, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 *
26 * Contributions after 2012-01-13 are licensed under the terms of the
27 * GNU GPL, version 2 or (at your option) any later version.
28 */
29
30 #include "qemu/osdep.h"
31 #include "hw/boards.h"
32 #include "hw/sysbus.h"
33 #include "strongarm.h"
34 #include "qemu/error-report.h"
35 #include "hw/arm/arm.h"
36 #include "sysemu/char.h"
37 #include "sysemu/sysemu.h"
38 #include "hw/ssi/ssi.h"
39
40 //#define DEBUG
41
42 /*
43 TODO
44 - Implement cp15, c14 ?
45 - Implement cp15, c15 !!! (idle used in L)
46 - Implement idle mode handling/DIM
47 - Implement sleep mode/Wake sources
48 - Implement reset control
49 - Implement memory control regs
50 - PCMCIA handling
51 - Maybe support MBGNT/MBREQ
52 - DMA channels
53 - GPCLK
54 - IrDA
55 - MCP
56 - Enhance UART with modem signals
57 */
58
59 #ifdef DEBUG
60 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
61 #else
62 # define DPRINTF(format, ...) do { } while (0)
63 #endif
64
65 static struct {
66 hwaddr io_base;
67 int irq;
68 } sa_serial[] = {
69 { 0x80010000, SA_PIC_UART1 },
70 { 0x80030000, SA_PIC_UART2 },
71 { 0x80050000, SA_PIC_UART3 },
72 { 0, 0 }
73 };
74
75 /* Interrupt Controller */
76
77 #define TYPE_STRONGARM_PIC "strongarm_pic"
78 #define STRONGARM_PIC(obj) \
79 OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC)
80
81 typedef struct StrongARMPICState {
82 SysBusDevice parent_obj;
83
84 MemoryRegion iomem;
85 qemu_irq irq;
86 qemu_irq fiq;
87
88 uint32_t pending;
89 uint32_t enabled;
90 uint32_t is_fiq;
91 uint32_t int_idle;
92 } StrongARMPICState;
93
94 #define ICIP 0x00
95 #define ICMR 0x04
96 #define ICLR 0x08
97 #define ICFP 0x10
98 #define ICPR 0x20
99 #define ICCR 0x0c
100
101 #define SA_PIC_SRCS 32
102
103
104 static void strongarm_pic_update(void *opaque)
105 {
106 StrongARMPICState *s = opaque;
107
108 /* FIXME: reflect DIM */
109 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq);
110 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
111 }
112
113 static void strongarm_pic_set_irq(void *opaque, int irq, int level)
114 {
115 StrongARMPICState *s = opaque;
116
117 if (level) {
118 s->pending |= 1 << irq;
119 } else {
120 s->pending &= ~(1 << irq);
121 }
122
123 strongarm_pic_update(s);
124 }
125
126 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset,
127 unsigned size)
128 {
129 StrongARMPICState *s = opaque;
130
131 switch (offset) {
132 case ICIP:
133 return s->pending & ~s->is_fiq & s->enabled;
134 case ICMR:
135 return s->enabled;
136 case ICLR:
137 return s->is_fiq;
138 case ICCR:
139 return s->int_idle == 0;
140 case ICFP:
141 return s->pending & s->is_fiq & s->enabled;
142 case ICPR:
143 return s->pending;
144 default:
145 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
146 __func__, offset);
147 return 0;
148 }
149 }
150
151 static void strongarm_pic_mem_write(void *opaque, hwaddr offset,
152 uint64_t value, unsigned size)
153 {
154 StrongARMPICState *s = opaque;
155
156 switch (offset) {
157 case ICMR:
158 s->enabled = value;
159 break;
160 case ICLR:
161 s->is_fiq = value;
162 break;
163 case ICCR:
164 s->int_idle = (value & 1) ? 0 : ~0;
165 break;
166 default:
167 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
168 __func__, offset);
169 break;
170 }
171 strongarm_pic_update(s);
172 }
173
174 static const MemoryRegionOps strongarm_pic_ops = {
175 .read = strongarm_pic_mem_read,
176 .write = strongarm_pic_mem_write,
177 .endianness = DEVICE_NATIVE_ENDIAN,
178 };
179
180 static int strongarm_pic_initfn(SysBusDevice *sbd)
181 {
182 DeviceState *dev = DEVICE(sbd);
183 StrongARMPICState *s = STRONGARM_PIC(dev);
184
185 qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS);
186 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_pic_ops, s,
187 "pic", 0x1000);
188 sysbus_init_mmio(sbd, &s->iomem);
189 sysbus_init_irq(sbd, &s->irq);
190 sysbus_init_irq(sbd, &s->fiq);
191
192 return 0;
193 }
194
195 static int strongarm_pic_post_load(void *opaque, int version_id)
196 {
197 strongarm_pic_update(opaque);
198 return 0;
199 }
200
201 static VMStateDescription vmstate_strongarm_pic_regs = {
202 .name = "strongarm_pic",
203 .version_id = 0,
204 .minimum_version_id = 0,
205 .post_load = strongarm_pic_post_load,
206 .fields = (VMStateField[]) {
207 VMSTATE_UINT32(pending, StrongARMPICState),
208 VMSTATE_UINT32(enabled, StrongARMPICState),
209 VMSTATE_UINT32(is_fiq, StrongARMPICState),
210 VMSTATE_UINT32(int_idle, StrongARMPICState),
211 VMSTATE_END_OF_LIST(),
212 },
213 };
214
215 static void strongarm_pic_class_init(ObjectClass *klass, void *data)
216 {
217 DeviceClass *dc = DEVICE_CLASS(klass);
218 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
219
220 k->init = strongarm_pic_initfn;
221 dc->desc = "StrongARM PIC";
222 dc->vmsd = &vmstate_strongarm_pic_regs;
223 }
224
225 static const TypeInfo strongarm_pic_info = {
226 .name = TYPE_STRONGARM_PIC,
227 .parent = TYPE_SYS_BUS_DEVICE,
228 .instance_size = sizeof(StrongARMPICState),
229 .class_init = strongarm_pic_class_init,
230 };
231
232 /* Real-Time Clock */
233 #define RTAR 0x00 /* RTC Alarm register */
234 #define RCNR 0x04 /* RTC Counter register */
235 #define RTTR 0x08 /* RTC Timer Trim register */
236 #define RTSR 0x10 /* RTC Status register */
237
238 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
239 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
240 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
241 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
242
243 /* 16 LSB of RTTR are clockdiv for internal trim logic,
244 * trim delete isn't emulated, so
245 * f = 32 768 / (RTTR_trim + 1) */
246
247 #define TYPE_STRONGARM_RTC "strongarm-rtc"
248 #define STRONGARM_RTC(obj) \
249 OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC)
250
251 typedef struct StrongARMRTCState {
252 SysBusDevice parent_obj;
253
254 MemoryRegion iomem;
255 uint32_t rttr;
256 uint32_t rtsr;
257 uint32_t rtar;
258 uint32_t last_rcnr;
259 int64_t last_hz;
260 QEMUTimer *rtc_alarm;
261 QEMUTimer *rtc_hz;
262 qemu_irq rtc_irq;
263 qemu_irq rtc_hz_irq;
264 } StrongARMRTCState;
265
266 static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
267 {
268 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
269 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
270 }
271
272 static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
273 {
274 int64_t rt = qemu_clock_get_ms(rtc_clock);
275 s->last_rcnr += ((rt - s->last_hz) << 15) /
276 (1000 * ((s->rttr & 0xffff) + 1));
277 s->last_hz = rt;
278 }
279
280 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
281 {
282 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
283 timer_mod(s->rtc_hz, s->last_hz + 1000);
284 } else {
285 timer_del(s->rtc_hz);
286 }
287
288 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
289 timer_mod(s->rtc_alarm, s->last_hz +
290 (((s->rtar - s->last_rcnr) * 1000 *
291 ((s->rttr & 0xffff) + 1)) >> 15));
292 } else {
293 timer_del(s->rtc_alarm);
294 }
295 }
296
297 static inline void strongarm_rtc_alarm_tick(void *opaque)
298 {
299 StrongARMRTCState *s = opaque;
300 s->rtsr |= RTSR_AL;
301 strongarm_rtc_timer_update(s);
302 strongarm_rtc_int_update(s);
303 }
304
305 static inline void strongarm_rtc_hz_tick(void *opaque)
306 {
307 StrongARMRTCState *s = opaque;
308 s->rtsr |= RTSR_HZ;
309 strongarm_rtc_timer_update(s);
310 strongarm_rtc_int_update(s);
311 }
312
313 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr,
314 unsigned size)
315 {
316 StrongARMRTCState *s = opaque;
317
318 switch (addr) {
319 case RTTR:
320 return s->rttr;
321 case RTSR:
322 return s->rtsr;
323 case RTAR:
324 return s->rtar;
325 case RCNR:
326 return s->last_rcnr +
327 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
328 (1000 * ((s->rttr & 0xffff) + 1));
329 default:
330 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
331 return 0;
332 }
333 }
334
335 static void strongarm_rtc_write(void *opaque, hwaddr addr,
336 uint64_t value, unsigned size)
337 {
338 StrongARMRTCState *s = opaque;
339 uint32_t old_rtsr;
340
341 switch (addr) {
342 case RTTR:
343 strongarm_rtc_hzupdate(s);
344 s->rttr = value;
345 strongarm_rtc_timer_update(s);
346 break;
347
348 case RTSR:
349 old_rtsr = s->rtsr;
350 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
351 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
352
353 if (s->rtsr != old_rtsr) {
354 strongarm_rtc_timer_update(s);
355 }
356
357 strongarm_rtc_int_update(s);
358 break;
359
360 case RTAR:
361 s->rtar = value;
362 strongarm_rtc_timer_update(s);
363 break;
364
365 case RCNR:
366 strongarm_rtc_hzupdate(s);
367 s->last_rcnr = value;
368 strongarm_rtc_timer_update(s);
369 break;
370
371 default:
372 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
373 }
374 }
375
376 static const MemoryRegionOps strongarm_rtc_ops = {
377 .read = strongarm_rtc_read,
378 .write = strongarm_rtc_write,
379 .endianness = DEVICE_NATIVE_ENDIAN,
380 };
381
382 static int strongarm_rtc_init(SysBusDevice *dev)
383 {
384 StrongARMRTCState *s = STRONGARM_RTC(dev);
385 struct tm tm;
386
387 s->rttr = 0x0;
388 s->rtsr = 0;
389
390 qemu_get_timedate(&tm, 0);
391
392 s->last_rcnr = (uint32_t) mktimegm(&tm);
393 s->last_hz = qemu_clock_get_ms(rtc_clock);
394
395 s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s);
396 s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s);
397
398 sysbus_init_irq(dev, &s->rtc_irq);
399 sysbus_init_irq(dev, &s->rtc_hz_irq);
400
401 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_rtc_ops, s,
402 "rtc", 0x10000);
403 sysbus_init_mmio(dev, &s->iomem);
404
405 return 0;
406 }
407
408 static void strongarm_rtc_pre_save(void *opaque)
409 {
410 StrongARMRTCState *s = opaque;
411
412 strongarm_rtc_hzupdate(s);
413 }
414
415 static int strongarm_rtc_post_load(void *opaque, int version_id)
416 {
417 StrongARMRTCState *s = opaque;
418
419 strongarm_rtc_timer_update(s);
420 strongarm_rtc_int_update(s);
421
422 return 0;
423 }
424
425 static const VMStateDescription vmstate_strongarm_rtc_regs = {
426 .name = "strongarm-rtc",
427 .version_id = 0,
428 .minimum_version_id = 0,
429 .pre_save = strongarm_rtc_pre_save,
430 .post_load = strongarm_rtc_post_load,
431 .fields = (VMStateField[]) {
432 VMSTATE_UINT32(rttr, StrongARMRTCState),
433 VMSTATE_UINT32(rtsr, StrongARMRTCState),
434 VMSTATE_UINT32(rtar, StrongARMRTCState),
435 VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
436 VMSTATE_INT64(last_hz, StrongARMRTCState),
437 VMSTATE_END_OF_LIST(),
438 },
439 };
440
441 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
442 {
443 DeviceClass *dc = DEVICE_CLASS(klass);
444 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
445
446 k->init = strongarm_rtc_init;
447 dc->desc = "StrongARM RTC Controller";
448 dc->vmsd = &vmstate_strongarm_rtc_regs;
449 }
450
451 static const TypeInfo strongarm_rtc_sysbus_info = {
452 .name = TYPE_STRONGARM_RTC,
453 .parent = TYPE_SYS_BUS_DEVICE,
454 .instance_size = sizeof(StrongARMRTCState),
455 .class_init = strongarm_rtc_sysbus_class_init,
456 };
457
458 /* GPIO */
459 #define GPLR 0x00
460 #define GPDR 0x04
461 #define GPSR 0x08
462 #define GPCR 0x0c
463 #define GRER 0x10
464 #define GFER 0x14
465 #define GEDR 0x18
466 #define GAFR 0x1c
467
468 #define TYPE_STRONGARM_GPIO "strongarm-gpio"
469 #define STRONGARM_GPIO(obj) \
470 OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO)
471
472 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
473 struct StrongARMGPIOInfo {
474 SysBusDevice busdev;
475 MemoryRegion iomem;
476 qemu_irq handler[28];
477 qemu_irq irqs[11];
478 qemu_irq irqX;
479
480 uint32_t ilevel;
481 uint32_t olevel;
482 uint32_t dir;
483 uint32_t rising;
484 uint32_t falling;
485 uint32_t status;
486 uint32_t gafr;
487
488 uint32_t prev_level;
489 };
490
491
492 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
493 {
494 int i;
495 for (i = 0; i < 11; i++) {
496 qemu_set_irq(s->irqs[i], s->status & (1 << i));
497 }
498
499 qemu_set_irq(s->irqX, (s->status & ~0x7ff));
500 }
501
502 static void strongarm_gpio_set(void *opaque, int line, int level)
503 {
504 StrongARMGPIOInfo *s = opaque;
505 uint32_t mask;
506
507 mask = 1 << line;
508
509 if (level) {
510 s->status |= s->rising & mask &
511 ~s->ilevel & ~s->dir;
512 s->ilevel |= mask;
513 } else {
514 s->status |= s->falling & mask &
515 s->ilevel & ~s->dir;
516 s->ilevel &= ~mask;
517 }
518
519 if (s->status & mask) {
520 strongarm_gpio_irq_update(s);
521 }
522 }
523
524 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
525 {
526 uint32_t level, diff;
527 int bit;
528
529 level = s->olevel & s->dir;
530
531 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
532 bit = ctz32(diff);
533 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
534 }
535
536 s->prev_level = level;
537 }
538
539 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset,
540 unsigned size)
541 {
542 StrongARMGPIOInfo *s = opaque;
543
544 switch (offset) {
545 case GPDR: /* GPIO Pin-Direction registers */
546 return s->dir;
547
548 case GPSR: /* GPIO Pin-Output Set registers */
549 qemu_log_mask(LOG_GUEST_ERROR,
550 "strongarm GPIO: read from write only register GPSR\n");
551 return 0;
552
553 case GPCR: /* GPIO Pin-Output Clear registers */
554 qemu_log_mask(LOG_GUEST_ERROR,
555 "strongarm GPIO: read from write only register GPCR\n");
556 return 0;
557
558 case GRER: /* GPIO Rising-Edge Detect Enable registers */
559 return s->rising;
560
561 case GFER: /* GPIO Falling-Edge Detect Enable registers */
562 return s->falling;
563
564 case GAFR: /* GPIO Alternate Function registers */
565 return s->gafr;
566
567 case GPLR: /* GPIO Pin-Level registers */
568 return (s->olevel & s->dir) |
569 (s->ilevel & ~s->dir);
570
571 case GEDR: /* GPIO Edge Detect Status registers */
572 return s->status;
573
574 default:
575 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
576 }
577
578 return 0;
579 }
580
581 static void strongarm_gpio_write(void *opaque, hwaddr offset,
582 uint64_t value, unsigned size)
583 {
584 StrongARMGPIOInfo *s = opaque;
585
586 switch (offset) {
587 case GPDR: /* GPIO Pin-Direction registers */
588 s->dir = value;
589 strongarm_gpio_handler_update(s);
590 break;
591
592 case GPSR: /* GPIO Pin-Output Set registers */
593 s->olevel |= value;
594 strongarm_gpio_handler_update(s);
595 break;
596
597 case GPCR: /* GPIO Pin-Output Clear registers */
598 s->olevel &= ~value;
599 strongarm_gpio_handler_update(s);
600 break;
601
602 case GRER: /* GPIO Rising-Edge Detect Enable registers */
603 s->rising = value;
604 break;
605
606 case GFER: /* GPIO Falling-Edge Detect Enable registers */
607 s->falling = value;
608 break;
609
610 case GAFR: /* GPIO Alternate Function registers */
611 s->gafr = value;
612 break;
613
614 case GEDR: /* GPIO Edge Detect Status registers */
615 s->status &= ~value;
616 strongarm_gpio_irq_update(s);
617 break;
618
619 default:
620 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
621 }
622 }
623
624 static const MemoryRegionOps strongarm_gpio_ops = {
625 .read = strongarm_gpio_read,
626 .write = strongarm_gpio_write,
627 .endianness = DEVICE_NATIVE_ENDIAN,
628 };
629
630 static DeviceState *strongarm_gpio_init(hwaddr base,
631 DeviceState *pic)
632 {
633 DeviceState *dev;
634 int i;
635
636 dev = qdev_create(NULL, TYPE_STRONGARM_GPIO);
637 qdev_init_nofail(dev);
638
639 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
640 for (i = 0; i < 12; i++)
641 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
642 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
643
644 return dev;
645 }
646
647 static int strongarm_gpio_initfn(SysBusDevice *sbd)
648 {
649 DeviceState *dev = DEVICE(sbd);
650 StrongARMGPIOInfo *s = STRONGARM_GPIO(dev);
651 int i;
652
653 qdev_init_gpio_in(dev, strongarm_gpio_set, 28);
654 qdev_init_gpio_out(dev, s->handler, 28);
655
656 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_gpio_ops, s,
657 "gpio", 0x1000);
658
659 sysbus_init_mmio(sbd, &s->iomem);
660 for (i = 0; i < 11; i++) {
661 sysbus_init_irq(sbd, &s->irqs[i]);
662 }
663 sysbus_init_irq(sbd, &s->irqX);
664
665 return 0;
666 }
667
668 static const VMStateDescription vmstate_strongarm_gpio_regs = {
669 .name = "strongarm-gpio",
670 .version_id = 0,
671 .minimum_version_id = 0,
672 .fields = (VMStateField[]) {
673 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
674 VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
675 VMSTATE_UINT32(dir, StrongARMGPIOInfo),
676 VMSTATE_UINT32(rising, StrongARMGPIOInfo),
677 VMSTATE_UINT32(falling, StrongARMGPIOInfo),
678 VMSTATE_UINT32(status, StrongARMGPIOInfo),
679 VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
680 VMSTATE_UINT32(prev_level, StrongARMGPIOInfo),
681 VMSTATE_END_OF_LIST(),
682 },
683 };
684
685 static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
686 {
687 DeviceClass *dc = DEVICE_CLASS(klass);
688 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
689
690 k->init = strongarm_gpio_initfn;
691 dc->desc = "StrongARM GPIO controller";
692 dc->vmsd = &vmstate_strongarm_gpio_regs;
693 }
694
695 static const TypeInfo strongarm_gpio_info = {
696 .name = TYPE_STRONGARM_GPIO,
697 .parent = TYPE_SYS_BUS_DEVICE,
698 .instance_size = sizeof(StrongARMGPIOInfo),
699 .class_init = strongarm_gpio_class_init,
700 };
701
702 /* Peripheral Pin Controller */
703 #define PPDR 0x00
704 #define PPSR 0x04
705 #define PPAR 0x08
706 #define PSDR 0x0c
707 #define PPFR 0x10
708
709 #define TYPE_STRONGARM_PPC "strongarm-ppc"
710 #define STRONGARM_PPC(obj) \
711 OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC)
712
713 typedef struct StrongARMPPCInfo StrongARMPPCInfo;
714 struct StrongARMPPCInfo {
715 SysBusDevice parent_obj;
716
717 MemoryRegion iomem;
718 qemu_irq handler[28];
719
720 uint32_t ilevel;
721 uint32_t olevel;
722 uint32_t dir;
723 uint32_t ppar;
724 uint32_t psdr;
725 uint32_t ppfr;
726
727 uint32_t prev_level;
728 };
729
730 static void strongarm_ppc_set(void *opaque, int line, int level)
731 {
732 StrongARMPPCInfo *s = opaque;
733
734 if (level) {
735 s->ilevel |= 1 << line;
736 } else {
737 s->ilevel &= ~(1 << line);
738 }
739 }
740
741 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
742 {
743 uint32_t level, diff;
744 int bit;
745
746 level = s->olevel & s->dir;
747
748 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
749 bit = ctz32(diff);
750 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
751 }
752
753 s->prev_level = level;
754 }
755
756 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset,
757 unsigned size)
758 {
759 StrongARMPPCInfo *s = opaque;
760
761 switch (offset) {
762 case PPDR: /* PPC Pin Direction registers */
763 return s->dir | ~0x3fffff;
764
765 case PPSR: /* PPC Pin State registers */
766 return (s->olevel & s->dir) |
767 (s->ilevel & ~s->dir) |
768 ~0x3fffff;
769
770 case PPAR:
771 return s->ppar | ~0x41000;
772
773 case PSDR:
774 return s->psdr;
775
776 case PPFR:
777 return s->ppfr | ~0x7f001;
778
779 default:
780 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
781 }
782
783 return 0;
784 }
785
786 static void strongarm_ppc_write(void *opaque, hwaddr offset,
787 uint64_t value, unsigned size)
788 {
789 StrongARMPPCInfo *s = opaque;
790
791 switch (offset) {
792 case PPDR: /* PPC Pin Direction registers */
793 s->dir = value & 0x3fffff;
794 strongarm_ppc_handler_update(s);
795 break;
796
797 case PPSR: /* PPC Pin State registers */
798 s->olevel = value & s->dir & 0x3fffff;
799 strongarm_ppc_handler_update(s);
800 break;
801
802 case PPAR:
803 s->ppar = value & 0x41000;
804 break;
805
806 case PSDR:
807 s->psdr = value & 0x3fffff;
808 break;
809
810 case PPFR:
811 s->ppfr = value & 0x7f001;
812 break;
813
814 default:
815 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
816 }
817 }
818
819 static const MemoryRegionOps strongarm_ppc_ops = {
820 .read = strongarm_ppc_read,
821 .write = strongarm_ppc_write,
822 .endianness = DEVICE_NATIVE_ENDIAN,
823 };
824
825 static int strongarm_ppc_init(SysBusDevice *sbd)
826 {
827 DeviceState *dev = DEVICE(sbd);
828 StrongARMPPCInfo *s = STRONGARM_PPC(dev);
829
830 qdev_init_gpio_in(dev, strongarm_ppc_set, 22);
831 qdev_init_gpio_out(dev, s->handler, 22);
832
833 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ppc_ops, s,
834 "ppc", 0x1000);
835
836 sysbus_init_mmio(sbd, &s->iomem);
837
838 return 0;
839 }
840
841 static const VMStateDescription vmstate_strongarm_ppc_regs = {
842 .name = "strongarm-ppc",
843 .version_id = 0,
844 .minimum_version_id = 0,
845 .fields = (VMStateField[]) {
846 VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
847 VMSTATE_UINT32(olevel, StrongARMPPCInfo),
848 VMSTATE_UINT32(dir, StrongARMPPCInfo),
849 VMSTATE_UINT32(ppar, StrongARMPPCInfo),
850 VMSTATE_UINT32(psdr, StrongARMPPCInfo),
851 VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
852 VMSTATE_UINT32(prev_level, StrongARMPPCInfo),
853 VMSTATE_END_OF_LIST(),
854 },
855 };
856
857 static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
858 {
859 DeviceClass *dc = DEVICE_CLASS(klass);
860 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
861
862 k->init = strongarm_ppc_init;
863 dc->desc = "StrongARM PPC controller";
864 dc->vmsd = &vmstate_strongarm_ppc_regs;
865 }
866
867 static const TypeInfo strongarm_ppc_info = {
868 .name = TYPE_STRONGARM_PPC,
869 .parent = TYPE_SYS_BUS_DEVICE,
870 .instance_size = sizeof(StrongARMPPCInfo),
871 .class_init = strongarm_ppc_class_init,
872 };
873
874 /* UART Ports */
875 #define UTCR0 0x00
876 #define UTCR1 0x04
877 #define UTCR2 0x08
878 #define UTCR3 0x0c
879 #define UTDR 0x14
880 #define UTSR0 0x1c
881 #define UTSR1 0x20
882
883 #define UTCR0_PE (1 << 0) /* Parity enable */
884 #define UTCR0_OES (1 << 1) /* Even parity */
885 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
886 #define UTCR0_DSS (1 << 3) /* 8-bit data */
887
888 #define UTCR3_RXE (1 << 0) /* Rx enable */
889 #define UTCR3_TXE (1 << 1) /* Tx enable */
890 #define UTCR3_BRK (1 << 2) /* Force Break */
891 #define UTCR3_RIE (1 << 3) /* Rx int enable */
892 #define UTCR3_TIE (1 << 4) /* Tx int enable */
893 #define UTCR3_LBM (1 << 5) /* Loopback */
894
895 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
896 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
897 #define UTSR0_RID (1 << 2) /* Receiver Idle */
898 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
899 #define UTSR0_REB (1 << 4) /* Receiver end break */
900 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
901
902 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
903 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
904 #define UTSR1_PRE (1 << 3) /* Parity error */
905 #define UTSR1_FRE (1 << 4) /* Frame error */
906 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
907
908 #define RX_FIFO_PRE (1 << 8)
909 #define RX_FIFO_FRE (1 << 9)
910 #define RX_FIFO_ROR (1 << 10)
911
912 #define TYPE_STRONGARM_UART "strongarm-uart"
913 #define STRONGARM_UART(obj) \
914 OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART)
915
916 typedef struct StrongARMUARTState {
917 SysBusDevice parent_obj;
918
919 MemoryRegion iomem;
920 CharDriverState *chr;
921 qemu_irq irq;
922
923 uint8_t utcr0;
924 uint16_t brd;
925 uint8_t utcr3;
926 uint8_t utsr0;
927 uint8_t utsr1;
928
929 uint8_t tx_fifo[8];
930 uint8_t tx_start;
931 uint8_t tx_len;
932 uint16_t rx_fifo[12]; /* value + error flags in high bits */
933 uint8_t rx_start;
934 uint8_t rx_len;
935
936 uint64_t char_transmit_time; /* time to transmit a char in ticks*/
937 bool wait_break_end;
938 QEMUTimer *rx_timeout_timer;
939 QEMUTimer *tx_timer;
940 } StrongARMUARTState;
941
942 static void strongarm_uart_update_status(StrongARMUARTState *s)
943 {
944 uint16_t utsr1 = 0;
945
946 if (s->tx_len != 8) {
947 utsr1 |= UTSR1_TNF;
948 }
949
950 if (s->rx_len != 0) {
951 uint16_t ent = s->rx_fifo[s->rx_start];
952
953 utsr1 |= UTSR1_RNE;
954 if (ent & RX_FIFO_PRE) {
955 s->utsr1 |= UTSR1_PRE;
956 }
957 if (ent & RX_FIFO_FRE) {
958 s->utsr1 |= UTSR1_FRE;
959 }
960 if (ent & RX_FIFO_ROR) {
961 s->utsr1 |= UTSR1_ROR;
962 }
963 }
964
965 s->utsr1 = utsr1;
966 }
967
968 static void strongarm_uart_update_int_status(StrongARMUARTState *s)
969 {
970 uint16_t utsr0 = s->utsr0 &
971 (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
972 int i;
973
974 if ((s->utcr3 & UTCR3_TXE) &&
975 (s->utcr3 & UTCR3_TIE) &&
976 s->tx_len <= 4) {
977 utsr0 |= UTSR0_TFS;
978 }
979
980 if ((s->utcr3 & UTCR3_RXE) &&
981 (s->utcr3 & UTCR3_RIE) &&
982 s->rx_len > 4) {
983 utsr0 |= UTSR0_RFS;
984 }
985
986 for (i = 0; i < s->rx_len && i < 4; i++)
987 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
988 utsr0 |= UTSR0_EIF;
989 break;
990 }
991
992 s->utsr0 = utsr0;
993 qemu_set_irq(s->irq, utsr0);
994 }
995
996 static void strongarm_uart_update_parameters(StrongARMUARTState *s)
997 {
998 int speed, parity, data_bits, stop_bits, frame_size;
999 QEMUSerialSetParams ssp;
1000
1001 /* Start bit. */
1002 frame_size = 1;
1003 if (s->utcr0 & UTCR0_PE) {
1004 /* Parity bit. */
1005 frame_size++;
1006 if (s->utcr0 & UTCR0_OES) {
1007 parity = 'E';
1008 } else {
1009 parity = 'O';
1010 }
1011 } else {
1012 parity = 'N';
1013 }
1014 if (s->utcr0 & UTCR0_SBS) {
1015 stop_bits = 2;
1016 } else {
1017 stop_bits = 1;
1018 }
1019
1020 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
1021 frame_size += data_bits + stop_bits;
1022 speed = 3686400 / 16 / (s->brd + 1);
1023 ssp.speed = speed;
1024 ssp.parity = parity;
1025 ssp.data_bits = data_bits;
1026 ssp.stop_bits = stop_bits;
1027 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
1028 if (s->chr) {
1029 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1030 }
1031
1032 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
1033 speed, parity, data_bits, stop_bits);
1034 }
1035
1036 static void strongarm_uart_rx_to(void *opaque)
1037 {
1038 StrongARMUARTState *s = opaque;
1039
1040 if (s->rx_len) {
1041 s->utsr0 |= UTSR0_RID;
1042 strongarm_uart_update_int_status(s);
1043 }
1044 }
1045
1046 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
1047 {
1048 if ((s->utcr3 & UTCR3_RXE) == 0) {
1049 /* rx disabled */
1050 return;
1051 }
1052
1053 if (s->wait_break_end) {
1054 s->utsr0 |= UTSR0_REB;
1055 s->wait_break_end = false;
1056 }
1057
1058 if (s->rx_len < 12) {
1059 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
1060 s->rx_len++;
1061 } else
1062 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
1063 }
1064
1065 static int strongarm_uart_can_receive(void *opaque)
1066 {
1067 StrongARMUARTState *s = opaque;
1068
1069 if (s->rx_len == 12) {
1070 return 0;
1071 }
1072 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1073 if (s->rx_len < 8) {
1074 return 8 - s->rx_len;
1075 }
1076 return 1;
1077 }
1078
1079 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1080 {
1081 StrongARMUARTState *s = opaque;
1082 int i;
1083
1084 for (i = 0; i < size; i++) {
1085 strongarm_uart_rx_push(s, buf[i]);
1086 }
1087
1088 /* call the timeout receive callback in 3 char transmit time */
1089 timer_mod(s->rx_timeout_timer,
1090 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1091
1092 strongarm_uart_update_status(s);
1093 strongarm_uart_update_int_status(s);
1094 }
1095
1096 static void strongarm_uart_event(void *opaque, int event)
1097 {
1098 StrongARMUARTState *s = opaque;
1099 if (event == CHR_EVENT_BREAK) {
1100 s->utsr0 |= UTSR0_RBB;
1101 strongarm_uart_rx_push(s, RX_FIFO_FRE);
1102 s->wait_break_end = true;
1103 strongarm_uart_update_status(s);
1104 strongarm_uart_update_int_status(s);
1105 }
1106 }
1107
1108 static void strongarm_uart_tx(void *opaque)
1109 {
1110 StrongARMUARTState *s = opaque;
1111 uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1112
1113 if (s->utcr3 & UTCR3_LBM) /* loopback */ {
1114 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1115 } else if (s->chr) {
1116 qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1);
1117 }
1118
1119 s->tx_start = (s->tx_start + 1) % 8;
1120 s->tx_len--;
1121 if (s->tx_len) {
1122 timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1123 }
1124 strongarm_uart_update_status(s);
1125 strongarm_uart_update_int_status(s);
1126 }
1127
1128 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr,
1129 unsigned size)
1130 {
1131 StrongARMUARTState *s = opaque;
1132 uint16_t ret;
1133
1134 switch (addr) {
1135 case UTCR0:
1136 return s->utcr0;
1137
1138 case UTCR1:
1139 return s->brd >> 8;
1140
1141 case UTCR2:
1142 return s->brd & 0xff;
1143
1144 case UTCR3:
1145 return s->utcr3;
1146
1147 case UTDR:
1148 if (s->rx_len != 0) {
1149 ret = s->rx_fifo[s->rx_start];
1150 s->rx_start = (s->rx_start + 1) % 12;
1151 s->rx_len--;
1152 strongarm_uart_update_status(s);
1153 strongarm_uart_update_int_status(s);
1154 return ret;
1155 }
1156 return 0;
1157
1158 case UTSR0:
1159 return s->utsr0;
1160
1161 case UTSR1:
1162 return s->utsr1;
1163
1164 default:
1165 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1166 return 0;
1167 }
1168 }
1169
1170 static void strongarm_uart_write(void *opaque, hwaddr addr,
1171 uint64_t value, unsigned size)
1172 {
1173 StrongARMUARTState *s = opaque;
1174
1175 switch (addr) {
1176 case UTCR0:
1177 s->utcr0 = value & 0x7f;
1178 strongarm_uart_update_parameters(s);
1179 break;
1180
1181 case UTCR1:
1182 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1183 strongarm_uart_update_parameters(s);
1184 break;
1185
1186 case UTCR2:
1187 s->brd = (s->brd & 0xf00) | (value & 0xff);
1188 strongarm_uart_update_parameters(s);
1189 break;
1190
1191 case UTCR3:
1192 s->utcr3 = value & 0x3f;
1193 if ((s->utcr3 & UTCR3_RXE) == 0) {
1194 s->rx_len = 0;
1195 }
1196 if ((s->utcr3 & UTCR3_TXE) == 0) {
1197 s->tx_len = 0;
1198 }
1199 strongarm_uart_update_status(s);
1200 strongarm_uart_update_int_status(s);
1201 break;
1202
1203 case UTDR:
1204 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1205 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1206 s->tx_len++;
1207 strongarm_uart_update_status(s);
1208 strongarm_uart_update_int_status(s);
1209 if (s->tx_len == 1) {
1210 strongarm_uart_tx(s);
1211 }
1212 }
1213 break;
1214
1215 case UTSR0:
1216 s->utsr0 = s->utsr0 & ~(value &
1217 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1218 strongarm_uart_update_int_status(s);
1219 break;
1220
1221 default:
1222 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1223 }
1224 }
1225
1226 static const MemoryRegionOps strongarm_uart_ops = {
1227 .read = strongarm_uart_read,
1228 .write = strongarm_uart_write,
1229 .endianness = DEVICE_NATIVE_ENDIAN,
1230 };
1231
1232 static int strongarm_uart_init(SysBusDevice *dev)
1233 {
1234 StrongARMUARTState *s = STRONGARM_UART(dev);
1235
1236 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_uart_ops, s,
1237 "uart", 0x10000);
1238 sysbus_init_mmio(dev, &s->iomem);
1239 sysbus_init_irq(dev, &s->irq);
1240
1241 s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s);
1242 s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s);
1243
1244 if (s->chr) {
1245 qemu_chr_add_handlers(s->chr,
1246 strongarm_uart_can_receive,
1247 strongarm_uart_receive,
1248 strongarm_uart_event,
1249 s);
1250 }
1251
1252 return 0;
1253 }
1254
1255 static void strongarm_uart_reset(DeviceState *dev)
1256 {
1257 StrongARMUARTState *s = STRONGARM_UART(dev);
1258
1259 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */
1260 s->brd = 23; /* 9600 */
1261 /* enable send & recv - this actually violates spec */
1262 s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1263
1264 s->rx_len = s->tx_len = 0;
1265
1266 strongarm_uart_update_parameters(s);
1267 strongarm_uart_update_status(s);
1268 strongarm_uart_update_int_status(s);
1269 }
1270
1271 static int strongarm_uart_post_load(void *opaque, int version_id)
1272 {
1273 StrongARMUARTState *s = opaque;
1274
1275 strongarm_uart_update_parameters(s);
1276 strongarm_uart_update_status(s);
1277 strongarm_uart_update_int_status(s);
1278
1279 /* tx and restart timer */
1280 if (s->tx_len) {
1281 strongarm_uart_tx(s);
1282 }
1283
1284 /* restart rx timeout timer */
1285 if (s->rx_len) {
1286 timer_mod(s->rx_timeout_timer,
1287 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1288 }
1289
1290 return 0;
1291 }
1292
1293 static const VMStateDescription vmstate_strongarm_uart_regs = {
1294 .name = "strongarm-uart",
1295 .version_id = 0,
1296 .minimum_version_id = 0,
1297 .post_load = strongarm_uart_post_load,
1298 .fields = (VMStateField[]) {
1299 VMSTATE_UINT8(utcr0, StrongARMUARTState),
1300 VMSTATE_UINT16(brd, StrongARMUARTState),
1301 VMSTATE_UINT8(utcr3, StrongARMUARTState),
1302 VMSTATE_UINT8(utsr0, StrongARMUARTState),
1303 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1304 VMSTATE_UINT8(tx_start, StrongARMUARTState),
1305 VMSTATE_UINT8(tx_len, StrongARMUARTState),
1306 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1307 VMSTATE_UINT8(rx_start, StrongARMUARTState),
1308 VMSTATE_UINT8(rx_len, StrongARMUARTState),
1309 VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1310 VMSTATE_END_OF_LIST(),
1311 },
1312 };
1313
1314 static Property strongarm_uart_properties[] = {
1315 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1316 DEFINE_PROP_END_OF_LIST(),
1317 };
1318
1319 static void strongarm_uart_class_init(ObjectClass *klass, void *data)
1320 {
1321 DeviceClass *dc = DEVICE_CLASS(klass);
1322 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1323
1324 k->init = strongarm_uart_init;
1325 dc->desc = "StrongARM UART controller";
1326 dc->reset = strongarm_uart_reset;
1327 dc->vmsd = &vmstate_strongarm_uart_regs;
1328 dc->props = strongarm_uart_properties;
1329 }
1330
1331 static const TypeInfo strongarm_uart_info = {
1332 .name = TYPE_STRONGARM_UART,
1333 .parent = TYPE_SYS_BUS_DEVICE,
1334 .instance_size = sizeof(StrongARMUARTState),
1335 .class_init = strongarm_uart_class_init,
1336 };
1337
1338 /* Synchronous Serial Ports */
1339
1340 #define TYPE_STRONGARM_SSP "strongarm-ssp"
1341 #define STRONGARM_SSP(obj) \
1342 OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP)
1343
1344 typedef struct StrongARMSSPState {
1345 SysBusDevice parent_obj;
1346
1347 MemoryRegion iomem;
1348 qemu_irq irq;
1349 SSIBus *bus;
1350
1351 uint16_t sscr[2];
1352 uint16_t sssr;
1353
1354 uint16_t rx_fifo[8];
1355 uint8_t rx_level;
1356 uint8_t rx_start;
1357 } StrongARMSSPState;
1358
1359 #define SSCR0 0x60 /* SSP Control register 0 */
1360 #define SSCR1 0x64 /* SSP Control register 1 */
1361 #define SSDR 0x6c /* SSP Data register */
1362 #define SSSR 0x74 /* SSP Status register */
1363
1364 /* Bitfields for above registers */
1365 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1366 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1367 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1368 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1369 #define SSCR0_SSE (1 << 7)
1370 #define SSCR0_DSS(x) (((x) & 0xf) + 1)
1371 #define SSCR1_RIE (1 << 0)
1372 #define SSCR1_TIE (1 << 1)
1373 #define SSCR1_LBM (1 << 2)
1374 #define SSSR_TNF (1 << 2)
1375 #define SSSR_RNE (1 << 3)
1376 #define SSSR_TFS (1 << 5)
1377 #define SSSR_RFS (1 << 6)
1378 #define SSSR_ROR (1 << 7)
1379 #define SSSR_RW 0x0080
1380
1381 static void strongarm_ssp_int_update(StrongARMSSPState *s)
1382 {
1383 int level = 0;
1384
1385 level |= (s->sssr & SSSR_ROR);
1386 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
1387 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
1388 qemu_set_irq(s->irq, level);
1389 }
1390
1391 static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1392 {
1393 s->sssr &= ~SSSR_TFS;
1394 s->sssr &= ~SSSR_TNF;
1395 if (s->sscr[0] & SSCR0_SSE) {
1396 if (s->rx_level >= 4) {
1397 s->sssr |= SSSR_RFS;
1398 } else {
1399 s->sssr &= ~SSSR_RFS;
1400 }
1401 if (s->rx_level) {
1402 s->sssr |= SSSR_RNE;
1403 } else {
1404 s->sssr &= ~SSSR_RNE;
1405 }
1406 /* TX FIFO is never filled, so it is always in underrun
1407 condition if SSP is enabled */
1408 s->sssr |= SSSR_TFS;
1409 s->sssr |= SSSR_TNF;
1410 }
1411
1412 strongarm_ssp_int_update(s);
1413 }
1414
1415 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr,
1416 unsigned size)
1417 {
1418 StrongARMSSPState *s = opaque;
1419 uint32_t retval;
1420
1421 switch (addr) {
1422 case SSCR0:
1423 return s->sscr[0];
1424 case SSCR1:
1425 return s->sscr[1];
1426 case SSSR:
1427 return s->sssr;
1428 case SSDR:
1429 if (~s->sscr[0] & SSCR0_SSE) {
1430 return 0xffffffff;
1431 }
1432 if (s->rx_level < 1) {
1433 printf("%s: SSP Rx Underrun\n", __func__);
1434 return 0xffffffff;
1435 }
1436 s->rx_level--;
1437 retval = s->rx_fifo[s->rx_start++];
1438 s->rx_start &= 0x7;
1439 strongarm_ssp_fifo_update(s);
1440 return retval;
1441 default:
1442 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1443 break;
1444 }
1445 return 0;
1446 }
1447
1448 static void strongarm_ssp_write(void *opaque, hwaddr addr,
1449 uint64_t value, unsigned size)
1450 {
1451 StrongARMSSPState *s = opaque;
1452
1453 switch (addr) {
1454 case SSCR0:
1455 s->sscr[0] = value & 0xffbf;
1456 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1457 printf("%s: Wrong data size: %i bits\n", __func__,
1458 (int)SSCR0_DSS(value));
1459 }
1460 if (!(value & SSCR0_SSE)) {
1461 s->sssr = 0;
1462 s->rx_level = 0;
1463 }
1464 strongarm_ssp_fifo_update(s);
1465 break;
1466
1467 case SSCR1:
1468 s->sscr[1] = value & 0x2f;
1469 if (value & SSCR1_LBM) {
1470 printf("%s: Attempt to use SSP LBM mode\n", __func__);
1471 }
1472 strongarm_ssp_fifo_update(s);
1473 break;
1474
1475 case SSSR:
1476 s->sssr &= ~(value & SSSR_RW);
1477 strongarm_ssp_int_update(s);
1478 break;
1479
1480 case SSDR:
1481 if (SSCR0_UWIRE(s->sscr[0])) {
1482 value &= 0xff;
1483 } else
1484 /* Note how 32bits overflow does no harm here */
1485 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1486
1487 /* Data goes from here to the Tx FIFO and is shifted out from
1488 * there directly to the slave, no need to buffer it.
1489 */
1490 if (s->sscr[0] & SSCR0_SSE) {
1491 uint32_t readval;
1492 if (s->sscr[1] & SSCR1_LBM) {
1493 readval = value;
1494 } else {
1495 readval = ssi_transfer(s->bus, value);
1496 }
1497
1498 if (s->rx_level < 0x08) {
1499 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1500 } else {
1501 s->sssr |= SSSR_ROR;
1502 }
1503 }
1504 strongarm_ssp_fifo_update(s);
1505 break;
1506
1507 default:
1508 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1509 break;
1510 }
1511 }
1512
1513 static const MemoryRegionOps strongarm_ssp_ops = {
1514 .read = strongarm_ssp_read,
1515 .write = strongarm_ssp_write,
1516 .endianness = DEVICE_NATIVE_ENDIAN,
1517 };
1518
1519 static int strongarm_ssp_post_load(void *opaque, int version_id)
1520 {
1521 StrongARMSSPState *s = opaque;
1522
1523 strongarm_ssp_fifo_update(s);
1524
1525 return 0;
1526 }
1527
1528 static int strongarm_ssp_init(SysBusDevice *sbd)
1529 {
1530 DeviceState *dev = DEVICE(sbd);
1531 StrongARMSSPState *s = STRONGARM_SSP(dev);
1532
1533 sysbus_init_irq(sbd, &s->irq);
1534
1535 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ssp_ops, s,
1536 "ssp", 0x1000);
1537 sysbus_init_mmio(sbd, &s->iomem);
1538
1539 s->bus = ssi_create_bus(dev, "ssi");
1540 return 0;
1541 }
1542
1543 static void strongarm_ssp_reset(DeviceState *dev)
1544 {
1545 StrongARMSSPState *s = STRONGARM_SSP(dev);
1546
1547 s->sssr = 0x03; /* 3 bit data, SPI, disabled */
1548 s->rx_start = 0;
1549 s->rx_level = 0;
1550 }
1551
1552 static const VMStateDescription vmstate_strongarm_ssp_regs = {
1553 .name = "strongarm-ssp",
1554 .version_id = 0,
1555 .minimum_version_id = 0,
1556 .post_load = strongarm_ssp_post_load,
1557 .fields = (VMStateField[]) {
1558 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1559 VMSTATE_UINT16(sssr, StrongARMSSPState),
1560 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1561 VMSTATE_UINT8(rx_start, StrongARMSSPState),
1562 VMSTATE_UINT8(rx_level, StrongARMSSPState),
1563 VMSTATE_END_OF_LIST(),
1564 },
1565 };
1566
1567 static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
1568 {
1569 DeviceClass *dc = DEVICE_CLASS(klass);
1570 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1571
1572 k->init = strongarm_ssp_init;
1573 dc->desc = "StrongARM SSP controller";
1574 dc->reset = strongarm_ssp_reset;
1575 dc->vmsd = &vmstate_strongarm_ssp_regs;
1576 }
1577
1578 static const TypeInfo strongarm_ssp_info = {
1579 .name = TYPE_STRONGARM_SSP,
1580 .parent = TYPE_SYS_BUS_DEVICE,
1581 .instance_size = sizeof(StrongARMSSPState),
1582 .class_init = strongarm_ssp_class_init,
1583 };
1584
1585 /* Main CPU functions */
1586 StrongARMState *sa1110_init(MemoryRegion *sysmem,
1587 unsigned int sdram_size, const char *rev)
1588 {
1589 StrongARMState *s;
1590 int i;
1591
1592 s = g_new0(StrongARMState, 1);
1593
1594 if (!rev) {
1595 rev = "sa1110-b5";
1596 }
1597
1598 if (strncmp(rev, "sa1110", 6)) {
1599 error_report("Machine requires a SA1110 processor.");
1600 exit(1);
1601 }
1602
1603 s->cpu = cpu_arm_init(rev);
1604
1605 if (!s->cpu) {
1606 error_report("Unable to find CPU definition");
1607 exit(1);
1608 }
1609
1610 memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram",
1611 sdram_size);
1612 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
1613
1614 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1615 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ),
1616 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ),
1617 NULL);
1618
1619 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1620 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1621 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1622 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1623 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1624 NULL);
1625
1626 sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000,
1627 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1628
1629 s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1630
1631 s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL);
1632
1633 for (i = 0; sa_serial[i].io_base; i++) {
1634 DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART);
1635 qdev_prop_set_chr(dev, "chardev", serial_hds[i]);
1636 qdev_init_nofail(dev);
1637 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
1638 sa_serial[i].io_base);
1639 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
1640 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1641 }
1642
1643 s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000,
1644 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1645 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1646
1647 return s;
1648 }
1649
1650 static void strongarm_register_types(void)
1651 {
1652 type_register_static(&strongarm_pic_info);
1653 type_register_static(&strongarm_rtc_sysbus_info);
1654 type_register_static(&strongarm_gpio_info);
1655 type_register_static(&strongarm_ppc_info);
1656 type_register_static(&strongarm_uart_info);
1657 type_register_static(&strongarm_ssp_info);
1658 }
1659
1660 type_init(strongarm_register_types)
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