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ivshmem: Implement shm=... with a memory backend
[qemu/kevin.git] / hw / arm / nseries.c
blob9a5f33bd8ae5fe54a5cfbeca05d5469099170493
1 /*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu-common.h"
23 #include "sysemu/sysemu.h"
24 #include "hw/arm/omap.h"
25 #include "hw/arm/arm.h"
26 #include "hw/irq.h"
27 #include "ui/console.h"
28 #include "hw/boards.h"
29 #include "hw/i2c/i2c.h"
30 #include "hw/devices.h"
31 #include "hw/block/flash.h"
32 #include "hw/hw.h"
33 #include "hw/bt.h"
34 #include "hw/loader.h"
35 #include "sysemu/block-backend.h"
36 #include "hw/sysbus.h"
37 #include "exec/address-spaces.h"
38
39 /* Nokia N8x0 support */
40 struct n800_s {
41 struct omap_mpu_state_s *mpu;
42
43 struct rfbi_chip_s blizzard;
44 struct {
45 void *opaque;
46 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
47 uWireSlave *chip;
48 } ts;
49
50 int keymap[0x80];
51 DeviceState *kbd;
52
53 DeviceState *usb;
54 void *retu;
55 void *tahvo;
56 DeviceState *nand;
57 };
58
59 /* GPIO pins */
60 #define N8X0_TUSB_ENABLE_GPIO 0
61 #define N800_MMC2_WP_GPIO 8
62 #define N800_UNKNOWN_GPIO0 9 /* out */
63 #define N810_MMC2_VIOSD_GPIO 9
64 #define N810_HEADSET_AMP_GPIO 10
65 #define N800_CAM_TURN_GPIO 12
66 #define N810_GPS_RESET_GPIO 12
67 #define N800_BLIZZARD_POWERDOWN_GPIO 15
68 #define N800_MMC1_WP_GPIO 23
69 #define N810_MMC2_VSD_GPIO 23
70 #define N8X0_ONENAND_GPIO 26
71 #define N810_BLIZZARD_RESET_GPIO 30
72 #define N800_UNKNOWN_GPIO2 53 /* out */
73 #define N8X0_TUSB_INT_GPIO 58
74 #define N8X0_BT_WKUP_GPIO 61
75 #define N8X0_STI_GPIO 62
76 #define N8X0_CBUS_SEL_GPIO 64
77 #define N8X0_CBUS_DAT_GPIO 65
78 #define N8X0_CBUS_CLK_GPIO 66
79 #define N8X0_WLAN_IRQ_GPIO 87
80 #define N8X0_BT_RESET_GPIO 92
81 #define N8X0_TEA5761_CS_GPIO 93
82 #define N800_UNKNOWN_GPIO 94
83 #define N810_TSC_RESET_GPIO 94
84 #define N800_CAM_ACT_GPIO 95
85 #define N810_GPS_WAKEUP_GPIO 95
86 #define N8X0_MMC_CS_GPIO 96
87 #define N8X0_WLAN_PWR_GPIO 97
88 #define N8X0_BT_HOST_WKUP_GPIO 98
89 #define N810_SPEAKER_AMP_GPIO 101
90 #define N810_KB_LOCK_GPIO 102
91 #define N800_TSC_TS_GPIO 103
92 #define N810_TSC_TS_GPIO 106
93 #define N8X0_HEADPHONE_GPIO 107
94 #define N8X0_RETU_GPIO 108
95 #define N800_TSC_KP_IRQ_GPIO 109
96 #define N810_KEYBOARD_GPIO 109
97 #define N800_BAT_COVER_GPIO 110
98 #define N810_SLIDE_GPIO 110
99 #define N8X0_TAHVO_GPIO 111
100 #define N800_UNKNOWN_GPIO4 112 /* out */
101 #define N810_SLEEPX_LED_GPIO 112
102 #define N800_TSC_RESET_GPIO 118 /* ? */
103 #define N810_AIC33_RESET_GPIO 118
104 #define N800_TSC_UNKNOWN_GPIO 119 /* out */
105 #define N8X0_TMP105_GPIO 125
106
107 /* Config */
108 #define BT_UART 0
109 #define XLDR_LL_UART 1
110
111 /* Addresses on the I2C bus 0 */
112 #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
113 #define N8X0_TCM825x_ADDR 0x29 /* Camera */
114 #define N810_LP5521_ADDR 0x32 /* LEDs */
115 #define N810_TSL2563_ADDR 0x3d /* Light sensor */
116 #define N810_LM8323_ADDR 0x45 /* Keyboard */
117 /* Addresses on the I2C bus 1 */
118 #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
119 #define N8X0_MENELAUS_ADDR 0x72 /* Power management */
120
121 /* Chipselects on GPMC NOR interface */
122 #define N8X0_ONENAND_CS 0
123 #define N8X0_USB_ASYNC_CS 1
124 #define N8X0_USB_SYNC_CS 4
125
126 #define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
127
128 static void n800_mmc_cs_cb(void *opaque, int line, int level)
129 {
130 /* TODO: this seems to actually be connected to the menelaus, to
131 * which also both MMC slots connect. */
132 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
133 }
134
135 static void n8x0_gpio_setup(struct n800_s *s)
136 {
137 qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO,
138 qemu_allocate_irq(n800_mmc_cs_cb, s->mpu->mmc, 0));
139 qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO));
140 }
141
142 #define MAEMO_CAL_HEADER(...) \
143 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
144 __VA_ARGS__, \
145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
146
147 static const uint8_t n8x0_cal_wlan_mac[] = {
148 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
149 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
150 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
151 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
152 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
153 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
154 };
155
156 static const uint8_t n8x0_cal_bt_id[] = {
157 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
158 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
159 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
160 N8X0_BD_ADDR,
161 };
162
163 static void n8x0_nand_setup(struct n800_s *s)
164 {
165 char *otp_region;
166 DriveInfo *dinfo;
167
168 s->nand = qdev_create(NULL, "onenand");
169 qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
170 /* Either 0x40 or 0x48 are OK for the device ID */
171 qdev_prop_set_uint16(s->nand, "device_id", 0x48);
172 qdev_prop_set_uint16(s->nand, "version_id", 0);
173 qdev_prop_set_int32(s->nand, "shift", 1);
174 dinfo = drive_get(IF_MTD, 0, 0);
175 if (dinfo) {
176 qdev_prop_set_drive(s->nand, "drive", blk_by_legacy_dinfo(dinfo),
177 &error_fatal);
178 }
179 qdev_init_nofail(s->nand);
180 sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
181 qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
182 omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
183 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->nand), 0));
184 otp_region = onenand_raw_otp(s->nand);
185
186 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
187 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
188 /* XXX: in theory should also update the OOB for both pages */
189 }
190
191 static qemu_irq n8x0_system_powerdown;
192
193 static void n8x0_powerdown_req(Notifier *n, void *opaque)
194 {
195 qemu_irq_raise(n8x0_system_powerdown);
196 }
197
198 static Notifier n8x0_system_powerdown_notifier = {
199 .notify = n8x0_powerdown_req
200 };
201
202 static void n8x0_i2c_setup(struct n800_s *s)
203 {
204 DeviceState *dev;
205 qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO);
206 I2CBus *i2c = omap_i2c_bus(s->mpu->i2c[0]);
207
208 /* Attach a menelaus PM chip */
209 dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR);
210 qdev_connect_gpio_out(dev, 3,
211 qdev_get_gpio_in(s->mpu->ih[0],
212 OMAP_INT_24XX_SYS_NIRQ));
213
214 n8x0_system_powerdown = qdev_get_gpio_in(dev, 3);
215 qemu_register_powerdown_notifier(&n8x0_system_powerdown_notifier);
216
217 /* Attach a TMP105 PM chip (A0 wired to ground) */
218 dev = i2c_create_slave(i2c, "tmp105", N8X0_TMP105_ADDR);
219 qdev_connect_gpio_out(dev, 0, tmp_irq);
220 }
221
222 /* Touchscreen and keypad controller */
223 static MouseTransformInfo n800_pointercal = {
224 .x = 800,
225 .y = 480,
226 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
227 };
228
229 static MouseTransformInfo n810_pointercal = {
230 .x = 800,
231 .y = 480,
232 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
233 };
234
235 #define RETU_KEYCODE 61 /* F3 */
236
237 static void n800_key_event(void *opaque, int keycode)
238 {
239 struct n800_s *s = (struct n800_s *) opaque;
240 int code = s->keymap[keycode & 0x7f];
241
242 if (code == -1) {
243 if ((keycode & 0x7f) == RETU_KEYCODE) {
244 retu_key_event(s->retu, !(keycode & 0x80));
245 }
246 return;
247 }
248
249 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
250 }
251
252 static const int n800_keys[16] = {
253 -1,
254 72, /* Up */
255 63, /* Home (F5) */
256 -1,
257 75, /* Left */
258 28, /* Enter */
259 77, /* Right */
260 -1,
261 1, /* Cycle (ESC) */
262 80, /* Down */
263 62, /* Menu (F4) */
264 -1,
265 66, /* Zoom- (F8) */
266 64, /* FullScreen (F6) */
267 65, /* Zoom+ (F7) */
268 -1,
269 };
270
271 static void n800_tsc_kbd_setup(struct n800_s *s)
272 {
273 int i;
274
275 /* XXX: are the three pins inverted inside the chip between the
276 * tsc and the cpu (N4111)? */
277 qemu_irq penirq = NULL; /* NC */
278 qemu_irq kbirq = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_KP_IRQ_GPIO);
279 qemu_irq dav = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_TS_GPIO);
280
281 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
282 s->ts.opaque = s->ts.chip->opaque;
283 s->ts.txrx = tsc210x_txrx;
284
285 for (i = 0; i < 0x80; i++) {
286 s->keymap[i] = -1;
287 }
288 for (i = 0; i < 0x10; i++) {
289 if (n800_keys[i] >= 0) {
290 s->keymap[n800_keys[i]] = i;
291 }
292 }
293
294 qemu_add_kbd_event_handler(n800_key_event, s);
295
296 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
297 }
298
299 static void n810_tsc_setup(struct n800_s *s)
300 {
301 qemu_irq pintdav = qdev_get_gpio_in(s->mpu->gpio, N810_TSC_TS_GPIO);
302
303 s->ts.opaque = tsc2005_init(pintdav);
304 s->ts.txrx = tsc2005_txrx;
305
306 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
307 }
308
309 /* N810 Keyboard controller */
310 static void n810_key_event(void *opaque, int keycode)
311 {
312 struct n800_s *s = (struct n800_s *) opaque;
313 int code = s->keymap[keycode & 0x7f];
314
315 if (code == -1) {
316 if ((keycode & 0x7f) == RETU_KEYCODE) {
317 retu_key_event(s->retu, !(keycode & 0x80));
318 }
319 return;
320 }
321
322 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
323 }
324
325 #define M 0
326
327 static int n810_keys[0x80] = {
328 [0x01] = 16, /* Q */
329 [0x02] = 37, /* K */
330 [0x03] = 24, /* O */
331 [0x04] = 25, /* P */
332 [0x05] = 14, /* Backspace */
333 [0x06] = 30, /* A */
334 [0x07] = 31, /* S */
335 [0x08] = 32, /* D */
336 [0x09] = 33, /* F */
337 [0x0a] = 34, /* G */
338 [0x0b] = 35, /* H */
339 [0x0c] = 36, /* J */
340
341 [0x11] = 17, /* W */
342 [0x12] = 62, /* Menu (F4) */
343 [0x13] = 38, /* L */
344 [0x14] = 40, /* ' (Apostrophe) */
345 [0x16] = 44, /* Z */
346 [0x17] = 45, /* X */
347 [0x18] = 46, /* C */
348 [0x19] = 47, /* V */
349 [0x1a] = 48, /* B */
350 [0x1b] = 49, /* N */
351 [0x1c] = 42, /* Shift (Left shift) */
352 [0x1f] = 65, /* Zoom+ (F7) */
353
354 [0x21] = 18, /* E */
355 [0x22] = 39, /* ; (Semicolon) */
356 [0x23] = 12, /* - (Minus) */
357 [0x24] = 13, /* = (Equal) */
358 [0x2b] = 56, /* Fn (Left Alt) */
359 [0x2c] = 50, /* M */
360 [0x2f] = 66, /* Zoom- (F8) */
361
362 [0x31] = 19, /* R */
363 [0x32] = 29 | M, /* Right Ctrl */
364 [0x34] = 57, /* Space */
365 [0x35] = 51, /* , (Comma) */
366 [0x37] = 72 | M, /* Up */
367 [0x3c] = 82 | M, /* Compose (Insert) */
368 [0x3f] = 64, /* FullScreen (F6) */
369
370 [0x41] = 20, /* T */
371 [0x44] = 52, /* . (Dot) */
372 [0x46] = 77 | M, /* Right */
373 [0x4f] = 63, /* Home (F5) */
374 [0x51] = 21, /* Y */
375 [0x53] = 80 | M, /* Down */
376 [0x55] = 28, /* Enter */
377 [0x5f] = 1, /* Cycle (ESC) */
378
379 [0x61] = 22, /* U */
380 [0x64] = 75 | M, /* Left */
381
382 [0x71] = 23, /* I */
383 #if 0
384 [0x75] = 28 | M, /* KP Enter (KP Enter) */
385 #else
386 [0x75] = 15, /* KP Enter (Tab) */
387 #endif
388 };
389
390 #undef M
391
392 static void n810_kbd_setup(struct n800_s *s)
393 {
394 qemu_irq kbd_irq = qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GPIO);
395 int i;
396
397 for (i = 0; i < 0x80; i++) {
398 s->keymap[i] = -1;
399 }
400 for (i = 0; i < 0x80; i++) {
401 if (n810_keys[i] > 0) {
402 s->keymap[n810_keys[i]] = i;
403 }
404 }
405
406 qemu_add_kbd_event_handler(n810_key_event, s);
407
408 /* Attach the LM8322 keyboard to the I2C bus,
409 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
410 s->kbd = i2c_create_slave(omap_i2c_bus(s->mpu->i2c[0]),
411 "lm8323", N810_LM8323_ADDR);
412 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
413 }
414
415 /* LCD MIPI DBI-C controller (URAL) */
416 struct mipid_s {
417 int resp[4];
418 int param[4];
419 int p;
420 int pm;
421 int cmd;
422
423 int sleep;
424 int booster;
425 int te;
426 int selfcheck;
427 int partial;
428 int normal;
429 int vscr;
430 int invert;
431 int onoff;
432 int gamma;
433 uint32_t id;
434 };
435
436 static void mipid_reset(struct mipid_s *s)
437 {
438 s->pm = 0;
439 s->cmd = 0;
440
441 s->sleep = 1;
442 s->booster = 0;
443 s->selfcheck =
444 (1 << 7) | /* Register loading OK. */
445 (1 << 5) | /* The chip is attached. */
446 (1 << 4); /* Display glass still in one piece. */
447 s->te = 0;
448 s->partial = 0;
449 s->normal = 1;
450 s->vscr = 0;
451 s->invert = 0;
452 s->onoff = 1;
453 s->gamma = 0;
454 }
455
456 static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
457 {
458 struct mipid_s *s = (struct mipid_s *) opaque;
459 uint8_t ret;
460
461 if (len > 9) {
462 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
463 }
464
465 if (s->p >= ARRAY_SIZE(s->resp)) {
466 ret = 0;
467 } else {
468 ret = s->resp[s->p++];
469 }
470 if (s->pm-- > 0) {
471 s->param[s->pm] = cmd;
472 } else {
473 s->cmd = cmd;
474 }
475
476 switch (s->cmd) {
477 case 0x00: /* NOP */
478 break;
479
480 case 0x01: /* SWRESET */
481 mipid_reset(s);
482 break;
483
484 case 0x02: /* BSTROFF */
485 s->booster = 0;
486 break;
487 case 0x03: /* BSTRON */
488 s->booster = 1;
489 break;
490
491 case 0x04: /* RDDID */
492 s->p = 0;
493 s->resp[0] = (s->id >> 16) & 0xff;
494 s->resp[1] = (s->id >> 8) & 0xff;
495 s->resp[2] = (s->id >> 0) & 0xff;
496 break;
497
498 case 0x06: /* RD_RED */
499 case 0x07: /* RD_GREEN */
500 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
501 * for the bootloader one needs to change this. */
502 case 0x08: /* RD_BLUE */
503 s->p = 0;
504 /* TODO: return first pixel components */
505 s->resp[0] = 0x01;
506 break;
507
508 case 0x09: /* RDDST */
509 s->p = 0;
510 s->resp[0] = s->booster << 7;
511 s->resp[1] = (5 << 4) | (s->partial << 2) |
512 (s->sleep << 1) | s->normal;
513 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
514 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
515 s->resp[3] = s->gamma << 6;
516 break;
517
518 case 0x0a: /* RDDPM */
519 s->p = 0;
520 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
521 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
522 break;
523 case 0x0b: /* RDDMADCTR */
524 s->p = 0;
525 s->resp[0] = 0;
526 break;
527 case 0x0c: /* RDDCOLMOD */
528 s->p = 0;
529 s->resp[0] = 5; /* 65K colours */
530 break;
531 case 0x0d: /* RDDIM */
532 s->p = 0;
533 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
534 break;
535 case 0x0e: /* RDDSM */
536 s->p = 0;
537 s->resp[0] = s->te << 7;
538 break;
539 case 0x0f: /* RDDSDR */
540 s->p = 0;
541 s->resp[0] = s->selfcheck;
542 break;
543
544 case 0x10: /* SLPIN */
545 s->sleep = 1;
546 break;
547 case 0x11: /* SLPOUT */
548 s->sleep = 0;
549 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
550 break;
551
552 case 0x12: /* PTLON */
553 s->partial = 1;
554 s->normal = 0;
555 s->vscr = 0;
556 break;
557 case 0x13: /* NORON */
558 s->partial = 0;
559 s->normal = 1;
560 s->vscr = 0;
561 break;
562
563 case 0x20: /* INVOFF */
564 s->invert = 0;
565 break;
566 case 0x21: /* INVON */
567 s->invert = 1;
568 break;
569
570 case 0x22: /* APOFF */
571 case 0x23: /* APON */
572 goto bad_cmd;
573
574 case 0x25: /* WRCNTR */
575 if (s->pm < 0) {
576 s->pm = 1;
577 }
578 goto bad_cmd;
579
580 case 0x26: /* GAMSET */
581 if (!s->pm) {
582 s->gamma = ctz32(s->param[0] & 0xf);
583 if (s->gamma == 32) {
584 s->gamma = -1; /* XXX: should this be 0? */
585 }
586 } else if (s->pm < 0) {
587 s->pm = 1;
588 }
589 break;
590
591 case 0x28: /* DISPOFF */
592 s->onoff = 0;
593 break;
594 case 0x29: /* DISPON */
595 s->onoff = 1;
596 break;
597
598 case 0x2a: /* CASET */
599 case 0x2b: /* RASET */
600 case 0x2c: /* RAMWR */
601 case 0x2d: /* RGBSET */
602 case 0x2e: /* RAMRD */
603 case 0x30: /* PTLAR */
604 case 0x33: /* SCRLAR */
605 goto bad_cmd;
606
607 case 0x34: /* TEOFF */
608 s->te = 0;
609 break;
610 case 0x35: /* TEON */
611 if (!s->pm) {
612 s->te = 1;
613 } else if (s->pm < 0) {
614 s->pm = 1;
615 }
616 break;
617
618 case 0x36: /* MADCTR */
619 goto bad_cmd;
620
621 case 0x37: /* VSCSAD */
622 s->partial = 0;
623 s->normal = 0;
624 s->vscr = 1;
625 break;
626
627 case 0x38: /* IDMOFF */
628 case 0x39: /* IDMON */
629 case 0x3a: /* COLMOD */
630 goto bad_cmd;
631
632 case 0xb0: /* CLKINT / DISCTL */
633 case 0xb1: /* CLKEXT */
634 if (s->pm < 0) {
635 s->pm = 2;
636 }
637 break;
638
639 case 0xb4: /* FRMSEL */
640 break;
641
642 case 0xb5: /* FRM8SEL */
643 case 0xb6: /* TMPRNG / INIESC */
644 case 0xb7: /* TMPHIS / NOP2 */
645 case 0xb8: /* TMPREAD / MADCTL */
646 case 0xba: /* DISTCTR */
647 case 0xbb: /* EPVOL */
648 goto bad_cmd;
649
650 case 0xbd: /* Unknown */
651 s->p = 0;
652 s->resp[0] = 0;
653 s->resp[1] = 1;
654 break;
655
656 case 0xc2: /* IFMOD */
657 if (s->pm < 0) {
658 s->pm = 2;
659 }
660 break;
661
662 case 0xc6: /* PWRCTL */
663 case 0xc7: /* PPWRCTL */
664 case 0xd0: /* EPWROUT */
665 case 0xd1: /* EPWRIN */
666 case 0xd4: /* RDEV */
667 case 0xd5: /* RDRR */
668 goto bad_cmd;
669
670 case 0xda: /* RDID1 */
671 s->p = 0;
672 s->resp[0] = (s->id >> 16) & 0xff;
673 break;
674 case 0xdb: /* RDID2 */
675 s->p = 0;
676 s->resp[0] = (s->id >> 8) & 0xff;
677 break;
678 case 0xdc: /* RDID3 */
679 s->p = 0;
680 s->resp[0] = (s->id >> 0) & 0xff;
681 break;
682
683 default:
684 bad_cmd:
685 qemu_log_mask(LOG_GUEST_ERROR,
686 "%s: unknown command %02x\n", __func__, s->cmd);
687 break;
688 }
689
690 return ret;
691 }
692
693 static void *mipid_init(void)
694 {
695 struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s));
696
697 s->id = 0x838f03;
698 mipid_reset(s);
699
700 return s;
701 }
702
703 static void n8x0_spi_setup(struct n800_s *s)
704 {
705 void *tsc = s->ts.opaque;
706 void *mipid = mipid_init();
707
708 omap_mcspi_attach(s->mpu->mcspi[0], s->ts.txrx, tsc, 0);
709 omap_mcspi_attach(s->mpu->mcspi[0], mipid_txrx, mipid, 1);
710 }
711
712 /* This task is normally performed by the bootloader. If we're loading
713 * a kernel directly, we need to enable the Blizzard ourselves. */
714 static void n800_dss_init(struct rfbi_chip_s *chip)
715 {
716 uint8_t *fb_blank;
717
718 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
719 chip->write(chip->opaque, 1, 0x64);
720 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
721 chip->write(chip->opaque, 1, 0x1e);
722 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
723 chip->write(chip->opaque, 1, 0xe0);
724 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
725 chip->write(chip->opaque, 1, 0x01);
726 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
727 chip->write(chip->opaque, 1, 0x06);
728 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
729 chip->write(chip->opaque, 1, 1); /* Enable bit */
730
731 chip->write(chip->opaque, 0, 0x6c);
732 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
733 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
734 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
735 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
736 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
737 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
738 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
739 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
740 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
741 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
742 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
743 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
744 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
745 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
746 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
747 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
748 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
749 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
750
751 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
752 /* Display Memory Data Port */
753 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
754 g_free(fb_blank);
755 }
756
757 static void n8x0_dss_setup(struct n800_s *s)
758 {
759 s->blizzard.opaque = s1d13745_init(NULL);
760 s->blizzard.block = s1d13745_write_block;
761 s->blizzard.write = s1d13745_write;
762 s->blizzard.read = s1d13745_read;
763
764 omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard);
765 }
766
767 static void n8x0_cbus_setup(struct n800_s *s)
768 {
769 qemu_irq dat_out = qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GPIO);
770 qemu_irq retu_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO);
771 qemu_irq tahvo_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPIO);
772
773 CBus *cbus = cbus_init(dat_out);
774
775 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
776 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
777 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
778
779 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
780 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
781 }
782
783 static void n8x0_uart_setup(struct n800_s *s)
784 {
785 CharDriverState *radio = uart_hci_init(
786 qdev_get_gpio_in(s->mpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
787
788 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_RESET_GPIO,
789 csrhci_pins_get(radio)[csrhci_pin_reset]);
790 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_WKUP_GPIO,
791 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
792
793 omap_uart_attach(s->mpu->uart[BT_UART], radio);
794 }
795
796 static void n8x0_usb_setup(struct n800_s *s)
797 {
798 SysBusDevice *dev;
799 s->usb = qdev_create(NULL, "tusb6010");
800 dev = SYS_BUS_DEVICE(s->usb);
801 qdev_init_nofail(s->usb);
802 sysbus_connect_irq(dev, 0,
803 qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
804 /* Using the NOR interface */
805 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS,
806 sysbus_mmio_get_region(dev, 0));
807 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS,
808 sysbus_mmio_get_region(dev, 1));
809 qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO,
810 qdev_get_gpio_in(s->usb, 0)); /* tusb_pwr */
811 }
812
813 /* Setup done before the main bootloader starts by some early setup code
814 * - used when we want to run the main bootloader in emulation. This
815 * isn't documented. */
816 static uint32_t n800_pinout[104] = {
817 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
818 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
819 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
820 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
821 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
822 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
823 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
824 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
825 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
826 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
827 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
828 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
829 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
830 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
831 0x00000000, 0x00000038, 0x00340000, 0x00000000,
832 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
833 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
834 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
835 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
836 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
837 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
838 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
839 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
840 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
841 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
842 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
843 };
844
845 static void n800_setup_nolo_tags(void *sram_base)
846 {
847 int i;
848 uint32_t *p = sram_base + 0x8000;
849 uint32_t *v = sram_base + 0xa000;
850
851 memset(p, 0, 0x3000);
852
853 strcpy((void *) (p + 0), "QEMU N800");
854
855 strcpy((void *) (p + 8), "F5");
856
857 stl_p(p + 10, 0x04f70000);
858 strcpy((void *) (p + 9), "RX-34");
859
860 /* RAM size in MB? */
861 stl_p(p + 12, 0x80);
862
863 /* Pointer to the list of tags */
864 stl_p(p + 13, OMAP2_SRAM_BASE + 0x9000);
865
866 /* The NOLO tags start here */
867 p = sram_base + 0x9000;
868 #define ADD_TAG(tag, len) \
869 stw_p((uint16_t *) p + 0, tag); \
870 stw_p((uint16_t *) p + 1, len); p++; \
871 stl_p(p++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
872
873 /* OMAP STI console? Pin out settings? */
874 ADD_TAG(0x6e01, 414);
875 for (i = 0; i < ARRAY_SIZE(n800_pinout); i++) {
876 stl_p(v++, n800_pinout[i]);
877 }
878
879 /* Kernel memsize? */
880 ADD_TAG(0x6e05, 1);
881 stl_p(v++, 2);
882
883 /* NOLO serial console */
884 ADD_TAG(0x6e02, 4);
885 stl_p(v++, XLDR_LL_UART); /* UART number (1 - 3) */
886
887 #if 0
888 /* CBUS settings (Retu/AVilma) */
889 ADD_TAG(0x6e03, 6);
890 stw_p((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
891 stw_p((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
892 stw_p((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
893 v += 2;
894 #endif
895
896 /* Nokia ASIC BB5 (Retu/Tahvo) */
897 ADD_TAG(0x6e0a, 4);
898 stw_p((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
899 stw_p((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
900 v++;
901
902 /* LCD console? */
903 ADD_TAG(0x6e04, 4);
904 stw_p((uint16_t *) v + 0, 30); /* ??? */
905 stw_p((uint16_t *) v + 1, 24); /* ??? */
906 v++;
907
908 #if 0
909 /* LCD settings */
910 ADD_TAG(0x6e06, 2);
911 stw_p((uint16_t *) (v++), 15); /* ??? */
912 #endif
913
914 /* I^2C (Menelaus) */
915 ADD_TAG(0x6e07, 4);
916 stl_p(v++, 0x00720000); /* ??? */
917
918 /* Unknown */
919 ADD_TAG(0x6e0b, 6);
920 stw_p((uint16_t *) v + 0, 94); /* ??? */
921 stw_p((uint16_t *) v + 1, 23); /* ??? */
922 stw_p((uint16_t *) v + 2, 0); /* ??? */
923 v += 2;
924
925 /* OMAP gpio switch info */
926 ADD_TAG(0x6e0c, 80);
927 strcpy((void *) v, "bat_cover"); v += 3;
928 stw_p((uint16_t *) v + 0, 110); /* GPIO num ??? */
929 stw_p((uint16_t *) v + 1, 1); /* GPIO num ??? */
930 v += 2;
931 strcpy((void *) v, "cam_act"); v += 3;
932 stw_p((uint16_t *) v + 0, 95); /* GPIO num ??? */
933 stw_p((uint16_t *) v + 1, 32); /* GPIO num ??? */
934 v += 2;
935 strcpy((void *) v, "cam_turn"); v += 3;
936 stw_p((uint16_t *) v + 0, 12); /* GPIO num ??? */
937 stw_p((uint16_t *) v + 1, 33); /* GPIO num ??? */
938 v += 2;
939 strcpy((void *) v, "headphone"); v += 3;
940 stw_p((uint16_t *) v + 0, 107); /* GPIO num ??? */
941 stw_p((uint16_t *) v + 1, 17); /* GPIO num ??? */
942 v += 2;
943
944 /* Bluetooth */
945 ADD_TAG(0x6e0e, 12);
946 stl_p(v++, 0x5c623d01); /* ??? */
947 stl_p(v++, 0x00000201); /* ??? */
948 stl_p(v++, 0x00000000); /* ??? */
949
950 /* CX3110x WLAN settings */
951 ADD_TAG(0x6e0f, 8);
952 stl_p(v++, 0x00610025); /* ??? */
953 stl_p(v++, 0xffff0057); /* ??? */
954
955 /* MMC host settings */
956 ADD_TAG(0x6e10, 12);
957 stl_p(v++, 0xffff000f); /* ??? */
958 stl_p(v++, 0xffffffff); /* ??? */
959 stl_p(v++, 0x00000060); /* ??? */
960
961 /* OneNAND chip select */
962 ADD_TAG(0x6e11, 10);
963 stl_p(v++, 0x00000401); /* ??? */
964 stl_p(v++, 0x0002003a); /* ??? */
965 stl_p(v++, 0x00000002); /* ??? */
966
967 /* TEA5761 sensor settings */
968 ADD_TAG(0x6e12, 2);
969 stl_p(v++, 93); /* GPIO num ??? */
970
971 #if 0
972 /* Unknown tag */
973 ADD_TAG(6e09, 0);
974
975 /* Kernel UART / console */
976 ADD_TAG(6e12, 0);
977 #endif
978
979 /* End of the list */
980 stl_p(p++, 0x00000000);
981 stl_p(p++, 0x00000000);
982 }
983
984 /* This task is normally performed by the bootloader. If we're loading
985 * a kernel directly, we need to set up GPMC mappings ourselves. */
986 static void n800_gpmc_init(struct n800_s *s)
987 {
988 uint32_t config7 =
989 (0xf << 8) | /* MASKADDRESS */
990 (1 << 6) | /* CSVALID */
991 (4 << 0); /* BASEADDRESS */
992
993 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
994 &config7, sizeof(config7));
995 }
996
997 /* Setup sequence done by the bootloader */
998 static void n8x0_boot_init(void *opaque)
999 {
1000 struct n800_s *s = (struct n800_s *) opaque;
1001 uint32_t buf;
1002
1003 /* PRCM setup */
1004 #define omap_writel(addr, val) \
1005 buf = (val); \
1006 cpu_physical_memory_write(addr, &buf, sizeof(buf))
1007
1008 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
1009 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
1010 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
1011 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
1012 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
1013 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
1014 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
1015 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
1016 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
1017 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
1018 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
1019 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
1020 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
1021 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
1022 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
1023 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
1024 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
1025 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
1026 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
1027 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
1028 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
1029 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
1030 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
1031 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
1032 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1033 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1034 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1035 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1036 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1037 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1038 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1039 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1040 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1041 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1042 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1043 (0x78 << 12) | (6 << 8));
1044 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1045
1046 /* GPMC setup */
1047 n800_gpmc_init(s);
1048
1049 /* Video setup */
1050 n800_dss_init(&s->blizzard);
1051
1052 /* CPU setup */
1053 s->mpu->cpu->env.GE = 0x5;
1054
1055 /* If the machine has a slided keyboard, open it */
1056 if (s->kbd) {
1057 qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO));
1058 }
1059 }
1060
1061 #define OMAP_TAG_NOKIA_BT 0x4e01
1062 #define OMAP_TAG_WLAN_CX3110X 0x4e02
1063 #define OMAP_TAG_CBUS 0x4e03
1064 #define OMAP_TAG_EM_ASIC_BB5 0x4e04
1065
1066 static struct omap_gpiosw_info_s {
1067 const char *name;
1068 int line;
1069 int type;
1070 } n800_gpiosw_info[] = {
1071 {
1072 "bat_cover", N800_BAT_COVER_GPIO,
1073 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1074 }, {
1075 "cam_act", N800_CAM_ACT_GPIO,
1076 OMAP_GPIOSW_TYPE_ACTIVITY,
1077 }, {
1078 "cam_turn", N800_CAM_TURN_GPIO,
1079 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1080 }, {
1081 "headphone", N8X0_HEADPHONE_GPIO,
1082 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1083 },
1084 { NULL }
1085 }, n810_gpiosw_info[] = {
1086 {
1087 "gps_reset", N810_GPS_RESET_GPIO,
1088 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1089 }, {
1090 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1091 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1092 }, {
1093 "headphone", N8X0_HEADPHONE_GPIO,
1094 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1095 }, {
1096 "kb_lock", N810_KB_LOCK_GPIO,
1097 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1098 }, {
1099 "sleepx_led", N810_SLEEPX_LED_GPIO,
1100 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1101 }, {
1102 "slide", N810_SLIDE_GPIO,
1103 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1104 },
1105 { NULL }
1106 };
1107
1108 static struct omap_partition_info_s {
1109 uint32_t offset;
1110 uint32_t size;
1111 int mask;
1112 const char *name;
1113 } n800_part_info[] = {
1114 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1115 { 0x00020000, 0x00060000, 0x0, "config" },
1116 { 0x00080000, 0x00200000, 0x0, "kernel" },
1117 { 0x00280000, 0x00200000, 0x3, "initfs" },
1118 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1119
1120 { 0, 0, 0, NULL }
1121 }, n810_part_info[] = {
1122 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1123 { 0x00020000, 0x00060000, 0x0, "config" },
1124 { 0x00080000, 0x00220000, 0x0, "kernel" },
1125 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1126 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1127
1128 { 0, 0, 0, NULL }
1129 };
1130
1131 static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1132
1133 static int n8x0_atag_setup(void *p, int model)
1134 {
1135 uint8_t *b;
1136 uint16_t *w;
1137 uint32_t *l;
1138 struct omap_gpiosw_info_s *gpiosw;
1139 struct omap_partition_info_s *partition;
1140 const char *tag;
1141
1142 w = p;
1143
1144 stw_p(w++, OMAP_TAG_UART); /* u16 tag */
1145 stw_p(w++, 4); /* u16 len */
1146 stw_p(w++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1147 w++;
1148
1149 #if 0
1150 stw_p(w++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1151 stw_p(w++, 4); /* u16 len */
1152 stw_p(w++, XLDR_LL_UART + 1); /* u8 console_uart */
1153 stw_p(w++, 115200); /* u32 console_speed */
1154 #endif
1155
1156 stw_p(w++, OMAP_TAG_LCD); /* u16 tag */
1157 stw_p(w++, 36); /* u16 len */
1158 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1159 w += 8;
1160 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1161 w += 8;
1162 stw_p(w++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1163 stw_p(w++, 24); /* u8 data_lines */
1164
1165 stw_p(w++, OMAP_TAG_CBUS); /* u16 tag */
1166 stw_p(w++, 8); /* u16 len */
1167 stw_p(w++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1168 stw_p(w++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1169 stw_p(w++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1170 w++;
1171
1172 stw_p(w++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1173 stw_p(w++, 4); /* u16 len */
1174 stw_p(w++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1175 stw_p(w++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1176
1177 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1178 for (; gpiosw->name; gpiosw++) {
1179 stw_p(w++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1180 stw_p(w++, 20); /* u16 len */
1181 strcpy((void *) w, gpiosw->name); /* char name[12] */
1182 w += 6;
1183 stw_p(w++, gpiosw->line); /* u16 gpio */
1184 stw_p(w++, gpiosw->type);
1185 stw_p(w++, 0);
1186 stw_p(w++, 0);
1187 }
1188
1189 stw_p(w++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1190 stw_p(w++, 12); /* u16 len */
1191 b = (void *) w;
1192 stb_p(b++, 0x01); /* u8 chip_type (CSR) */
1193 stb_p(b++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1194 stb_p(b++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1195 stb_p(b++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1196 stb_p(b++, BT_UART + 1); /* u8 bt_uart */
1197 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
1198 b += 6;
1199 stb_p(b++, 0x02); /* u8 bt_sysclk (38.4) */
1200 w = (void *) b;
1201
1202 stw_p(w++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1203 stw_p(w++, 8); /* u16 len */
1204 stw_p(w++, 0x25); /* u8 chip_type */
1205 stw_p(w++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1206 stw_p(w++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1207 stw_p(w++, -1); /* s16 spi_cs_gpio */
1208
1209 stw_p(w++, OMAP_TAG_MMC); /* u16 tag */
1210 stw_p(w++, 16); /* u16 len */
1211 if (model == 810) {
1212 stw_p(w++, 0x23f); /* unsigned flags */
1213 stw_p(w++, -1); /* s16 power_pin */
1214 stw_p(w++, -1); /* s16 switch_pin */
1215 stw_p(w++, -1); /* s16 wp_pin */
1216 stw_p(w++, 0x240); /* unsigned flags */
1217 stw_p(w++, 0xc000); /* s16 power_pin */
1218 stw_p(w++, 0x0248); /* s16 switch_pin */
1219 stw_p(w++, 0xc000); /* s16 wp_pin */
1220 } else {
1221 stw_p(w++, 0xf); /* unsigned flags */
1222 stw_p(w++, -1); /* s16 power_pin */
1223 stw_p(w++, -1); /* s16 switch_pin */
1224 stw_p(w++, -1); /* s16 wp_pin */
1225 stw_p(w++, 0); /* unsigned flags */
1226 stw_p(w++, 0); /* s16 power_pin */
1227 stw_p(w++, 0); /* s16 switch_pin */
1228 stw_p(w++, 0); /* s16 wp_pin */
1229 }
1230
1231 stw_p(w++, OMAP_TAG_TEA5761); /* u16 tag */
1232 stw_p(w++, 4); /* u16 len */
1233 stw_p(w++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
1234 w++;
1235
1236 partition = (model == 810) ? n810_part_info : n800_part_info;
1237 for (; partition->name; partition++) {
1238 stw_p(w++, OMAP_TAG_PARTITION); /* u16 tag */
1239 stw_p(w++, 28); /* u16 len */
1240 strcpy((void *) w, partition->name); /* char name[16] */
1241 l = (void *) (w + 8);
1242 stl_p(l++, partition->size); /* unsigned int size */
1243 stl_p(l++, partition->offset); /* unsigned int offset */
1244 stl_p(l++, partition->mask); /* unsigned int mask_flags */
1245 w = (void *) l;
1246 }
1247
1248 stw_p(w++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1249 stw_p(w++, 12); /* u16 len */
1250 #if 0
1251 strcpy((void *) w, "por"); /* char reason_str[12] */
1252 strcpy((void *) w, "charger"); /* char reason_str[12] */
1253 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1254 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1255 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1256 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1257 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1258 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1259 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1260 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1261 #else
1262 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1263 #endif
1264 w += 6;
1265
1266 tag = (model == 810) ? "RX-44" : "RX-34";
1267 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */
1268 stw_p(w++, 24); /* u16 len */
1269 strcpy((void *) w, "product"); /* char component[12] */
1270 w += 6;
1271 strcpy((void *) w, tag); /* char version[12] */
1272 w += 6;
1273
1274 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */
1275 stw_p(w++, 24); /* u16 len */
1276 strcpy((void *) w, "hw-build"); /* char component[12] */
1277 w += 6;
1278 strcpy((void *) w, "QEMU ");
1279 pstrcat((void *) w, 12, qemu_hw_version()); /* char version[12] */
1280 w += 6;
1281
1282 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1283 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */
1284 stw_p(w++, 24); /* u16 len */
1285 strcpy((void *) w, "nolo"); /* char component[12] */
1286 w += 6;
1287 strcpy((void *) w, tag); /* char version[12] */
1288 w += 6;
1289
1290 return (void *) w - p;
1291 }
1292
1293 static int n800_atag_setup(const struct arm_boot_info *info, void *p)
1294 {
1295 return n8x0_atag_setup(p, 800);
1296 }
1297
1298 static int n810_atag_setup(const struct arm_boot_info *info, void *p)
1299 {
1300 return n8x0_atag_setup(p, 810);
1301 }
1302
1303 static void n8x0_init(MachineState *machine,
1304 struct arm_boot_info *binfo, int model)
1305 {
1306 MemoryRegion *sysmem = get_system_memory();
1307 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
1308 int sdram_size = binfo->ram_size;
1309
1310 s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_model);
1311
1312 /* Setup peripherals
1313 *
1314 * Believed external peripherals layout in the N810:
1315 * (spi bus 1)
1316 * tsc2005
1317 * lcd_mipid
1318 * (spi bus 2)
1319 * Conexant cx3110x (WLAN)
1320 * optional: pc2400m (WiMAX)
1321 * (i2c bus 0)
1322 * TLV320AIC33 (audio codec)
1323 * TCM825x (camera by Toshiba)
1324 * lp5521 (clever LEDs)
1325 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1326 * lm8323 (keypad, manf 00, rev 04)
1327 * (i2c bus 1)
1328 * tmp105 (temperature sensor, hwmon)
1329 * menelaus (pm)
1330 * (somewhere on i2c - maybe N800-only)
1331 * tea5761 (FM tuner)
1332 * (serial 0)
1333 * GPS
1334 * (some serial port)
1335 * csr41814 (Bluetooth)
1336 */
1337 n8x0_gpio_setup(s);
1338 n8x0_nand_setup(s);
1339 n8x0_i2c_setup(s);
1340 if (model == 800) {
1341 n800_tsc_kbd_setup(s);
1342 } else if (model == 810) {
1343 n810_tsc_setup(s);
1344 n810_kbd_setup(s);
1345 }
1346 n8x0_spi_setup(s);
1347 n8x0_dss_setup(s);
1348 n8x0_cbus_setup(s);
1349 n8x0_uart_setup(s);
1350 if (usb_enabled()) {
1351 n8x0_usb_setup(s);
1352 }
1353
1354 if (machine->kernel_filename) {
1355 /* Or at the linux loader. */
1356 binfo->kernel_filename = machine->kernel_filename;
1357 binfo->kernel_cmdline = machine->kernel_cmdline;
1358 binfo->initrd_filename = machine->initrd_filename;
1359 arm_load_kernel(s->mpu->cpu, binfo);
1360
1361 qemu_register_reset(n8x0_boot_init, s);
1362 }
1363
1364 if (option_rom[0].name &&
1365 (machine->boot_order[0] == 'n' || !machine->kernel_filename)) {
1366 uint8_t nolo_tags[0x10000];
1367 /* No, wait, better start at the ROM. */
1368 s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
1369
1370 /* This is intended for loading the `secondary.bin' program from
1371 * Nokia images (the NOLO bootloader). The entry point seems
1372 * to be at OMAP2_Q2_BASE + 0x400000.
1373 *
1374 * The `2nd.bin' files contain some kind of earlier boot code and
1375 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1376 *
1377 * The code above is for loading the `zImage' file from Nokia
1378 * images. */
1379 load_image_targphys(option_rom[0].name,
1380 OMAP2_Q2_BASE + 0x400000,
1381 sdram_size - 0x400000);
1382
1383 n800_setup_nolo_tags(nolo_tags);
1384 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
1385 }
1386 }
1387
1388 static struct arm_boot_info n800_binfo = {
1389 .loader_start = OMAP2_Q2_BASE,
1390 /* Actually two chips of 0x4000000 bytes each */
1391 .ram_size = 0x08000000,
1392 .board_id = 0x4f7,
1393 .atag_board = n800_atag_setup,
1394 };
1395
1396 static struct arm_boot_info n810_binfo = {
1397 .loader_start = OMAP2_Q2_BASE,
1398 /* Actually two chips of 0x4000000 bytes each */
1399 .ram_size = 0x08000000,
1400 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1401 * used by some older versions of the bootloader and 5555 is used
1402 * instead (including versions that shipped with many devices). */
1403 .board_id = 0x60c,
1404 .atag_board = n810_atag_setup,
1405 };
1406
1407 static void n800_init(MachineState *machine)
1408 {
1409 n8x0_init(machine, &n800_binfo, 800);
1410 }
1411
1412 static void n810_init(MachineState *machine)
1413 {
1414 n8x0_init(machine, &n810_binfo, 810);
1415 }
1416
1417 static void n800_class_init(ObjectClass *oc, void *data)
1418 {
1419 MachineClass *mc = MACHINE_CLASS(oc);
1420
1421 mc->desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)";
1422 mc->init = n800_init;
1423 mc->default_boot_order = "";
1424 }
1425
1426 static const TypeInfo n800_type = {
1427 .name = MACHINE_TYPE_NAME("n800"),
1428 .parent = TYPE_MACHINE,
1429 .class_init = n800_class_init,
1430 };
1431
1432 static void n810_class_init(ObjectClass *oc, void *data)
1433 {
1434 MachineClass *mc = MACHINE_CLASS(oc);
1435
1436 mc->desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)";
1437 mc->init = n810_init;
1438 mc->default_boot_order = "";
1439 }
1440
1441 static const TypeInfo n810_type = {
1442 .name = MACHINE_TYPE_NAME("n810"),
1443 .parent = TYPE_MACHINE,
1444 .class_init = n810_class_init,
1445 };
1446
1447 static void nseries_machine_init(void)
1448 {
1449 type_register_static(&n800_type);
1450 type_register_static(&n810_type);
1451 }
1452
1453 type_init(nseries_machine_init)
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