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libqos/ahci: ATAPI support
[qemu/kevin.git] / tests / libqos / ahci.c
blob4bdde4c1a78ecac1497dabfa3def021a0adf62c7
1 /*
2 * libqos AHCI functions
3 *
4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include <glib.h>
26
27 #include "libqtest.h"
28 #include "libqos/ahci.h"
29 #include "libqos/pci-pc.h"
30
31 #include "qemu-common.h"
32 #include "qemu/host-utils.h"
33
34 #include "hw/pci/pci_ids.h"
35 #include "hw/pci/pci_regs.h"
36
37 typedef struct AHCICommandProp {
38 uint8_t cmd; /* Command Code */
39 bool data; /* Data transfer command? */
40 bool pio;
41 bool dma;
42 bool lba28;
43 bool lba48;
44 bool read;
45 bool write;
46 bool atapi;
47 bool ncq;
48 uint64_t size; /* Static transfer size, for commands like IDENTIFY. */
49 uint32_t interrupts; /* Expected interrupts for this command. */
50 } AHCICommandProp;
51
52 AHCICommandProp ahci_command_properties[] = {
53 { .cmd = CMD_READ_PIO, .data = true, .pio = true,
54 .lba28 = true, .read = true },
55 { .cmd = CMD_WRITE_PIO, .data = true, .pio = true,
56 .lba28 = true, .write = true },
57 { .cmd = CMD_READ_PIO_EXT, .data = true, .pio = true,
58 .lba48 = true, .read = true },
59 { .cmd = CMD_WRITE_PIO_EXT, .data = true, .pio = true,
60 .lba48 = true, .write = true },
61 { .cmd = CMD_READ_DMA, .data = true, .dma = true,
62 .lba28 = true, .read = true },
63 { .cmd = CMD_WRITE_DMA, .data = true, .dma = true,
64 .lba28 = true, .write = true },
65 { .cmd = CMD_READ_DMA_EXT, .data = true, .dma = true,
66 .lba48 = true, .read = true },
67 { .cmd = CMD_WRITE_DMA_EXT, .data = true, .dma = true,
68 .lba48 = true, .write = true },
69 { .cmd = CMD_IDENTIFY, .data = true, .pio = true,
70 .size = 512, .read = true },
71 { .cmd = READ_FPDMA_QUEUED, .data = true, .dma = true,
72 .lba48 = true, .read = true, .ncq = true },
73 { .cmd = WRITE_FPDMA_QUEUED, .data = true, .dma = true,
74 .lba48 = true, .write = true, .ncq = true },
75 { .cmd = CMD_READ_MAX, .lba28 = true },
76 { .cmd = CMD_READ_MAX_EXT, .lba48 = true },
77 { .cmd = CMD_FLUSH_CACHE, .data = false },
78 { .cmd = CMD_PACKET, .data = true, .size = 16,
79 .atapi = true, },
80 { .cmd = CMD_PACKET_ID, .data = true, .pio = true,
81 .size = 512, .read = true }
82 };
83
84 struct AHCICommand {
85 /* Test Management Data */
86 uint8_t name;
87 uint8_t port;
88 uint8_t slot;
89 uint32_t interrupts;
90 uint64_t xbytes;
91 uint32_t prd_size;
92 uint64_t buffer;
93 AHCICommandProp *props;
94 /* Data to be transferred to the guest */
95 AHCICommandHeader header;
96 RegH2DFIS fis;
97 unsigned char *atapi_cmd;
98 };
99
100 /**
101 * Allocate space in the guest using information in the AHCIQState object.
102 */
103 uint64_t ahci_alloc(AHCIQState *ahci, size_t bytes)
104 {
105 g_assert(ahci);
106 g_assert(ahci->parent);
107 return qmalloc(ahci->parent, bytes);
108 }
109
110 void ahci_free(AHCIQState *ahci, uint64_t addr)
111 {
112 g_assert(ahci);
113 g_assert(ahci->parent);
114 qfree(ahci->parent, addr);
115 }
116
117 /**
118 * Locate, verify, and return a handle to the AHCI device.
119 */
120 QPCIDevice *get_ahci_device(uint32_t *fingerprint)
121 {
122 QPCIDevice *ahci;
123 uint32_t ahci_fingerprint;
124 QPCIBus *pcibus;
125
126 pcibus = qpci_init_pc();
127
128 /* Find the AHCI PCI device and verify it's the right one. */
129 ahci = qpci_device_find(pcibus, QPCI_DEVFN(0x1F, 0x02));
130 g_assert(ahci != NULL);
131
132 ahci_fingerprint = qpci_config_readl(ahci, PCI_VENDOR_ID);
133
134 switch (ahci_fingerprint) {
135 case AHCI_INTEL_ICH9:
136 break;
137 default:
138 /* Unknown device. */
139 g_assert_not_reached();
140 }
141
142 if (fingerprint) {
143 *fingerprint = ahci_fingerprint;
144 }
145 return ahci;
146 }
147
148 void free_ahci_device(QPCIDevice *dev)
149 {
150 QPCIBus *pcibus = dev ? dev->bus : NULL;
151
152 /* libqos doesn't have a function for this, so free it manually */
153 g_free(dev);
154 qpci_free_pc(pcibus);
155 }
156
157 /* Free all memory in-use by the AHCI device. */
158 void ahci_clean_mem(AHCIQState *ahci)
159 {
160 uint8_t port, slot;
161
162 for (port = 0; port < 32; ++port) {
163 if (ahci->port[port].fb) {
164 ahci_free(ahci, ahci->port[port].fb);
165 ahci->port[port].fb = 0;
166 }
167 if (ahci->port[port].clb) {
168 for (slot = 0; slot < 32; slot++) {
169 ahci_destroy_command(ahci, port, slot);
170 }
171 ahci_free(ahci, ahci->port[port].clb);
172 ahci->port[port].clb = 0;
173 }
174 }
175 }
176
177 /*** Logical Device Initialization ***/
178
179 /**
180 * Start the PCI device and sanity-check default operation.
181 */
182 void ahci_pci_enable(AHCIQState *ahci)
183 {
184 uint8_t reg;
185
186 start_ahci_device(ahci);
187
188 switch (ahci->fingerprint) {
189 case AHCI_INTEL_ICH9:
190 /* ICH9 has a register at PCI 0x92 that
191 * acts as a master port enabler mask. */
192 reg = qpci_config_readb(ahci->dev, 0x92);
193 reg |= 0x3F;
194 qpci_config_writeb(ahci->dev, 0x92, reg);
195 /* 0...0111111b -- bit significant, ports 0-5 enabled. */
196 ASSERT_BIT_SET(qpci_config_readb(ahci->dev, 0x92), 0x3F);
197 break;
198 }
199
200 }
201
202 /**
203 * Map BAR5/ABAR, and engage the PCI device.
204 */
205 void start_ahci_device(AHCIQState *ahci)
206 {
207 /* Map AHCI's ABAR (BAR5) */
208 ahci->hba_base = qpci_iomap(ahci->dev, 5, &ahci->barsize);
209 g_assert(ahci->hba_base);
210
211 /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
212 qpci_device_enable(ahci->dev);
213 }
214
215 /**
216 * Test and initialize the AHCI's HBA memory areas.
217 * Initialize and start any ports with devices attached.
218 * Bring the HBA into the idle state.
219 */
220 void ahci_hba_enable(AHCIQState *ahci)
221 {
222 /* Bits of interest in this section:
223 * GHC.AE Global Host Control / AHCI Enable
224 * PxCMD.ST Port Command: Start
225 * PxCMD.SUD "Spin Up Device"
226 * PxCMD.POD "Power On Device"
227 * PxCMD.FRE "FIS Receive Enable"
228 * PxCMD.FR "FIS Receive Running"
229 * PxCMD.CR "Command List Running"
230 */
231 uint32_t reg, ports_impl;
232 uint16_t i;
233 uint8_t num_cmd_slots;
234
235 g_assert(ahci != NULL);
236
237 /* Set GHC.AE to 1 */
238 ahci_set(ahci, AHCI_GHC, AHCI_GHC_AE);
239 reg = ahci_rreg(ahci, AHCI_GHC);
240 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
241
242 /* Cache CAP and CAP2. */
243 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
244 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
245
246 /* Read CAP.NCS, how many command slots do we have? */
247 num_cmd_slots = ((ahci->cap & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1;
248 g_test_message("Number of Command Slots: %u", num_cmd_slots);
249
250 /* Determine which ports are implemented. */
251 ports_impl = ahci_rreg(ahci, AHCI_PI);
252
253 for (i = 0; ports_impl; ports_impl >>= 1, ++i) {
254 if (!(ports_impl & 0x01)) {
255 continue;
256 }
257
258 g_test_message("Initializing port %u", i);
259
260 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
261 if (BITCLR(reg, AHCI_PX_CMD_ST | AHCI_PX_CMD_CR |
262 AHCI_PX_CMD_FRE | AHCI_PX_CMD_FR)) {
263 g_test_message("port is idle");
264 } else {
265 g_test_message("port needs to be idled");
266 ahci_px_clr(ahci, i, AHCI_PX_CMD,
267 (AHCI_PX_CMD_ST | AHCI_PX_CMD_FRE));
268 /* The port has 500ms to disengage. */
269 usleep(500000);
270 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
271 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
272 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
273 g_test_message("port is now idle");
274 /* The spec does allow for possibly needing a PORT RESET
275 * or HBA reset if we fail to idle the port. */
276 }
277
278 /* Allocate Memory for the Command List Buffer & FIS Buffer */
279 /* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */
280 ahci->port[i].clb = ahci_alloc(ahci, num_cmd_slots * 0x20);
281 qmemset(ahci->port[i].clb, 0x00, num_cmd_slots * 0x20);
282 g_test_message("CLB: 0x%08" PRIx64, ahci->port[i].clb);
283 ahci_px_wreg(ahci, i, AHCI_PX_CLB, ahci->port[i].clb);
284 g_assert_cmphex(ahci->port[i].clb, ==,
285 ahci_px_rreg(ahci, i, AHCI_PX_CLB));
286
287 /* PxFB space ... 0x100, as in 4.2.1 p 35 */
288 ahci->port[i].fb = ahci_alloc(ahci, 0x100);
289 qmemset(ahci->port[i].fb, 0x00, 0x100);
290 g_test_message("FB: 0x%08" PRIx64, ahci->port[i].fb);
291 ahci_px_wreg(ahci, i, AHCI_PX_FB, ahci->port[i].fb);
292 g_assert_cmphex(ahci->port[i].fb, ==,
293 ahci_px_rreg(ahci, i, AHCI_PX_FB));
294
295 /* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */
296 ahci_px_wreg(ahci, i, AHCI_PX_SERR, 0xFFFFFFFF);
297 ahci_px_wreg(ahci, i, AHCI_PX_IS, 0xFFFFFFFF);
298 ahci_wreg(ahci, AHCI_IS, (1 << i));
299
300 /* Verify Interrupts Cleared */
301 reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
302 g_assert_cmphex(reg, ==, 0);
303
304 reg = ahci_px_rreg(ahci, i, AHCI_PX_IS);
305 g_assert_cmphex(reg, ==, 0);
306
307 reg = ahci_rreg(ahci, AHCI_IS);
308 ASSERT_BIT_CLEAR(reg, (1 << i));
309
310 /* Enable All Interrupts: */
311 ahci_px_wreg(ahci, i, AHCI_PX_IE, 0xFFFFFFFF);
312 reg = ahci_px_rreg(ahci, i, AHCI_PX_IE);
313 g_assert_cmphex(reg, ==, ~((uint32_t)AHCI_PX_IE_RESERVED));
314
315 /* Enable the FIS Receive Engine. */
316 ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_FRE);
317 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
318 ASSERT_BIT_SET(reg, AHCI_PX_CMD_FR);
319
320 /* AHCI 1.3 spec: if !STS.BSY, !STS.DRQ and PxSSTS.DET indicates
321 * physical presence, a device is present and may be started. However,
322 * PxSERR.DIAG.X /may/ need to be cleared a priori. */
323 reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
324 if (BITSET(reg, AHCI_PX_SERR_DIAG_X)) {
325 ahci_px_set(ahci, i, AHCI_PX_SERR, AHCI_PX_SERR_DIAG_X);
326 }
327
328 reg = ahci_px_rreg(ahci, i, AHCI_PX_TFD);
329 if (BITCLR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ)) {
330 reg = ahci_px_rreg(ahci, i, AHCI_PX_SSTS);
331 if ((reg & AHCI_PX_SSTS_DET) == SSTS_DET_ESTABLISHED) {
332 /* Device Found: set PxCMD.ST := 1 */
333 ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_ST);
334 ASSERT_BIT_SET(ahci_px_rreg(ahci, i, AHCI_PX_CMD),
335 AHCI_PX_CMD_CR);
336 g_test_message("Started Device %u", i);
337 } else if ((reg & AHCI_PX_SSTS_DET)) {
338 /* Device present, but in some unknown state. */
339 g_assert_not_reached();
340 }
341 }
342 }
343
344 /* Enable GHC.IE */
345 ahci_set(ahci, AHCI_GHC, AHCI_GHC_IE);
346 reg = ahci_rreg(ahci, AHCI_GHC);
347 ASSERT_BIT_SET(reg, AHCI_GHC_IE);
348
349 /* TODO: The device should now be idling and waiting for commands.
350 * In the future, a small test-case to inspect the Register D2H FIS
351 * and clear the initial interrupts might be good. */
352 }
353
354 /**
355 * Pick the first implemented and running port
356 */
357 unsigned ahci_port_select(AHCIQState *ahci)
358 {
359 uint32_t ports, reg;
360 unsigned i;
361
362 ports = ahci_rreg(ahci, AHCI_PI);
363 for (i = 0; i < 32; ports >>= 1, ++i) {
364 if (ports == 0) {
365 i = 32;
366 }
367
368 if (!(ports & 0x01)) {
369 continue;
370 }
371
372 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
373 if (BITSET(reg, AHCI_PX_CMD_ST)) {
374 break;
375 }
376 }
377 g_assert(i < 32);
378 return i;
379 }
380
381 /**
382 * Clear a port's interrupts and status information prior to a test.
383 */
384 void ahci_port_clear(AHCIQState *ahci, uint8_t port)
385 {
386 uint32_t reg;
387
388 /* Clear out this port's interrupts (ignore the init register d2h fis) */
389 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
390 ahci_px_wreg(ahci, port, AHCI_PX_IS, reg);
391 g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);
392
393 /* Wipe the FIS-Receive Buffer */
394 qmemset(ahci->port[port].fb, 0x00, 0x100);
395 }
396
397 /**
398 * Check a port for errors.
399 */
400 void ahci_port_check_error(AHCIQState *ahci, uint8_t port)
401 {
402 uint32_t reg;
403
404 /* The upper 9 bits of the IS register all indicate errors. */
405 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
406 reg >>= 23;
407 g_assert_cmphex(reg, ==, 0);
408
409 /* The Sata Error Register should be empty. */
410 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
411 g_assert_cmphex(reg, ==, 0);
412
413 /* The TFD also has two error sections. */
414 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
415 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR);
416 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
417 }
418
419 void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port,
420 uint32_t intr_mask)
421 {
422 uint32_t reg;
423
424 /* Check for expected interrupts */
425 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
426 ASSERT_BIT_SET(reg, intr_mask);
427
428 /* Clear expected interrupts and assert all interrupts now cleared. */
429 ahci_px_wreg(ahci, port, AHCI_PX_IS, intr_mask);
430 g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);
431 }
432
433 void ahci_port_check_nonbusy(AHCIQState *ahci, uint8_t port, uint8_t slot)
434 {
435 uint32_t reg;
436
437 /* Assert that the command slot is no longer busy (NCQ) */
438 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
439 ASSERT_BIT_CLEAR(reg, (1 << slot));
440
441 /* Non-NCQ */
442 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
443 ASSERT_BIT_CLEAR(reg, (1 << slot));
444
445 /* And assert that we are generally not busy. */
446 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
447 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
448 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_DRQ);
449 }
450
451 void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot)
452 {
453 RegD2HFIS *d2h = g_malloc0(0x20);
454 uint32_t reg;
455
456 memread(ahci->port[port].fb + 0x40, d2h, 0x20);
457 g_assert_cmphex(d2h->fis_type, ==, 0x34);
458
459 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
460 g_assert_cmphex((reg & AHCI_PX_TFD_ERR) >> 8, ==, d2h->error);
461 g_assert_cmphex((reg & AHCI_PX_TFD_STS), ==, d2h->status);
462
463 g_free(d2h);
464 }
465
466 void ahci_port_check_pio_sanity(AHCIQState *ahci, uint8_t port,
467 uint8_t slot, size_t buffsize)
468 {
469 PIOSetupFIS *pio = g_malloc0(0x20);
470
471 /* We cannot check the Status or E_Status registers, because
472 * the status may have again changed between the PIO Setup FIS
473 * and the conclusion of the command with the D2H Register FIS. */
474 memread(ahci->port[port].fb + 0x20, pio, 0x20);
475 g_assert_cmphex(pio->fis_type, ==, 0x5f);
476
477 /* BUG: PIO Setup FIS as utilized by QEMU tries to fit the entire
478 * transfer size in a uint16_t field. The maximum transfer size can
479 * eclipse this; the field is meant to convey the size of data per
480 * each Data FIS, not the entire operation as a whole. For now,
481 * we will sanity check the broken case where applicable. */
482 if (buffsize <= UINT16_MAX) {
483 g_assert_cmphex(le16_to_cpu(pio->tx_count), ==, buffsize);
484 }
485
486 g_free(pio);
487 }
488
489 void ahci_port_check_cmd_sanity(AHCIQState *ahci, AHCICommand *cmd)
490 {
491 AHCICommandHeader cmdh;
492
493 ahci_get_command_header(ahci, cmd->port, cmd->slot, &cmdh);
494 /* Physical Region Descriptor Byte Count is not required to work for NCQ. */
495 if (!cmd->props->ncq) {
496 g_assert_cmphex(cmd->xbytes, ==, cmdh.prdbc);
497 }
498 }
499
500 /* Get the command in #slot of port #port. */
501 void ahci_get_command_header(AHCIQState *ahci, uint8_t port,
502 uint8_t slot, AHCICommandHeader *cmd)
503 {
504 uint64_t ba = ahci->port[port].clb;
505 ba += slot * sizeof(AHCICommandHeader);
506 memread(ba, cmd, sizeof(AHCICommandHeader));
507
508 cmd->flags = le16_to_cpu(cmd->flags);
509 cmd->prdtl = le16_to_cpu(cmd->prdtl);
510 cmd->prdbc = le32_to_cpu(cmd->prdbc);
511 cmd->ctba = le64_to_cpu(cmd->ctba);
512 }
513
514 /* Set the command in #slot of port #port. */
515 void ahci_set_command_header(AHCIQState *ahci, uint8_t port,
516 uint8_t slot, AHCICommandHeader *cmd)
517 {
518 AHCICommandHeader tmp = { .flags = 0 };
519 uint64_t ba = ahci->port[port].clb;
520 ba += slot * sizeof(AHCICommandHeader);
521
522 tmp.flags = cpu_to_le16(cmd->flags);
523 tmp.prdtl = cpu_to_le16(cmd->prdtl);
524 tmp.prdbc = cpu_to_le32(cmd->prdbc);
525 tmp.ctba = cpu_to_le64(cmd->ctba);
526
527 memwrite(ba, &tmp, sizeof(AHCICommandHeader));
528 }
529
530 void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot)
531 {
532 AHCICommandHeader cmd;
533
534 /* Obtain the Nth Command Header */
535 ahci_get_command_header(ahci, port, slot, &cmd);
536 if (cmd.ctba == 0) {
537 /* No address in it, so just return -- it's empty. */
538 goto tidy;
539 }
540
541 /* Free the Table */
542 ahci_free(ahci, cmd.ctba);
543
544 tidy:
545 /* NULL the header. */
546 memset(&cmd, 0x00, sizeof(cmd));
547 ahci_set_command_header(ahci, port, slot, &cmd);
548 ahci->port[port].ctba[slot] = 0;
549 ahci->port[port].prdtl[slot] = 0;
550 }
551
552 void ahci_write_fis(AHCIQState *ahci, AHCICommand *cmd)
553 {
554 RegH2DFIS tmp = cmd->fis;
555 uint64_t addr = cmd->header.ctba;
556
557 /* NCQ commands use exclusively 8 bit fields and needs no adjustment.
558 * Only the count field needs to be adjusted for non-NCQ commands.
559 * The auxiliary FIS fields are defined per-command and are not currently
560 * implemented in libqos/ahci.o, but may or may not need to be flipped. */
561 if (!cmd->props->ncq) {
562 tmp.count = cpu_to_le16(tmp.count);
563 }
564
565 memwrite(addr, &tmp, sizeof(tmp));
566 }
567
568 unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port)
569 {
570 unsigned i;
571 unsigned j;
572 uint32_t reg;
573
574 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
575
576 /* Pick the least recently used command slot that's available */
577 for (i = 0; i < 32; ++i) {
578 j = ((ahci->port[port].next + i) % 32);
579 if (reg & (1 << j)) {
580 continue;
581 }
582 ahci_destroy_command(ahci, port, j);
583 ahci->port[port].next = (j + 1) % 32;
584 return j;
585 }
586
587 g_test_message("All command slots were busy.");
588 g_assert_not_reached();
589 }
590
591 inline unsigned size_to_prdtl(unsigned bytes, unsigned bytes_per_prd)
592 {
593 /* Each PRD can describe up to 4MiB */
594 g_assert_cmphex(bytes_per_prd, <=, 4096 * 1024);
595 g_assert_cmphex(bytes_per_prd & 0x01, ==, 0x00);
596 return (bytes + bytes_per_prd - 1) / bytes_per_prd;
597 }
598
599 /* Issue a command, expecting it to fail and STOP the VM */
600 AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port,
601 uint8_t ide_cmd, uint64_t buffer,
602 size_t bufsize, uint64_t sector)
603 {
604 AHCICommand *cmd;
605
606 cmd = ahci_command_create(ide_cmd);
607 ahci_command_adjust(cmd, sector, buffer, bufsize, 0);
608 ahci_command_commit(ahci, cmd, port);
609 ahci_command_issue_async(ahci, cmd);
610 qmp_eventwait("STOP");
611
612 return cmd;
613 }
614
615 /* Resume a previously failed command and verify/finalize */
616 void ahci_guest_io_resume(AHCIQState *ahci, AHCICommand *cmd)
617 {
618 /* Complete the command */
619 qmp_async("{'execute':'cont' }");
620 qmp_eventwait("RESUME");
621 ahci_command_wait(ahci, cmd);
622 ahci_command_verify(ahci, cmd);
623 ahci_command_free(cmd);
624 }
625
626 /* Given a guest buffer address, perform an IO operation */
627 void ahci_guest_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
628 uint64_t buffer, size_t bufsize, uint64_t sector)
629 {
630 AHCICommand *cmd;
631 cmd = ahci_command_create(ide_cmd);
632 ahci_command_set_buffer(cmd, buffer);
633 ahci_command_set_size(cmd, bufsize);
634 if (sector) {
635 ahci_command_set_offset(cmd, sector);
636 }
637 ahci_command_commit(ahci, cmd, port);
638 ahci_command_issue(ahci, cmd);
639 ahci_command_verify(ahci, cmd);
640 ahci_command_free(cmd);
641 }
642
643 static AHCICommandProp *ahci_command_find(uint8_t command_name)
644 {
645 int i;
646
647 for (i = 0; i < ARRAY_SIZE(ahci_command_properties); i++) {
648 if (ahci_command_properties[i].cmd == command_name) {
649 return &ahci_command_properties[i];
650 }
651 }
652
653 return NULL;
654 }
655
656 /* Given a HOST buffer, create a buffer address and perform an IO operation. */
657 void ahci_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
658 void *buffer, size_t bufsize, uint64_t sector)
659 {
660 uint64_t ptr;
661 AHCICommandProp *props;
662
663 props = ahci_command_find(ide_cmd);
664 g_assert(props);
665 ptr = ahci_alloc(ahci, bufsize);
666 g_assert(ptr);
667 qmemset(ptr, 0x00, bufsize);
668
669 if (props->write) {
670 bufwrite(ptr, buffer, bufsize);
671 }
672
673 ahci_guest_io(ahci, port, ide_cmd, ptr, bufsize, sector);
674
675 if (props->read) {
676 bufread(ptr, buffer, bufsize);
677 }
678
679 ahci_free(ahci, ptr);
680 }
681
682 /**
683 * Initializes a basic command header in memory.
684 * We assume that this is for an ATA command using RegH2DFIS.
685 */
686 static void command_header_init(AHCICommand *cmd)
687 {
688 AHCICommandHeader *hdr = &cmd->header;
689 AHCICommandProp *props = cmd->props;
690
691 hdr->flags = 5; /* RegH2DFIS is 5 DW long. Must be < 32 */
692 hdr->flags |= CMDH_CLR_BSY; /* Clear the BSY bit when done */
693 if (props->write) {
694 hdr->flags |= CMDH_WRITE;
695 }
696 if (props->atapi) {
697 hdr->flags |= CMDH_ATAPI;
698 }
699 /* Other flags: PREFETCH, RESET, and BIST */
700 hdr->prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
701 hdr->prdbc = 0;
702 hdr->ctba = 0;
703 }
704
705 static void command_table_init(AHCICommand *cmd)
706 {
707 RegH2DFIS *fis = &(cmd->fis);
708 uint16_t sect_count = (cmd->xbytes / AHCI_SECTOR_SIZE);
709
710 fis->fis_type = REG_H2D_FIS;
711 fis->flags = REG_H2D_FIS_CMD; /* "Command" bit */
712 fis->command = cmd->name;
713
714 if (cmd->props->ncq) {
715 NCQFIS *ncqfis = (NCQFIS *)fis;
716 /* NCQ is weird and re-uses FIS frames for unrelated data.
717 * See SATA 3.2, 13.6.4.1 READ FPDMA QUEUED for an example. */
718 ncqfis->sector_low = sect_count & 0xFF;
719 ncqfis->sector_hi = (sect_count >> 8) & 0xFF;
720 ncqfis->device = NCQ_DEVICE_MAGIC;
721 /* Force Unit Access is bit 7 in the device register */
722 ncqfis->tag = 0; /* bits 3-7 are the NCQ tag */
723 ncqfis->prio = 0; /* bits 6,7 are a prio tag */
724 /* RARC bit is bit 0 of TAG field */
725 } else {
726 fis->feature_low = 0x00;
727 fis->feature_high = 0x00;
728 if (cmd->props->lba28 || cmd->props->lba48) {
729 fis->device = ATA_DEVICE_LBA;
730 }
731 fis->count = (cmd->xbytes / AHCI_SECTOR_SIZE);
732 }
733 fis->icc = 0x00;
734 fis->control = 0x00;
735 memset(fis->aux, 0x00, ARRAY_SIZE(fis->aux));
736 }
737
738 void ahci_command_enable_atapi_dma(AHCICommand *cmd)
739 {
740 RegH2DFIS *fis = &(cmd->fis);
741 g_assert(cmd->props->atapi);
742 fis->feature_low |= 0x01;
743 }
744
745 AHCICommand *ahci_command_create(uint8_t command_name)
746 {
747 AHCICommandProp *props = ahci_command_find(command_name);
748 AHCICommand *cmd;
749
750 g_assert(props);
751 cmd = g_malloc0(sizeof(AHCICommand));
752 g_assert(!(props->dma && props->pio));
753 g_assert(!(props->lba28 && props->lba48));
754 g_assert(!(props->read && props->write));
755 g_assert(!props->size || props->data);
756 g_assert(!props->ncq || props->lba48);
757
758 /* Defaults and book-keeping */
759 cmd->props = props;
760 cmd->name = command_name;
761 cmd->xbytes = props->size;
762 cmd->prd_size = 4096;
763 cmd->buffer = 0xabad1dea;
764
765 if (!cmd->props->ncq) {
766 cmd->interrupts = AHCI_PX_IS_DHRS;
767 }
768 /* BUG: We expect the DPS interrupt for data commands */
769 /* cmd->interrupts |= props->data ? AHCI_PX_IS_DPS : 0; */
770 /* BUG: We expect the DMA Setup interrupt for DMA commands */
771 /* cmd->interrupts |= props->dma ? AHCI_PX_IS_DSS : 0; */
772 cmd->interrupts |= props->pio ? AHCI_PX_IS_PSS : 0;
773 cmd->interrupts |= props->ncq ? AHCI_PX_IS_SDBS : 0;
774
775 command_header_init(cmd);
776 command_table_init(cmd);
777
778 return cmd;
779 }
780
781 AHCICommand *ahci_atapi_command_create(uint8_t scsi_cmd)
782 {
783 AHCICommand *cmd = ahci_command_create(CMD_PACKET);
784 cmd->atapi_cmd = g_malloc0(16);
785 cmd->atapi_cmd[0] = scsi_cmd;
786 /* ATAPI needs a PIO transfer chunk size set inside of the LBA registers.
787 * The block/sector size is a natural default. */
788 cmd->fis.lba_lo[1] = ATAPI_SECTOR_SIZE >> 8 & 0xFF;
789 cmd->fis.lba_lo[2] = ATAPI_SECTOR_SIZE & 0xFF;
790
791 return cmd;
792 }
793
794 void ahci_command_free(AHCICommand *cmd)
795 {
796 g_free(cmd->atapi_cmd);
797 g_free(cmd);
798 }
799
800 void ahci_command_set_flags(AHCICommand *cmd, uint16_t cmdh_flags)
801 {
802 cmd->header.flags |= cmdh_flags;
803 }
804
805 void ahci_command_clr_flags(AHCICommand *cmd, uint16_t cmdh_flags)
806 {
807 cmd->header.flags &= ~cmdh_flags;
808 }
809
810 static void ahci_atapi_command_set_offset(AHCICommand *cmd, uint64_t lba)
811 {
812 unsigned char *cbd = cmd->atapi_cmd;
813 g_assert(cbd);
814
815 switch (cbd[0]) {
816 case CMD_ATAPI_READ_10:
817 g_assert_cmpuint(lba, <=, UINT32_MAX);
818 stl_be_p(&cbd[2], lba);
819 break;
820 default:
821 /* SCSI doesn't have uniform packet formats,
822 * so you have to add support for it manually. Sorry! */
823 g_assert_not_reached();
824 }
825 }
826
827 void ahci_command_set_offset(AHCICommand *cmd, uint64_t lba_sect)
828 {
829 RegH2DFIS *fis = &(cmd->fis);
830
831 if (cmd->props->atapi) {
832 ahci_atapi_command_set_offset(cmd, lba_sect);
833 return;
834 } else if (cmd->props->lba28) {
835 g_assert_cmphex(lba_sect, <=, 0xFFFFFFF);
836 } else if (cmd->props->lba48 || cmd->props->ncq) {
837 g_assert_cmphex(lba_sect, <=, 0xFFFFFFFFFFFF);
838 } else {
839 /* Can't set offset if we don't know the format. */
840 g_assert_not_reached();
841 }
842
843 /* LBA28 uses the low nibble of the device/control register for LBA24:27 */
844 fis->lba_lo[0] = (lba_sect & 0xFF);
845 fis->lba_lo[1] = (lba_sect >> 8) & 0xFF;
846 fis->lba_lo[2] = (lba_sect >> 16) & 0xFF;
847 if (cmd->props->lba28) {
848 fis->device = (fis->device & 0xF0) | ((lba_sect >> 24) & 0x0F);
849 }
850 fis->lba_hi[0] = (lba_sect >> 24) & 0xFF;
851 fis->lba_hi[1] = (lba_sect >> 32) & 0xFF;
852 fis->lba_hi[2] = (lba_sect >> 40) & 0xFF;
853 }
854
855 void ahci_command_set_buffer(AHCICommand *cmd, uint64_t buffer)
856 {
857 cmd->buffer = buffer;
858 }
859
860 static void ahci_atapi_set_size(AHCICommand *cmd, uint64_t xbytes)
861 {
862 unsigned char *cbd = cmd->atapi_cmd;
863 uint64_t nsectors = xbytes / 2048;
864 g_assert(cbd);
865
866 switch (cbd[0]) {
867 case CMD_ATAPI_READ_10:
868 g_assert_cmpuint(nsectors, <=, UINT16_MAX);
869 stw_be_p(&cbd[7], nsectors);
870 break;
871 default:
872 /* SCSI doesn't have uniform packet formats,
873 * so you have to add support for it manually. Sorry! */
874 g_assert_not_reached();
875 }
876 }
877
878 void ahci_command_set_sizes(AHCICommand *cmd, uint64_t xbytes,
879 unsigned prd_size)
880 {
881 uint16_t sect_count;
882
883 /* Each PRD can describe up to 4MiB, and must not be odd. */
884 g_assert_cmphex(prd_size, <=, 4096 * 1024);
885 g_assert_cmphex(prd_size & 0x01, ==, 0x00);
886 if (prd_size) {
887 cmd->prd_size = prd_size;
888 }
889 cmd->xbytes = xbytes;
890 sect_count = (cmd->xbytes / AHCI_SECTOR_SIZE);
891
892 if (cmd->props->ncq) {
893 NCQFIS *nfis = (NCQFIS *)&(cmd->fis);
894 nfis->sector_low = sect_count & 0xFF;
895 nfis->sector_hi = (sect_count >> 8) & 0xFF;
896 } else if (cmd->props->atapi) {
897 ahci_atapi_set_size(cmd, xbytes);
898 } else {
899 cmd->fis.count = sect_count;
900 }
901 cmd->header.prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
902 }
903
904 void ahci_command_set_size(AHCICommand *cmd, uint64_t xbytes)
905 {
906 ahci_command_set_sizes(cmd, xbytes, cmd->prd_size);
907 }
908
909 void ahci_command_set_prd_size(AHCICommand *cmd, unsigned prd_size)
910 {
911 ahci_command_set_sizes(cmd, cmd->xbytes, prd_size);
912 }
913
914 void ahci_command_adjust(AHCICommand *cmd, uint64_t offset, uint64_t buffer,
915 uint64_t xbytes, unsigned prd_size)
916 {
917 ahci_command_set_sizes(cmd, xbytes, prd_size);
918 ahci_command_set_buffer(cmd, buffer);
919 ahci_command_set_offset(cmd, offset);
920 }
921
922 void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port)
923 {
924 uint16_t i, prdtl;
925 uint64_t table_size, table_ptr, remaining;
926 PRD prd;
927
928 /* This command is now tied to this port/command slot */
929 cmd->port = port;
930 cmd->slot = ahci_pick_cmd(ahci, port);
931
932 if (cmd->props->ncq) {
933 NCQFIS *nfis = (NCQFIS *)&cmd->fis;
934 nfis->tag = (cmd->slot << 3) & 0xFC;
935 }
936
937 /* Create a buffer for the command table */
938 prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
939 table_size = CMD_TBL_SIZ(prdtl);
940 table_ptr = ahci_alloc(ahci, table_size);
941 g_assert(table_ptr);
942 /* AHCI 1.3: Must be aligned to 0x80 */
943 g_assert((table_ptr & 0x7F) == 0x00);
944 cmd->header.ctba = table_ptr;
945
946 /* Commit the command header (part of the Command List Buffer) */
947 ahci_set_command_header(ahci, port, cmd->slot, &(cmd->header));
948 /* Now, write the command table (FIS, ACMD, and PRDT) -- FIS first, */
949 ahci_write_fis(ahci, cmd);
950 /* Then ATAPI CMD, if needed */
951 if (cmd->props->atapi) {
952 memwrite(table_ptr + 0x40, cmd->atapi_cmd, 16);
953 }
954
955 /* Construct and write the PRDs to the command table */
956 g_assert_cmphex(prdtl, ==, cmd->header.prdtl);
957 remaining = cmd->xbytes;
958 for (i = 0; i < prdtl; ++i) {
959 prd.dba = cpu_to_le64(cmd->buffer + (cmd->prd_size * i));
960 prd.res = 0;
961 if (remaining > cmd->prd_size) {
962 /* Note that byte count is 0-based. */
963 prd.dbc = cpu_to_le32(cmd->prd_size - 1);
964 remaining -= cmd->prd_size;
965 } else {
966 /* Again, dbc is 0-based. */
967 prd.dbc = cpu_to_le32(remaining - 1);
968 remaining = 0;
969 }
970 prd.dbc |= cpu_to_le32(0x80000000); /* Request DPS Interrupt */
971
972 /* Commit the PRD entry to the Command Table */
973 memwrite(table_ptr + 0x80 + (i * sizeof(PRD)),
974 &prd, sizeof(PRD));
975 }
976
977 /* Bookmark the PRDTL and CTBA values */
978 ahci->port[port].ctba[cmd->slot] = table_ptr;
979 ahci->port[port].prdtl[cmd->slot] = prdtl;
980 }
981
982 void ahci_command_issue_async(AHCIQState *ahci, AHCICommand *cmd)
983 {
984 if (cmd->props->ncq) {
985 ahci_px_wreg(ahci, cmd->port, AHCI_PX_SACT, (1 << cmd->slot));
986 }
987
988 ahci_px_wreg(ahci, cmd->port, AHCI_PX_CI, (1 << cmd->slot));
989 }
990
991 void ahci_command_wait(AHCIQState *ahci, AHCICommand *cmd)
992 {
993 /* We can't rely on STS_BSY until the command has started processing.
994 * Therefore, we also use the Command Issue bit as indication of
995 * a command in-flight. */
996
997 #define RSET(REG, MASK) (BITSET(ahci_px_rreg(ahci, cmd->port, (REG)), (MASK)))
998
999 while (RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_BSY) ||
1000 RSET(AHCI_PX_CI, 1 << cmd->slot) ||
1001 (cmd->props->ncq && RSET(AHCI_PX_SACT, 1 << cmd->slot))) {
1002 usleep(50);
1003 }
1004
1005 }
1006
1007 void ahci_command_issue(AHCIQState *ahci, AHCICommand *cmd)
1008 {
1009 ahci_command_issue_async(ahci, cmd);
1010 ahci_command_wait(ahci, cmd);
1011 }
1012
1013 void ahci_command_verify(AHCIQState *ahci, AHCICommand *cmd)
1014 {
1015 uint8_t slot = cmd->slot;
1016 uint8_t port = cmd->port;
1017
1018 ahci_port_check_error(ahci, port);
1019 ahci_port_check_interrupts(ahci, port, cmd->interrupts);
1020 ahci_port_check_nonbusy(ahci, port, slot);
1021 ahci_port_check_cmd_sanity(ahci, cmd);
1022 if (cmd->interrupts & AHCI_PX_IS_DHRS) {
1023 ahci_port_check_d2h_sanity(ahci, port, slot);
1024 }
1025 if (cmd->props->pio) {
1026 ahci_port_check_pio_sanity(ahci, port, slot, cmd->xbytes);
1027 }
1028 }
1029
1030 uint8_t ahci_command_slot(AHCICommand *cmd)
1031 {
1032 return cmd->slot;
1033 }
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