2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
33 #include "hw/sysbus.h"
34 #include "hw/arm/arm.h"
35 #include "hw/arm/primecell.h"
36 #include "hw/arm/virt.h"
37 #include "hw/devices.h"
39 #include "sysemu/block-backend.h"
40 #include "sysemu/device_tree.h"
41 #include "sysemu/numa.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/kvm.h"
44 #include "hw/compat.h"
45 #include "hw/loader.h"
46 #include "exec/address-spaces.h"
47 #include "qemu/bitops.h"
48 #include "qemu/error-report.h"
49 #include "hw/pci-host/gpex.h"
50 #include "hw/arm/sysbus-fdt.h"
51 #include "hw/platform-bus.h"
52 #include "hw/arm/fdt.h"
53 #include "hw/intc/arm_gic.h"
54 #include "hw/intc/arm_gicv3_common.h"
56 #include "hw/smbios/smbios.h"
57 #include "qapi/visitor.h"
58 #include "standard-headers/linux/input.h"
60 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
61 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
64 MachineClass *mc = MACHINE_CLASS(oc); \
65 virt_machine_##major##_##minor##_options(mc); \
66 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
71 static const TypeInfo machvirt_##major##_##minor##_info = { \
72 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
73 .parent = TYPE_VIRT_MACHINE, \
74 .instance_init = virt_##major##_##minor##_instance_init, \
75 .class_init = virt_##major##_##minor##_class_init, \
77 static void machvirt_machine_##major##_##minor##_init(void) \
79 type_register_static(&machvirt_##major##_##minor##_info); \
81 type_init(machvirt_machine_##major##_##minor##_init);
83 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
84 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
85 #define DEFINE_VIRT_MACHINE(major, minor) \
86 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
89 /* Number of external interrupt lines to configure the GIC with */
92 #define PLATFORM_BUS_NUM_IRQS 64
94 static ARMPlatformBusSystemParams platform_bus_params
;
96 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
97 * RAM can go up to the 256GB mark, leaving 256GB of the physical
98 * address space unallocated and free for future use between 256G and 512G.
99 * If we need to provide more RAM to VMs in the future then we need to:
100 * * allocate a second bank of RAM starting at 2TB and working up
101 * * fix the DT and ACPI table generation code in QEMU to correctly
102 * report two split lumps of RAM to the guest
103 * * fix KVM in the host kernel to allow guests with >40 bit address spaces
104 * (We don't want to fill all the way up to 512GB with RAM because
105 * we might want it for non-RAM purposes later. Conversely it seems
106 * reasonable to assume that anybody configuring a VM with a quarter
107 * of a terabyte of RAM will be doing it on a host with more than a
108 * terabyte of physical address space.)
110 #define RAMLIMIT_GB 255
111 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
113 /* Addresses and sizes of our components.
114 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
115 * 128MB..256MB is used for miscellaneous device I/O.
116 * 256MB..1GB is reserved for possible future PCI support (ie where the
117 * PCI memory window will go if we add a PCI host controller).
118 * 1GB and up is RAM (which may happily spill over into the
119 * high memory region beyond 4GB).
120 * This represents a compromise between how much RAM can be given to
121 * a 32 bit VM and leaving space for expansion and in particular for PCI.
122 * Note that devices should generally be placed at multiples of 0x10000,
123 * to accommodate guests using 64K pages.
125 static const MemMapEntry a15memmap
[] = {
126 /* Space up to 0x8000000 is reserved for a boot ROM */
127 [VIRT_FLASH
] = { 0, 0x08000000 },
128 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
129 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
130 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
131 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
132 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
133 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
134 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
135 /* This redistributor space allows up to 2*64kB*123 CPUs */
136 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
137 [VIRT_UART
] = { 0x09000000, 0x00001000 },
138 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
139 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
140 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
141 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
142 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
143 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
144 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
145 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
146 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
147 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
148 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
149 [VIRT_MEM
] = { 0x40000000, RAMLIMIT_BYTES
},
150 /* Second PCIe window, 512GB wide at the 512GB boundary */
151 [VIRT_PCIE_MMIO_HIGH
] = { 0x8000000000ULL
, 0x8000000000ULL
},
154 static const int a15irqmap
[] = {
157 [VIRT_PCIE
] = 3, /* ... to 6 */
159 [VIRT_SECURE_UART
] = 8,
160 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
161 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
162 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
165 static const char *valid_cpus
[] = {
172 static bool cpuname_valid(const char *cpu
)
176 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
177 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
184 static void create_fdt(VirtMachineState
*vms
)
186 void *fdt
= create_device_tree(&vms
->fdt_size
);
189 error_report("create_device_tree() failed");
196 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
197 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
198 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
201 * /chosen and /memory nodes must exist for load_dtb
202 * to fill in necessary properties later
204 qemu_fdt_add_subnode(fdt
, "/chosen");
205 qemu_fdt_add_subnode(fdt
, "/memory");
206 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
208 /* Clock node, for the benefit of the UART. The kernel device tree
209 * binding documentation claims the PL011 node clock properties are
210 * optional but in practice if you omit them the kernel refuses to
211 * probe for the device.
213 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
214 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
215 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
216 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
217 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
218 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
220 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
224 static void fdt_add_psci_node(const VirtMachineState
*vms
)
226 uint32_t cpu_suspend_fn
;
230 void *fdt
= vms
->fdt
;
231 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
233 if (!vms
->using_psci
) {
237 qemu_fdt_add_subnode(fdt
, "/psci");
238 if (armcpu
->psci_version
== 2) {
239 const char comp
[] = "arm,psci-0.2\0arm,psci";
240 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
242 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
243 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
244 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
245 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
246 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
248 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
249 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
250 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
253 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
255 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
256 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
257 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
258 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
261 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
262 * to the instruction that should be used to invoke PSCI functions.
263 * However, the device tree binding uses 'method' instead, so that is
264 * what we should use here.
266 qemu_fdt_setprop_string(fdt
, "/psci", "method", "hvc");
268 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
269 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
270 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
271 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
274 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
276 /* On real hardware these interrupts are level-triggered.
277 * On KVM they were edge-triggered before host kernel version 4.4,
278 * and level-triggered afterwards.
279 * On emulated QEMU they are level-triggered.
281 * Getting the DTB info about them wrong is awkward for some
283 * pre-4.8 ignore the DT and leave the interrupt configured
284 * with whatever the GIC reset value (or the bootloader) left it at
285 * 4.8 before rc6 honour the incorrect data by programming it back
286 * into the GIC, causing problems
287 * 4.8rc6 and later ignore the DT and always write "level triggered"
290 * For backwards-compatibility, virt-2.8 and earlier will continue
291 * to say these are edge-triggered, but later machines will report
292 * the correct information.
295 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
296 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
298 if (vmc
->claim_edge_triggered_timers
) {
299 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
302 if (vms
->gic_version
== 2) {
303 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
304 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
305 (1 << vms
->smp_cpus
) - 1);
308 qemu_fdt_add_subnode(vms
->fdt
, "/timer");
310 armcpu
= ARM_CPU(qemu_get_cpu(0));
311 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
312 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
313 qemu_fdt_setprop(vms
->fdt
, "/timer", "compatible",
314 compat
, sizeof(compat
));
316 qemu_fdt_setprop_string(vms
->fdt
, "/timer", "compatible",
319 qemu_fdt_setprop(vms
->fdt
, "/timer", "always-on", NULL
, 0);
320 qemu_fdt_setprop_cells(vms
->fdt
, "/timer", "interrupts",
321 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
322 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
323 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
324 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
327 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
334 * From Documentation/devicetree/bindings/arm/cpus.txt
335 * On ARM v8 64-bit systems value should be set to 2,
336 * that corresponds to the MPIDR_EL1 register size.
337 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
338 * in the system, #address-cells can be set to 1, since
339 * MPIDR_EL1[63:32] bits are not used for CPUs
342 * Here we actually don't know whether our system is 32- or 64-bit one.
343 * The simplest way to go is to examine affinity IDs of all our CPUs. If
344 * at least one of them has Aff3 populated, we set #address-cells to 2.
346 for (cpu
= 0; cpu
< vms
->smp_cpus
; cpu
++) {
347 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
349 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
355 qemu_fdt_add_subnode(vms
->fdt
, "/cpus");
356 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#address-cells", addr_cells
);
357 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#size-cells", 0x0);
359 for (cpu
= vms
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
360 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
361 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
363 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
364 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "cpu");
365 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
366 armcpu
->dtb_compatible
);
368 if (vms
->using_psci
&& vms
->smp_cpus
> 1) {
369 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
370 "enable-method", "psci");
373 if (addr_cells
== 2) {
374 qemu_fdt_setprop_u64(vms
->fdt
, nodename
, "reg",
375 armcpu
->mp_affinity
);
377 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "reg",
378 armcpu
->mp_affinity
);
381 i
= numa_get_node_for_cpu(cpu
);
382 if (i
< nb_numa_nodes
) {
383 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "numa-node-id", i
);
390 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
392 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
393 qemu_fdt_add_subnode(vms
->fdt
, "/intc/its");
394 qemu_fdt_setprop_string(vms
->fdt
, "/intc/its", "compatible",
396 qemu_fdt_setprop(vms
->fdt
, "/intc/its", "msi-controller", NULL
, 0);
397 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc/its", "reg",
398 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
399 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
400 qemu_fdt_setprop_cell(vms
->fdt
, "/intc/its", "phandle", vms
->msi_phandle
);
403 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
405 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
406 qemu_fdt_add_subnode(vms
->fdt
, "/intc/v2m");
407 qemu_fdt_setprop_string(vms
->fdt
, "/intc/v2m", "compatible",
408 "arm,gic-v2m-frame");
409 qemu_fdt_setprop(vms
->fdt
, "/intc/v2m", "msi-controller", NULL
, 0);
410 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc/v2m", "reg",
411 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
412 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
413 qemu_fdt_setprop_cell(vms
->fdt
, "/intc/v2m", "phandle", vms
->msi_phandle
);
416 static void fdt_add_gic_node(VirtMachineState
*vms
)
418 vms
->gic_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
419 qemu_fdt_setprop_cell(vms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
421 qemu_fdt_add_subnode(vms
->fdt
, "/intc");
422 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#interrupt-cells", 3);
423 qemu_fdt_setprop(vms
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
424 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#address-cells", 0x2);
425 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#size-cells", 0x2);
426 qemu_fdt_setprop(vms
->fdt
, "/intc", "ranges", NULL
, 0);
427 if (vms
->gic_version
== 3) {
428 qemu_fdt_setprop_string(vms
->fdt
, "/intc", "compatible",
430 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
431 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
432 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
433 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
434 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
436 /* 'cortex-a15-gic' means 'GIC v2' */
437 qemu_fdt_setprop_string(vms
->fdt
, "/intc", "compatible",
438 "arm,cortex-a15-gic");
439 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
440 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
441 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
442 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
443 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
446 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "phandle", vms
->gic_phandle
);
449 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
453 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
456 armcpu
= ARM_CPU(cpu
);
457 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
) ||
458 !kvm_arm_pmu_create(cpu
, PPI(VIRTUAL_PMU_IRQ
))) {
463 if (vms
->gic_version
== 2) {
464 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
465 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
466 (1 << vms
->smp_cpus
) - 1);
469 armcpu
= ARM_CPU(qemu_get_cpu(0));
470 qemu_fdt_add_subnode(vms
->fdt
, "/pmu");
471 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
472 const char compat
[] = "arm,armv8-pmuv3";
473 qemu_fdt_setprop(vms
->fdt
, "/pmu", "compatible",
474 compat
, sizeof(compat
));
475 qemu_fdt_setprop_cells(vms
->fdt
, "/pmu", "interrupts",
476 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
480 static void create_its(VirtMachineState
*vms
, DeviceState
*gicdev
)
482 const char *itsclass
= its_class_name();
486 /* Do nothing if not supported */
490 dev
= qdev_create(NULL
, itsclass
);
492 object_property_set_link(OBJECT(dev
), OBJECT(gicdev
), "parent-gicv3",
494 qdev_init_nofail(dev
);
495 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
497 fdt_add_its_gic_node(vms
);
500 static void create_v2m(VirtMachineState
*vms
, qemu_irq
*pic
)
503 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
506 dev
= qdev_create(NULL
, "arm-gicv2m");
507 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
508 qdev_prop_set_uint32(dev
, "base-spi", irq
);
509 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
510 qdev_init_nofail(dev
);
512 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
513 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
516 fdt_add_v2m_gic_node(vms
);
519 static void create_gic(VirtMachineState
*vms
, qemu_irq
*pic
)
521 /* We create a standalone GIC */
522 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
524 SysBusDevice
*gicbusdev
;
526 int type
= vms
->gic_version
, i
;
528 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
530 gicdev
= qdev_create(NULL
, gictype
);
531 qdev_prop_set_uint32(gicdev
, "revision", type
);
532 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
533 /* Note that the num-irq property counts both internal and external
534 * interrupts; there are always 32 of the former (mandated by GIC spec).
536 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
537 if (!kvm_irqchip_in_kernel()) {
538 qdev_prop_set_bit(gicdev
, "has-security-extensions", vms
->secure
);
540 qdev_init_nofail(gicdev
);
541 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
542 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
544 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
546 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
549 /* Wire the outputs from each CPU's generic timer and the GICv3
550 * maintenance interrupt signal to the appropriate GIC PPI inputs,
551 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
553 for (i
= 0; i
< smp_cpus
; i
++) {
554 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
555 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
557 /* Mapping from the output timer irq lines from the CPU to the
558 * GIC PPI inputs we use for the virt board.
560 const int timer_irq
[] = {
561 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
562 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
563 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
564 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
567 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
568 qdev_connect_gpio_out(cpudev
, irq
,
569 qdev_get_gpio_in(gicdev
,
570 ppibase
+ timer_irq
[irq
]));
573 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt", 0,
574 qdev_get_gpio_in(gicdev
, ppibase
575 + ARCH_GICV3_MAINT_IRQ
));
577 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
578 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
579 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
580 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
581 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
582 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
583 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
586 for (i
= 0; i
< NUM_IRQS
; i
++) {
587 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
590 fdt_add_gic_node(vms
);
592 if (type
== 3 && !vmc
->no_its
) {
593 create_its(vms
, gicdev
);
594 } else if (type
== 2) {
595 create_v2m(vms
, pic
);
599 static void create_uart(const VirtMachineState
*vms
, qemu_irq
*pic
, int uart
,
600 MemoryRegion
*mem
, CharDriverState
*chr
)
603 hwaddr base
= vms
->memmap
[uart
].base
;
604 hwaddr size
= vms
->memmap
[uart
].size
;
605 int irq
= vms
->irqmap
[uart
];
606 const char compat
[] = "arm,pl011\0arm,primecell";
607 const char clocknames
[] = "uartclk\0apb_pclk";
608 DeviceState
*dev
= qdev_create(NULL
, "pl011");
609 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
611 qdev_prop_set_chr(dev
, "chardev", chr
);
612 qdev_init_nofail(dev
);
613 memory_region_add_subregion(mem
, base
,
614 sysbus_mmio_get_region(s
, 0));
615 sysbus_connect_irq(s
, 0, pic
[irq
]);
617 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
618 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
619 /* Note that we can't use setprop_string because of the embedded NUL */
620 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible",
621 compat
, sizeof(compat
));
622 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
624 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
625 GIC_FDT_IRQ_TYPE_SPI
, irq
,
626 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
627 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "clocks",
628 vms
->clock_phandle
, vms
->clock_phandle
);
629 qemu_fdt_setprop(vms
->fdt
, nodename
, "clock-names",
630 clocknames
, sizeof(clocknames
));
632 if (uart
== VIRT_UART
) {
633 qemu_fdt_setprop_string(vms
->fdt
, "/chosen", "stdout-path", nodename
);
635 /* Mark as not usable by the normal world */
636 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
637 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
643 static void create_rtc(const VirtMachineState
*vms
, qemu_irq
*pic
)
646 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
647 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
648 int irq
= vms
->irqmap
[VIRT_RTC
];
649 const char compat
[] = "arm,pl031\0arm,primecell";
651 sysbus_create_simple("pl031", base
, pic
[irq
]);
653 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
654 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
655 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
656 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
658 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
659 GIC_FDT_IRQ_TYPE_SPI
, irq
,
660 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
661 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
662 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
666 static DeviceState
*gpio_key_dev
;
667 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
669 /* use gpio Pin 3 for power button event */
670 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
673 static Notifier virt_system_powerdown_notifier
= {
674 .notify
= virt_powerdown_req
677 static void create_gpio(const VirtMachineState
*vms
, qemu_irq
*pic
)
680 DeviceState
*pl061_dev
;
681 hwaddr base
= vms
->memmap
[VIRT_GPIO
].base
;
682 hwaddr size
= vms
->memmap
[VIRT_GPIO
].size
;
683 int irq
= vms
->irqmap
[VIRT_GPIO
];
684 const char compat
[] = "arm,pl061\0arm,primecell";
686 pl061_dev
= sysbus_create_simple("pl061", base
, pic
[irq
]);
688 uint32_t phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
689 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
690 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
691 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
693 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
694 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#gpio-cells", 2);
695 qemu_fdt_setprop(vms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
696 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
697 GIC_FDT_IRQ_TYPE_SPI
, irq
,
698 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
699 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
700 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
701 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", phandle
);
703 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
704 qdev_get_gpio_in(pl061_dev
, 3));
705 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys");
706 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
707 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#size-cells", 0);
708 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#address-cells", 1);
710 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys/poweroff");
711 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys/poweroff",
712 "label", "GPIO Key Poweroff");
713 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys/poweroff", "linux,code",
715 qemu_fdt_setprop_cells(vms
->fdt
, "/gpio-keys/poweroff",
716 "gpios", phandle
, 3, 0);
718 /* connect powerdown request */
719 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier
);
724 static void create_virtio_devices(const VirtMachineState
*vms
, qemu_irq
*pic
)
727 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
729 /* We create the transports in forwards order. Since qbus_realize()
730 * prepends (not appends) new child buses, the incrementing loop below will
731 * create a list of virtio-mmio buses with decreasing base addresses.
733 * When a -device option is processed from the command line,
734 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
735 * order. The upshot is that -device options in increasing command line
736 * order are mapped to virtio-mmio buses with decreasing base addresses.
738 * When this code was originally written, that arrangement ensured that the
739 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
740 * the first -device on the command line. (The end-to-end order is a
741 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
742 * guest kernel's name-to-address assignment strategy.)
744 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
745 * the message, if not necessarily the code, of commit 70161ff336.
746 * Therefore the loop now establishes the inverse of the original intent.
748 * Unfortunately, we can't counteract the kernel change by reversing the
749 * loop; it would break existing command lines.
751 * In any case, the kernel makes no guarantee about the stability of
752 * enumeration order of virtio devices (as demonstrated by it changing
753 * between kernel versions). For reliable and stable identification
754 * of disks users must use UUIDs or similar mechanisms.
756 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
757 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
758 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
760 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
763 /* We add dtb nodes in reverse order so that they appear in the finished
764 * device tree lowest address first.
766 * Note that this mapping is independent of the loop above. The previous
767 * loop influences virtio device to virtio transport assignment, whereas
768 * this loop controls how virtio transports are laid out in the dtb.
770 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
772 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
773 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
775 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
776 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
777 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
778 "compatible", "virtio,mmio");
779 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
781 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
782 GIC_FDT_IRQ_TYPE_SPI
, irq
,
783 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
788 static void create_one_flash(const char *name
, hwaddr flashbase
,
789 hwaddr flashsize
, const char *file
,
790 MemoryRegion
*sysmem
)
792 /* Create and map a single flash device. We use the same
793 * parameters as the flash devices on the Versatile Express board.
795 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
796 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
797 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
798 const uint64_t sectorlength
= 256 * 1024;
801 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
805 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
806 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
807 qdev_prop_set_uint8(dev
, "width", 4);
808 qdev_prop_set_uint8(dev
, "device-width", 2);
809 qdev_prop_set_bit(dev
, "big-endian", false);
810 qdev_prop_set_uint16(dev
, "id0", 0x89);
811 qdev_prop_set_uint16(dev
, "id1", 0x18);
812 qdev_prop_set_uint16(dev
, "id2", 0x00);
813 qdev_prop_set_uint16(dev
, "id3", 0x00);
814 qdev_prop_set_string(dev
, "name", name
);
815 qdev_init_nofail(dev
);
817 memory_region_add_subregion(sysmem
, flashbase
,
818 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0));
824 if (drive_get(IF_PFLASH
, 0, 0)) {
825 error_report("The contents of the first flash device may be "
826 "specified with -bios or with -drive if=pflash... "
827 "but you cannot use both options at once");
830 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, file
);
832 error_report("Could not find ROM image '%s'", file
);
835 image_size
= load_image_mr(fn
, sysbus_mmio_get_region(sbd
, 0));
837 if (image_size
< 0) {
838 error_report("Could not load ROM image '%s'", file
);
844 static void create_flash(const VirtMachineState
*vms
,
845 MemoryRegion
*sysmem
,
846 MemoryRegion
*secure_sysmem
)
848 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
849 * Any file passed via -bios goes in the first of these.
850 * sysmem is the system memory space. secure_sysmem is the secure view
851 * of the system, and the first flash device should be made visible only
852 * there. The second flash device is visible to both secure and nonsecure.
853 * If sysmem == secure_sysmem this means there is no separate Secure
854 * address space and both flash devices are generally visible.
856 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
857 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
860 create_one_flash("virt.flash0", flashbase
, flashsize
,
861 bios_name
, secure_sysmem
);
862 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
,
865 if (sysmem
== secure_sysmem
) {
866 /* Report both flash devices as a single node in the DT */
867 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
868 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
869 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
870 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
871 2, flashbase
, 2, flashsize
,
872 2, flashbase
+ flashsize
, 2, flashsize
);
873 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
876 /* Report the devices as separate nodes so we can mark one as
877 * only visible to the secure world.
879 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
880 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
881 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
882 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
883 2, flashbase
, 2, flashsize
);
884 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
885 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
886 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
889 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
890 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
891 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
892 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
893 2, flashbase
+ flashsize
, 2, flashsize
);
894 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
899 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
901 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
902 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
906 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
907 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)smp_cpus
);
909 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
910 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
911 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
912 "compatible", "qemu,fw-cfg-mmio");
913 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
919 static void create_pcie_irq_map(const VirtMachineState
*vms
,
920 uint32_t gic_phandle
,
921 int first_irq
, const char *nodename
)
924 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
925 uint32_t *irq_map
= full_irq_map
;
927 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
928 for (pin
= 0; pin
< 4; pin
++) {
929 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
930 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
931 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
935 devfn
<< 8, 0, 0, /* devfn */
936 pin
+ 1, /* PCI pin */
937 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
939 /* Convert map to big endian */
940 for (i
= 0; i
< 10; i
++) {
941 irq_map
[i
] = cpu_to_be32(map
[i
]);
947 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-map",
948 full_irq_map
, sizeof(full_irq_map
));
950 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupt-map-mask",
951 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
955 static void create_pcie(const VirtMachineState
*vms
, qemu_irq
*pic
)
957 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
958 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
959 hwaddr base_mmio_high
= vms
->memmap
[VIRT_PCIE_MMIO_HIGH
].base
;
960 hwaddr size_mmio_high
= vms
->memmap
[VIRT_PCIE_MMIO_HIGH
].size
;
961 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
962 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
963 hwaddr base_ecam
= vms
->memmap
[VIRT_PCIE_ECAM
].base
;
964 hwaddr size_ecam
= vms
->memmap
[VIRT_PCIE_ECAM
].size
;
965 hwaddr base
= base_mmio
;
966 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
967 int irq
= vms
->irqmap
[VIRT_PCIE
];
968 MemoryRegion
*mmio_alias
;
969 MemoryRegion
*mmio_reg
;
970 MemoryRegion
*ecam_alias
;
971 MemoryRegion
*ecam_reg
;
977 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
978 qdev_init_nofail(dev
);
980 /* Map only the first size_ecam bytes of ECAM space */
981 ecam_alias
= g_new0(MemoryRegion
, 1);
982 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
983 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
984 ecam_reg
, 0, size_ecam
);
985 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
987 /* Map the MMIO window into system address space so as to expose
988 * the section of PCI MMIO space which starts at the same base address
989 * (ie 1:1 mapping for that part of PCI MMIO space visible through
992 mmio_alias
= g_new0(MemoryRegion
, 1);
993 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
994 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
995 mmio_reg
, base_mmio
, size_mmio
);
996 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
999 /* Map high MMIO space */
1000 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1002 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1003 mmio_reg
, base_mmio_high
, size_mmio_high
);
1004 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1008 /* Map IO port space */
1009 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1011 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1012 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
1015 pci
= PCI_HOST_BRIDGE(dev
);
1017 for (i
= 0; i
< nb_nics
; i
++) {
1018 NICInfo
*nd
= &nd_table
[i
];
1021 nd
->model
= g_strdup("virtio");
1024 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1028 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1029 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1030 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
1031 "compatible", "pci-host-ecam-generic");
1032 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "pci");
1033 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 3);
1034 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 2);
1035 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "bus-range", 0,
1037 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1039 if (vms
->msi_phandle
) {
1040 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "msi-parent",
1044 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1045 2, base_ecam
, 2, size_ecam
);
1048 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1049 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1050 2, base_pio
, 2, size_pio
,
1051 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1052 2, base_mmio
, 2, size_mmio
,
1053 1, FDT_PCI_RANGE_MMIO_64BIT
,
1055 2, base_mmio_high
, 2, size_mmio_high
);
1057 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1058 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1059 2, base_pio
, 2, size_pio
,
1060 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1061 2, base_mmio
, 2, size_mmio
);
1064 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 1);
1065 create_pcie_irq_map(vms
, vms
->gic_phandle
, irq
, nodename
);
1070 static void create_platform_bus(VirtMachineState
*vms
, qemu_irq
*pic
)
1075 ARMPlatformBusFDTParams
*fdt_params
= g_new(ARMPlatformBusFDTParams
, 1);
1076 MemoryRegion
*sysmem
= get_system_memory();
1078 platform_bus_params
.platform_bus_base
= vms
->memmap
[VIRT_PLATFORM_BUS
].base
;
1079 platform_bus_params
.platform_bus_size
= vms
->memmap
[VIRT_PLATFORM_BUS
].size
;
1080 platform_bus_params
.platform_bus_first_irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
];
1081 platform_bus_params
.platform_bus_num_irqs
= PLATFORM_BUS_NUM_IRQS
;
1083 fdt_params
->system_params
= &platform_bus_params
;
1084 fdt_params
->binfo
= &vms
->bootinfo
;
1085 fdt_params
->intc
= "/intc";
1087 * register a machine init done notifier that creates the device tree
1088 * nodes of the platform bus and its children dynamic sysbus devices
1090 arm_register_platform_bus_fdt_creator(fdt_params
);
1092 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
1093 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1094 qdev_prop_set_uint32(dev
, "num_irqs",
1095 platform_bus_params
.platform_bus_num_irqs
);
1096 qdev_prop_set_uint32(dev
, "mmio_size",
1097 platform_bus_params
.platform_bus_size
);
1098 qdev_init_nofail(dev
);
1099 s
= SYS_BUS_DEVICE(dev
);
1101 for (i
= 0; i
< platform_bus_params
.platform_bus_num_irqs
; i
++) {
1102 int irqn
= platform_bus_params
.platform_bus_first_irq
+ i
;
1103 sysbus_connect_irq(s
, i
, pic
[irqn
]);
1106 memory_region_add_subregion(sysmem
,
1107 platform_bus_params
.platform_bus_base
,
1108 sysbus_mmio_get_region(s
, 0));
1111 static void create_secure_ram(VirtMachineState
*vms
,
1112 MemoryRegion
*secure_sysmem
)
1114 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1116 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1117 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1119 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
, &error_fatal
);
1120 vmstate_register_ram_global(secram
);
1121 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1123 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1124 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1125 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "memory");
1126 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1127 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
1128 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
1133 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1135 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1138 *fdt_size
= board
->fdt_size
;
1142 static void virt_build_smbios(VirtMachineState
*vms
)
1144 uint8_t *smbios_tables
, *smbios_anchor
;
1145 size_t smbios_tables_len
, smbios_anchor_len
;
1146 const char *product
= "QEMU Virtual Machine";
1152 if (kvm_enabled()) {
1153 product
= "KVM Virtual Machine";
1156 smbios_set_defaults("QEMU", product
,
1157 "1.0", false, true, SMBIOS_ENTRY_POINT_30
);
1159 smbios_get_tables(NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1160 &smbios_anchor
, &smbios_anchor_len
);
1162 if (smbios_anchor
) {
1163 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1164 smbios_tables
, smbios_tables_len
);
1165 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1166 smbios_anchor
, smbios_anchor_len
);
1171 void virt_machine_done(Notifier
*notifier
, void *data
)
1173 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1176 virt_acpi_setup(vms
);
1177 virt_build_smbios(vms
);
1180 static void machvirt_init(MachineState
*machine
)
1182 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1183 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1184 qemu_irq pic
[NUM_IRQS
];
1185 MemoryRegion
*sysmem
= get_system_memory();
1186 MemoryRegion
*secure_sysmem
= NULL
;
1187 int n
, virt_max_cpus
;
1188 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1189 const char *cpu_model
= machine
->cpu_model
;
1192 const char *typename
;
1195 bool firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
1199 cpu_model
= "cortex-a15";
1202 /* We can probe only here because during property set
1203 * KVM is not available yet
1205 if (!vms
->gic_version
) {
1206 if (!kvm_enabled()) {
1207 error_report("gic-version=host requires KVM");
1211 vms
->gic_version
= kvm_arm_vgic_probe();
1212 if (!vms
->gic_version
) {
1213 error_report("Unable to determine GIC version supported by host");
1218 /* Separate the actual CPU model name from any appended features */
1219 cpustr
= g_strsplit(cpu_model
, ",", 2);
1221 if (!cpuname_valid(cpustr
[0])) {
1222 error_report("mach-virt: CPU %s not supported", cpustr
[0]);
1226 /* If we have an EL3 boot ROM then the assumption is that it will
1227 * implement PSCI itself, so disable QEMU's internal implementation
1228 * so it doesn't get in the way. Instead of starting secondary
1229 * CPUs in PSCI powerdown state we will start them all running and
1230 * let the boot ROM sort them out.
1231 * The usual case is that we do use QEMU's PSCI implementation.
1233 vms
->using_psci
= !(vms
->secure
&& firmware_loaded
);
1235 /* The maximum number of CPUs depends on the GIC version, or on how
1236 * many redistributors we can fit into the memory map.
1238 if (vms
->gic_version
== 3) {
1239 virt_max_cpus
= vms
->memmap
[VIRT_GIC_REDIST
].size
/ 0x20000;
1240 clustersz
= GICV3_TARGETLIST_BITS
;
1242 virt_max_cpus
= GIC_NCPU
;
1243 clustersz
= GIC_TARGETLIST_BITS
;
1246 if (max_cpus
> virt_max_cpus
) {
1247 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1248 "supported by machine 'mach-virt' (%d)",
1249 max_cpus
, virt_max_cpus
);
1253 vms
->smp_cpus
= smp_cpus
;
1255 if (machine
->ram_size
> vms
->memmap
[VIRT_MEM
].size
) {
1256 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB
);
1261 if (kvm_enabled()) {
1262 error_report("mach-virt: KVM does not support Security extensions");
1266 /* The Secure view of the world is the same as the NonSecure,
1267 * but with a few extra devices. Create it as a container region
1268 * containing the system memory at low priority; any secure-only
1269 * devices go in at higher priority and take precedence.
1271 secure_sysmem
= g_new(MemoryRegion
, 1);
1272 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1274 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1279 oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpustr
[0]);
1281 error_report("Unable to find CPU definition");
1284 typename
= object_class_get_name(oc
);
1286 /* convert -smp CPU options specified by the user into global props */
1288 cc
->parse_features(typename
, cpustr
[1], &err
);
1291 error_report_err(err
);
1295 for (n
= 0; n
< smp_cpus
; n
++) {
1296 Object
*cpuobj
= object_new(typename
);
1297 if (!vmc
->disallow_affinity_adjustment
) {
1298 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1299 * GIC's target-list limitations. 32-bit KVM hosts currently
1300 * always create clusters of 4 CPUs, but that is expected to
1301 * change when they gain support for gicv3. When KVM is enabled
1302 * it will override the changes we make here, therefore our
1303 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1304 * and to improve SGI efficiency.
1306 uint8_t aff1
= n
/ clustersz
;
1307 uint8_t aff0
= n
% clustersz
;
1308 object_property_set_int(cpuobj
, (aff1
<< ARM_AFF1_SHIFT
) | aff0
,
1309 "mp-affinity", NULL
);
1313 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1316 if (vms
->using_psci
) {
1317 object_property_set_int(cpuobj
, QEMU_PSCI_CONDUIT_HVC
,
1318 "psci-conduit", NULL
);
1320 /* Secondary CPUs start in PSCI powered-down state */
1322 object_property_set_bool(cpuobj
, true,
1323 "start-powered-off", NULL
);
1327 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu", NULL
)) {
1328 object_property_set_bool(cpuobj
, false, "pmu", NULL
);
1331 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1332 object_property_set_int(cpuobj
, vms
->memmap
[VIRT_CPUPERIPHS
].base
,
1333 "reset-cbar", &error_abort
);
1336 object_property_set_link(cpuobj
, OBJECT(sysmem
), "memory",
1339 object_property_set_link(cpuobj
, OBJECT(secure_sysmem
),
1340 "secure-memory", &error_abort
);
1343 object_property_set_bool(cpuobj
, true, "realized", NULL
);
1345 fdt_add_timer_nodes(vms
);
1346 fdt_add_cpu_nodes(vms
);
1347 fdt_add_psci_node(vms
);
1349 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
1351 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
, ram
);
1353 create_flash(vms
, sysmem
, secure_sysmem
? secure_sysmem
: sysmem
);
1355 create_gic(vms
, pic
);
1357 fdt_add_pmu_nodes(vms
);
1359 create_uart(vms
, pic
, VIRT_UART
, sysmem
, serial_hds
[0]);
1362 create_secure_ram(vms
, secure_sysmem
);
1363 create_uart(vms
, pic
, VIRT_SECURE_UART
, secure_sysmem
, serial_hds
[1]);
1366 create_rtc(vms
, pic
);
1368 create_pcie(vms
, pic
);
1370 create_gpio(vms
, pic
);
1372 /* Create mmio transports, so the user can create virtio backends
1373 * (which will be automatically plugged in to the transports). If
1374 * no backend is created the transport will just sit harmlessly idle.
1376 create_virtio_devices(vms
, pic
);
1378 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
1379 rom_set_fw(vms
->fw_cfg
);
1381 vms
->machine_done
.notify
= virt_machine_done
;
1382 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
1384 vms
->bootinfo
.ram_size
= machine
->ram_size
;
1385 vms
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1386 vms
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1387 vms
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1388 vms
->bootinfo
.nb_cpus
= smp_cpus
;
1389 vms
->bootinfo
.board_id
= -1;
1390 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
1391 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
1392 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
1393 arm_load_kernel(ARM_CPU(first_cpu
), &vms
->bootinfo
);
1396 * arm_load_kernel machine init done notifier registration must
1397 * happen before the platform_bus_create call. In this latter,
1398 * another notifier is registered which adds platform bus nodes.
1399 * Notifiers are executed in registration reverse order.
1401 create_platform_bus(vms
, pic
);
1404 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1406 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1411 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1413 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1415 vms
->secure
= value
;
1418 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1420 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1422 return vms
->highmem
;
1425 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1427 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1429 vms
->highmem
= value
;
1432 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1434 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1435 const char *val
= vms
->gic_version
== 3 ? "3" : "2";
1437 return g_strdup(val
);
1440 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1442 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1444 if (!strcmp(value
, "3")) {
1445 vms
->gic_version
= 3;
1446 } else if (!strcmp(value
, "2")) {
1447 vms
->gic_version
= 2;
1448 } else if (!strcmp(value
, "host")) {
1449 vms
->gic_version
= 0; /* Will probe later */
1451 error_setg(errp
, "Invalid gic-version value");
1452 error_append_hint(errp
, "Valid values are 3, 2, host.\n");
1456 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1458 MachineClass
*mc
= MACHINE_CLASS(oc
);
1460 mc
->init
= machvirt_init
;
1461 /* Start max_cpus at the maximum QEMU supports. We'll further restrict
1462 * it later in machvirt_init, where we have more information about the
1463 * configuration of the particular instance.
1466 mc
->has_dynamic_sysbus
= true;
1467 mc
->block_default_type
= IF_VIRTIO
;
1469 mc
->pci_allow_0_address
= true;
1470 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1471 mc
->minimum_page_bits
= 12;
1474 static const TypeInfo virt_machine_info
= {
1475 .name
= TYPE_VIRT_MACHINE
,
1476 .parent
= TYPE_MACHINE
,
1478 .instance_size
= sizeof(VirtMachineState
),
1479 .class_size
= sizeof(VirtMachineClass
),
1480 .class_init
= virt_machine_class_init
,
1483 static void machvirt_machine_init(void)
1485 type_register_static(&virt_machine_info
);
1487 type_init(machvirt_machine_init
);
1489 static void virt_2_9_instance_init(Object
*obj
)
1491 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1493 /* EL3 is disabled by default on virt: this makes us consistent
1494 * between KVM and TCG for this board, and it also allows us to
1495 * boot UEFI blobs which assume no TrustZone support.
1497 vms
->secure
= false;
1498 object_property_add_bool(obj
, "secure", virt_get_secure
,
1499 virt_set_secure
, NULL
);
1500 object_property_set_description(obj
, "secure",
1501 "Set on/off to enable/disable the ARM "
1502 "Security Extensions (TrustZone)",
1505 /* High memory is enabled by default */
1506 vms
->highmem
= true;
1507 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1508 virt_set_highmem
, NULL
);
1509 object_property_set_description(obj
, "highmem",
1510 "Set on/off to enable/disable using "
1511 "physical address space above 32 bits",
1513 /* Default GIC type is v2 */
1514 vms
->gic_version
= 2;
1515 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
1516 virt_set_gic_version
, NULL
);
1517 object_property_set_description(obj
, "gic-version",
1519 "Valid values are 2, 3 and host", NULL
);
1521 vms
->memmap
= a15memmap
;
1522 vms
->irqmap
= a15irqmap
;
1525 static void virt_machine_2_9_options(MachineClass
*mc
)
1528 DEFINE_VIRT_MACHINE_AS_LATEST(2, 9)
1530 #define VIRT_COMPAT_2_8 \
1533 static void virt_2_8_instance_init(Object
*obj
)
1535 virt_2_9_instance_init(obj
);
1538 static void virt_machine_2_8_options(MachineClass
*mc
)
1540 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1542 virt_machine_2_9_options(mc
);
1543 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_8
);
1544 /* For 2.8 and earlier we falsely claimed in the DT that
1545 * our timers were edge-triggered, not level-triggered.
1547 vmc
->claim_edge_triggered_timers
= true;
1549 DEFINE_VIRT_MACHINE(2, 8)
1551 #define VIRT_COMPAT_2_7 \
1554 static void virt_2_7_instance_init(Object
*obj
)
1556 virt_2_8_instance_init(obj
);
1559 static void virt_machine_2_7_options(MachineClass
*mc
)
1561 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1563 virt_machine_2_8_options(mc
);
1564 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_7
);
1565 /* ITS was introduced with 2.8 */
1567 /* Stick with 1K pages for migration compatibility */
1568 mc
->minimum_page_bits
= 0;
1570 DEFINE_VIRT_MACHINE(2, 7)
1572 #define VIRT_COMPAT_2_6 \
1575 static void virt_2_6_instance_init(Object
*obj
)
1577 virt_2_7_instance_init(obj
);
1580 static void virt_machine_2_6_options(MachineClass
*mc
)
1582 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1584 virt_machine_2_7_options(mc
);
1585 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_6
);
1586 vmc
->disallow_affinity_adjustment
= true;
1587 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
1590 DEFINE_VIRT_MACHINE(2, 6)