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fdc: Add a floppy qbus
[qemu/kevin.git] / hw / block / fdc.c
blob094c1e895f46bdefb480e6571fb1c2ef4d93f167
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "qemu/osdep.h"
31 #include "hw/hw.h"
32 #include "hw/block/fdc.h"
33 #include "qapi/error.h"
34 #include "qemu/error-report.h"
35 #include "qemu/timer.h"
36 #include "hw/isa/isa.h"
37 #include "hw/sysbus.h"
38 #include "sysemu/block-backend.h"
39 #include "sysemu/blockdev.h"
40 #include "sysemu/sysemu.h"
41 #include "qemu/log.h"
42
43 /********************************************************/
44 /* debug Floppy devices */
45
46 #define DEBUG_FLOPPY 0
47
48 #define FLOPPY_DPRINTF(fmt, ...) \
49 do { \
50 if (DEBUG_FLOPPY) { \
51 fprintf(stderr, "FLOPPY: " fmt , ## __VA_ARGS__); \
52 } \
53 } while (0)
54
55
56 /********************************************************/
57 /* qdev floppy bus */
58
59 #define TYPE_FLOPPY_BUS "floppy-bus"
60 #define FLOPPY_BUS(obj) OBJECT_CHECK(FloppyBus, (obj), TYPE_FLOPPY_BUS)
61
62 typedef struct FDCtrl FDCtrl;
63
64 typedef struct FloppyBus {
65 BusState bus;
66 FDCtrl *fdc;
67 } FloppyBus;
68
69 static const TypeInfo floppy_bus_info = {
70 .name = TYPE_FLOPPY_BUS,
71 .parent = TYPE_BUS,
72 .instance_size = sizeof(FloppyBus),
73 };
74
75 static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev)
76 {
77 qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
78 bus->fdc = fdc;
79 }
80
81
82 /********************************************************/
83 /* Floppy drive emulation */
84
85 typedef enum FDriveRate {
86 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
87 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
88 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
89 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
90 } FDriveRate;
91
92 typedef enum FDriveSize {
93 FDRIVE_SIZE_UNKNOWN,
94 FDRIVE_SIZE_350,
95 FDRIVE_SIZE_525,
96 } FDriveSize;
97
98 typedef struct FDFormat {
99 FloppyDriveType drive;
100 uint8_t last_sect;
101 uint8_t max_track;
102 uint8_t max_head;
103 FDriveRate rate;
104 } FDFormat;
105
106 /* In many cases, the total sector size of a format is enough to uniquely
107 * identify it. However, there are some total sector collisions between
108 * formats of different physical size, and these are noted below by
109 * highlighting the total sector size for entries with collisions. */
110 static const FDFormat fd_formats[] = {
111 /* First entry is default format */
112 /* 1.44 MB 3"1/2 floppy disks */
113 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */
114 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */
115 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, },
116 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, },
117 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, },
118 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, },
119 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, },
120 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, },
121 /* 2.88 MB 3"1/2 floppy disks */
122 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, },
123 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, },
124 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, },
125 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, },
126 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, },
127 /* 720 kB 3"1/2 floppy disks */
128 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */
129 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, },
130 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, },
131 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, },
132 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, },
133 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, },
134 /* 1.2 MB 5"1/4 floppy disks */
135 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, },
136 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */
137 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, },
138 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, },
139 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */
140 /* 720 kB 5"1/4 floppy disks */
141 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */
142 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, },
143 /* 360 kB 5"1/4 floppy disks */
144 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */
145 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, },
146 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, },
147 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, },
148 /* 320 kB 5"1/4 floppy disks */
149 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, },
150 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, },
151 /* 360 kB must match 5"1/4 better than 3"1/2... */
152 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */
153 /* end */
154 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },
155 };
156
157 static FDriveSize drive_size(FloppyDriveType drive)
158 {
159 switch (drive) {
160 case FLOPPY_DRIVE_TYPE_120:
161 return FDRIVE_SIZE_525;
162 case FLOPPY_DRIVE_TYPE_144:
163 case FLOPPY_DRIVE_TYPE_288:
164 return FDRIVE_SIZE_350;
165 default:
166 return FDRIVE_SIZE_UNKNOWN;
167 }
168 }
169
170 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
171 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
172
173 /* Will always be a fixed parameter for us */
174 #define FD_SECTOR_LEN 512
175 #define FD_SECTOR_SC 2 /* Sector size code */
176 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
177
178 /* Floppy disk drive emulation */
179 typedef enum FDiskFlags {
180 FDISK_DBL_SIDES = 0x01,
181 } FDiskFlags;
182
183 typedef struct FDrive {
184 FDCtrl *fdctrl;
185 BlockBackend *blk;
186 /* Drive status */
187 FloppyDriveType drive; /* CMOS drive type */
188 uint8_t perpendicular; /* 2.88 MB access mode */
189 /* Position */
190 uint8_t head;
191 uint8_t track;
192 uint8_t sect;
193 /* Media */
194 FloppyDriveType disk; /* Current disk type */
195 FDiskFlags flags;
196 uint8_t last_sect; /* Nb sector per track */
197 uint8_t max_track; /* Nb of tracks */
198 uint16_t bps; /* Bytes per sector */
199 uint8_t ro; /* Is read-only */
200 uint8_t media_changed; /* Is media changed */
201 uint8_t media_rate; /* Data rate of medium */
202
203 bool media_validated; /* Have we validated the media? */
204 } FDrive;
205
206
207 static FloppyDriveType get_fallback_drive_type(FDrive *drv);
208
209 /* Hack: FD_SEEK is expected to work on empty drives. However, QEMU
210 * currently goes through some pains to keep seeks within the bounds
211 * established by last_sect and max_track. Correcting this is difficult,
212 * as refactoring FDC code tends to expose nasty bugs in the Linux kernel.
213 *
214 * For now: allow empty drives to have large bounds so we can seek around,
215 * with the understanding that when a diskette is inserted, the bounds will
216 * properly tighten to match the geometry of that inserted medium.
217 */
218 static void fd_empty_seek_hack(FDrive *drv)
219 {
220 drv->last_sect = 0xFF;
221 drv->max_track = 0xFF;
222 }
223
224 static void fd_init(FDrive *drv)
225 {
226 /* Drive */
227 drv->perpendicular = 0;
228 /* Disk */
229 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
230 drv->last_sect = 0;
231 drv->max_track = 0;
232 drv->ro = true;
233 drv->media_changed = 1;
234 }
235
236 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
237
238 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
239 uint8_t last_sect, uint8_t num_sides)
240 {
241 return (((track * num_sides) + head) * last_sect) + sect - 1;
242 }
243
244 /* Returns current position, in sectors, for given drive */
245 static int fd_sector(FDrive *drv)
246 {
247 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
248 NUM_SIDES(drv));
249 }
250
251 /* Returns current position, in bytes, for given drive */
252 static int fd_offset(FDrive *drv)
253 {
254 g_assert(fd_sector(drv) < INT_MAX >> BDRV_SECTOR_BITS);
255 return fd_sector(drv) << BDRV_SECTOR_BITS;
256 }
257
258 /* Seek to a new position:
259 * returns 0 if already on right track
260 * returns 1 if track changed
261 * returns 2 if track is invalid
262 * returns 3 if sector is invalid
263 * returns 4 if seek is disabled
264 */
265 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
266 int enable_seek)
267 {
268 uint32_t sector;
269 int ret;
270
271 if (track > drv->max_track ||
272 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
273 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
274 head, track, sect, 1,
275 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
276 drv->max_track, drv->last_sect);
277 return 2;
278 }
279 if (sect > drv->last_sect) {
280 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
281 head, track, sect, 1,
282 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
283 drv->max_track, drv->last_sect);
284 return 3;
285 }
286 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
287 ret = 0;
288 if (sector != fd_sector(drv)) {
289 #if 0
290 if (!enable_seek) {
291 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
292 " (max=%d %02x %02x)\n",
293 head, track, sect, 1, drv->max_track,
294 drv->last_sect);
295 return 4;
296 }
297 #endif
298 drv->head = head;
299 if (drv->track != track) {
300 if (drv->blk != NULL && blk_is_inserted(drv->blk)) {
301 drv->media_changed = 0;
302 }
303 ret = 1;
304 }
305 drv->track = track;
306 drv->sect = sect;
307 }
308
309 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) {
310 ret = 2;
311 }
312
313 return ret;
314 }
315
316 /* Set drive back to track 0 */
317 static void fd_recalibrate(FDrive *drv)
318 {
319 FLOPPY_DPRINTF("recalibrate\n");
320 fd_seek(drv, 0, 0, 1, 1);
321 }
322
323 /**
324 * Determine geometry based on inserted diskette.
325 * Will not operate on an empty drive.
326 *
327 * @return: 0 on success, -1 if the drive is empty.
328 */
329 static int pick_geometry(FDrive *drv)
330 {
331 BlockBackend *blk = drv->blk;
332 const FDFormat *parse;
333 uint64_t nb_sectors, size;
334 int i;
335 int match, size_match, type_match;
336 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO;
337
338 /* We can only pick a geometry if we have a diskette. */
339 if (!drv->blk || !blk_is_inserted(drv->blk) ||
340 drv->drive == FLOPPY_DRIVE_TYPE_NONE)
341 {
342 return -1;
343 }
344
345 /* We need to determine the likely geometry of the inserted medium.
346 * In order of preference, we look for:
347 * (1) The same drive type and number of sectors,
348 * (2) The same diskette size and number of sectors,
349 * (3) The same drive type.
350 *
351 * In all cases, matches that occur higher in the drive table will take
352 * precedence over matches that occur later in the table.
353 */
354 blk_get_geometry(blk, &nb_sectors);
355 match = size_match = type_match = -1;
356 for (i = 0; ; i++) {
357 parse = &fd_formats[i];
358 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) {
359 break;
360 }
361 size = (parse->max_head + 1) * parse->max_track * parse->last_sect;
362 if (nb_sectors == size) {
363 if (magic || parse->drive == drv->drive) {
364 /* (1) perfect match -- nb_sectors and drive type */
365 goto out;
366 } else if (drive_size(parse->drive) == drive_size(drv->drive)) {
367 /* (2) size match -- nb_sectors and physical medium size */
368 match = (match == -1) ? i : match;
369 } else {
370 /* This is suspicious -- Did the user misconfigure? */
371 size_match = (size_match == -1) ? i : size_match;
372 }
373 } else if (type_match == -1) {
374 if ((parse->drive == drv->drive) ||
375 (magic && (parse->drive == get_fallback_drive_type(drv)))) {
376 /* (3) type match -- nb_sectors mismatch, but matches the type
377 * specified explicitly by the user, or matches the fallback
378 * default type when using the drive autodetect mechanism */
379 type_match = i;
380 }
381 }
382 }
383
384 /* No exact match found */
385 if (match == -1) {
386 if (size_match != -1) {
387 parse = &fd_formats[size_match];
388 FLOPPY_DPRINTF("User requested floppy drive type '%s', "
389 "but inserted medium appears to be a "
390 "%"PRId64" sector '%s' type\n",
391 FloppyDriveType_lookup[drv->drive],
392 nb_sectors,
393 FloppyDriveType_lookup[parse->drive]);
394 }
395 match = type_match;
396 }
397
398 /* No match of any kind found -- fd_format is misconfigured, abort. */
399 if (match == -1) {
400 error_setg(&error_abort, "No candidate geometries present in table "
401 " for floppy drive type '%s'",
402 FloppyDriveType_lookup[drv->drive]);
403 }
404
405 parse = &(fd_formats[match]);
406
407 out:
408 if (parse->max_head == 0) {
409 drv->flags &= ~FDISK_DBL_SIDES;
410 } else {
411 drv->flags |= FDISK_DBL_SIDES;
412 }
413 drv->max_track = parse->max_track;
414 drv->last_sect = parse->last_sect;
415 drv->disk = parse->drive;
416 drv->media_rate = parse->rate;
417 return 0;
418 }
419
420 static void pick_drive_type(FDrive *drv)
421 {
422 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) {
423 return;
424 }
425
426 if (pick_geometry(drv) == 0) {
427 drv->drive = drv->disk;
428 } else {
429 drv->drive = get_fallback_drive_type(drv);
430 }
431
432 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO);
433 }
434
435 /* Revalidate a disk drive after a disk change */
436 static void fd_revalidate(FDrive *drv)
437 {
438 int rc;
439
440 FLOPPY_DPRINTF("revalidate\n");
441 if (drv->blk != NULL) {
442 drv->ro = blk_is_read_only(drv->blk);
443 if (!blk_is_inserted(drv->blk)) {
444 FLOPPY_DPRINTF("No disk in drive\n");
445 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
446 fd_empty_seek_hack(drv);
447 } else if (!drv->media_validated) {
448 rc = pick_geometry(drv);
449 if (rc) {
450 FLOPPY_DPRINTF("Could not validate floppy drive media");
451 } else {
452 drv->media_validated = true;
453 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n",
454 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1,
455 drv->max_track, drv->last_sect,
456 drv->ro ? "ro" : "rw");
457 }
458 }
459 } else {
460 FLOPPY_DPRINTF("No drive connected\n");
461 drv->last_sect = 0;
462 drv->max_track = 0;
463 drv->flags &= ~FDISK_DBL_SIDES;
464 drv->drive = FLOPPY_DRIVE_TYPE_NONE;
465 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
466 }
467 }
468
469 /********************************************************/
470 /* Intel 82078 floppy disk controller emulation */
471
472 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
473 static void fdctrl_to_command_phase(FDCtrl *fdctrl);
474 static int fdctrl_transfer_handler (void *opaque, int nchan,
475 int dma_pos, int dma_len);
476 static void fdctrl_raise_irq(FDCtrl *fdctrl);
477 static FDrive *get_cur_drv(FDCtrl *fdctrl);
478
479 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
480 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
481 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
482 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
483 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
484 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
485 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
486 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
487 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
488 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
489 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
490 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
491
492 enum {
493 FD_DIR_WRITE = 0,
494 FD_DIR_READ = 1,
495 FD_DIR_SCANE = 2,
496 FD_DIR_SCANL = 3,
497 FD_DIR_SCANH = 4,
498 FD_DIR_VERIFY = 5,
499 };
500
501 enum {
502 FD_STATE_MULTI = 0x01, /* multi track flag */
503 FD_STATE_FORMAT = 0x02, /* format flag */
504 };
505
506 enum {
507 FD_REG_SRA = 0x00,
508 FD_REG_SRB = 0x01,
509 FD_REG_DOR = 0x02,
510 FD_REG_TDR = 0x03,
511 FD_REG_MSR = 0x04,
512 FD_REG_DSR = 0x04,
513 FD_REG_FIFO = 0x05,
514 FD_REG_DIR = 0x07,
515 FD_REG_CCR = 0x07,
516 };
517
518 enum {
519 FD_CMD_READ_TRACK = 0x02,
520 FD_CMD_SPECIFY = 0x03,
521 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
522 FD_CMD_WRITE = 0x05,
523 FD_CMD_READ = 0x06,
524 FD_CMD_RECALIBRATE = 0x07,
525 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
526 FD_CMD_WRITE_DELETED = 0x09,
527 FD_CMD_READ_ID = 0x0a,
528 FD_CMD_READ_DELETED = 0x0c,
529 FD_CMD_FORMAT_TRACK = 0x0d,
530 FD_CMD_DUMPREG = 0x0e,
531 FD_CMD_SEEK = 0x0f,
532 FD_CMD_VERSION = 0x10,
533 FD_CMD_SCAN_EQUAL = 0x11,
534 FD_CMD_PERPENDICULAR_MODE = 0x12,
535 FD_CMD_CONFIGURE = 0x13,
536 FD_CMD_LOCK = 0x14,
537 FD_CMD_VERIFY = 0x16,
538 FD_CMD_POWERDOWN_MODE = 0x17,
539 FD_CMD_PART_ID = 0x18,
540 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
541 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
542 FD_CMD_SAVE = 0x2e,
543 FD_CMD_OPTION = 0x33,
544 FD_CMD_RESTORE = 0x4e,
545 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
546 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
547 FD_CMD_FORMAT_AND_WRITE = 0xcd,
548 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
549 };
550
551 enum {
552 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
553 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
554 FD_CONFIG_POLL = 0x10, /* Poll enabled */
555 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
556 FD_CONFIG_EIS = 0x40, /* No implied seeks */
557 };
558
559 enum {
560 FD_SR0_DS0 = 0x01,
561 FD_SR0_DS1 = 0x02,
562 FD_SR0_HEAD = 0x04,
563 FD_SR0_EQPMT = 0x10,
564 FD_SR0_SEEK = 0x20,
565 FD_SR0_ABNTERM = 0x40,
566 FD_SR0_INVCMD = 0x80,
567 FD_SR0_RDYCHG = 0xc0,
568 };
569
570 enum {
571 FD_SR1_MA = 0x01, /* Missing address mark */
572 FD_SR1_NW = 0x02, /* Not writable */
573 FD_SR1_EC = 0x80, /* End of cylinder */
574 };
575
576 enum {
577 FD_SR2_SNS = 0x04, /* Scan not satisfied */
578 FD_SR2_SEH = 0x08, /* Scan equal hit */
579 };
580
581 enum {
582 FD_SRA_DIR = 0x01,
583 FD_SRA_nWP = 0x02,
584 FD_SRA_nINDX = 0x04,
585 FD_SRA_HDSEL = 0x08,
586 FD_SRA_nTRK0 = 0x10,
587 FD_SRA_STEP = 0x20,
588 FD_SRA_nDRV2 = 0x40,
589 FD_SRA_INTPEND = 0x80,
590 };
591
592 enum {
593 FD_SRB_MTR0 = 0x01,
594 FD_SRB_MTR1 = 0x02,
595 FD_SRB_WGATE = 0x04,
596 FD_SRB_RDATA = 0x08,
597 FD_SRB_WDATA = 0x10,
598 FD_SRB_DR0 = 0x20,
599 };
600
601 enum {
602 #if MAX_FD == 4
603 FD_DOR_SELMASK = 0x03,
604 #else
605 FD_DOR_SELMASK = 0x01,
606 #endif
607 FD_DOR_nRESET = 0x04,
608 FD_DOR_DMAEN = 0x08,
609 FD_DOR_MOTEN0 = 0x10,
610 FD_DOR_MOTEN1 = 0x20,
611 FD_DOR_MOTEN2 = 0x40,
612 FD_DOR_MOTEN3 = 0x80,
613 };
614
615 enum {
616 #if MAX_FD == 4
617 FD_TDR_BOOTSEL = 0x0c,
618 #else
619 FD_TDR_BOOTSEL = 0x04,
620 #endif
621 };
622
623 enum {
624 FD_DSR_DRATEMASK= 0x03,
625 FD_DSR_PWRDOWN = 0x40,
626 FD_DSR_SWRESET = 0x80,
627 };
628
629 enum {
630 FD_MSR_DRV0BUSY = 0x01,
631 FD_MSR_DRV1BUSY = 0x02,
632 FD_MSR_DRV2BUSY = 0x04,
633 FD_MSR_DRV3BUSY = 0x08,
634 FD_MSR_CMDBUSY = 0x10,
635 FD_MSR_NONDMA = 0x20,
636 FD_MSR_DIO = 0x40,
637 FD_MSR_RQM = 0x80,
638 };
639
640 enum {
641 FD_DIR_DSKCHG = 0x80,
642 };
643
644 /*
645 * See chapter 5.0 "Controller phases" of the spec:
646 *
647 * Command phase:
648 * The host writes a command and its parameters into the FIFO. The command
649 * phase is completed when all parameters for the command have been supplied,
650 * and execution phase is entered.
651 *
652 * Execution phase:
653 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
654 * contains the payload now, otherwise it's unused. When all bytes of the
655 * required data have been transferred, the state is switched to either result
656 * phase (if the command produces status bytes) or directly back into the
657 * command phase for the next command.
658 *
659 * Result phase:
660 * The host reads out the FIFO, which contains one or more result bytes now.
661 */
662 enum {
663 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
664 FD_PHASE_RECONSTRUCT = 0,
665
666 FD_PHASE_COMMAND = 1,
667 FD_PHASE_EXECUTION = 2,
668 FD_PHASE_RESULT = 3,
669 };
670
671 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
672 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
673
674 struct FDCtrl {
675 MemoryRegion iomem;
676 qemu_irq irq;
677 /* Controller state */
678 QEMUTimer *result_timer;
679 int dma_chann;
680 uint8_t phase;
681 IsaDma *dma;
682 /* Controller's identification */
683 uint8_t version;
684 /* HW */
685 uint8_t sra;
686 uint8_t srb;
687 uint8_t dor;
688 uint8_t dor_vmstate; /* only used as temp during vmstate */
689 uint8_t tdr;
690 uint8_t dsr;
691 uint8_t msr;
692 uint8_t cur_drv;
693 uint8_t status0;
694 uint8_t status1;
695 uint8_t status2;
696 /* Command FIFO */
697 uint8_t *fifo;
698 int32_t fifo_size;
699 uint32_t data_pos;
700 uint32_t data_len;
701 uint8_t data_state;
702 uint8_t data_dir;
703 uint8_t eot; /* last wanted sector */
704 /* States kept only to be returned back */
705 /* precompensation */
706 uint8_t precomp_trk;
707 uint8_t config;
708 uint8_t lock;
709 /* Power down config (also with status regB access mode */
710 uint8_t pwrd;
711 /* Floppy drives */
712 FloppyBus bus;
713 uint8_t num_floppies;
714 FDrive drives[MAX_FD];
715 int reset_sensei;
716 uint32_t check_media_rate;
717 FloppyDriveType fallback; /* type=auto failure fallback */
718 /* Timers state */
719 uint8_t timer0;
720 uint8_t timer1;
721 PortioList portio_list;
722 };
723
724 static FloppyDriveType get_fallback_drive_type(FDrive *drv)
725 {
726 return drv->fdctrl->fallback;
727 }
728
729 #define TYPE_SYSBUS_FDC "base-sysbus-fdc"
730 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
731
732 typedef struct FDCtrlSysBus {
733 /*< private >*/
734 SysBusDevice parent_obj;
735 /*< public >*/
736
737 struct FDCtrl state;
738 } FDCtrlSysBus;
739
740 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
741
742 typedef struct FDCtrlISABus {
743 ISADevice parent_obj;
744
745 uint32_t iobase;
746 uint32_t irq;
747 uint32_t dma;
748 struct FDCtrl state;
749 int32_t bootindexA;
750 int32_t bootindexB;
751 } FDCtrlISABus;
752
753 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
754 {
755 FDCtrl *fdctrl = opaque;
756 uint32_t retval;
757
758 reg &= 7;
759 switch (reg) {
760 case FD_REG_SRA:
761 retval = fdctrl_read_statusA(fdctrl);
762 break;
763 case FD_REG_SRB:
764 retval = fdctrl_read_statusB(fdctrl);
765 break;
766 case FD_REG_DOR:
767 retval = fdctrl_read_dor(fdctrl);
768 break;
769 case FD_REG_TDR:
770 retval = fdctrl_read_tape(fdctrl);
771 break;
772 case FD_REG_MSR:
773 retval = fdctrl_read_main_status(fdctrl);
774 break;
775 case FD_REG_FIFO:
776 retval = fdctrl_read_data(fdctrl);
777 break;
778 case FD_REG_DIR:
779 retval = fdctrl_read_dir(fdctrl);
780 break;
781 default:
782 retval = (uint32_t)(-1);
783 break;
784 }
785 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
786
787 return retval;
788 }
789
790 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
791 {
792 FDCtrl *fdctrl = opaque;
793
794 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
795
796 reg &= 7;
797 switch (reg) {
798 case FD_REG_DOR:
799 fdctrl_write_dor(fdctrl, value);
800 break;
801 case FD_REG_TDR:
802 fdctrl_write_tape(fdctrl, value);
803 break;
804 case FD_REG_DSR:
805 fdctrl_write_rate(fdctrl, value);
806 break;
807 case FD_REG_FIFO:
808 fdctrl_write_data(fdctrl, value);
809 break;
810 case FD_REG_CCR:
811 fdctrl_write_ccr(fdctrl, value);
812 break;
813 default:
814 break;
815 }
816 }
817
818 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
819 unsigned ize)
820 {
821 return fdctrl_read(opaque, (uint32_t)reg);
822 }
823
824 static void fdctrl_write_mem (void *opaque, hwaddr reg,
825 uint64_t value, unsigned size)
826 {
827 fdctrl_write(opaque, (uint32_t)reg, value);
828 }
829
830 static const MemoryRegionOps fdctrl_mem_ops = {
831 .read = fdctrl_read_mem,
832 .write = fdctrl_write_mem,
833 .endianness = DEVICE_NATIVE_ENDIAN,
834 };
835
836 static const MemoryRegionOps fdctrl_mem_strict_ops = {
837 .read = fdctrl_read_mem,
838 .write = fdctrl_write_mem,
839 .endianness = DEVICE_NATIVE_ENDIAN,
840 .valid = {
841 .min_access_size = 1,
842 .max_access_size = 1,
843 },
844 };
845
846 static bool fdrive_media_changed_needed(void *opaque)
847 {
848 FDrive *drive = opaque;
849
850 return (drive->blk != NULL && drive->media_changed != 1);
851 }
852
853 static const VMStateDescription vmstate_fdrive_media_changed = {
854 .name = "fdrive/media_changed",
855 .version_id = 1,
856 .minimum_version_id = 1,
857 .needed = fdrive_media_changed_needed,
858 .fields = (VMStateField[]) {
859 VMSTATE_UINT8(media_changed, FDrive),
860 VMSTATE_END_OF_LIST()
861 }
862 };
863
864 static bool fdrive_media_rate_needed(void *opaque)
865 {
866 FDrive *drive = opaque;
867
868 return drive->fdctrl->check_media_rate;
869 }
870
871 static const VMStateDescription vmstate_fdrive_media_rate = {
872 .name = "fdrive/media_rate",
873 .version_id = 1,
874 .minimum_version_id = 1,
875 .needed = fdrive_media_rate_needed,
876 .fields = (VMStateField[]) {
877 VMSTATE_UINT8(media_rate, FDrive),
878 VMSTATE_END_OF_LIST()
879 }
880 };
881
882 static bool fdrive_perpendicular_needed(void *opaque)
883 {
884 FDrive *drive = opaque;
885
886 return drive->perpendicular != 0;
887 }
888
889 static const VMStateDescription vmstate_fdrive_perpendicular = {
890 .name = "fdrive/perpendicular",
891 .version_id = 1,
892 .minimum_version_id = 1,
893 .needed = fdrive_perpendicular_needed,
894 .fields = (VMStateField[]) {
895 VMSTATE_UINT8(perpendicular, FDrive),
896 VMSTATE_END_OF_LIST()
897 }
898 };
899
900 static int fdrive_post_load(void *opaque, int version_id)
901 {
902 fd_revalidate(opaque);
903 return 0;
904 }
905
906 static const VMStateDescription vmstate_fdrive = {
907 .name = "fdrive",
908 .version_id = 1,
909 .minimum_version_id = 1,
910 .post_load = fdrive_post_load,
911 .fields = (VMStateField[]) {
912 VMSTATE_UINT8(head, FDrive),
913 VMSTATE_UINT8(track, FDrive),
914 VMSTATE_UINT8(sect, FDrive),
915 VMSTATE_END_OF_LIST()
916 },
917 .subsections = (const VMStateDescription*[]) {
918 &vmstate_fdrive_media_changed,
919 &vmstate_fdrive_media_rate,
920 &vmstate_fdrive_perpendicular,
921 NULL
922 }
923 };
924
925 /*
926 * Reconstructs the phase from register values according to the logic that was
927 * implemented in qemu 2.3. This is the default value that is used if the phase
928 * subsection is not present on migration.
929 *
930 * Don't change this function to reflect newer qemu versions, it is part of
931 * the migration ABI.
932 */
933 static int reconstruct_phase(FDCtrl *fdctrl)
934 {
935 if (fdctrl->msr & FD_MSR_NONDMA) {
936 return FD_PHASE_EXECUTION;
937 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
938 /* qemu 2.3 disabled RQM only during DMA transfers */
939 return FD_PHASE_EXECUTION;
940 } else if (fdctrl->msr & FD_MSR_DIO) {
941 return FD_PHASE_RESULT;
942 } else {
943 return FD_PHASE_COMMAND;
944 }
945 }
946
947 static void fdc_pre_save(void *opaque)
948 {
949 FDCtrl *s = opaque;
950
951 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
952 }
953
954 static int fdc_pre_load(void *opaque)
955 {
956 FDCtrl *s = opaque;
957 s->phase = FD_PHASE_RECONSTRUCT;
958 return 0;
959 }
960
961 static int fdc_post_load(void *opaque, int version_id)
962 {
963 FDCtrl *s = opaque;
964
965 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
966 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
967
968 if (s->phase == FD_PHASE_RECONSTRUCT) {
969 s->phase = reconstruct_phase(s);
970 }
971
972 return 0;
973 }
974
975 static bool fdc_reset_sensei_needed(void *opaque)
976 {
977 FDCtrl *s = opaque;
978
979 return s->reset_sensei != 0;
980 }
981
982 static const VMStateDescription vmstate_fdc_reset_sensei = {
983 .name = "fdc/reset_sensei",
984 .version_id = 1,
985 .minimum_version_id = 1,
986 .needed = fdc_reset_sensei_needed,
987 .fields = (VMStateField[]) {
988 VMSTATE_INT32(reset_sensei, FDCtrl),
989 VMSTATE_END_OF_LIST()
990 }
991 };
992
993 static bool fdc_result_timer_needed(void *opaque)
994 {
995 FDCtrl *s = opaque;
996
997 return timer_pending(s->result_timer);
998 }
999
1000 static const VMStateDescription vmstate_fdc_result_timer = {
1001 .name = "fdc/result_timer",
1002 .version_id = 1,
1003 .minimum_version_id = 1,
1004 .needed = fdc_result_timer_needed,
1005 .fields = (VMStateField[]) {
1006 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
1007 VMSTATE_END_OF_LIST()
1008 }
1009 };
1010
1011 static bool fdc_phase_needed(void *opaque)
1012 {
1013 FDCtrl *fdctrl = opaque;
1014
1015 return reconstruct_phase(fdctrl) != fdctrl->phase;
1016 }
1017
1018 static const VMStateDescription vmstate_fdc_phase = {
1019 .name = "fdc/phase",
1020 .version_id = 1,
1021 .minimum_version_id = 1,
1022 .needed = fdc_phase_needed,
1023 .fields = (VMStateField[]) {
1024 VMSTATE_UINT8(phase, FDCtrl),
1025 VMSTATE_END_OF_LIST()
1026 }
1027 };
1028
1029 static const VMStateDescription vmstate_fdc = {
1030 .name = "fdc",
1031 .version_id = 2,
1032 .minimum_version_id = 2,
1033 .pre_save = fdc_pre_save,
1034 .pre_load = fdc_pre_load,
1035 .post_load = fdc_post_load,
1036 .fields = (VMStateField[]) {
1037 /* Controller State */
1038 VMSTATE_UINT8(sra, FDCtrl),
1039 VMSTATE_UINT8(srb, FDCtrl),
1040 VMSTATE_UINT8(dor_vmstate, FDCtrl),
1041 VMSTATE_UINT8(tdr, FDCtrl),
1042 VMSTATE_UINT8(dsr, FDCtrl),
1043 VMSTATE_UINT8(msr, FDCtrl),
1044 VMSTATE_UINT8(status0, FDCtrl),
1045 VMSTATE_UINT8(status1, FDCtrl),
1046 VMSTATE_UINT8(status2, FDCtrl),
1047 /* Command FIFO */
1048 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
1049 uint8_t),
1050 VMSTATE_UINT32(data_pos, FDCtrl),
1051 VMSTATE_UINT32(data_len, FDCtrl),
1052 VMSTATE_UINT8(data_state, FDCtrl),
1053 VMSTATE_UINT8(data_dir, FDCtrl),
1054 VMSTATE_UINT8(eot, FDCtrl),
1055 /* States kept only to be returned back */
1056 VMSTATE_UINT8(timer0, FDCtrl),
1057 VMSTATE_UINT8(timer1, FDCtrl),
1058 VMSTATE_UINT8(precomp_trk, FDCtrl),
1059 VMSTATE_UINT8(config, FDCtrl),
1060 VMSTATE_UINT8(lock, FDCtrl),
1061 VMSTATE_UINT8(pwrd, FDCtrl),
1062 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
1063 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
1064 vmstate_fdrive, FDrive),
1065 VMSTATE_END_OF_LIST()
1066 },
1067 .subsections = (const VMStateDescription*[]) {
1068 &vmstate_fdc_reset_sensei,
1069 &vmstate_fdc_result_timer,
1070 &vmstate_fdc_phase,
1071 NULL
1072 }
1073 };
1074
1075 static void fdctrl_external_reset_sysbus(DeviceState *d)
1076 {
1077 FDCtrlSysBus *sys = SYSBUS_FDC(d);
1078 FDCtrl *s = &sys->state;
1079
1080 fdctrl_reset(s, 0);
1081 }
1082
1083 static void fdctrl_external_reset_isa(DeviceState *d)
1084 {
1085 FDCtrlISABus *isa = ISA_FDC(d);
1086 FDCtrl *s = &isa->state;
1087
1088 fdctrl_reset(s, 0);
1089 }
1090
1091 static void fdctrl_handle_tc(void *opaque, int irq, int level)
1092 {
1093 //FDCtrl *s = opaque;
1094
1095 if (level) {
1096 // XXX
1097 FLOPPY_DPRINTF("TC pulsed\n");
1098 }
1099 }
1100
1101 /* Change IRQ state */
1102 static void fdctrl_reset_irq(FDCtrl *fdctrl)
1103 {
1104 fdctrl->status0 = 0;
1105 if (!(fdctrl->sra & FD_SRA_INTPEND))
1106 return;
1107 FLOPPY_DPRINTF("Reset interrupt\n");
1108 qemu_set_irq(fdctrl->irq, 0);
1109 fdctrl->sra &= ~FD_SRA_INTPEND;
1110 }
1111
1112 static void fdctrl_raise_irq(FDCtrl *fdctrl)
1113 {
1114 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1115 qemu_set_irq(fdctrl->irq, 1);
1116 fdctrl->sra |= FD_SRA_INTPEND;
1117 }
1118
1119 fdctrl->reset_sensei = 0;
1120 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
1121 }
1122
1123 /* Reset controller */
1124 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
1125 {
1126 int i;
1127
1128 FLOPPY_DPRINTF("reset controller\n");
1129 fdctrl_reset_irq(fdctrl);
1130 /* Initialise controller */
1131 fdctrl->sra = 0;
1132 fdctrl->srb = 0xc0;
1133 if (!fdctrl->drives[1].blk) {
1134 fdctrl->sra |= FD_SRA_nDRV2;
1135 }
1136 fdctrl->cur_drv = 0;
1137 fdctrl->dor = FD_DOR_nRESET;
1138 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
1139 fdctrl->msr = FD_MSR_RQM;
1140 fdctrl->reset_sensei = 0;
1141 timer_del(fdctrl->result_timer);
1142 /* FIFO state */
1143 fdctrl->data_pos = 0;
1144 fdctrl->data_len = 0;
1145 fdctrl->data_state = 0;
1146 fdctrl->data_dir = FD_DIR_WRITE;
1147 for (i = 0; i < MAX_FD; i++)
1148 fd_recalibrate(&fdctrl->drives[i]);
1149 fdctrl_to_command_phase(fdctrl);
1150 if (do_irq) {
1151 fdctrl->status0 |= FD_SR0_RDYCHG;
1152 fdctrl_raise_irq(fdctrl);
1153 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
1154 }
1155 }
1156
1157 static inline FDrive *drv0(FDCtrl *fdctrl)
1158 {
1159 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
1160 }
1161
1162 static inline FDrive *drv1(FDCtrl *fdctrl)
1163 {
1164 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1165 return &fdctrl->drives[1];
1166 else
1167 return &fdctrl->drives[0];
1168 }
1169
1170 #if MAX_FD == 4
1171 static inline FDrive *drv2(FDCtrl *fdctrl)
1172 {
1173 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1174 return &fdctrl->drives[2];
1175 else
1176 return &fdctrl->drives[1];
1177 }
1178
1179 static inline FDrive *drv3(FDCtrl *fdctrl)
1180 {
1181 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1182 return &fdctrl->drives[3];
1183 else
1184 return &fdctrl->drives[2];
1185 }
1186 #endif
1187
1188 static FDrive *get_cur_drv(FDCtrl *fdctrl)
1189 {
1190 switch (fdctrl->cur_drv) {
1191 case 0: return drv0(fdctrl);
1192 case 1: return drv1(fdctrl);
1193 #if MAX_FD == 4
1194 case 2: return drv2(fdctrl);
1195 case 3: return drv3(fdctrl);
1196 #endif
1197 default: return NULL;
1198 }
1199 }
1200
1201 /* Status A register : 0x00 (read-only) */
1202 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
1203 {
1204 uint32_t retval = fdctrl->sra;
1205
1206 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1207
1208 return retval;
1209 }
1210
1211 /* Status B register : 0x01 (read-only) */
1212 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
1213 {
1214 uint32_t retval = fdctrl->srb;
1215
1216 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1217
1218 return retval;
1219 }
1220
1221 /* Digital output register : 0x02 */
1222 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
1223 {
1224 uint32_t retval = fdctrl->dor;
1225
1226 /* Selected drive */
1227 retval |= fdctrl->cur_drv;
1228 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1229
1230 return retval;
1231 }
1232
1233 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
1234 {
1235 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
1236
1237 /* Motors */
1238 if (value & FD_DOR_MOTEN0)
1239 fdctrl->srb |= FD_SRB_MTR0;
1240 else
1241 fdctrl->srb &= ~FD_SRB_MTR0;
1242 if (value & FD_DOR_MOTEN1)
1243 fdctrl->srb |= FD_SRB_MTR1;
1244 else
1245 fdctrl->srb &= ~FD_SRB_MTR1;
1246
1247 /* Drive */
1248 if (value & 1)
1249 fdctrl->srb |= FD_SRB_DR0;
1250 else
1251 fdctrl->srb &= ~FD_SRB_DR0;
1252
1253 /* Reset */
1254 if (!(value & FD_DOR_nRESET)) {
1255 if (fdctrl->dor & FD_DOR_nRESET) {
1256 FLOPPY_DPRINTF("controller enter RESET state\n");
1257 }
1258 } else {
1259 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1260 FLOPPY_DPRINTF("controller out of RESET state\n");
1261 fdctrl_reset(fdctrl, 1);
1262 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1263 }
1264 }
1265 /* Selected drive */
1266 fdctrl->cur_drv = value & FD_DOR_SELMASK;
1267
1268 fdctrl->dor = value;
1269 }
1270
1271 /* Tape drive register : 0x03 */
1272 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
1273 {
1274 uint32_t retval = fdctrl->tdr;
1275
1276 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1277
1278 return retval;
1279 }
1280
1281 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
1282 {
1283 /* Reset mode */
1284 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1285 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1286 return;
1287 }
1288 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1289 /* Disk boot selection indicator */
1290 fdctrl->tdr = value & FD_TDR_BOOTSEL;
1291 /* Tape indicators: never allow */
1292 }
1293
1294 /* Main status register : 0x04 (read) */
1295 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
1296 {
1297 uint32_t retval = fdctrl->msr;
1298
1299 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1300 fdctrl->dor |= FD_DOR_nRESET;
1301
1302 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1303
1304 return retval;
1305 }
1306
1307 /* Data select rate register : 0x04 (write) */
1308 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
1309 {
1310 /* Reset mode */
1311 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1312 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1313 return;
1314 }
1315 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1316 /* Reset: autoclear */
1317 if (value & FD_DSR_SWRESET) {
1318 fdctrl->dor &= ~FD_DOR_nRESET;
1319 fdctrl_reset(fdctrl, 1);
1320 fdctrl->dor |= FD_DOR_nRESET;
1321 }
1322 if (value & FD_DSR_PWRDOWN) {
1323 fdctrl_reset(fdctrl, 1);
1324 }
1325 fdctrl->dsr = value;
1326 }
1327
1328 /* Configuration control register: 0x07 (write) */
1329 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1330 {
1331 /* Reset mode */
1332 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1333 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1334 return;
1335 }
1336 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1337
1338 /* Only the rate selection bits used in AT mode, and we
1339 * store those in the DSR.
1340 */
1341 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1342 (value & FD_DSR_DRATEMASK);
1343 }
1344
1345 static int fdctrl_media_changed(FDrive *drv)
1346 {
1347 return drv->media_changed;
1348 }
1349
1350 /* Digital input register : 0x07 (read-only) */
1351 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
1352 {
1353 uint32_t retval = 0;
1354
1355 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
1356 retval |= FD_DIR_DSKCHG;
1357 }
1358 if (retval != 0) {
1359 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1360 }
1361
1362 return retval;
1363 }
1364
1365 /* Clear the FIFO and update the state for receiving the next command */
1366 static void fdctrl_to_command_phase(FDCtrl *fdctrl)
1367 {
1368 fdctrl->phase = FD_PHASE_COMMAND;
1369 fdctrl->data_dir = FD_DIR_WRITE;
1370 fdctrl->data_pos = 0;
1371 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
1372 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1373 fdctrl->msr |= FD_MSR_RQM;
1374 }
1375
1376 /* Update the state to allow the guest to read out the command status.
1377 * @fifo_len is the number of result bytes to be read out. */
1378 static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
1379 {
1380 fdctrl->phase = FD_PHASE_RESULT;
1381 fdctrl->data_dir = FD_DIR_READ;
1382 fdctrl->data_len = fifo_len;
1383 fdctrl->data_pos = 0;
1384 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1385 }
1386
1387 /* Set an error: unimplemented/unknown command */
1388 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1389 {
1390 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1391 fdctrl->fifo[0]);
1392 fdctrl->fifo[0] = FD_SR0_INVCMD;
1393 fdctrl_to_result_phase(fdctrl, 1);
1394 }
1395
1396 /* Seek to next sector
1397 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1398 * otherwise returns 1
1399 */
1400 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1401 {
1402 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1403 cur_drv->head, cur_drv->track, cur_drv->sect,
1404 fd_sector(cur_drv));
1405 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1406 error in fact */
1407 uint8_t new_head = cur_drv->head;
1408 uint8_t new_track = cur_drv->track;
1409 uint8_t new_sect = cur_drv->sect;
1410
1411 int ret = 1;
1412
1413 if (new_sect >= cur_drv->last_sect ||
1414 new_sect == fdctrl->eot) {
1415 new_sect = 1;
1416 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1417 if (new_head == 0 &&
1418 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1419 new_head = 1;
1420 } else {
1421 new_head = 0;
1422 new_track++;
1423 fdctrl->status0 |= FD_SR0_SEEK;
1424 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1425 ret = 0;
1426 }
1427 }
1428 } else {
1429 fdctrl->status0 |= FD_SR0_SEEK;
1430 new_track++;
1431 ret = 0;
1432 }
1433 if (ret == 1) {
1434 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1435 new_head, new_track, new_sect, fd_sector(cur_drv));
1436 }
1437 } else {
1438 new_sect++;
1439 }
1440 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1441 return ret;
1442 }
1443
1444 /* Callback for transfer end (stop or abort) */
1445 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1446 uint8_t status1, uint8_t status2)
1447 {
1448 FDrive *cur_drv;
1449 cur_drv = get_cur_drv(fdctrl);
1450
1451 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1452 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1453 if (cur_drv->head) {
1454 fdctrl->status0 |= FD_SR0_HEAD;
1455 }
1456 fdctrl->status0 |= status0;
1457
1458 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1459 status0, status1, status2, fdctrl->status0);
1460 fdctrl->fifo[0] = fdctrl->status0;
1461 fdctrl->fifo[1] = status1;
1462 fdctrl->fifo[2] = status2;
1463 fdctrl->fifo[3] = cur_drv->track;
1464 fdctrl->fifo[4] = cur_drv->head;
1465 fdctrl->fifo[5] = cur_drv->sect;
1466 fdctrl->fifo[6] = FD_SECTOR_SC;
1467 fdctrl->data_dir = FD_DIR_READ;
1468 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1469 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1470 k->release_DREQ(fdctrl->dma, fdctrl->dma_chann);
1471 }
1472 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1473 fdctrl->msr &= ~FD_MSR_NONDMA;
1474
1475 fdctrl_to_result_phase(fdctrl, 7);
1476 fdctrl_raise_irq(fdctrl);
1477 }
1478
1479 /* Prepare a data transfer (either DMA or FIFO) */
1480 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1481 {
1482 FDrive *cur_drv;
1483 uint8_t kh, kt, ks;
1484
1485 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1486 cur_drv = get_cur_drv(fdctrl);
1487 kt = fdctrl->fifo[2];
1488 kh = fdctrl->fifo[3];
1489 ks = fdctrl->fifo[4];
1490 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1491 GET_CUR_DRV(fdctrl), kh, kt, ks,
1492 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1493 NUM_SIDES(cur_drv)));
1494 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1495 case 2:
1496 /* sect too big */
1497 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1498 fdctrl->fifo[3] = kt;
1499 fdctrl->fifo[4] = kh;
1500 fdctrl->fifo[5] = ks;
1501 return;
1502 case 3:
1503 /* track too big */
1504 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1505 fdctrl->fifo[3] = kt;
1506 fdctrl->fifo[4] = kh;
1507 fdctrl->fifo[5] = ks;
1508 return;
1509 case 4:
1510 /* No seek enabled */
1511 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1512 fdctrl->fifo[3] = kt;
1513 fdctrl->fifo[4] = kh;
1514 fdctrl->fifo[5] = ks;
1515 return;
1516 case 1:
1517 fdctrl->status0 |= FD_SR0_SEEK;
1518 break;
1519 default:
1520 break;
1521 }
1522
1523 /* Check the data rate. If the programmed data rate does not match
1524 * the currently inserted medium, the operation has to fail. */
1525 if (fdctrl->check_media_rate &&
1526 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1527 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1528 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1529 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1530 fdctrl->fifo[3] = kt;
1531 fdctrl->fifo[4] = kh;
1532 fdctrl->fifo[5] = ks;
1533 return;
1534 }
1535
1536 /* Set the FIFO state */
1537 fdctrl->data_dir = direction;
1538 fdctrl->data_pos = 0;
1539 assert(fdctrl->msr & FD_MSR_CMDBUSY);
1540 if (fdctrl->fifo[0] & 0x80)
1541 fdctrl->data_state |= FD_STATE_MULTI;
1542 else
1543 fdctrl->data_state &= ~FD_STATE_MULTI;
1544 if (fdctrl->fifo[5] == 0) {
1545 fdctrl->data_len = fdctrl->fifo[8];
1546 } else {
1547 int tmp;
1548 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1549 tmp = (fdctrl->fifo[6] - ks + 1);
1550 if (fdctrl->fifo[0] & 0x80)
1551 tmp += fdctrl->fifo[6];
1552 fdctrl->data_len *= tmp;
1553 }
1554 fdctrl->eot = fdctrl->fifo[6];
1555 if (fdctrl->dor & FD_DOR_DMAEN) {
1556 IsaDmaTransferMode dma_mode;
1557 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1558 bool dma_mode_ok;
1559 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1560 dma_mode = k->get_transfer_mode(fdctrl->dma, fdctrl->dma_chann);
1561 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1562 dma_mode, direction,
1563 (128 << fdctrl->fifo[5]) *
1564 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1565 switch (direction) {
1566 case FD_DIR_SCANE:
1567 case FD_DIR_SCANL:
1568 case FD_DIR_SCANH:
1569 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_VERIFY);
1570 break;
1571 case FD_DIR_WRITE:
1572 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_WRITE);
1573 break;
1574 case FD_DIR_READ:
1575 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_READ);
1576 break;
1577 case FD_DIR_VERIFY:
1578 dma_mode_ok = true;
1579 break;
1580 default:
1581 dma_mode_ok = false;
1582 break;
1583 }
1584 if (dma_mode_ok) {
1585 /* No access is allowed until DMA transfer has completed */
1586 fdctrl->msr &= ~FD_MSR_RQM;
1587 if (direction != FD_DIR_VERIFY) {
1588 /* Now, we just have to wait for the DMA controller to
1589 * recall us...
1590 */
1591 k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann);
1592 k->schedule(fdctrl->dma);
1593 } else {
1594 /* Start transfer */
1595 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1596 fdctrl->data_len);
1597 }
1598 return;
1599 } else {
1600 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1601 direction);
1602 }
1603 }
1604 FLOPPY_DPRINTF("start non-DMA transfer\n");
1605 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
1606 if (direction != FD_DIR_WRITE)
1607 fdctrl->msr |= FD_MSR_DIO;
1608 /* IO based transfer: calculate len */
1609 fdctrl_raise_irq(fdctrl);
1610 }
1611
1612 /* Prepare a transfer of deleted data */
1613 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1614 {
1615 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
1616
1617 /* We don't handle deleted data,
1618 * so we don't return *ANYTHING*
1619 */
1620 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1621 }
1622
1623 /* handlers for DMA transfers */
1624 static int fdctrl_transfer_handler (void *opaque, int nchan,
1625 int dma_pos, int dma_len)
1626 {
1627 FDCtrl *fdctrl;
1628 FDrive *cur_drv;
1629 int len, start_pos, rel_pos;
1630 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1631 IsaDmaClass *k;
1632
1633 fdctrl = opaque;
1634 if (fdctrl->msr & FD_MSR_RQM) {
1635 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1636 return 0;
1637 }
1638 k = ISADMA_GET_CLASS(fdctrl->dma);
1639 cur_drv = get_cur_drv(fdctrl);
1640 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1641 fdctrl->data_dir == FD_DIR_SCANH)
1642 status2 = FD_SR2_SNS;
1643 if (dma_len > fdctrl->data_len)
1644 dma_len = fdctrl->data_len;
1645 if (cur_drv->blk == NULL) {
1646 if (fdctrl->data_dir == FD_DIR_WRITE)
1647 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1648 else
1649 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1650 len = 0;
1651 goto transfer_error;
1652 }
1653 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1654 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1655 len = dma_len - fdctrl->data_pos;
1656 if (len + rel_pos > FD_SECTOR_LEN)
1657 len = FD_SECTOR_LEN - rel_pos;
1658 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1659 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1660 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1661 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1662 fd_sector(cur_drv) * FD_SECTOR_LEN);
1663 if (fdctrl->data_dir != FD_DIR_WRITE ||
1664 len < FD_SECTOR_LEN || rel_pos != 0) {
1665 /* READ & SCAN commands and realign to a sector for WRITE */
1666 if (blk_pread(cur_drv->blk, fd_offset(cur_drv),
1667 fdctrl->fifo, BDRV_SECTOR_SIZE) < 0) {
1668 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1669 fd_sector(cur_drv));
1670 /* Sure, image size is too small... */
1671 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1672 }
1673 }
1674 switch (fdctrl->data_dir) {
1675 case FD_DIR_READ:
1676 /* READ commands */
1677 k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1678 fdctrl->data_pos, len);
1679 break;
1680 case FD_DIR_WRITE:
1681 /* WRITE commands */
1682 if (cur_drv->ro) {
1683 /* Handle readonly medium early, no need to do DMA, touch the
1684 * LED or attempt any writes. A real floppy doesn't attempt
1685 * to write to readonly media either. */
1686 fdctrl_stop_transfer(fdctrl,
1687 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1688 0x00);
1689 goto transfer_error;
1690 }
1691
1692 k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1693 fdctrl->data_pos, len);
1694 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv),
1695 fdctrl->fifo, BDRV_SECTOR_SIZE, 0) < 0) {
1696 FLOPPY_DPRINTF("error writing sector %d\n",
1697 fd_sector(cur_drv));
1698 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1699 goto transfer_error;
1700 }
1701 break;
1702 case FD_DIR_VERIFY:
1703 /* VERIFY commands */
1704 break;
1705 default:
1706 /* SCAN commands */
1707 {
1708 uint8_t tmpbuf[FD_SECTOR_LEN];
1709 int ret;
1710 k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos,
1711 len);
1712 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1713 if (ret == 0) {
1714 status2 = FD_SR2_SEH;
1715 goto end_transfer;
1716 }
1717 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1718 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1719 status2 = 0x00;
1720 goto end_transfer;
1721 }
1722 }
1723 break;
1724 }
1725 fdctrl->data_pos += len;
1726 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1727 if (rel_pos == 0) {
1728 /* Seek to next sector */
1729 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1730 break;
1731 }
1732 }
1733 end_transfer:
1734 len = fdctrl->data_pos - start_pos;
1735 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1736 fdctrl->data_pos, len, fdctrl->data_len);
1737 if (fdctrl->data_dir == FD_DIR_SCANE ||
1738 fdctrl->data_dir == FD_DIR_SCANL ||
1739 fdctrl->data_dir == FD_DIR_SCANH)
1740 status2 = FD_SR2_SEH;
1741 fdctrl->data_len -= len;
1742 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1743 transfer_error:
1744
1745 return len;
1746 }
1747
1748 /* Data register : 0x05 */
1749 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1750 {
1751 FDrive *cur_drv;
1752 uint32_t retval = 0;
1753 uint32_t pos;
1754
1755 cur_drv = get_cur_drv(fdctrl);
1756 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1757 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1758 FLOPPY_DPRINTF("error: controller not ready for reading\n");
1759 return 0;
1760 }
1761
1762 /* If data_len spans multiple sectors, the current position in the FIFO
1763 * wraps around while fdctrl->data_pos is the real position in the whole
1764 * request. */
1765 pos = fdctrl->data_pos;
1766 pos %= FD_SECTOR_LEN;
1767
1768 switch (fdctrl->phase) {
1769 case FD_PHASE_EXECUTION:
1770 assert(fdctrl->msr & FD_MSR_NONDMA);
1771 if (pos == 0) {
1772 if (fdctrl->data_pos != 0)
1773 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1774 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1775 fd_sector(cur_drv));
1776 return 0;
1777 }
1778 if (blk_pread(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1779 BDRV_SECTOR_SIZE)
1780 < 0) {
1781 FLOPPY_DPRINTF("error getting sector %d\n",
1782 fd_sector(cur_drv));
1783 /* Sure, image size is too small... */
1784 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1785 }
1786 }
1787
1788 if (++fdctrl->data_pos == fdctrl->data_len) {
1789 fdctrl->msr &= ~FD_MSR_RQM;
1790 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1791 }
1792 break;
1793
1794 case FD_PHASE_RESULT:
1795 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1796 if (++fdctrl->data_pos == fdctrl->data_len) {
1797 fdctrl->msr &= ~FD_MSR_RQM;
1798 fdctrl_to_command_phase(fdctrl);
1799 fdctrl_reset_irq(fdctrl);
1800 }
1801 break;
1802
1803 case FD_PHASE_COMMAND:
1804 default:
1805 abort();
1806 }
1807
1808 retval = fdctrl->fifo[pos];
1809 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1810
1811 return retval;
1812 }
1813
1814 static void fdctrl_format_sector(FDCtrl *fdctrl)
1815 {
1816 FDrive *cur_drv;
1817 uint8_t kh, kt, ks;
1818
1819 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1820 cur_drv = get_cur_drv(fdctrl);
1821 kt = fdctrl->fifo[6];
1822 kh = fdctrl->fifo[7];
1823 ks = fdctrl->fifo[8];
1824 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1825 GET_CUR_DRV(fdctrl), kh, kt, ks,
1826 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1827 NUM_SIDES(cur_drv)));
1828 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1829 case 2:
1830 /* sect too big */
1831 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1832 fdctrl->fifo[3] = kt;
1833 fdctrl->fifo[4] = kh;
1834 fdctrl->fifo[5] = ks;
1835 return;
1836 case 3:
1837 /* track too big */
1838 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1839 fdctrl->fifo[3] = kt;
1840 fdctrl->fifo[4] = kh;
1841 fdctrl->fifo[5] = ks;
1842 return;
1843 case 4:
1844 /* No seek enabled */
1845 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1846 fdctrl->fifo[3] = kt;
1847 fdctrl->fifo[4] = kh;
1848 fdctrl->fifo[5] = ks;
1849 return;
1850 case 1:
1851 fdctrl->status0 |= FD_SR0_SEEK;
1852 break;
1853 default:
1854 break;
1855 }
1856 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1857 if (cur_drv->blk == NULL ||
1858 blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1859 BDRV_SECTOR_SIZE, 0) < 0) {
1860 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
1861 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1862 } else {
1863 if (cur_drv->sect == cur_drv->last_sect) {
1864 fdctrl->data_state &= ~FD_STATE_FORMAT;
1865 /* Last sector done */
1866 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1867 } else {
1868 /* More to do */
1869 fdctrl->data_pos = 0;
1870 fdctrl->data_len = 4;
1871 }
1872 }
1873 }
1874
1875 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1876 {
1877 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1878 fdctrl->fifo[0] = fdctrl->lock << 4;
1879 fdctrl_to_result_phase(fdctrl, 1);
1880 }
1881
1882 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1883 {
1884 FDrive *cur_drv = get_cur_drv(fdctrl);
1885
1886 /* Drives position */
1887 fdctrl->fifo[0] = drv0(fdctrl)->track;
1888 fdctrl->fifo[1] = drv1(fdctrl)->track;
1889 #if MAX_FD == 4
1890 fdctrl->fifo[2] = drv2(fdctrl)->track;
1891 fdctrl->fifo[3] = drv3(fdctrl)->track;
1892 #else
1893 fdctrl->fifo[2] = 0;
1894 fdctrl->fifo[3] = 0;
1895 #endif
1896 /* timers */
1897 fdctrl->fifo[4] = fdctrl->timer0;
1898 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1899 fdctrl->fifo[6] = cur_drv->last_sect;
1900 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1901 (cur_drv->perpendicular << 2);
1902 fdctrl->fifo[8] = fdctrl->config;
1903 fdctrl->fifo[9] = fdctrl->precomp_trk;
1904 fdctrl_to_result_phase(fdctrl, 10);
1905 }
1906
1907 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1908 {
1909 /* Controller's version */
1910 fdctrl->fifo[0] = fdctrl->version;
1911 fdctrl_to_result_phase(fdctrl, 1);
1912 }
1913
1914 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1915 {
1916 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1917 fdctrl_to_result_phase(fdctrl, 1);
1918 }
1919
1920 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1921 {
1922 FDrive *cur_drv = get_cur_drv(fdctrl);
1923
1924 /* Drives position */
1925 drv0(fdctrl)->track = fdctrl->fifo[3];
1926 drv1(fdctrl)->track = fdctrl->fifo[4];
1927 #if MAX_FD == 4
1928 drv2(fdctrl)->track = fdctrl->fifo[5];
1929 drv3(fdctrl)->track = fdctrl->fifo[6];
1930 #endif
1931 /* timers */
1932 fdctrl->timer0 = fdctrl->fifo[7];
1933 fdctrl->timer1 = fdctrl->fifo[8];
1934 cur_drv->last_sect = fdctrl->fifo[9];
1935 fdctrl->lock = fdctrl->fifo[10] >> 7;
1936 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1937 fdctrl->config = fdctrl->fifo[11];
1938 fdctrl->precomp_trk = fdctrl->fifo[12];
1939 fdctrl->pwrd = fdctrl->fifo[13];
1940 fdctrl_to_command_phase(fdctrl);
1941 }
1942
1943 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1944 {
1945 FDrive *cur_drv = get_cur_drv(fdctrl);
1946
1947 fdctrl->fifo[0] = 0;
1948 fdctrl->fifo[1] = 0;
1949 /* Drives position */
1950 fdctrl->fifo[2] = drv0(fdctrl)->track;
1951 fdctrl->fifo[3] = drv1(fdctrl)->track;
1952 #if MAX_FD == 4
1953 fdctrl->fifo[4] = drv2(fdctrl)->track;
1954 fdctrl->fifo[5] = drv3(fdctrl)->track;
1955 #else
1956 fdctrl->fifo[4] = 0;
1957 fdctrl->fifo[5] = 0;
1958 #endif
1959 /* timers */
1960 fdctrl->fifo[6] = fdctrl->timer0;
1961 fdctrl->fifo[7] = fdctrl->timer1;
1962 fdctrl->fifo[8] = cur_drv->last_sect;
1963 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1964 (cur_drv->perpendicular << 2);
1965 fdctrl->fifo[10] = fdctrl->config;
1966 fdctrl->fifo[11] = fdctrl->precomp_trk;
1967 fdctrl->fifo[12] = fdctrl->pwrd;
1968 fdctrl->fifo[13] = 0;
1969 fdctrl->fifo[14] = 0;
1970 fdctrl_to_result_phase(fdctrl, 15);
1971 }
1972
1973 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1974 {
1975 FDrive *cur_drv = get_cur_drv(fdctrl);
1976
1977 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1978 timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1979 (NANOSECONDS_PER_SECOND / 50));
1980 }
1981
1982 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1983 {
1984 FDrive *cur_drv;
1985
1986 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1987 cur_drv = get_cur_drv(fdctrl);
1988 fdctrl->data_state |= FD_STATE_FORMAT;
1989 if (fdctrl->fifo[0] & 0x80)
1990 fdctrl->data_state |= FD_STATE_MULTI;
1991 else
1992 fdctrl->data_state &= ~FD_STATE_MULTI;
1993 cur_drv->bps =
1994 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1995 #if 0
1996 cur_drv->last_sect =
1997 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1998 fdctrl->fifo[3] / 2;
1999 #else
2000 cur_drv->last_sect = fdctrl->fifo[3];
2001 #endif
2002 /* TODO: implement format using DMA expected by the Bochs BIOS
2003 * and Linux fdformat (read 3 bytes per sector via DMA and fill
2004 * the sector with the specified fill byte
2005 */
2006 fdctrl->data_state &= ~FD_STATE_FORMAT;
2007 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2008 }
2009
2010 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
2011 {
2012 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
2013 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
2014 if (fdctrl->fifo[2] & 1)
2015 fdctrl->dor &= ~FD_DOR_DMAEN;
2016 else
2017 fdctrl->dor |= FD_DOR_DMAEN;
2018 /* No result back */
2019 fdctrl_to_command_phase(fdctrl);
2020 }
2021
2022 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
2023 {
2024 FDrive *cur_drv;
2025
2026 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2027 cur_drv = get_cur_drv(fdctrl);
2028 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
2029 /* 1 Byte status back */
2030 fdctrl->fifo[0] = (cur_drv->ro << 6) |
2031 (cur_drv->track == 0 ? 0x10 : 0x00) |
2032 (cur_drv->head << 2) |
2033 GET_CUR_DRV(fdctrl) |
2034 0x28;
2035 fdctrl_to_result_phase(fdctrl, 1);
2036 }
2037
2038 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
2039 {
2040 FDrive *cur_drv;
2041
2042 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2043 cur_drv = get_cur_drv(fdctrl);
2044 fd_recalibrate(cur_drv);
2045 fdctrl_to_command_phase(fdctrl);
2046 /* Raise Interrupt */
2047 fdctrl->status0 |= FD_SR0_SEEK;
2048 fdctrl_raise_irq(fdctrl);
2049 }
2050
2051 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
2052 {
2053 FDrive *cur_drv = get_cur_drv(fdctrl);
2054
2055 if (fdctrl->reset_sensei > 0) {
2056 fdctrl->fifo[0] =
2057 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
2058 fdctrl->reset_sensei--;
2059 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
2060 fdctrl->fifo[0] = FD_SR0_INVCMD;
2061 fdctrl_to_result_phase(fdctrl, 1);
2062 return;
2063 } else {
2064 fdctrl->fifo[0] =
2065 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
2066 | GET_CUR_DRV(fdctrl);
2067 }
2068
2069 fdctrl->fifo[1] = cur_drv->track;
2070 fdctrl_to_result_phase(fdctrl, 2);
2071 fdctrl_reset_irq(fdctrl);
2072 fdctrl->status0 = FD_SR0_RDYCHG;
2073 }
2074
2075 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
2076 {
2077 FDrive *cur_drv;
2078
2079 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2080 cur_drv = get_cur_drv(fdctrl);
2081 fdctrl_to_command_phase(fdctrl);
2082 /* The seek command just sends step pulses to the drive and doesn't care if
2083 * there is a medium inserted of if it's banging the head against the drive.
2084 */
2085 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
2086 /* Raise Interrupt */
2087 fdctrl->status0 |= FD_SR0_SEEK;
2088 fdctrl_raise_irq(fdctrl);
2089 }
2090
2091 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
2092 {
2093 FDrive *cur_drv = get_cur_drv(fdctrl);
2094
2095 if (fdctrl->fifo[1] & 0x80)
2096 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
2097 /* No result back */
2098 fdctrl_to_command_phase(fdctrl);
2099 }
2100
2101 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
2102 {
2103 fdctrl->config = fdctrl->fifo[2];
2104 fdctrl->precomp_trk = fdctrl->fifo[3];
2105 /* No result back */
2106 fdctrl_to_command_phase(fdctrl);
2107 }
2108
2109 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
2110 {
2111 fdctrl->pwrd = fdctrl->fifo[1];
2112 fdctrl->fifo[0] = fdctrl->fifo[1];
2113 fdctrl_to_result_phase(fdctrl, 1);
2114 }
2115
2116 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
2117 {
2118 /* No result back */
2119 fdctrl_to_command_phase(fdctrl);
2120 }
2121
2122 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
2123 {
2124 FDrive *cur_drv = get_cur_drv(fdctrl);
2125 uint32_t pos;
2126
2127 pos = fdctrl->data_pos - 1;
2128 pos %= FD_SECTOR_LEN;
2129 if (fdctrl->fifo[pos] & 0x80) {
2130 /* Command parameters done */
2131 if (fdctrl->fifo[pos] & 0x40) {
2132 fdctrl->fifo[0] = fdctrl->fifo[1];
2133 fdctrl->fifo[2] = 0;
2134 fdctrl->fifo[3] = 0;
2135 fdctrl_to_result_phase(fdctrl, 4);
2136 } else {
2137 fdctrl_to_command_phase(fdctrl);
2138 }
2139 } else if (fdctrl->data_len > 7) {
2140 /* ERROR */
2141 fdctrl->fifo[0] = 0x80 |
2142 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
2143 fdctrl_to_result_phase(fdctrl, 1);
2144 }
2145 }
2146
2147 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
2148 {
2149 FDrive *cur_drv;
2150
2151 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2152 cur_drv = get_cur_drv(fdctrl);
2153 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
2154 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
2155 cur_drv->sect, 1);
2156 } else {
2157 fd_seek(cur_drv, cur_drv->head,
2158 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
2159 }
2160 fdctrl_to_command_phase(fdctrl);
2161 /* Raise Interrupt */
2162 fdctrl->status0 |= FD_SR0_SEEK;
2163 fdctrl_raise_irq(fdctrl);
2164 }
2165
2166 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
2167 {
2168 FDrive *cur_drv;
2169
2170 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2171 cur_drv = get_cur_drv(fdctrl);
2172 if (fdctrl->fifo[2] > cur_drv->track) {
2173 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
2174 } else {
2175 fd_seek(cur_drv, cur_drv->head,
2176 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
2177 }
2178 fdctrl_to_command_phase(fdctrl);
2179 /* Raise Interrupt */
2180 fdctrl->status0 |= FD_SR0_SEEK;
2181 fdctrl_raise_irq(fdctrl);
2182 }
2183
2184 /*
2185 * Handlers for the execution phase of each command
2186 */
2187 typedef struct FDCtrlCommand {
2188 uint8_t value;
2189 uint8_t mask;
2190 const char* name;
2191 int parameters;
2192 void (*handler)(FDCtrl *fdctrl, int direction);
2193 int direction;
2194 } FDCtrlCommand;
2195
2196 static const FDCtrlCommand handlers[] = {
2197 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2198 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2199 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2200 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2201 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2202 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2203 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2204 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2205 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2206 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2207 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
2208 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
2209 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2210 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2211 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2212 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2213 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2214 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2215 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2216 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2217 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2218 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2219 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2220 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2221 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2222 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2223 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2224 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2225 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2226 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2227 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2228 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2229 };
2230 /* Associate command to an index in the 'handlers' array */
2231 static uint8_t command_to_handler[256];
2232
2233 static const FDCtrlCommand *get_command(uint8_t cmd)
2234 {
2235 int idx;
2236
2237 idx = command_to_handler[cmd];
2238 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2239 return &handlers[idx];
2240 }
2241
2242 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
2243 {
2244 FDrive *cur_drv;
2245 const FDCtrlCommand *cmd;
2246 uint32_t pos;
2247
2248 /* Reset mode */
2249 if (!(fdctrl->dor & FD_DOR_nRESET)) {
2250 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
2251 return;
2252 }
2253 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
2254 FLOPPY_DPRINTF("error: controller not ready for writing\n");
2255 return;
2256 }
2257 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
2258
2259 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2260
2261 /* If data_len spans multiple sectors, the current position in the FIFO
2262 * wraps around while fdctrl->data_pos is the real position in the whole
2263 * request. */
2264 pos = fdctrl->data_pos++;
2265 pos %= FD_SECTOR_LEN;
2266 fdctrl->fifo[pos] = value;
2267
2268 if (fdctrl->data_pos == fdctrl->data_len) {
2269 fdctrl->msr &= ~FD_MSR_RQM;
2270 }
2271
2272 switch (fdctrl->phase) {
2273 case FD_PHASE_EXECUTION:
2274 /* For DMA requests, RQM should be cleared during execution phase, so
2275 * we would have errored out above. */
2276 assert(fdctrl->msr & FD_MSR_NONDMA);
2277
2278 /* FIFO data write */
2279 if (pos == FD_SECTOR_LEN - 1 ||
2280 fdctrl->data_pos == fdctrl->data_len) {
2281 cur_drv = get_cur_drv(fdctrl);
2282 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2283 BDRV_SECTOR_SIZE, 0) < 0) {
2284 FLOPPY_DPRINTF("error writing sector %d\n",
2285 fd_sector(cur_drv));
2286 break;
2287 }
2288 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2289 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2290 fd_sector(cur_drv));
2291 break;
2292 }
2293 }
2294
2295 /* Switch to result phase when done with the transfer */
2296 if (fdctrl->data_pos == fdctrl->data_len) {
2297 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2298 }
2299 break;
2300
2301 case FD_PHASE_COMMAND:
2302 assert(!(fdctrl->msr & FD_MSR_NONDMA));
2303 assert(fdctrl->data_pos < FD_SECTOR_LEN);
2304
2305 if (pos == 0) {
2306 /* The first byte specifies the command. Now we start reading
2307 * as many parameters as this command requires. */
2308 cmd = get_command(value);
2309 fdctrl->data_len = cmd->parameters + 1;
2310 if (cmd->parameters) {
2311 fdctrl->msr |= FD_MSR_RQM;
2312 }
2313 fdctrl->msr |= FD_MSR_CMDBUSY;
2314 }
2315
2316 if (fdctrl->data_pos == fdctrl->data_len) {
2317 /* We have all parameters now, execute the command */
2318 fdctrl->phase = FD_PHASE_EXECUTION;
2319
2320 if (fdctrl->data_state & FD_STATE_FORMAT) {
2321 fdctrl_format_sector(fdctrl);
2322 break;
2323 }
2324
2325 cmd = get_command(fdctrl->fifo[0]);
2326 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2327 cmd->handler(fdctrl, cmd->direction);
2328 }
2329 break;
2330
2331 case FD_PHASE_RESULT:
2332 default:
2333 abort();
2334 }
2335 }
2336
2337 static void fdctrl_result_timer(void *opaque)
2338 {
2339 FDCtrl *fdctrl = opaque;
2340 FDrive *cur_drv = get_cur_drv(fdctrl);
2341
2342 /* Pretend we are spinning.
2343 * This is needed for Coherent, which uses READ ID to check for
2344 * sector interleaving.
2345 */
2346 if (cur_drv->last_sect != 0) {
2347 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2348 }
2349 /* READ_ID can't automatically succeed! */
2350 if (fdctrl->check_media_rate &&
2351 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2352 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2353 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2354 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2355 } else {
2356 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2357 }
2358 }
2359
2360 static void fdctrl_change_cb(void *opaque, bool load)
2361 {
2362 FDrive *drive = opaque;
2363
2364 drive->media_changed = 1;
2365 drive->media_validated = false;
2366 fd_revalidate(drive);
2367 }
2368
2369 static const BlockDevOps fdctrl_block_ops = {
2370 .change_media_cb = fdctrl_change_cb,
2371 };
2372
2373 /* Init functions */
2374 static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp)
2375 {
2376 unsigned int i;
2377 FDrive *drive;
2378
2379 for (i = 0; i < MAX_FD; i++) {
2380 drive = &fdctrl->drives[i];
2381 drive->fdctrl = fdctrl;
2382
2383 if (drive->blk) {
2384 if (blk_get_on_error(drive->blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC) {
2385 error_setg(errp, "fdc doesn't support drive option werror");
2386 return;
2387 }
2388 if (blk_get_on_error(drive->blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
2389 error_setg(errp, "fdc doesn't support drive option rerror");
2390 return;
2391 }
2392 }
2393
2394 fd_init(drive);
2395 if (drive->blk) {
2396 blk_set_dev_ops(drive->blk, &fdctrl_block_ops, drive);
2397 pick_drive_type(drive);
2398 }
2399 fd_revalidate(drive);
2400 }
2401 }
2402
2403 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2404 {
2405 DeviceState *dev;
2406 ISADevice *isadev;
2407
2408 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2409 if (!isadev) {
2410 return NULL;
2411 }
2412 dev = DEVICE(isadev);
2413
2414 if (fds[0]) {
2415 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2416 &error_fatal);
2417 }
2418 if (fds[1]) {
2419 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2420 &error_fatal);
2421 }
2422 qdev_init_nofail(dev);
2423
2424 return isadev;
2425 }
2426
2427 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
2428 hwaddr mmio_base, DriveInfo **fds)
2429 {
2430 FDCtrl *fdctrl;
2431 DeviceState *dev;
2432 SysBusDevice *sbd;
2433 FDCtrlSysBus *sys;
2434
2435 dev = qdev_create(NULL, "sysbus-fdc");
2436 sys = SYSBUS_FDC(dev);
2437 fdctrl = &sys->state;
2438 fdctrl->dma_chann = dma_chann; /* FIXME */
2439 if (fds[0]) {
2440 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2441 &error_fatal);
2442 }
2443 if (fds[1]) {
2444 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2445 &error_fatal);
2446 }
2447 qdev_init_nofail(dev);
2448 sbd = SYS_BUS_DEVICE(dev);
2449 sysbus_connect_irq(sbd, 0, irq);
2450 sysbus_mmio_map(sbd, 0, mmio_base);
2451 }
2452
2453 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
2454 DriveInfo **fds, qemu_irq *fdc_tc)
2455 {
2456 DeviceState *dev;
2457 FDCtrlSysBus *sys;
2458
2459 dev = qdev_create(NULL, "SUNW,fdtwo");
2460 if (fds[0]) {
2461 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
2462 &error_fatal);
2463 }
2464 qdev_init_nofail(dev);
2465 sys = SYSBUS_FDC(dev);
2466 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2467 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
2468 *fdc_tc = qdev_get_gpio_in(dev, 0);
2469 }
2470
2471 static void fdctrl_realize_common(DeviceState *dev, FDCtrl *fdctrl,
2472 Error **errp)
2473 {
2474 int i, j;
2475 static int command_tables_inited = 0;
2476
2477 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) {
2478 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'");
2479 }
2480
2481 /* Fill 'command_to_handler' lookup table */
2482 if (!command_tables_inited) {
2483 command_tables_inited = 1;
2484 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2485 for (j = 0; j < sizeof(command_to_handler); j++) {
2486 if ((j & handlers[i].mask) == handlers[i].value) {
2487 command_to_handler[j] = i;
2488 }
2489 }
2490 }
2491 }
2492
2493 FLOPPY_DPRINTF("init controller\n");
2494 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
2495 fdctrl->fifo_size = 512;
2496 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2497 fdctrl_result_timer, fdctrl);
2498
2499 fdctrl->version = 0x90; /* Intel 82078 controller */
2500 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
2501 fdctrl->num_floppies = MAX_FD;
2502
2503 if (fdctrl->dma_chann != -1) {
2504 IsaDmaClass *k;
2505 assert(fdctrl->dma);
2506 k = ISADMA_GET_CLASS(fdctrl->dma);
2507 k->register_channel(fdctrl->dma, fdctrl->dma_chann,
2508 &fdctrl_transfer_handler, fdctrl);
2509 }
2510
2511 floppy_bus_create(fdctrl, &fdctrl->bus, dev);
2512 fdctrl_connect_drives(fdctrl, errp);
2513 }
2514
2515 static const MemoryRegionPortio fdc_portio_list[] = {
2516 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
2517 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2518 PORTIO_END_OF_LIST(),
2519 };
2520
2521 static void isabus_fdc_realize(DeviceState *dev, Error **errp)
2522 {
2523 ISADevice *isadev = ISA_DEVICE(dev);
2524 FDCtrlISABus *isa = ISA_FDC(dev);
2525 FDCtrl *fdctrl = &isa->state;
2526 Error *err = NULL;
2527
2528 isa_register_portio_list(isadev, &fdctrl->portio_list,
2529 isa->iobase, fdc_portio_list, fdctrl,
2530 "fdc");
2531
2532 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
2533 fdctrl->dma_chann = isa->dma;
2534 if (fdctrl->dma_chann != -1) {
2535 fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma);
2536 assert(fdctrl->dma);
2537 }
2538
2539 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
2540 fdctrl_realize_common(dev, fdctrl, &err);
2541 if (err != NULL) {
2542 error_propagate(errp, err);
2543 return;
2544 }
2545 }
2546
2547 static void sysbus_fdc_initfn(Object *obj)
2548 {
2549 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2550 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2551 FDCtrl *fdctrl = &sys->state;
2552
2553 fdctrl->dma_chann = -1;
2554
2555 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2556 "fdc", 0x08);
2557 sysbus_init_mmio(sbd, &fdctrl->iomem);
2558 }
2559
2560 static void sun4m_fdc_initfn(Object *obj)
2561 {
2562 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2563 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2564 FDCtrl *fdctrl = &sys->state;
2565
2566 fdctrl->dma_chann = -1;
2567
2568 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2569 fdctrl, "fdctrl", 0x08);
2570 sysbus_init_mmio(sbd, &fdctrl->iomem);
2571 }
2572
2573 static void sysbus_fdc_common_initfn(Object *obj)
2574 {
2575 DeviceState *dev = DEVICE(obj);
2576 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
2577 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2578 FDCtrl *fdctrl = &sys->state;
2579
2580 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2581
2582 sysbus_init_irq(sbd, &fdctrl->irq);
2583 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
2584 }
2585
2586 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
2587 {
2588 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2589 FDCtrl *fdctrl = &sys->state;
2590
2591 fdctrl_realize_common(dev, fdctrl, errp);
2592 }
2593
2594 FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
2595 {
2596 FDCtrlISABus *isa = ISA_FDC(fdc);
2597
2598 return isa->state.drives[i].drive;
2599 }
2600
2601 void isa_fdc_get_drive_max_chs(FloppyDriveType type,
2602 uint8_t *maxc, uint8_t *maxh, uint8_t *maxs)
2603 {
2604 const FDFormat *fdf;
2605
2606 *maxc = *maxh = *maxs = 0;
2607 for (fdf = fd_formats; fdf->drive != FLOPPY_DRIVE_TYPE_NONE; fdf++) {
2608 if (fdf->drive != type) {
2609 continue;
2610 }
2611 if (*maxc < fdf->max_track) {
2612 *maxc = fdf->max_track;
2613 }
2614 if (*maxh < fdf->max_head) {
2615 *maxh = fdf->max_head;
2616 }
2617 if (*maxs < fdf->last_sect) {
2618 *maxs = fdf->last_sect;
2619 }
2620 }
2621 (*maxc)--;
2622 }
2623
2624 static const VMStateDescription vmstate_isa_fdc ={
2625 .name = "fdc",
2626 .version_id = 2,
2627 .minimum_version_id = 2,
2628 .fields = (VMStateField[]) {
2629 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2630 VMSTATE_END_OF_LIST()
2631 }
2632 };
2633
2634 static Property isa_fdc_properties[] = {
2635 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
2636 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2637 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2638 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].blk),
2639 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].blk),
2640 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2641 0, true),
2642 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlISABus, state.drives[0].drive,
2643 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2644 FloppyDriveType),
2645 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlISABus, state.drives[1].drive,
2646 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2647 FloppyDriveType),
2648 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2649 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type,
2650 FloppyDriveType),
2651 DEFINE_PROP_END_OF_LIST(),
2652 };
2653
2654 static void isabus_fdc_class_init(ObjectClass *klass, void *data)
2655 {
2656 DeviceClass *dc = DEVICE_CLASS(klass);
2657
2658 dc->realize = isabus_fdc_realize;
2659 dc->fw_name = "fdc";
2660 dc->reset = fdctrl_external_reset_isa;
2661 dc->vmsd = &vmstate_isa_fdc;
2662 dc->props = isa_fdc_properties;
2663 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2664 }
2665
2666 static void isabus_fdc_instance_init(Object *obj)
2667 {
2668 FDCtrlISABus *isa = ISA_FDC(obj);
2669
2670 device_add_bootindex_property(obj, &isa->bootindexA,
2671 "bootindexA", "/floppy@0",
2672 DEVICE(obj), NULL);
2673 device_add_bootindex_property(obj, &isa->bootindexB,
2674 "bootindexB", "/floppy@1",
2675 DEVICE(obj), NULL);
2676 }
2677
2678 static const TypeInfo isa_fdc_info = {
2679 .name = TYPE_ISA_FDC,
2680 .parent = TYPE_ISA_DEVICE,
2681 .instance_size = sizeof(FDCtrlISABus),
2682 .class_init = isabus_fdc_class_init,
2683 .instance_init = isabus_fdc_instance_init,
2684 };
2685
2686 static const VMStateDescription vmstate_sysbus_fdc ={
2687 .name = "fdc",
2688 .version_id = 2,
2689 .minimum_version_id = 2,
2690 .fields = (VMStateField[]) {
2691 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2692 VMSTATE_END_OF_LIST()
2693 }
2694 };
2695
2696 static Property sysbus_fdc_properties[] = {
2697 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].blk),
2698 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].blk),
2699 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlSysBus, state.drives[0].drive,
2700 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2701 FloppyDriveType),
2702 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlSysBus, state.drives[1].drive,
2703 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2704 FloppyDriveType),
2705 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2706 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2707 FloppyDriveType),
2708 DEFINE_PROP_END_OF_LIST(),
2709 };
2710
2711 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2712 {
2713 DeviceClass *dc = DEVICE_CLASS(klass);
2714
2715 dc->props = sysbus_fdc_properties;
2716 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2717 }
2718
2719 static const TypeInfo sysbus_fdc_info = {
2720 .name = "sysbus-fdc",
2721 .parent = TYPE_SYSBUS_FDC,
2722 .instance_init = sysbus_fdc_initfn,
2723 .class_init = sysbus_fdc_class_init,
2724 };
2725
2726 static Property sun4m_fdc_properties[] = {
2727 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].blk),
2728 DEFINE_PROP_DEFAULT("fdtype", FDCtrlSysBus, state.drives[0].drive,
2729 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2730 FloppyDriveType),
2731 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2732 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2733 FloppyDriveType),
2734 DEFINE_PROP_END_OF_LIST(),
2735 };
2736
2737 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2738 {
2739 DeviceClass *dc = DEVICE_CLASS(klass);
2740
2741 dc->props = sun4m_fdc_properties;
2742 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2743 }
2744
2745 static const TypeInfo sun4m_fdc_info = {
2746 .name = "SUNW,fdtwo",
2747 .parent = TYPE_SYSBUS_FDC,
2748 .instance_init = sun4m_fdc_initfn,
2749 .class_init = sun4m_fdc_class_init,
2750 };
2751
2752 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2753 {
2754 DeviceClass *dc = DEVICE_CLASS(klass);
2755
2756 dc->realize = sysbus_fdc_common_realize;
2757 dc->reset = fdctrl_external_reset_sysbus;
2758 dc->vmsd = &vmstate_sysbus_fdc;
2759 }
2760
2761 static const TypeInfo sysbus_fdc_type_info = {
2762 .name = TYPE_SYSBUS_FDC,
2763 .parent = TYPE_SYS_BUS_DEVICE,
2764 .instance_size = sizeof(FDCtrlSysBus),
2765 .instance_init = sysbus_fdc_common_initfn,
2766 .abstract = true,
2767 .class_init = sysbus_fdc_common_class_init,
2768 };
2769
2770 static void fdc_register_types(void)
2771 {
2772 type_register_static(&isa_fdc_info);
2773 type_register_static(&sysbus_fdc_type_info);
2774 type_register_static(&sysbus_fdc_info);
2775 type_register_static(&sun4m_fdc_info);
2776 type_register_static(&floppy_bus_info);
2777 }
2778
2779 type_init(fdc_register_types)
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