target-i386/smm_helper.c

   1 /*
   2  *  x86 SMM helpers
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "exec/helper-proto.h"
  23
  24 /* SMM support */
  25
  26 #if defined(CONFIG_USER_ONLY)
  27
  28 void do_smm_enter(X86CPU *cpu)
  29 {
  30 }
  31
  32 void helper_rsm(CPUX86State *env)
  33 {
  34 }
  35
  36 #else
  37
  38 #ifdef TARGET_X86_64
  39 #define SMM_REVISION_ID 0x00020064
  40 #else
  41 #define SMM_REVISION_ID 0x00020000
  42 #endif
  43
  44 void cpu_smm_update(X86CPU *cpu)
  45 {
  46     CPUX86State *env = &cpu->env;
  47     bool smm_enabled = (env->hflags & HF_SMM_MASK);
  48
  49     if (cpu->smram) {
  50         memory_region_set_enabled(cpu->smram, smm_enabled);
  51     }
  52 }
  53
  54 void do_smm_enter(X86CPU *cpu)
  55 {
  56     CPUX86State *env = &cpu->env;
  57     CPUState *cs = CPU(cpu);
  58     target_ulong sm_state;
  59     SegmentCache *dt;
  60     int i, offset;
  61
  62     qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
  63     log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
  64
  65     env->hflags |= HF_SMM_MASK;
  66     if (env->hflags2 & HF2_NMI_MASK) {
  67         env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
  68     } else {
  69         env->hflags2 |= HF2_NMI_MASK;
  70     }
  71     cpu_smm_update(cpu);
  72
  73     sm_state = env->smbase + 0x8000;
  74
  75 #ifdef TARGET_X86_64
  76     for (i = 0; i < 6; i++) {
  77         dt = &env->segs[i];
  78         offset = 0x7e00 + i * 16;
  79         x86_stw_phys(cs, sm_state + offset, dt->selector);
  80         x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
  81         x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
  82         x86_stq_phys(cs, sm_state + offset + 8, dt->base);
  83     }
  84
  85     x86_stq_phys(cs, sm_state + 0x7e68, env->gdt.base);
  86     x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit);
  87
  88     x86_stw_phys(cs, sm_state + 0x7e70, env->ldt.selector);
  89     x86_stq_phys(cs, sm_state + 0x7e78, env->ldt.base);
  90     x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit);
  91     x86_stw_phys(cs, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
  92
  93     x86_stq_phys(cs, sm_state + 0x7e88, env->idt.base);
  94     x86_stl_phys(cs, sm_state + 0x7e84, env->idt.limit);
  95
  96     x86_stw_phys(cs, sm_state + 0x7e90, env->tr.selector);
  97     x86_stq_phys(cs, sm_state + 0x7e98, env->tr.base);
  98     x86_stl_phys(cs, sm_state + 0x7e94, env->tr.limit);
  99     x86_stw_phys(cs, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
 100
 101     x86_stq_phys(cs, sm_state + 0x7ed0, env->efer);
 102
 103     x86_stq_phys(cs, sm_state + 0x7ff8, env->regs[R_EAX]);
 104     x86_stq_phys(cs, sm_state + 0x7ff0, env->regs[R_ECX]);
 105     x86_stq_phys(cs, sm_state + 0x7fe8, env->regs[R_EDX]);
 106     x86_stq_phys(cs, sm_state + 0x7fe0, env->regs[R_EBX]);
 107     x86_stq_phys(cs, sm_state + 0x7fd8, env->regs[R_ESP]);
 108     x86_stq_phys(cs, sm_state + 0x7fd0, env->regs[R_EBP]);
 109     x86_stq_phys(cs, sm_state + 0x7fc8, env->regs[R_ESI]);
 110     x86_stq_phys(cs, sm_state + 0x7fc0, env->regs[R_EDI]);
 111     for (i = 8; i < 16; i++) {
 112         x86_stq_phys(cs, sm_state + 0x7ff8 - i * 8, env->regs[i]);
 113     }
 114     x86_stq_phys(cs, sm_state + 0x7f78, env->eip);
 115     x86_stl_phys(cs, sm_state + 0x7f70, cpu_compute_eflags(env));
 116     x86_stl_phys(cs, sm_state + 0x7f68, env->dr[6]);
 117     x86_stl_phys(cs, sm_state + 0x7f60, env->dr[7]);
 118
 119     x86_stl_phys(cs, sm_state + 0x7f48, env->cr[4]);
 120     x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]);
 121     x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]);
 122
 123     x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
 124     x86_stl_phys(cs, sm_state + 0x7f00, env->smbase);
 125 #else
 126     x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]);
 127     x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]);
 128     x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env));
 129     x86_stl_phys(cs, sm_state + 0x7ff0, env->eip);
 130     x86_stl_phys(cs, sm_state + 0x7fec, env->regs[R_EDI]);
 131     x86_stl_phys(cs, sm_state + 0x7fe8, env->regs[R_ESI]);
 132     x86_stl_phys(cs, sm_state + 0x7fe4, env->regs[R_EBP]);
 133     x86_stl_phys(cs, sm_state + 0x7fe0, env->regs[R_ESP]);
 134     x86_stl_phys(cs, sm_state + 0x7fdc, env->regs[R_EBX]);
 135     x86_stl_phys(cs, sm_state + 0x7fd8, env->regs[R_EDX]);
 136     x86_stl_phys(cs, sm_state + 0x7fd4, env->regs[R_ECX]);
 137     x86_stl_phys(cs, sm_state + 0x7fd0, env->regs[R_EAX]);
 138     x86_stl_phys(cs, sm_state + 0x7fcc, env->dr[6]);
 139     x86_stl_phys(cs, sm_state + 0x7fc8, env->dr[7]);
 140
 141     x86_stl_phys(cs, sm_state + 0x7fc4, env->tr.selector);
 142     x86_stl_phys(cs, sm_state + 0x7f64, env->tr.base);
 143     x86_stl_phys(cs, sm_state + 0x7f60, env->tr.limit);
 144     x86_stl_phys(cs, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
 145
 146     x86_stl_phys(cs, sm_state + 0x7fc0, env->ldt.selector);
 147     x86_stl_phys(cs, sm_state + 0x7f80, env->ldt.base);
 148     x86_stl_phys(cs, sm_state + 0x7f7c, env->ldt.limit);
 149     x86_stl_phys(cs, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
 150
 151     x86_stl_phys(cs, sm_state + 0x7f74, env->gdt.base);
 152     x86_stl_phys(cs, sm_state + 0x7f70, env->gdt.limit);
 153
 154     x86_stl_phys(cs, sm_state + 0x7f58, env->idt.base);
 155     x86_stl_phys(cs, sm_state + 0x7f54, env->idt.limit);
 156
 157     for (i = 0; i < 6; i++) {
 158         dt = &env->segs[i];
 159         if (i < 3) {
 160             offset = 0x7f84 + i * 12;
 161         } else {
 162             offset = 0x7f2c + (i - 3) * 12;
 163         }
 164         x86_stl_phys(cs, sm_state + 0x7fa8 + i * 4, dt->selector);
 165         x86_stl_phys(cs, sm_state + offset + 8, dt->base);
 166         x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
 167         x86_stl_phys(cs, sm_state + offset, (dt->flags >> 8) & 0xf0ff);
 168     }
 169     x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]);
 170
 171     x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
 172     x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase);
 173 #endif
 174     /* init SMM cpu state */
 175
 176 #ifdef TARGET_X86_64
 177     cpu_load_efer(env, 0);
 178 #endif
 179     cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C |
 180                               DF_MASK));
 181     env->eip = 0x00008000;
 182     cpu_x86_update_cr0(env,
 183                        env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK |
 184                                       CR0_PG_MASK));
 185     cpu_x86_update_cr4(env, 0);
 186     env->dr[7] = 0x00000400;
 187
 188     cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
 189                            0xffffffff,
 190                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 191                            DESC_G_MASK | DESC_A_MASK);
 192     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff,
 193                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 194                            DESC_G_MASK | DESC_A_MASK);
 195     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff,
 196                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 197                            DESC_G_MASK | DESC_A_MASK);
 198     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff,
 199                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 200                            DESC_G_MASK | DESC_A_MASK);
 201     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff,
 202                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 203                            DESC_G_MASK | DESC_A_MASK);
 204     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff,
 205                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 206                            DESC_G_MASK | DESC_A_MASK);
 207 }
 208
 209 void helper_rsm(CPUX86State *env)
 210 {
 211     X86CPU *cpu = x86_env_get_cpu(env);
 212     CPUState *cs = CPU(cpu);
 213     target_ulong sm_state;
 214     int i, offset;
 215     uint32_t val;
 216
 217     sm_state = env->smbase + 0x8000;
 218 #ifdef TARGET_X86_64
 219     cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0));
 220
 221     env->gdt.base = x86_ldq_phys(cs, sm_state + 0x7e68);
 222     env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7e64);
 223
 224     env->ldt.selector = x86_lduw_phys(cs, sm_state + 0x7e70);
 225     env->ldt.base = x86_ldq_phys(cs, sm_state + 0x7e78);
 226     env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7e74);
 227     env->ldt.flags = (x86_lduw_phys(cs, sm_state + 0x7e72) & 0xf0ff) << 8;
 228
 229     env->idt.base = x86_ldq_phys(cs, sm_state + 0x7e88);
 230     env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7e84);
 231
 232     env->tr.selector = x86_lduw_phys(cs, sm_state + 0x7e90);
 233     env->tr.base = x86_ldq_phys(cs, sm_state + 0x7e98);
 234     env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7e94);
 235     env->tr.flags = (x86_lduw_phys(cs, sm_state + 0x7e92) & 0xf0ff) << 8;
 236
 237     env->regs[R_EAX] = x86_ldq_phys(cs, sm_state + 0x7ff8);
 238     env->regs[R_ECX] = x86_ldq_phys(cs, sm_state + 0x7ff0);
 239     env->regs[R_EDX] = x86_ldq_phys(cs, sm_state + 0x7fe8);
 240     env->regs[R_EBX] = x86_ldq_phys(cs, sm_state + 0x7fe0);
 241     env->regs[R_ESP] = x86_ldq_phys(cs, sm_state + 0x7fd8);
 242     env->regs[R_EBP] = x86_ldq_phys(cs, sm_state + 0x7fd0);
 243     env->regs[R_ESI] = x86_ldq_phys(cs, sm_state + 0x7fc8);
 244     env->regs[R_EDI] = x86_ldq_phys(cs, sm_state + 0x7fc0);
 245     for (i = 8; i < 16; i++) {
 246         env->regs[i] = x86_ldq_phys(cs, sm_state + 0x7ff8 - i * 8);
 247     }
 248     env->eip = x86_ldq_phys(cs, sm_state + 0x7f78);
 249     cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7f70),
 250                     ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
 251     env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7f68);
 252     env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7f60);
 253
 254     cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f48));
 255     cpu_x86_update_cr3(env, x86_ldq_phys(cs, sm_state + 0x7f50));
 256     cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7f58));
 257
 258     for (i = 0; i < 6; i++) {
 259         offset = 0x7e00 + i * 16;
 260         cpu_x86_load_seg_cache(env, i,
 261                                x86_lduw_phys(cs, sm_state + offset),
 262                                x86_ldq_phys(cs, sm_state + offset + 8),
 263                                x86_ldl_phys(cs, sm_state + offset + 4),
 264                                (x86_lduw_phys(cs, sm_state + offset + 2) &
 265                                 0xf0ff) << 8);
 266     }
 267
 268     val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
 269     if (val & 0x20000) {
 270         env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00);
 271     }
 272 #else
 273     cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));
 274     cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8));
 275     cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4),
 276                     ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
 277     env->eip = x86_ldl_phys(cs, sm_state + 0x7ff0);
 278     env->regs[R_EDI] = x86_ldl_phys(cs, sm_state + 0x7fec);
 279     env->regs[R_ESI] = x86_ldl_phys(cs, sm_state + 0x7fe8);
 280     env->regs[R_EBP] = x86_ldl_phys(cs, sm_state + 0x7fe4);
 281     env->regs[R_ESP] = x86_ldl_phys(cs, sm_state + 0x7fe0);
 282     env->regs[R_EBX] = x86_ldl_phys(cs, sm_state + 0x7fdc);
 283     env->regs[R_EDX] = x86_ldl_phys(cs, sm_state + 0x7fd8);
 284     env->regs[R_ECX] = x86_ldl_phys(cs, sm_state + 0x7fd4);
 285     env->regs[R_EAX] = x86_ldl_phys(cs, sm_state + 0x7fd0);
 286     env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7fcc);
 287     env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7fc8);
 288
 289     env->tr.selector = x86_ldl_phys(cs, sm_state + 0x7fc4) & 0xffff;
 290     env->tr.base = x86_ldl_phys(cs, sm_state + 0x7f64);
 291     env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7f60);
 292     env->tr.flags = (x86_ldl_phys(cs, sm_state + 0x7f5c) & 0xf0ff) << 8;
 293
 294     env->ldt.selector = x86_ldl_phys(cs, sm_state + 0x7fc0) & 0xffff;
 295     env->ldt.base = x86_ldl_phys(cs, sm_state + 0x7f80);
 296     env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7f7c);
 297     env->ldt.flags = (x86_ldl_phys(cs, sm_state + 0x7f78) & 0xf0ff) << 8;
 298
 299     env->gdt.base = x86_ldl_phys(cs, sm_state + 0x7f74);
 300     env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7f70);
 301
 302     env->idt.base = x86_ldl_phys(cs, sm_state + 0x7f58);
 303     env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7f54);
 304
 305     for (i = 0; i < 6; i++) {
 306         if (i < 3) {
 307             offset = 0x7f84 + i * 12;
 308         } else {
 309             offset = 0x7f2c + (i - 3) * 12;
 310         }
 311         cpu_x86_load_seg_cache(env, i,
 312                                x86_ldl_phys(cs,
 313                                         sm_state + 0x7fa8 + i * 4) & 0xffff,
 314                                x86_ldl_phys(cs, sm_state + offset + 8),
 315                                x86_ldl_phys(cs, sm_state + offset + 4),
 316                                (x86_ldl_phys(cs,
 317                                          sm_state + offset) & 0xf0ff) << 8);
 318     }
 319     cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f14));
 320
 321     val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
 322     if (val & 0x20000) {
 323         env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8);
 324     }
 325 #endif
 326     if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) {
 327         env->hflags2 &= ~HF2_NMI_MASK;
 328     }
 329     env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
 330     env->hflags &= ~HF_SMM_MASK;
 331     cpu_smm_update(cpu);
 332
 333     qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
 334     log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
 335 }
 336
 337 #endif /* !CONFIG_USER_ONLY */