tcg/riscv/tcg-target.inc.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2018 SiFive, Inc
   5  * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
   6  * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
   7  * Copyright (c) 2008 Fabrice Bellard
   8  *
   9  * Based on i386/tcg-target.c and mips/tcg-target.c
  10  *
  11  * Permission is hereby granted, free of charge, to any person obtaining a copy
  12  * of this software and associated documentation files (the "Software"), to deal
  13  * in the Software without restriction, including without limitation the rights
  14  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  15  * copies of the Software, and to permit persons to whom the Software is
  16  * furnished to do so, subject to the following conditions:
  17  *
  18  * The above copyright notice and this permission notice shall be included in
  19  * all copies or substantial portions of the Software.
  20  *
  21  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  22  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  23  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  24  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  25  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  26  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  27  * THE SOFTWARE.
  28  */
  29
  30 #include "tcg-pool.inc.c"
  31
  32 #ifdef CONFIG_DEBUG_TCG
  33 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
  34     "zero",
  35     "ra",
  36     "sp",
  37     "gp",
  38     "tp",
  39     "t0",
  40     "t1",
  41     "t2",
  42     "s0",
  43     "s1",
  44     "a0",
  45     "a1",
  46     "a2",
  47     "a3",
  48     "a4",
  49     "a5",
  50     "a6",
  51     "a7",
  52     "s2",
  53     "s3",
  54     "s4",
  55     "s5",
  56     "s6",
  57     "s7",
  58     "s8",
  59     "s9",
  60     "s10",
  61     "s11",
  62     "t3",
  63     "t4",
  64     "t5",
  65     "t6"
  66 };
  67 #endif
  68
  69 static const int tcg_target_reg_alloc_order[] = {
  70     /* Call saved registers */
  71     /* TCG_REG_S0 reservered for TCG_AREG0 */
  72     TCG_REG_S1,
  73     TCG_REG_S2,
  74     TCG_REG_S3,
  75     TCG_REG_S4,
  76     TCG_REG_S5,
  77     TCG_REG_S6,
  78     TCG_REG_S7,
  79     TCG_REG_S8,
  80     TCG_REG_S9,
  81     TCG_REG_S10,
  82     TCG_REG_S11,
  83
  84     /* Call clobbered registers */
  85     TCG_REG_T0,
  86     TCG_REG_T1,
  87     TCG_REG_T2,
  88     TCG_REG_T3,
  89     TCG_REG_T4,
  90     TCG_REG_T5,
  91     TCG_REG_T6,
  92
  93     /* Argument registers */
  94     TCG_REG_A0,
  95     TCG_REG_A1,
  96     TCG_REG_A2,
  97     TCG_REG_A3,
  98     TCG_REG_A4,
  99     TCG_REG_A5,
 100     TCG_REG_A6,
 101     TCG_REG_A7,
 102 };
 103
 104 static const int tcg_target_call_iarg_regs[] = {
 105     TCG_REG_A0,
 106     TCG_REG_A1,
 107     TCG_REG_A2,
 108     TCG_REG_A3,
 109     TCG_REG_A4,
 110     TCG_REG_A5,
 111     TCG_REG_A6,
 112     TCG_REG_A7,
 113 };
 114
 115 static const int tcg_target_call_oarg_regs[] = {
 116     TCG_REG_A0,
 117     TCG_REG_A1,
 118 };