2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, see <http://www.gnu.org/licenses/>.
14 * Copyright IBM Corp. 2008
16 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 /* This file implements emulation of the 32-bit PCI controller found in some
20 * 4xx SoCs, such as the 440EP. */
22 #include "qemu/osdep.h"
25 #include "hw/ppc/ppc.h"
26 #include "hw/ppc/ppc4xx.h"
27 #include "migration/vmstate.h"
28 #include "qemu/module.h"
29 #include "sysemu/reset.h"
30 #include "hw/pci/pci.h"
31 #include "hw/pci/pci_host.h"
33 #include "qom/object.h"
47 OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxPCIState
, PPC4xx_PCI_HOST_BRIDGE
)
49 #define PPC4xx_PCI_NR_PMMS 3
50 #define PPC4xx_PCI_NR_PTMS 2
52 #define PPC4xx_PCI_NUM_DEVS 5
54 struct PPC4xxPCIState
{
55 PCIHostState parent_obj
;
57 struct PCIMasterMap pmm
[PPC4xx_PCI_NR_PMMS
];
58 struct PCITargetMap ptm
[PPC4xx_PCI_NR_PTMS
];
59 qemu_irq irq
[PPC4xx_PCI_NUM_DEVS
];
61 MemoryRegion container
;
65 #define PCIC0_CFGADDR 0x0
66 #define PCIC0_CFGDATA 0x4
68 /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
70 #define PCIL0_PMM0LA 0x0
71 #define PCIL0_PMM0MA 0x4
72 #define PCIL0_PMM0PCILA 0x8
73 #define PCIL0_PMM0PCIHA 0xc
74 #define PCIL0_PMM1LA 0x10
75 #define PCIL0_PMM1MA 0x14
76 #define PCIL0_PMM1PCILA 0x18
77 #define PCIL0_PMM1PCIHA 0x1c
78 #define PCIL0_PMM2LA 0x20
79 #define PCIL0_PMM2MA 0x24
80 #define PCIL0_PMM2PCILA 0x28
81 #define PCIL0_PMM2PCIHA 0x2c
83 /* PCI Target Map (PTM) registers specify which PCI addresses are translated to
85 #define PCIL0_PTM1MS 0x30
86 #define PCIL0_PTM1LA 0x34
87 #define PCIL0_PTM2MS 0x38
88 #define PCIL0_PTM2LA 0x3c
89 #define PCI_REG_BASE 0x800000
90 #define PCI_REG_SIZE 0x40
92 #define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
94 static void ppc4xx_pci_reg_write4(void *opaque
, hwaddr offset
,
95 uint64_t value
, unsigned size
)
97 struct PPC4xxPCIState
*pci
= opaque
;
99 /* We ignore all target attempts at PCI configuration, effectively
100 * assuming a bidirectional 1:1 mapping of PLB and PCI space. */
104 pci
->pmm
[0].la
= value
;
107 pci
->pmm
[0].ma
= value
;
109 case PCIL0_PMM0PCIHA
:
110 pci
->pmm
[0].pciha
= value
;
112 case PCIL0_PMM0PCILA
:
113 pci
->pmm
[0].pcila
= value
;
117 pci
->pmm
[1].la
= value
;
120 pci
->pmm
[1].ma
= value
;
122 case PCIL0_PMM1PCIHA
:
123 pci
->pmm
[1].pciha
= value
;
125 case PCIL0_PMM1PCILA
:
126 pci
->pmm
[1].pcila
= value
;
130 pci
->pmm
[2].la
= value
;
133 pci
->pmm
[2].ma
= value
;
135 case PCIL0_PMM2PCIHA
:
136 pci
->pmm
[2].pciha
= value
;
138 case PCIL0_PMM2PCILA
:
139 pci
->pmm
[2].pcila
= value
;
143 pci
->ptm
[0].ms
= value
;
146 pci
->ptm
[0].la
= value
;
149 pci
->ptm
[1].ms
= value
;
152 pci
->ptm
[1].la
= value
;
156 qemu_log_mask(LOG_GUEST_ERROR
,
157 "%s: unhandled PCI internal register 0x%" HWADDR_PRIx
"\n",
163 static uint64_t ppc4xx_pci_reg_read4(void *opaque
, hwaddr offset
,
166 struct PPC4xxPCIState
*pci
= opaque
;
171 value
= pci
->pmm
[0].la
;
174 value
= pci
->pmm
[0].ma
;
176 case PCIL0_PMM0PCIHA
:
177 value
= pci
->pmm
[0].pciha
;
179 case PCIL0_PMM0PCILA
:
180 value
= pci
->pmm
[0].pcila
;
184 value
= pci
->pmm
[1].la
;
187 value
= pci
->pmm
[1].ma
;
189 case PCIL0_PMM1PCIHA
:
190 value
= pci
->pmm
[1].pciha
;
192 case PCIL0_PMM1PCILA
:
193 value
= pci
->pmm
[1].pcila
;
197 value
= pci
->pmm
[2].la
;
200 value
= pci
->pmm
[2].ma
;
202 case PCIL0_PMM2PCIHA
:
203 value
= pci
->pmm
[2].pciha
;
205 case PCIL0_PMM2PCILA
:
206 value
= pci
->pmm
[2].pcila
;
210 value
= pci
->ptm
[0].ms
;
213 value
= pci
->ptm
[0].la
;
216 value
= pci
->ptm
[1].ms
;
219 value
= pci
->ptm
[1].la
;
223 qemu_log_mask(LOG_GUEST_ERROR
,
224 "%s: invalid PCI internal register 0x%" HWADDR_PRIx
"\n",
232 static const MemoryRegionOps pci_reg_ops
= {
233 .read
= ppc4xx_pci_reg_read4
,
234 .write
= ppc4xx_pci_reg_write4
,
235 .endianness
= DEVICE_LITTLE_ENDIAN
,
238 static void ppc4xx_pci_reset(void *opaque
)
240 struct PPC4xxPCIState
*pci
= opaque
;
242 memset(pci
->pmm
, 0, sizeof(pci
->pmm
));
243 memset(pci
->ptm
, 0, sizeof(pci
->ptm
));
246 /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
247 * may need further refactoring for other boards. */
248 static int ppc4xx_pci_map_irq(PCIDevice
*pci_dev
, int irq_num
)
250 int slot
= PCI_SLOT(pci_dev
->devfn
);
252 trace_ppc4xx_pci_map_irq(pci_dev
->devfn
, irq_num
, slot
);
254 return slot
> 0 ? slot
- 1 : PPC4xx_PCI_NUM_DEVS
- 1;
257 static void ppc4xx_pci_set_irq(void *opaque
, int irq_num
, int level
)
259 qemu_irq
*pci_irqs
= opaque
;
261 trace_ppc4xx_pci_set_irq(irq_num
);
262 assert(irq_num
>= 0 && irq_num
< PPC4xx_PCI_NUM_DEVS
);
263 qemu_set_irq(pci_irqs
[irq_num
], level
);
266 static const VMStateDescription vmstate_pci_master_map
= {
267 .name
= "pci_master_map",
269 .minimum_version_id
= 0,
270 .fields
= (VMStateField
[]) {
271 VMSTATE_UINT32(la
, struct PCIMasterMap
),
272 VMSTATE_UINT32(ma
, struct PCIMasterMap
),
273 VMSTATE_UINT32(pcila
, struct PCIMasterMap
),
274 VMSTATE_UINT32(pciha
, struct PCIMasterMap
),
275 VMSTATE_END_OF_LIST()
279 static const VMStateDescription vmstate_pci_target_map
= {
280 .name
= "pci_target_map",
282 .minimum_version_id
= 0,
283 .fields
= (VMStateField
[]) {
284 VMSTATE_UINT32(ms
, struct PCITargetMap
),
285 VMSTATE_UINT32(la
, struct PCITargetMap
),
286 VMSTATE_END_OF_LIST()
290 static const VMStateDescription vmstate_ppc4xx_pci
= {
291 .name
= "ppc4xx_pci",
293 .minimum_version_id
= 1,
294 .fields
= (VMStateField
[]) {
295 VMSTATE_STRUCT_ARRAY(pmm
, PPC4xxPCIState
, PPC4xx_PCI_NR_PMMS
, 1,
296 vmstate_pci_master_map
,
297 struct PCIMasterMap
),
298 VMSTATE_STRUCT_ARRAY(ptm
, PPC4xxPCIState
, PPC4xx_PCI_NR_PTMS
, 1,
299 vmstate_pci_target_map
,
300 struct PCITargetMap
),
301 VMSTATE_END_OF_LIST()
305 /* XXX Interrupt acknowledge cycles not supported. */
306 static void ppc4xx_pcihost_realize(DeviceState
*dev
, Error
**errp
)
308 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
314 h
= PCI_HOST_BRIDGE(dev
);
315 s
= PPC4xx_PCI_HOST_BRIDGE(dev
);
317 for (i
= 0; i
< ARRAY_SIZE(s
->irq
); i
++) {
318 sysbus_init_irq(sbd
, &s
->irq
[i
]);
321 b
= pci_register_root_bus(dev
, NULL
, ppc4xx_pci_set_irq
,
322 ppc4xx_pci_map_irq
, s
->irq
, get_system_memory(),
323 get_system_io(), 0, ARRAY_SIZE(s
->irq
),
327 pci_create_simple(b
, 0, "ppc4xx-host-bridge");
329 /* XXX split into 2 memory regions, one for config space, one for regs */
330 memory_region_init(&s
->container
, OBJECT(s
), "pci-container", PCI_ALL_SIZE
);
331 memory_region_init_io(&h
->conf_mem
, OBJECT(s
), &pci_host_conf_le_ops
, h
,
333 memory_region_init_io(&h
->data_mem
, OBJECT(s
), &pci_host_data_le_ops
, h
,
335 memory_region_init_io(&s
->iomem
, OBJECT(s
), &pci_reg_ops
, s
,
336 "pci.reg", PCI_REG_SIZE
);
337 memory_region_add_subregion(&s
->container
, PCIC0_CFGADDR
, &h
->conf_mem
);
338 memory_region_add_subregion(&s
->container
, PCIC0_CFGDATA
, &h
->data_mem
);
339 memory_region_add_subregion(&s
->container
, PCI_REG_BASE
, &s
->iomem
);
340 sysbus_init_mmio(sbd
, &s
->container
);
341 qemu_register_reset(ppc4xx_pci_reset
, s
);
344 static void ppc4xx_host_bridge_class_init(ObjectClass
*klass
, void *data
)
346 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
347 DeviceClass
*dc
= DEVICE_CLASS(klass
);
349 dc
->desc
= "Host bridge";
350 k
->vendor_id
= PCI_VENDOR_ID_IBM
;
351 k
->device_id
= PCI_DEVICE_ID_IBM_440GX
;
352 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
354 * PCI-facing part of the host bridge, not usable without the
355 * host-facing part, which can't be device_add'ed, yet.
357 dc
->user_creatable
= false;
360 static const TypeInfo ppc4xx_host_bridge_info
= {
361 .name
= "ppc4xx-host-bridge",
362 .parent
= TYPE_PCI_DEVICE
,
363 .instance_size
= sizeof(PCIDevice
),
364 .class_init
= ppc4xx_host_bridge_class_init
,
365 .interfaces
= (InterfaceInfo
[]) {
366 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
371 static void ppc4xx_pcihost_class_init(ObjectClass
*klass
, void *data
)
373 DeviceClass
*dc
= DEVICE_CLASS(klass
);
375 dc
->realize
= ppc4xx_pcihost_realize
;
376 dc
->vmsd
= &vmstate_ppc4xx_pci
;
379 static const TypeInfo ppc4xx_pcihost_info
= {
380 .name
= TYPE_PPC4xx_PCI_HOST_BRIDGE
,
381 .parent
= TYPE_PCI_HOST_BRIDGE
,
382 .instance_size
= sizeof(PPC4xxPCIState
),
383 .class_init
= ppc4xx_pcihost_class_init
,
386 static void ppc4xx_pci_register_types(void)
388 type_register_static(&ppc4xx_pcihost_info
);
389 type_register_static(&ppc4xx_host_bridge_info
);
392 type_init(ppc4xx_pci_register_types
)