include/hw/pci/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "exec/memory.h"
   5 #include "sysemu/dma.h"
   6
   7 /* PCI includes legacy ISA access.  */
   8 #include "hw/isa/isa.h"
   9
  10 #include "hw/pci/pcie.h"
  11
  12 extern bool pci_available;
  13
  14 /* PCI bus */
  15
  16 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  17 #define PCI_BUS_NUM(x)          (((x) >> 8) & 0xff)
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_BUILD_BDF(bus, devfn)     ((bus << 8) | (devfn))
  21 #define PCI_BUS_MAX             256
  22 #define PCI_DEVFN_MAX           256
  23 #define PCI_SLOT_MAX            32
  24 #define PCI_FUNC_MAX            8
  25
  26 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  27 #include "hw/pci/pci_ids.h"
  28
  29 /* QEMU-specific Vendor and Device ID definitions */
  30
  31 /* IBM (0x1014) */
  32 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  33 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  34
  35 /* Hitachi (0x1054) */
  36 #define PCI_VENDOR_ID_HITACHI            0x1054
  37 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  38
  39 /* Apple (0x106b) */
  40 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  41 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  42 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  43 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  44 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  45
  46 /* Realtek (0x10ec) */
  47 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  48
  49 /* Xilinx (0x10ee) */
  50 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  51
  52 /* Marvell (0x11ab) */
  53 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  54
  55 /* QEMU/Bochs VGA (0x1234) */
  56 #define PCI_VENDOR_ID_QEMU               0x1234
  57 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  58 #define PCI_DEVICE_ID_QEMU_IPMI          0x1112
  59
  60 /* VMWare (0x15ad) */
  61 #define PCI_VENDOR_ID_VMWARE             0x15ad
  62 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  63 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  64 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  65 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  66 #define PCI_DEVICE_ID_VMWARE_PVSCSI      0x07C0
  67 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  68 #define PCI_DEVICE_ID_VMWARE_VMXNET3     0x07B0
  69
  70 /* Intel (0x8086) */
  71 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  72 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  73 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  74
  75 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  76 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  77 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  78 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  79
  80 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  81 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  82 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  84 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  85 #define PCI_DEVICE_ID_VIRTIO_RNG         0x1005
  86 #define PCI_DEVICE_ID_VIRTIO_9P          0x1009
  87 #define PCI_DEVICE_ID_VIRTIO_VSOCK       0x1012
  88 #define PCI_DEVICE_ID_VIRTIO_PMEM        0x1013
  89
  90 #define PCI_VENDOR_ID_REDHAT             0x1b36
  91 #define PCI_DEVICE_ID_REDHAT_BRIDGE      0x0001
  92 #define PCI_DEVICE_ID_REDHAT_SERIAL      0x0002
  93 #define PCI_DEVICE_ID_REDHAT_SERIAL2     0x0003
  94 #define PCI_DEVICE_ID_REDHAT_SERIAL4     0x0004
  95 #define PCI_DEVICE_ID_REDHAT_TEST        0x0005
  96 #define PCI_DEVICE_ID_REDHAT_ROCKER      0x0006
  97 #define PCI_DEVICE_ID_REDHAT_SDHCI       0x0007
  98 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST   0x0008
  99 #define PCI_DEVICE_ID_REDHAT_PXB         0x0009
 100 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
 101 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE    0x000b
 102 #define PCI_DEVICE_ID_REDHAT_PCIE_RP     0x000c
 103 #define PCI_DEVICE_ID_REDHAT_XHCI        0x000d
 104 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
 105 #define PCI_DEVICE_ID_REDHAT_MDPY        0x000f
 106 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
 107
 108 #define FMT_PCIBUS                      PRIx64
 109
 110 typedef uint64_t pcibus_t;
 111
 112 struct PCIHostDeviceAddress {
 113     unsigned int domain;
 114     unsigned int bus;
 115     unsigned int slot;
 116     unsigned int function;
 117 };
 118
 119 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
 120                                 uint32_t address, uint32_t data, int len);
 121 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
 122                                    uint32_t address, int len);
 123 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
 124                                 pcibus_t addr, pcibus_t size, int type);
 125 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
 126
 127 typedef struct PCIIORegion {
 128     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
 129 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
 130     pcibus_t size;
 131     uint8_t type;
 132     MemoryRegion *memory;
 133     MemoryRegion *address_space;
 134 } PCIIORegion;
 135
 136 #define PCI_ROM_SLOT 6
 137 #define PCI_NUM_REGIONS 7
 138
 139 enum {
 140     QEMU_PCI_VGA_MEM,
 141     QEMU_PCI_VGA_IO_LO,
 142     QEMU_PCI_VGA_IO_HI,
 143     QEMU_PCI_VGA_NUM_REGIONS,
 144 };
 145
 146 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
 147 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
 148 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
 149 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
 150 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
 151 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
 152
 153 #include "hw/pci/pci_regs.h"
 154
 155 /* PCI HEADER_TYPE */
 156 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 157
 158 /* Size of the standard PCI config header */
 159 #define PCI_CONFIG_HEADER_SIZE 0x40
 160 /* Size of the standard PCI config space */
 161 #define PCI_CONFIG_SPACE_SIZE 0x100
 162 /* Size of the standard PCIe config space: 4KB */
 163 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 164
 165 #define PCI_NUM_PINS 4 /* A-D */
 166
 167 /* Bits in cap_present field. */
 168 enum {
 169     QEMU_PCI_CAP_MSI = 0x1,
 170     QEMU_PCI_CAP_MSIX = 0x2,
 171     QEMU_PCI_CAP_EXPRESS = 0x4,
 172
 173     /* multifunction capable device */
 174 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 175     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 176
 177     /* command register SERR bit enabled */
 178 #define QEMU_PCI_CAP_SERR_BITNR 4
 179     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 180     /* Standard hot plug controller. */
 181 #define QEMU_PCI_SHPC_BITNR 5
 182     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 183 #define QEMU_PCI_SLOTID_BITNR 6
 184     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 185     /* PCI Express capability - Power Controller Present */
 186 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
 187     QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
 188     /* Link active status in endpoint capability is always set */
 189 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
 190     QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
 191 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
 192     QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
 193 };
 194
 195 #define TYPE_PCI_DEVICE "pci-device"
 196 #define PCI_DEVICE(obj) \
 197      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 198 #define PCI_DEVICE_CLASS(klass) \
 199      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 200 #define PCI_DEVICE_GET_CLASS(obj) \
 201      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 202
 203 /* Implemented by devices that can be plugged on PCI Express buses */
 204 #define INTERFACE_PCIE_DEVICE "pci-express-device"
 205
 206 /* Implemented by devices that can be plugged on Conventional PCI buses */
 207 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
 208
 209 typedef struct PCIINTxRoute {
 210     enum {
 211         PCI_INTX_ENABLED,
 212         PCI_INTX_INVERTED,
 213         PCI_INTX_DISABLED,
 214     } mode;
 215     int irq;
 216 } PCIINTxRoute;
 217
 218 typedef struct PCIDeviceClass {
 219     DeviceClass parent_class;
 220
 221     void (*realize)(PCIDevice *dev, Error **errp);
 222     PCIUnregisterFunc *exit;
 223     PCIConfigReadFunc *config_read;
 224     PCIConfigWriteFunc *config_write;
 225
 226     uint16_t vendor_id;
 227     uint16_t device_id;
 228     uint8_t revision;
 229     uint16_t class_id;
 230     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 231     uint16_t subsystem_id;              /* only for header type = 0 */
 232
 233     /*
 234      * pci-to-pci bridge or normal device.
 235      * This doesn't mean pci host switch.
 236      * When card bus bridge is supported, this would be enhanced.
 237      */
 238     bool is_bridge;
 239
 240     /* rom bar */
 241     const char *romfile;
 242 } PCIDeviceClass;
 243
 244 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
 245 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 246                                       MSIMessage msg);
 247 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 248 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
 249                                       unsigned int vector_start,
 250                                       unsigned int vector_end);
 251
 252 enum PCIReqIDType {
 253     PCI_REQ_ID_INVALID = 0,
 254     PCI_REQ_ID_BDF,
 255     PCI_REQ_ID_SECONDARY_BUS,
 256     PCI_REQ_ID_MAX,
 257 };
 258 typedef enum PCIReqIDType PCIReqIDType;
 259
 260 struct PCIReqIDCache {
 261     PCIDevice *dev;
 262     PCIReqIDType type;
 263 };
 264 typedef struct PCIReqIDCache PCIReqIDCache;
 265
 266 struct PCIDevice {
 267     DeviceState qdev;
 268
 269     /* PCI config space */
 270     uint8_t *config;
 271
 272     /* Used to enable config checks on load. Note that writable bits are
 273      * never checked even if set in cmask. */
 274     uint8_t *cmask;
 275
 276     /* Used to implement R/W bytes */
 277     uint8_t *wmask;
 278
 279     /* Used to implement RW1C(Write 1 to Clear) bytes */
 280     uint8_t *w1cmask;
 281
 282     /* Used to allocate config space for capabilities. */
 283     uint8_t *used;
 284
 285     /* the following fields are read only */
 286     int32_t devfn;
 287     /* Cached device to fetch requester ID from, to avoid the PCI
 288      * tree walking every time we invoke PCI request (e.g.,
 289      * MSI). For conventional PCI root complex, this field is
 290      * meaningless. */
 291     PCIReqIDCache requester_id_cache;
 292     char name[64];
 293     PCIIORegion io_regions[PCI_NUM_REGIONS];
 294     AddressSpace bus_master_as;
 295     MemoryRegion bus_master_container_region;
 296     MemoryRegion bus_master_enable_region;
 297
 298     /* do not access the following fields */
 299     PCIConfigReadFunc *config_read;
 300     PCIConfigWriteFunc *config_write;
 301
 302     /* Legacy PCI VGA regions */
 303     MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
 304     bool has_vga;
 305
 306     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 307     uint8_t irq_state;
 308
 309     /* Capability bits */
 310     uint32_t cap_present;
 311
 312     /* Offset of MSI-X capability in config space */
 313     uint8_t msix_cap;
 314
 315     /* MSI-X entries */
 316     int msix_entries_nr;
 317
 318     /* Space to store MSIX table & pending bit array */
 319     uint8_t *msix_table;
 320     uint8_t *msix_pba;
 321     /* MemoryRegion container for msix exclusive BAR setup */
 322     MemoryRegion msix_exclusive_bar;
 323     /* Memory Regions for MSIX table and pending bit entries. */
 324     MemoryRegion msix_table_mmio;
 325     MemoryRegion msix_pba_mmio;
 326     /* Reference-count for entries actually in use by driver. */
 327     unsigned *msix_entry_used;
 328     /* MSIX function mask set or MSIX disabled */
 329     bool msix_function_masked;
 330     /* Version id needed for VMState */
 331     int32_t version_id;
 332
 333     /* Offset of MSI capability in config space */
 334     uint8_t msi_cap;
 335
 336     /* PCI Express */
 337     PCIExpressDevice exp;
 338
 339     /* SHPC */
 340     SHPCDevice *shpc;
 341
 342     /* Location of option rom */
 343     char *romfile;
 344     bool has_rom;
 345     MemoryRegion rom;
 346     uint32_t rom_bar;
 347
 348     /* INTx routing notifier */
 349     PCIINTxRoutingNotifier intx_routing_notifier;
 350
 351     /* MSI-X notifiers */
 352     MSIVectorUseNotifier msix_vector_use_notifier;
 353     MSIVectorReleaseNotifier msix_vector_release_notifier;
 354     MSIVectorPollNotifier msix_vector_poll_notifier;
 355
 356     /* ID of standby device in net_failover pair */
 357     char *failover_pair_id;
 358 };
 359
 360 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 361                       uint8_t attr, MemoryRegion *memory);
 362 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
 363                       MemoryRegion *io_lo, MemoryRegion *io_hi);
 364 void pci_unregister_vga(PCIDevice *pci_dev);
 365 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 366
 367 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 368                        uint8_t offset, uint8_t size,
 369                        Error **errp);
 370
 371 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 372
 373 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 374
 375
 376 uint32_t pci_default_read_config(PCIDevice *d,
 377                                  uint32_t address, int len);
 378 void pci_default_write_config(PCIDevice *d,
 379                               uint32_t address, uint32_t val, int len);
 380 void pci_device_save(PCIDevice *s, QEMUFile *f);
 381 int pci_device_load(PCIDevice *s, QEMUFile *f);
 382 MemoryRegion *pci_address_space(PCIDevice *dev);
 383 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 384
 385 /*
 386  * Should not normally be used by devices. For use by sPAPR target
 387  * where QEMU emulates firmware.
 388  */
 389 int pci_bar(PCIDevice *d, int reg);
 390
 391 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 392 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 393 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
 394
 395 #define TYPE_PCI_BUS "PCI"
 396 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
 397 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
 398 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
 399 #define TYPE_PCIE_BUS "PCIE"
 400
 401 bool pci_bus_is_express(PCIBus *bus);
 402
 403 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
 404                               const char *name,
 405                               MemoryRegion *address_space_mem,
 406                               MemoryRegion *address_space_io,
 407                               uint8_t devfn_min, const char *typename);
 408 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
 409                          MemoryRegion *address_space_mem,
 410                          MemoryRegion *address_space_io,
 411                          uint8_t devfn_min, const char *typename);
 412 void pci_root_bus_cleanup(PCIBus *bus);
 413 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 414                   void *irq_opaque, int nirq);
 415 void pci_bus_irqs_cleanup(PCIBus *bus);
 416 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 417 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
 418 static inline int pci_swizzle(int slot, int pin)
 419 {
 420     return (slot + pin) % PCI_NUM_PINS;
 421 }
 422 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
 423 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
 424                               pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 425                               void *irq_opaque,
 426                               MemoryRegion *address_space_mem,
 427                               MemoryRegion *address_space_io,
 428                               uint8_t devfn_min, int nirq,
 429                               const char *typename);
 430 void pci_unregister_root_bus(PCIBus *bus);
 431 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 432 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 433 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
 434 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
 435 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
 436                                           PCIINTxRoutingNotifier notifier);
 437 void pci_device_reset(PCIDevice *dev);
 438
 439 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
 440                                const char *default_model,
 441                                const char *default_devaddr);
 442
 443 PCIDevice *pci_vga_init(PCIBus *bus);
 444
 445 static inline PCIBus *pci_get_bus(const PCIDevice *dev)
 446 {
 447     return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
 448 }
 449 int pci_bus_num(PCIBus *s);
 450 static inline int pci_dev_bus_num(const PCIDevice *dev)
 451 {
 452     return pci_bus_num(pci_get_bus(dev));
 453 }
 454
 455 int pci_bus_numa_node(PCIBus *bus);
 456 void pci_for_each_device(PCIBus *bus, int bus_num,
 457                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
 458                          void *opaque);
 459 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
 460                                  void (*fn)(PCIBus *bus, PCIDevice *d,
 461                                             void *opaque),
 462                                  void *opaque);
 463 void pci_for_each_bus_depth_first(PCIBus *bus,
 464                                   void *(*begin)(PCIBus *bus, void *parent_state),
 465                                   void (*end)(PCIBus *bus, void *state),
 466                                   void *parent_state);
 467 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
 468
 469 /* Use this wrapper when specific scan order is not required. */
 470 static inline
 471 void pci_for_each_bus(PCIBus *bus,
 472                       void (*fn)(PCIBus *bus, void *opaque),
 473                       void *opaque)
 474 {
 475     pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
 476 }
 477
 478 PCIBus *pci_device_root_bus(const PCIDevice *d);
 479 const char *pci_root_bus_path(PCIDevice *dev);
 480 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 481 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 482 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
 483
 484 void pci_device_deassert_intx(PCIDevice *dev);
 485
 486 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
 487
 488 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
 489 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
 490
 491 static inline void
 492 pci_set_byte(uint8_t *config, uint8_t val)
 493 {
 494     *config = val;
 495 }
 496
 497 static inline uint8_t
 498 pci_get_byte(const uint8_t *config)
 499 {
 500     return *config;
 501 }
 502
 503 static inline void
 504 pci_set_word(uint8_t *config, uint16_t val)
 505 {
 506     stw_le_p(config, val);
 507 }
 508
 509 static inline uint16_t
 510 pci_get_word(const uint8_t *config)
 511 {
 512     return lduw_le_p(config);
 513 }
 514
 515 static inline void
 516 pci_set_long(uint8_t *config, uint32_t val)
 517 {
 518     stl_le_p(config, val);
 519 }
 520
 521 static inline uint32_t
 522 pci_get_long(const uint8_t *config)
 523 {
 524     return ldl_le_p(config);
 525 }
 526
 527 /*
 528  * PCI capabilities and/or their fields
 529  * are generally DWORD aligned only so
 530  * mechanism used by pci_set/get_quad()
 531  * must be tolerant to unaligned pointers
 532  *
 533  */
 534 static inline void
 535 pci_set_quad(uint8_t *config, uint64_t val)
 536 {
 537     stq_le_p(config, val);
 538 }
 539
 540 static inline uint64_t
 541 pci_get_quad(const uint8_t *config)
 542 {
 543     return ldq_le_p(config);
 544 }
 545
 546 static inline void
 547 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 548 {
 549     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 550 }
 551
 552 static inline void
 553 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 554 {
 555     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 556 }
 557
 558 static inline void
 559 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 560 {
 561     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 562 }
 563
 564 static inline void
 565 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 566 {
 567     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 568 }
 569
 570 static inline void
 571 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 572 {
 573     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 574 }
 575
 576 static inline void
 577 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 578 {
 579     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 580 }
 581
 582 /*
 583  * helper functions to do bit mask operation on configuration space.
 584  * Just to set bit, use test-and-set and discard returned value.
 585  * Just to clear bit, use test-and-clear and discard returned value.
 586  * NOTE: They aren't atomic.
 587  */
 588 static inline uint8_t
 589 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 590 {
 591     uint8_t val = pci_get_byte(config);
 592     pci_set_byte(config, val & ~mask);
 593     return val & mask;
 594 }
 595
 596 static inline uint8_t
 597 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 598 {
 599     uint8_t val = pci_get_byte(config);
 600     pci_set_byte(config, val | mask);
 601     return val & mask;
 602 }
 603
 604 static inline uint16_t
 605 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 606 {
 607     uint16_t val = pci_get_word(config);
 608     pci_set_word(config, val & ~mask);
 609     return val & mask;
 610 }
 611
 612 static inline uint16_t
 613 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 614 {
 615     uint16_t val = pci_get_word(config);
 616     pci_set_word(config, val | mask);
 617     return val & mask;
 618 }
 619
 620 static inline uint32_t
 621 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 622 {
 623     uint32_t val = pci_get_long(config);
 624     pci_set_long(config, val & ~mask);
 625     return val & mask;
 626 }
 627
 628 static inline uint32_t
 629 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 630 {
 631     uint32_t val = pci_get_long(config);
 632     pci_set_long(config, val | mask);
 633     return val & mask;
 634 }
 635
 636 static inline uint64_t
 637 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 638 {
 639     uint64_t val = pci_get_quad(config);
 640     pci_set_quad(config, val & ~mask);
 641     return val & mask;
 642 }
 643
 644 static inline uint64_t
 645 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 646 {
 647     uint64_t val = pci_get_quad(config);
 648     pci_set_quad(config, val | mask);
 649     return val & mask;
 650 }
 651
 652 /* Access a register specified by a mask */
 653 static inline void
 654 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 655 {
 656     uint8_t val = pci_get_byte(config);
 657     uint8_t rval = reg << ctz32(mask);
 658     pci_set_byte(config, (~mask & val) | (mask & rval));
 659 }
 660
 661 static inline uint8_t
 662 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 663 {
 664     uint8_t val = pci_get_byte(config);
 665     return (val & mask) >> ctz32(mask);
 666 }
 667
 668 static inline void
 669 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 670 {
 671     uint16_t val = pci_get_word(config);
 672     uint16_t rval = reg << ctz32(mask);
 673     pci_set_word(config, (~mask & val) | (mask & rval));
 674 }
 675
 676 static inline uint16_t
 677 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 678 {
 679     uint16_t val = pci_get_word(config);
 680     return (val & mask) >> ctz32(mask);
 681 }
 682
 683 static inline void
 684 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 685 {
 686     uint32_t val = pci_get_long(config);
 687     uint32_t rval = reg << ctz32(mask);
 688     pci_set_long(config, (~mask & val) | (mask & rval));
 689 }
 690
 691 static inline uint32_t
 692 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 693 {
 694     uint32_t val = pci_get_long(config);
 695     return (val & mask) >> ctz32(mask);
 696 }
 697
 698 static inline void
 699 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 700 {
 701     uint64_t val = pci_get_quad(config);
 702     uint64_t rval = reg << ctz32(mask);
 703     pci_set_quad(config, (~mask & val) | (mask & rval));
 704 }
 705
 706 static inline uint64_t
 707 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 708 {
 709     uint64_t val = pci_get_quad(config);
 710     return (val & mask) >> ctz32(mask);
 711 }
 712
 713 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 714                                     const char *name);
 715 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 716                                            bool multifunction,
 717                                            const char *name);
 718 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 719 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 720
 721 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
 722
 723 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
 724 void pci_set_irq(PCIDevice *pci_dev, int level);
 725
 726 static inline void pci_irq_assert(PCIDevice *pci_dev)
 727 {
 728     pci_set_irq(pci_dev, 1);
 729 }
 730
 731 static inline void pci_irq_deassert(PCIDevice *pci_dev)
 732 {
 733     pci_set_irq(pci_dev, 0);
 734 }
 735
 736 /*
 737  * FIXME: PCI does not work this way.
 738  * All the callers to this method should be fixed.
 739  */
 740 static inline void pci_irq_pulse(PCIDevice *pci_dev)
 741 {
 742     pci_irq_assert(pci_dev);
 743     pci_irq_deassert(pci_dev);
 744 }
 745
 746 static inline int pci_is_express(const PCIDevice *d)
 747 {
 748     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 749 }
 750
 751 static inline int pci_is_express_downstream_port(const PCIDevice *d)
 752 {
 753     uint8_t type;
 754
 755     if (!pci_is_express(d) || !d->exp.exp_cap) {
 756         return 0;
 757     }
 758
 759     type = pcie_cap_get_type(d);
 760
 761     return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
 762 }
 763
 764 static inline uint32_t pci_config_size(const PCIDevice *d)
 765 {
 766     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 767 }
 768
 769 static inline uint16_t pci_get_bdf(PCIDevice *dev)
 770 {
 771     return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
 772 }
 773
 774 uint16_t pci_requester_id(PCIDevice *dev);
 775
 776 /* DMA access functions */
 777 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
 778 {
 779     return &dev->bus_master_as;
 780 }
 781
 782 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 783                              void *buf, dma_addr_t len, DMADirection dir)
 784 {
 785     dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
 786     return 0;
 787 }
 788
 789 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 790                                void *buf, dma_addr_t len)
 791 {
 792     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 793 }
 794
 795 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 796                                 const void *buf, dma_addr_t len)
 797 {
 798     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 799 }
 800
 801 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 802     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 803                                                    dma_addr_t addr)     \
 804     {                                                                   \
 805         return ld##_l##_dma(pci_get_address_space(dev), addr);          \
 806     }                                                                   \
 807     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 808                                         dma_addr_t addr, uint##_bits##_t val) \
 809     {                                                                   \
 810         st##_s##_dma(pci_get_address_space(dev), addr, val);            \
 811     }
 812
 813 PCI_DMA_DEFINE_LDST(ub, b, 8);
 814 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 815 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 816 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 817 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 818 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 819 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 820
 821 #undef PCI_DMA_DEFINE_LDST
 822
 823 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 824                                 dma_addr_t *plen, DMADirection dir)
 825 {
 826     void *buf;
 827
 828     buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
 829     return buf;
 830 }
 831
 832 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 833                                  DMADirection dir, dma_addr_t access_len)
 834 {
 835     dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
 836 }
 837
 838 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 839                                        int alloc_hint)
 840 {
 841     qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
 842 }
 843
 844 extern const VMStateDescription vmstate_pci_device;
 845
 846 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 847     .name       = (stringify(_field)),                               \
 848     .size       = sizeof(PCIDevice),                                 \
 849     .vmsd       = &vmstate_pci_device,                               \
 850     .flags      = VMS_STRUCT,                                        \
 851     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 852 }
 853
 854 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 855     .name       = (stringify(_field)),                               \
 856     .size       = sizeof(PCIDevice),                                 \
 857     .vmsd       = &vmstate_pci_device,                               \
 858     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 859     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 860 }
 861
 862 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
 863
 864 #endif