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esp (sparc32) Extra scsi data.
[qemu/kevin.git] / hw / pc.c
blob32713b452ac07784ba76125f6ad6d96c7392bea6
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pc.h"
26 #include "fdc.h"
27 #include "pci.h"
28 #include "block.h"
29 #include "sysemu.h"
30 #include "audio/audio.h"
31 #include "net.h"
32 #include "smbus.h"
33 #include "boards.h"
34 #include "monitor.h"
35 #include "fw_cfg.h"
36 #include "hpet_emul.h"
37 #include "watchdog.h"
38 #include "smbios.h"
39 #include "ide.h"
40
41 /* output Bochs bios info messages */
42 //#define DEBUG_BIOS
43
44 /* Show multiboot debug output */
45 //#define DEBUG_MULTIBOOT
46
47 #define BIOS_FILENAME "bios.bin"
48 #define VGABIOS_FILENAME "vgabios.bin"
49 #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
50
51 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
52
53 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
54 #define ACPI_DATA_SIZE 0x10000
55 #define BIOS_CFG_IOPORT 0x510
56 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
57 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
58 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
59
60 #define MAX_IDE_BUS 2
61
62 static fdctrl_t *floppy_controller;
63 static RTCState *rtc_state;
64 static PITState *pit;
65 static PCIDevice *i440fx_state;
66
67 typedef struct rom_reset_data {
68 uint8_t *data;
69 target_phys_addr_t addr;
70 unsigned size;
71 } RomResetData;
72
73 static void option_rom_reset(void *_rrd)
74 {
75 RomResetData *rrd = _rrd;
76
77 cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size);
78 }
79
80 static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
81 {
82 RomResetData *rrd = qemu_malloc(sizeof *rrd);
83
84 rrd->data = qemu_malloc(size);
85 cpu_physical_memory_read(addr, rrd->data, size);
86 rrd->addr = addr;
87 rrd->size = size;
88 qemu_register_reset(option_rom_reset, rrd);
89 }
90
91 typedef struct isa_irq_state {
92 qemu_irq *i8259;
93 qemu_irq *ioapic;
94 } IsaIrqState;
95
96 static void isa_irq_handler(void *opaque, int n, int level)
97 {
98 IsaIrqState *isa = (IsaIrqState *)opaque;
99
100 if (n < 16) {
101 qemu_set_irq(isa->i8259[n], level);
102 }
103 qemu_set_irq(isa->ioapic[n], level);
104 };
105
106 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
107 {
108 }
109
110 /* MSDOS compatibility mode FPU exception support */
111 static qemu_irq ferr_irq;
112 /* XXX: add IGNNE support */
113 void cpu_set_ferr(CPUX86State *s)
114 {
115 qemu_irq_raise(ferr_irq);
116 }
117
118 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
119 {
120 qemu_irq_lower(ferr_irq);
121 }
122
123 /* TSC handling */
124 uint64_t cpu_get_tsc(CPUX86State *env)
125 {
126 return cpu_get_ticks();
127 }
128
129 /* SMM support */
130 void cpu_smm_update(CPUState *env)
131 {
132 if (i440fx_state && env == first_cpu)
133 i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
134 }
135
136
137 /* IRQ handling */
138 int cpu_get_pic_interrupt(CPUState *env)
139 {
140 int intno;
141
142 intno = apic_get_interrupt(env);
143 if (intno >= 0) {
144 /* set irq request if a PIC irq is still pending */
145 /* XXX: improve that */
146 pic_update_irq(isa_pic);
147 return intno;
148 }
149 /* read the irq from the PIC */
150 if (!apic_accept_pic_intr(env))
151 return -1;
152
153 intno = pic_read_irq(isa_pic);
154 return intno;
155 }
156
157 static void pic_irq_request(void *opaque, int irq, int level)
158 {
159 CPUState *env = first_cpu;
160
161 if (env->apic_state) {
162 while (env) {
163 if (apic_accept_pic_intr(env))
164 apic_deliver_pic_intr(env, level);
165 env = env->next_cpu;
166 }
167 } else {
168 if (level)
169 cpu_interrupt(env, CPU_INTERRUPT_HARD);
170 else
171 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
172 }
173 }
174
175 /* PC cmos mappings */
176
177 #define REG_EQUIPMENT_BYTE 0x14
178
179 static int cmos_get_fd_drive_type(int fd0)
180 {
181 int val;
182
183 switch (fd0) {
184 case 0:
185 /* 1.44 Mb 3"5 drive */
186 val = 4;
187 break;
188 case 1:
189 /* 2.88 Mb 3"5 drive */
190 val = 5;
191 break;
192 case 2:
193 /* 1.2 Mb 5"5 drive */
194 val = 2;
195 break;
196 default:
197 val = 0;
198 break;
199 }
200 return val;
201 }
202
203 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
204 {
205 RTCState *s = rtc_state;
206 int cylinders, heads, sectors;
207 bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
208 rtc_set_memory(s, type_ofs, 47);
209 rtc_set_memory(s, info_ofs, cylinders);
210 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
211 rtc_set_memory(s, info_ofs + 2, heads);
212 rtc_set_memory(s, info_ofs + 3, 0xff);
213 rtc_set_memory(s, info_ofs + 4, 0xff);
214 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
215 rtc_set_memory(s, info_ofs + 6, cylinders);
216 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
217 rtc_set_memory(s, info_ofs + 8, sectors);
218 }
219
220 /* convert boot_device letter to something recognizable by the bios */
221 static int boot_device2nibble(char boot_device)
222 {
223 switch(boot_device) {
224 case 'a':
225 case 'b':
226 return 0x01; /* floppy boot */
227 case 'c':
228 return 0x02; /* hard drive boot */
229 case 'd':
230 return 0x03; /* CD-ROM boot */
231 case 'n':
232 return 0x04; /* Network boot */
233 }
234 return 0;
235 }
236
237 /* copy/pasted from cmos_init, should be made a general function
238 and used there as well */
239 static int pc_boot_set(void *opaque, const char *boot_device)
240 {
241 Monitor *mon = cur_mon;
242 #define PC_MAX_BOOT_DEVICES 3
243 RTCState *s = (RTCState *)opaque;
244 int nbds, bds[3] = { 0, };
245 int i;
246
247 nbds = strlen(boot_device);
248 if (nbds > PC_MAX_BOOT_DEVICES) {
249 monitor_printf(mon, "Too many boot devices for PC\n");
250 return(1);
251 }
252 for (i = 0; i < nbds; i++) {
253 bds[i] = boot_device2nibble(boot_device[i]);
254 if (bds[i] == 0) {
255 monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
256 boot_device[i]);
257 return(1);
258 }
259 }
260 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
261 rtc_set_memory(s, 0x38, (bds[2] << 4));
262 return(0);
263 }
264
265 /* hd_table must contain 4 block drivers */
266 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
267 const char *boot_device, BlockDriverState **hd_table)
268 {
269 RTCState *s = rtc_state;
270 int nbds, bds[3] = { 0, };
271 int val;
272 int fd0, fd1, nb;
273 int i;
274
275 /* various important CMOS locations needed by PC/Bochs bios */
276
277 /* memory size */
278 val = 640; /* base memory in K */
279 rtc_set_memory(s, 0x15, val);
280 rtc_set_memory(s, 0x16, val >> 8);
281
282 val = (ram_size / 1024) - 1024;
283 if (val > 65535)
284 val = 65535;
285 rtc_set_memory(s, 0x17, val);
286 rtc_set_memory(s, 0x18, val >> 8);
287 rtc_set_memory(s, 0x30, val);
288 rtc_set_memory(s, 0x31, val >> 8);
289
290 if (above_4g_mem_size) {
291 rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
292 rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
293 rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
294 }
295
296 if (ram_size > (16 * 1024 * 1024))
297 val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
298 else
299 val = 0;
300 if (val > 65535)
301 val = 65535;
302 rtc_set_memory(s, 0x34, val);
303 rtc_set_memory(s, 0x35, val >> 8);
304
305 /* set the number of CPU */
306 rtc_set_memory(s, 0x5f, smp_cpus - 1);
307
308 /* set boot devices, and disable floppy signature check if requested */
309 #define PC_MAX_BOOT_DEVICES 3
310 nbds = strlen(boot_device);
311 if (nbds > PC_MAX_BOOT_DEVICES) {
312 fprintf(stderr, "Too many boot devices for PC\n");
313 exit(1);
314 }
315 for (i = 0; i < nbds; i++) {
316 bds[i] = boot_device2nibble(boot_device[i]);
317 if (bds[i] == 0) {
318 fprintf(stderr, "Invalid boot device for PC: '%c'\n",
319 boot_device[i]);
320 exit(1);
321 }
322 }
323 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
324 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
325
326 /* floppy type */
327
328 fd0 = fdctrl_get_drive_type(floppy_controller, 0);
329 fd1 = fdctrl_get_drive_type(floppy_controller, 1);
330
331 val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
332 rtc_set_memory(s, 0x10, val);
333
334 val = 0;
335 nb = 0;
336 if (fd0 < 3)
337 nb++;
338 if (fd1 < 3)
339 nb++;
340 switch (nb) {
341 case 0:
342 break;
343 case 1:
344 val |= 0x01; /* 1 drive, ready for boot */
345 break;
346 case 2:
347 val |= 0x41; /* 2 drives, ready for boot */
348 break;
349 }
350 val |= 0x02; /* FPU is there */
351 val |= 0x04; /* PS/2 mouse installed */
352 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
353
354 /* hard drives */
355
356 rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
357 if (hd_table[0])
358 cmos_init_hd(0x19, 0x1b, hd_table[0]);
359 if (hd_table[1])
360 cmos_init_hd(0x1a, 0x24, hd_table[1]);
361
362 val = 0;
363 for (i = 0; i < 4; i++) {
364 if (hd_table[i]) {
365 int cylinders, heads, sectors, translation;
366 /* NOTE: bdrv_get_geometry_hint() returns the physical
367 geometry. It is always such that: 1 <= sects <= 63, 1
368 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
369 geometry can be different if a translation is done. */
370 translation = bdrv_get_translation_hint(hd_table[i]);
371 if (translation == BIOS_ATA_TRANSLATION_AUTO) {
372 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
373 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
374 /* No translation. */
375 translation = 0;
376 } else {
377 /* LBA translation. */
378 translation = 1;
379 }
380 } else {
381 translation--;
382 }
383 val |= translation << (i * 2);
384 }
385 }
386 rtc_set_memory(s, 0x39, val);
387 }
388
389 void ioport_set_a20(int enable)
390 {
391 /* XXX: send to all CPUs ? */
392 cpu_x86_set_a20(first_cpu, enable);
393 }
394
395 int ioport_get_a20(void)
396 {
397 return ((first_cpu->a20_mask >> 20) & 1);
398 }
399
400 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
401 {
402 ioport_set_a20((val >> 1) & 1);
403 /* XXX: bit 0 is fast reset */
404 }
405
406 static uint32_t ioport92_read(void *opaque, uint32_t addr)
407 {
408 return ioport_get_a20() << 1;
409 }
410
411 /***********************************************************/
412 /* Bochs BIOS debug ports */
413
414 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
415 {
416 static const char shutdown_str[8] = "Shutdown";
417 static int shutdown_index = 0;
418
419 switch(addr) {
420 /* Bochs BIOS messages */
421 case 0x400:
422 case 0x401:
423 fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
424 exit(1);
425 case 0x402:
426 case 0x403:
427 #ifdef DEBUG_BIOS
428 fprintf(stderr, "%c", val);
429 #endif
430 break;
431 case 0x8900:
432 /* same as Bochs power off */
433 if (val == shutdown_str[shutdown_index]) {
434 shutdown_index++;
435 if (shutdown_index == 8) {
436 shutdown_index = 0;
437 qemu_system_shutdown_request();
438 }
439 } else {
440 shutdown_index = 0;
441 }
442 break;
443
444 /* LGPL'ed VGA BIOS messages */
445 case 0x501:
446 case 0x502:
447 fprintf(stderr, "VGA BIOS panic, line %d\n", val);
448 exit(1);
449 case 0x500:
450 case 0x503:
451 #ifdef DEBUG_BIOS
452 fprintf(stderr, "%c", val);
453 #endif
454 break;
455 }
456 }
457
458 extern uint64_t node_cpumask[MAX_NODES];
459
460 static void *bochs_bios_init(void)
461 {
462 void *fw_cfg;
463 uint8_t *smbios_table;
464 size_t smbios_len;
465 uint64_t *numa_fw_cfg;
466 int i, j;
467
468 register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
469 register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
470 register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
471 register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
472 register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
473
474 register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
475 register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
476 register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
477 register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
478
479 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
480
481 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
482 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
483 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
484 acpi_tables_len);
485 fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
486
487 smbios_table = smbios_get_table(&smbios_len);
488 if (smbios_table)
489 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
490 smbios_table, smbios_len);
491
492 /* allocate memory for the NUMA channel: one (64bit) word for the number
493 * of nodes, one word for each VCPU->node and one word for each node to
494 * hold the amount of memory.
495 */
496 numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
497 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
498 for (i = 0; i < smp_cpus; i++) {
499 for (j = 0; j < nb_numa_nodes; j++) {
500 if (node_cpumask[j] & (1 << i)) {
501 numa_fw_cfg[i + 1] = cpu_to_le64(j);
502 break;
503 }
504 }
505 }
506 for (i = 0; i < nb_numa_nodes; i++) {
507 numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
508 }
509 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
510 (1 + smp_cpus + nb_numa_nodes) * 8);
511
512 return fw_cfg;
513 }
514
515 /* Generate an initial boot sector which sets state and jump to
516 a specified vector */
517 static void generate_bootsect(target_phys_addr_t option_rom,
518 uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
519 {
520 uint8_t rom[512], *p, *reloc;
521 uint8_t sum;
522 int i;
523
524 memset(rom, 0, sizeof(rom));
525
526 p = rom;
527 /* Make sure we have an option rom signature */
528 *p++ = 0x55;
529 *p++ = 0xaa;
530
531 /* ROM size in sectors*/
532 *p++ = 1;
533
534 /* Hook int19 */
535
536 *p++ = 0x50; /* push ax */
537 *p++ = 0x1e; /* push ds */
538 *p++ = 0x31; *p++ = 0xc0; /* xor ax, ax */
539 *p++ = 0x8e; *p++ = 0xd8; /* mov ax, ds */
540
541 *p++ = 0xc7; *p++ = 0x06; /* movvw _start,0x64 */
542 *p++ = 0x64; *p++ = 0x00;
543 reloc = p;
544 *p++ = 0x00; *p++ = 0x00;
545
546 *p++ = 0x8c; *p++ = 0x0e; /* mov cs,0x66 */
547 *p++ = 0x66; *p++ = 0x00;
548
549 *p++ = 0x1f; /* pop ds */
550 *p++ = 0x58; /* pop ax */
551 *p++ = 0xcb; /* lret */
552
553 /* Actual code */
554 *reloc = (p - rom);
555
556 *p++ = 0xfa; /* CLI */
557 *p++ = 0xfc; /* CLD */
558
559 for (i = 0; i < 6; i++) {
560 if (i == 1) /* Skip CS */
561 continue;
562
563 *p++ = 0xb8; /* MOV AX,imm16 */
564 *p++ = segs[i];
565 *p++ = segs[i] >> 8;
566 *p++ = 0x8e; /* MOV <seg>,AX */
567 *p++ = 0xc0 + (i << 3);
568 }
569
570 for (i = 0; i < 8; i++) {
571 *p++ = 0x66; /* 32-bit operand size */
572 *p++ = 0xb8 + i; /* MOV <reg>,imm32 */
573 *p++ = gpr[i];
574 *p++ = gpr[i] >> 8;
575 *p++ = gpr[i] >> 16;
576 *p++ = gpr[i] >> 24;
577 }
578
579 *p++ = 0xea; /* JMP FAR */
580 *p++ = ip; /* IP */
581 *p++ = ip >> 8;
582 *p++ = segs[1]; /* CS */
583 *p++ = segs[1] >> 8;
584
585 /* sign rom */
586 sum = 0;
587 for (i = 0; i < (sizeof(rom) - 1); i++)
588 sum += rom[i];
589 rom[sizeof(rom) - 1] = -sum;
590
591 cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom));
592 option_rom_setup_reset(option_rom, sizeof (rom));
593 }
594
595 static long get_file_size(FILE *f)
596 {
597 long where, size;
598
599 /* XXX: on Unix systems, using fstat() probably makes more sense */
600
601 where = ftell(f);
602 fseek(f, 0, SEEK_END);
603 size = ftell(f);
604 fseek(f, where, SEEK_SET);
605
606 return size;
607 }
608
609 #define MULTIBOOT_STRUCT_ADDR 0x9000
610
611 #if MULTIBOOT_STRUCT_ADDR > 0xf0000
612 #error multiboot struct needs to fit in 16 bit real mode
613 #endif
614
615 static int load_multiboot(void *fw_cfg,
616 FILE *f,
617 const char *kernel_filename,
618 const char *initrd_filename,
619 const char *kernel_cmdline,
620 uint8_t *header)
621 {
622 int i, t, is_multiboot = 0;
623 uint32_t flags = 0;
624 uint32_t mh_entry_addr;
625 uint32_t mh_load_addr;
626 uint32_t mb_kernel_size;
627 uint32_t mmap_addr = MULTIBOOT_STRUCT_ADDR;
628 uint32_t mb_bootinfo = MULTIBOOT_STRUCT_ADDR + 0x500;
629 uint32_t mb_cmdline = mb_bootinfo + 0x200;
630 uint32_t mb_mod_end;
631
632 /* Ok, let's see if it is a multiboot image.
633 The header is 12x32bit long, so the latest entry may be 8192 - 48. */
634 for (i = 0; i < (8192 - 48); i += 4) {
635 if (ldl_p(header+i) == 0x1BADB002) {
636 uint32_t checksum = ldl_p(header+i+8);
637 flags = ldl_p(header+i+4);
638 checksum += flags;
639 checksum += (uint32_t)0x1BADB002;
640 if (!checksum) {
641 is_multiboot = 1;
642 break;
643 }
644 }
645 }
646
647 if (!is_multiboot)
648 return 0; /* no multiboot */
649
650 #ifdef DEBUG_MULTIBOOT
651 fprintf(stderr, "qemu: I believe we found a multiboot image!\n");
652 #endif
653
654 if (flags & 0x00000004) { /* MULTIBOOT_HEADER_HAS_VBE */
655 fprintf(stderr, "qemu: multiboot knows VBE. we don't.\n");
656 }
657 if (!(flags & 0x00010000)) { /* MULTIBOOT_HEADER_HAS_ADDR */
658 uint64_t elf_entry;
659 int kernel_size;
660 fclose(f);
661 kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL);
662 if (kernel_size < 0) {
663 fprintf(stderr, "Error while loading elf kernel\n");
664 exit(1);
665 }
666 mh_load_addr = mh_entry_addr = elf_entry;
667 mb_kernel_size = kernel_size;
668
669 #ifdef DEBUG_MULTIBOOT
670 fprintf(stderr, "qemu: loading multiboot-elf kernel (%#x bytes) with entry %#zx\n",
671 mb_kernel_size, (size_t)mh_entry_addr);
672 #endif
673 } else {
674 /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */
675 uint32_t mh_header_addr = ldl_p(header+i+12);
676 mh_load_addr = ldl_p(header+i+16);
677 #ifdef DEBUG_MULTIBOOT
678 uint32_t mh_load_end_addr = ldl_p(header+i+20);
679 uint32_t mh_bss_end_addr = ldl_p(header+i+24);
680 #endif
681 uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr);
682
683 mh_entry_addr = ldl_p(header+i+28);
684 mb_kernel_size = get_file_size(f) - mb_kernel_text_offset;
685
686 /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE.
687 uint32_t mh_mode_type = ldl_p(header+i+32);
688 uint32_t mh_width = ldl_p(header+i+36);
689 uint32_t mh_height = ldl_p(header+i+40);
690 uint32_t mh_depth = ldl_p(header+i+44); */
691
692 #ifdef DEBUG_MULTIBOOT
693 fprintf(stderr, "multiboot: mh_header_addr = %#x\n", mh_header_addr);
694 fprintf(stderr, "multiboot: mh_load_addr = %#x\n", mh_load_addr);
695 fprintf(stderr, "multiboot: mh_load_end_addr = %#x\n", mh_load_end_addr);
696 fprintf(stderr, "multiboot: mh_bss_end_addr = %#x\n", mh_bss_end_addr);
697 #endif
698
699 fseek(f, mb_kernel_text_offset, SEEK_SET);
700
701 #ifdef DEBUG_MULTIBOOT
702 fprintf(stderr, "qemu: loading multiboot kernel (%#x bytes) at %#x\n",
703 mb_kernel_size, mh_load_addr);
704 #endif
705
706 if (!fread_targphys_ok(mh_load_addr, mb_kernel_size, f)) {
707 fprintf(stderr, "qemu: read error on multiboot kernel '%s' (%#x)\n",
708 kernel_filename, mb_kernel_size);
709 exit(1);
710 }
711 fclose(f);
712 }
713
714 /* blob size is only the kernel for now */
715 mb_mod_end = mh_load_addr + mb_kernel_size;
716
717 /* load modules */
718 stl_phys(mb_bootinfo + 20, 0x0); /* mods_count */
719 if (initrd_filename) {
720 uint32_t mb_mod_info = mb_bootinfo + 0x100;
721 uint32_t mb_mod_cmdline = mb_bootinfo + 0x300;
722 uint32_t mb_mod_start = mh_load_addr;
723 uint32_t mb_mod_length = mb_kernel_size;
724 char *next_initrd;
725 char *next_space;
726 int mb_mod_count = 0;
727
728 do {
729 next_initrd = strchr(initrd_filename, ',');
730 if (next_initrd)
731 *next_initrd = '\0';
732 /* if a space comes after the module filename, treat everything
733 after that as parameters */
734 cpu_physical_memory_write(mb_mod_cmdline, (uint8_t*)initrd_filename,
735 strlen(initrd_filename) + 1);
736 stl_phys(mb_mod_info + 8, mb_mod_cmdline); /* string */
737 mb_mod_cmdline += strlen(initrd_filename) + 1;
738 if ((next_space = strchr(initrd_filename, ' ')))
739 *next_space = '\0';
740 #ifdef DEBUG_MULTIBOOT
741 printf("multiboot loading module: %s\n", initrd_filename);
742 #endif
743 f = fopen(initrd_filename, "rb");
744 if (f) {
745 mb_mod_start = (mb_mod_start + mb_mod_length + (TARGET_PAGE_SIZE - 1))
746 & (TARGET_PAGE_MASK);
747 mb_mod_length = get_file_size(f);
748 mb_mod_end = mb_mod_start + mb_mod_length;
749
750 if (!fread_targphys_ok(mb_mod_start, mb_mod_length, f)) {
751 fprintf(stderr, "qemu: read error on multiboot module '%s' (%#x)\n",
752 initrd_filename, mb_mod_length);
753 exit(1);
754 }
755
756 mb_mod_count++;
757 stl_phys(mb_mod_info + 0, mb_mod_start);
758 stl_phys(mb_mod_info + 4, mb_mod_start + mb_mod_length);
759 #ifdef DEBUG_MULTIBOOT
760 printf("mod_start: %#x\nmod_end: %#x\n", mb_mod_start,
761 mb_mod_start + mb_mod_length);
762 #endif
763 stl_phys(mb_mod_info + 12, 0x0); /* reserved */
764 }
765 initrd_filename = next_initrd+1;
766 mb_mod_info += 16;
767 } while (next_initrd);
768 stl_phys(mb_bootinfo + 20, mb_mod_count); /* mods_count */
769 stl_phys(mb_bootinfo + 24, mb_bootinfo + 0x100); /* mods_addr */
770 }
771
772 /* Make sure we're getting kernel + modules back after reset */
773 option_rom_setup_reset(mh_load_addr, mb_mod_end - mh_load_addr);
774
775 /* Commandline support */
776 stl_phys(mb_bootinfo + 16, mb_cmdline);
777 t = strlen(kernel_filename);
778 cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_filename, t);
779 mb_cmdline += t;
780 stb_phys(mb_cmdline++, ' ');
781 t = strlen(kernel_cmdline) + 1;
782 cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_cmdline, t);
783
784 /* the kernel is where we want it to be now */
785
786 #define MULTIBOOT_FLAGS_MEMORY (1 << 0)
787 #define MULTIBOOT_FLAGS_BOOT_DEVICE (1 << 1)
788 #define MULTIBOOT_FLAGS_CMDLINE (1 << 2)
789 #define MULTIBOOT_FLAGS_MODULES (1 << 3)
790 #define MULTIBOOT_FLAGS_MMAP (1 << 6)
791 stl_phys(mb_bootinfo, MULTIBOOT_FLAGS_MEMORY
792 | MULTIBOOT_FLAGS_BOOT_DEVICE
793 | MULTIBOOT_FLAGS_CMDLINE
794 | MULTIBOOT_FLAGS_MODULES
795 | MULTIBOOT_FLAGS_MMAP);
796 stl_phys(mb_bootinfo + 4, 640); /* mem_lower */
797 stl_phys(mb_bootinfo + 8, ram_size / 1024); /* mem_upper */
798 stl_phys(mb_bootinfo + 12, 0x8001ffff); /* XXX: use the -boot switch? */
799 stl_phys(mb_bootinfo + 48, mmap_addr); /* mmap_addr */
800
801 #ifdef DEBUG_MULTIBOOT
802 fprintf(stderr, "multiboot: mh_entry_addr = %#x\n", mh_entry_addr);
803 #endif
804
805 /* Pass variables to option rom */
806 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_entry_addr);
807 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, mb_bootinfo);
808 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, mmap_addr);
809
810 /* Make sure we're getting the config space back after reset */
811 option_rom_setup_reset(mb_bootinfo, 0x500);
812
813 option_rom[nb_option_roms] = "multiboot.bin";
814 nb_option_roms++;
815
816 return 1; /* yes, we are multiboot */
817 }
818
819 static void load_linux(void *fw_cfg,
820 target_phys_addr_t option_rom,
821 const char *kernel_filename,
822 const char *initrd_filename,
823 const char *kernel_cmdline,
824 target_phys_addr_t max_ram_size)
825 {
826 uint16_t protocol;
827 uint32_t gpr[8];
828 uint16_t seg[6];
829 uint16_t real_seg;
830 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
831 uint32_t initrd_max;
832 uint8_t header[8192];
833 target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
834 FILE *f, *fi;
835 char *vmode;
836
837 /* Align to 16 bytes as a paranoia measure */
838 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
839
840 /* load the kernel header */
841 f = fopen(kernel_filename, "rb");
842 if (!f || !(kernel_size = get_file_size(f)) ||
843 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
844 MIN(ARRAY_SIZE(header), kernel_size)) {
845 fprintf(stderr, "qemu: could not load kernel '%s'\n",
846 kernel_filename);
847 exit(1);
848 }
849
850 /* kernel protocol version */
851 #if 0
852 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
853 #endif
854 if (ldl_p(header+0x202) == 0x53726448)
855 protocol = lduw_p(header+0x206);
856 else {
857 /* This looks like a multiboot kernel. If it is, let's stop
858 treating it like a Linux kernel. */
859 if (load_multiboot(fw_cfg, f, kernel_filename,
860 initrd_filename, kernel_cmdline, header))
861 return;
862 protocol = 0;
863 }
864
865 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
866 /* Low kernel */
867 real_addr = 0x90000;
868 cmdline_addr = 0x9a000 - cmdline_size;
869 prot_addr = 0x10000;
870 } else if (protocol < 0x202) {
871 /* High but ancient kernel */
872 real_addr = 0x90000;
873 cmdline_addr = 0x9a000 - cmdline_size;
874 prot_addr = 0x100000;
875 } else {
876 /* High and recent kernel */
877 real_addr = 0x10000;
878 cmdline_addr = 0x20000;
879 prot_addr = 0x100000;
880 }
881
882 #if 0
883 fprintf(stderr,
884 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
885 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
886 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
887 real_addr,
888 cmdline_addr,
889 prot_addr);
890 #endif
891
892 /* highest address for loading the initrd */
893 if (protocol >= 0x203)
894 initrd_max = ldl_p(header+0x22c);
895 else
896 initrd_max = 0x37ffffff;
897
898 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
899 initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
900
901 /* kernel command line */
902 pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
903
904 if (protocol >= 0x202) {
905 stl_p(header+0x228, cmdline_addr);
906 } else {
907 stw_p(header+0x20, 0xA33F);
908 stw_p(header+0x22, cmdline_addr-real_addr);
909 }
910
911 /* handle vga= parameter */
912 vmode = strstr(kernel_cmdline, "vga=");
913 if (vmode) {
914 unsigned int video_mode;
915 /* skip "vga=" */
916 vmode += 4;
917 if (!strncmp(vmode, "normal", 6)) {
918 video_mode = 0xffff;
919 } else if (!strncmp(vmode, "ext", 3)) {
920 video_mode = 0xfffe;
921 } else if (!strncmp(vmode, "ask", 3)) {
922 video_mode = 0xfffd;
923 } else {
924 video_mode = strtol(vmode, NULL, 0);
925 }
926 stw_p(header+0x1fa, video_mode);
927 }
928
929 /* loader type */
930 /* High nybble = B reserved for Qemu; low nybble is revision number.
931 If this code is substantially changed, you may want to consider
932 incrementing the revision. */
933 if (protocol >= 0x200)
934 header[0x210] = 0xB0;
935
936 /* heap */
937 if (protocol >= 0x201) {
938 header[0x211] |= 0x80; /* CAN_USE_HEAP */
939 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
940 }
941
942 /* load initrd */
943 if (initrd_filename) {
944 if (protocol < 0x200) {
945 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
946 exit(1);
947 }
948
949 fi = fopen(initrd_filename, "rb");
950 if (!fi) {
951 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
952 initrd_filename);
953 exit(1);
954 }
955
956 initrd_size = get_file_size(fi);
957 initrd_addr = (initrd_max-initrd_size) & ~4095;
958
959 if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
960 fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
961 initrd_filename);
962 exit(1);
963 }
964 fclose(fi);
965
966 stl_p(header+0x218, initrd_addr);
967 stl_p(header+0x21c, initrd_size);
968 }
969
970 /* store the finalized header and load the rest of the kernel */
971 cpu_physical_memory_write(real_addr, header, ARRAY_SIZE(header));
972
973 setup_size = header[0x1f1];
974 if (setup_size == 0)
975 setup_size = 4;
976
977 setup_size = (setup_size+1)*512;
978 /* Size of protected-mode code */
979 kernel_size -= (setup_size > ARRAY_SIZE(header)) ? setup_size : ARRAY_SIZE(header);
980
981 /* In case we have read too much already, copy that over */
982 if (setup_size < ARRAY_SIZE(header)) {
983 cpu_physical_memory_write(prot_addr, header + setup_size, ARRAY_SIZE(header) - setup_size);
984 prot_addr += (ARRAY_SIZE(header) - setup_size);
985 setup_size = ARRAY_SIZE(header);
986 }
987
988 if (!fread_targphys_ok(real_addr + ARRAY_SIZE(header),
989 setup_size - ARRAY_SIZE(header), f) ||
990 !fread_targphys_ok(prot_addr, kernel_size, f)) {
991 fprintf(stderr, "qemu: read error on kernel '%s'\n",
992 kernel_filename);
993 exit(1);
994 }
995 fclose(f);
996
997 /* generate bootsector to set up the initial register state */
998 real_seg = real_addr >> 4;
999 seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
1000 seg[1] = real_seg+0x20; /* CS */
1001 memset(gpr, 0, sizeof gpr);
1002 gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */
1003
1004 option_rom_setup_reset(real_addr, setup_size);
1005 option_rom_setup_reset(prot_addr, kernel_size);
1006 option_rom_setup_reset(cmdline_addr, cmdline_size);
1007 if (initrd_filename)
1008 option_rom_setup_reset(initrd_addr, initrd_size);
1009
1010 generate_bootsect(option_rom, gpr, seg, 0);
1011 }
1012
1013 static const int ide_iobase[2] = { 0x1f0, 0x170 };
1014 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
1015 static const int ide_irq[2] = { 14, 15 };
1016
1017 #define NE2000_NB_MAX 6
1018
1019 static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
1020 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1021
1022 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
1023 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
1024
1025 static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
1026 static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
1027
1028 #ifdef HAS_AUDIO
1029 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
1030 {
1031 struct soundhw *c;
1032
1033 for (c = soundhw; c->name; ++c) {
1034 if (c->enabled) {
1035 if (c->isa) {
1036 c->init.init_isa(pic);
1037 } else {
1038 if (pci_bus) {
1039 c->init.init_pci(pci_bus);
1040 }
1041 }
1042 }
1043 }
1044 }
1045 #endif
1046
1047 static void pc_init_ne2k_isa(NICInfo *nd)
1048 {
1049 static int nb_ne2k = 0;
1050
1051 if (nb_ne2k == NE2000_NB_MAX)
1052 return;
1053 isa_ne2000_init(ne2000_io[nb_ne2k],
1054 isa_reserve_irq(ne2000_irq[nb_ne2k]), nd);
1055 nb_ne2k++;
1056 }
1057
1058 static int load_option_rom(const char *oprom, target_phys_addr_t start,
1059 target_phys_addr_t end)
1060 {
1061 int size;
1062 char *filename;
1063
1064 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, oprom);
1065 if (filename) {
1066 size = get_image_size(filename);
1067 if (size > 0 && start + size > end) {
1068 fprintf(stderr, "Not enough space to load option rom '%s'\n",
1069 oprom);
1070 exit(1);
1071 }
1072 size = load_image_targphys(filename, start, end - start);
1073 qemu_free(filename);
1074 } else {
1075 size = -1;
1076 }
1077 if (size < 0) {
1078 fprintf(stderr, "Could not load option rom '%s'\n", oprom);
1079 exit(1);
1080 }
1081 /* Round up optiom rom size to the next 2k boundary */
1082 size = (size + 2047) & ~2047;
1083 option_rom_setup_reset(start, size);
1084 return size;
1085 }
1086
1087 int cpu_is_bsp(CPUState *env)
1088 {
1089 return env->cpuid_apic_id == 0;
1090 }
1091
1092 static CPUState *pc_new_cpu(const char *cpu_model)
1093 {
1094 CPUState *env;
1095
1096 env = cpu_init(cpu_model);
1097 if (!env) {
1098 fprintf(stderr, "Unable to find x86 CPU definition\n");
1099 exit(1);
1100 }
1101 if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
1102 env->cpuid_apic_id = env->cpu_index;
1103 /* APIC reset callback resets cpu */
1104 apic_init(env);
1105 } else {
1106 qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
1107 }
1108 return env;
1109 }
1110
1111 /* PC hardware initialisation */
1112 static void pc_init1(ram_addr_t ram_size,
1113 const char *boot_device,
1114 const char *kernel_filename,
1115 const char *kernel_cmdline,
1116 const char *initrd_filename,
1117 const char *cpu_model,
1118 int pci_enabled)
1119 {
1120 char *filename;
1121 int ret, linux_boot, i;
1122 ram_addr_t ram_addr, bios_offset, option_rom_offset;
1123 ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
1124 int bios_size, isa_bios_size, oprom_area_size;
1125 PCIBus *pci_bus;
1126 ISADevice *isa_dev;
1127 int piix3_devfn = -1;
1128 CPUState *env;
1129 qemu_irq *cpu_irq;
1130 qemu_irq *isa_irq;
1131 qemu_irq *i8259;
1132 IsaIrqState *isa_irq_state;
1133 DriveInfo *dinfo;
1134 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
1135 BlockDriverState *fd[MAX_FD];
1136 int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled;
1137 void *fw_cfg;
1138
1139 if (ram_size >= 0xe0000000 ) {
1140 above_4g_mem_size = ram_size - 0xe0000000;
1141 below_4g_mem_size = 0xe0000000;
1142 } else {
1143 below_4g_mem_size = ram_size;
1144 }
1145
1146 linux_boot = (kernel_filename != NULL);
1147
1148 /* init CPUs */
1149 if (cpu_model == NULL) {
1150 #ifdef TARGET_X86_64
1151 cpu_model = "qemu64";
1152 #else
1153 cpu_model = "qemu32";
1154 #endif
1155 }
1156
1157 for (i = 0; i < smp_cpus; i++) {
1158 env = pc_new_cpu(cpu_model);
1159 }
1160
1161 vmport_init();
1162
1163 /* allocate RAM */
1164 ram_addr = qemu_ram_alloc(0xa0000);
1165 cpu_register_physical_memory(0, 0xa0000, ram_addr);
1166
1167 /* Allocate, even though we won't register, so we don't break the
1168 * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
1169 * and some bios areas, which will be registered later
1170 */
1171 ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
1172 ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
1173 cpu_register_physical_memory(0x100000,
1174 below_4g_mem_size - 0x100000,
1175 ram_addr);
1176
1177 /* above 4giga memory allocation */
1178 if (above_4g_mem_size > 0) {
1179 #if TARGET_PHYS_ADDR_BITS == 32
1180 hw_error("To much RAM for 32-bit physical address");
1181 #else
1182 ram_addr = qemu_ram_alloc(above_4g_mem_size);
1183 cpu_register_physical_memory(0x100000000ULL,
1184 above_4g_mem_size,
1185 ram_addr);
1186 #endif
1187 }
1188
1189
1190 /* BIOS load */
1191 if (bios_name == NULL)
1192 bios_name = BIOS_FILENAME;
1193 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1194 if (filename) {
1195 bios_size = get_image_size(filename);
1196 } else {
1197 bios_size = -1;
1198 }
1199 if (bios_size <= 0 ||
1200 (bios_size % 65536) != 0) {
1201 goto bios_error;
1202 }
1203 bios_offset = qemu_ram_alloc(bios_size);
1204 ret = load_image(filename, qemu_get_ram_ptr(bios_offset));
1205 if (ret != bios_size) {
1206 bios_error:
1207 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
1208 exit(1);
1209 }
1210 if (filename) {
1211 qemu_free(filename);
1212 }
1213 /* map the last 128KB of the BIOS in ISA space */
1214 isa_bios_size = bios_size;
1215 if (isa_bios_size > (128 * 1024))
1216 isa_bios_size = 128 * 1024;
1217 cpu_register_physical_memory(0x100000 - isa_bios_size,
1218 isa_bios_size,
1219 (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
1220
1221
1222
1223 option_rom_offset = qemu_ram_alloc(0x20000);
1224 oprom_area_size = 0;
1225 cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset);
1226
1227 if (using_vga) {
1228 const char *vgabios_filename;
1229 /* VGA BIOS load */
1230 if (cirrus_vga_enabled) {
1231 vgabios_filename = VGABIOS_CIRRUS_FILENAME;
1232 } else {
1233 vgabios_filename = VGABIOS_FILENAME;
1234 }
1235 oprom_area_size = load_option_rom(vgabios_filename, 0xc0000, 0xe0000);
1236 }
1237 /* Although video roms can grow larger than 0x8000, the area between
1238 * 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking
1239 * for any other kind of option rom inside this area */
1240 if (oprom_area_size < 0x8000)
1241 oprom_area_size = 0x8000;
1242
1243 /* map all the bios at the top of memory */
1244 cpu_register_physical_memory((uint32_t)(-bios_size),
1245 bios_size, bios_offset | IO_MEM_ROM);
1246
1247 fw_cfg = bochs_bios_init();
1248
1249 if (linux_boot) {
1250 load_linux(fw_cfg, 0xc0000 + oprom_area_size,
1251 kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1252 oprom_area_size += 2048;
1253 }
1254
1255 for (i = 0; i < nb_option_roms; i++) {
1256 oprom_area_size += load_option_rom(option_rom[i], 0xc0000 + oprom_area_size,
1257 0xe0000);
1258 }
1259
1260 for (i = 0; i < nb_nics; i++) {
1261 char nic_oprom[1024];
1262 const char *model = nd_table[i].model;
1263
1264 if (!nd_table[i].bootable)
1265 continue;
1266
1267 if (model == NULL)
1268 model = "e1000";
1269 snprintf(nic_oprom, sizeof(nic_oprom), "pxe-%s.bin", model);
1270
1271 oprom_area_size += load_option_rom(nic_oprom, 0xc0000 + oprom_area_size,
1272 0xe0000);
1273 }
1274
1275 cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
1276 i8259 = i8259_init(cpu_irq[0]);
1277 isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
1278 isa_irq_state->i8259 = i8259;
1279 isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
1280
1281 if (pci_enabled) {
1282 pci_bus = i440fx_init(&i440fx_state, isa_irq);
1283 piix3_devfn = piix3_init(pci_bus, -1);
1284 } else {
1285 pci_bus = NULL;
1286 isa_bus_new(NULL);
1287 }
1288 isa_bus_irqs(isa_irq);
1289
1290 ferr_irq = isa_reserve_irq(13);
1291
1292 /* init basic PC hardware */
1293 register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1294
1295 register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1296
1297 if (cirrus_vga_enabled) {
1298 if (pci_enabled) {
1299 pci_cirrus_vga_init(pci_bus);
1300 } else {
1301 isa_cirrus_vga_init();
1302 }
1303 } else if (vmsvga_enabled) {
1304 if (pci_enabled)
1305 pci_vmsvga_init(pci_bus);
1306 else
1307 fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1308 } else if (std_vga_enabled) {
1309 if (pci_enabled) {
1310 pci_vga_init(pci_bus, 0, 0);
1311 } else {
1312 isa_vga_init();
1313 }
1314 }
1315
1316 rtc_state = rtc_init(0x70, isa_reserve_irq(8), 2000);
1317
1318 qemu_register_boot_set(pc_boot_set, rtc_state);
1319
1320 register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1321 register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1322
1323 if (pci_enabled) {
1324 isa_irq_state->ioapic = ioapic_init();
1325 }
1326 pit = pit_init(0x40, isa_reserve_irq(0));
1327 pcspk_init(pit);
1328 if (!no_hpet) {
1329 hpet_init(isa_irq);
1330 }
1331
1332 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1333 if (serial_hds[i]) {
1334 serial_init(serial_io[i], isa_reserve_irq(serial_irq[i]), 115200,
1335 serial_hds[i]);
1336 }
1337 }
1338
1339 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1340 if (parallel_hds[i]) {
1341 parallel_init(parallel_io[i], isa_reserve_irq(parallel_irq[i]),
1342 parallel_hds[i]);
1343 }
1344 }
1345
1346 for(i = 0; i < nb_nics; i++) {
1347 NICInfo *nd = &nd_table[i];
1348
1349 if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1350 pc_init_ne2k_isa(nd);
1351 else
1352 pci_nic_init(nd, "e1000", NULL);
1353 }
1354
1355 piix4_acpi_system_hot_add_init();
1356
1357 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1358 fprintf(stderr, "qemu: too many IDE bus\n");
1359 exit(1);
1360 }
1361
1362 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1363 dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1364 hd[i] = dinfo ? dinfo->bdrv : NULL;
1365 }
1366
1367 if (pci_enabled) {
1368 pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, isa_irq);
1369 } else {
1370 for(i = 0; i < MAX_IDE_BUS; i++) {
1371 isa_ide_init(ide_iobase[i], ide_iobase2[i],
1372 isa_reserve_irq(ide_irq[i]),
1373 hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1374 }
1375 }
1376
1377 isa_dev = isa_create_simple("i8042", 0x60, 0x64, 1, 12);
1378 DMA_init(0);
1379 #ifdef HAS_AUDIO
1380 audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
1381 #endif
1382
1383 for(i = 0; i < MAX_FD; i++) {
1384 dinfo = drive_get(IF_FLOPPY, 0, i);
1385 fd[i] = dinfo ? dinfo->bdrv : NULL;
1386 }
1387 floppy_controller = fdctrl_init_isa(6, 2, 0x3f0, fd);
1388
1389 cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1390
1391 if (pci_enabled && usb_enabled) {
1392 usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1393 }
1394
1395 if (pci_enabled && acpi_enabled) {
1396 uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1397 i2c_bus *smbus;
1398
1399 /* TODO: Populate SPD eeprom data. */
1400 smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
1401 isa_reserve_irq(9));
1402 for (i = 0; i < 8; i++) {
1403 DeviceState *eeprom;
1404 eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
1405 qdev_prop_set_uint32(eeprom, "address", 0x50 + i);
1406 qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
1407 qdev_init(eeprom);
1408 }
1409 }
1410
1411 if (i440fx_state) {
1412 i440fx_init_memory_mappings(i440fx_state);
1413 }
1414
1415 if (pci_enabled) {
1416 int max_bus;
1417 int bus;
1418
1419 max_bus = drive_get_max_bus(IF_SCSI);
1420 for (bus = 0; bus <= max_bus; bus++) {
1421 pci_create_simple(pci_bus, -1, "lsi53c895a");
1422 }
1423 }
1424
1425 /* Add virtio console devices */
1426 if (pci_enabled) {
1427 for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
1428 if (virtcon_hds[i]) {
1429 pci_create_simple(pci_bus, -1, "virtio-console-pci");
1430 }
1431 }
1432 }
1433 }
1434
1435 static void pc_init_pci(ram_addr_t ram_size,
1436 const char *boot_device,
1437 const char *kernel_filename,
1438 const char *kernel_cmdline,
1439 const char *initrd_filename,
1440 const char *cpu_model)
1441 {
1442 pc_init1(ram_size, boot_device,
1443 kernel_filename, kernel_cmdline,
1444 initrd_filename, cpu_model, 1);
1445 }
1446
1447 static void pc_init_isa(ram_addr_t ram_size,
1448 const char *boot_device,
1449 const char *kernel_filename,
1450 const char *kernel_cmdline,
1451 const char *initrd_filename,
1452 const char *cpu_model)
1453 {
1454 pc_init1(ram_size, boot_device,
1455 kernel_filename, kernel_cmdline,
1456 initrd_filename, cpu_model, 0);
1457 }
1458
1459 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1460 BIOS will read it and start S3 resume at POST Entry */
1461 void cmos_set_s3_resume(void)
1462 {
1463 if (rtc_state)
1464 rtc_set_memory(rtc_state, 0xF, 0xFE);
1465 }
1466
1467 static QEMUMachine pc_machine = {
1468 .name = "pc-0.11",
1469 .alias = "pc",
1470 .desc = "Standard PC",
1471 .init = pc_init_pci,
1472 .max_cpus = 255,
1473 .is_default = 1,
1474 };
1475
1476 static QEMUMachine pc_machine_v0_10 = {
1477 .name = "pc-0.10",
1478 .desc = "Standard PC, qemu 0.10",
1479 .init = pc_init_pci,
1480 .max_cpus = 255,
1481 .compat_props = (CompatProperty[]) {
1482 {
1483 .driver = "virtio-blk-pci",
1484 .property = "class",
1485 .value = stringify(PCI_CLASS_STORAGE_OTHER),
1486 },{
1487 .driver = "virtio-console-pci",
1488 .property = "class",
1489 .value = stringify(PCI_CLASS_DISPLAY_OTHER),
1490 },{
1491 .driver = "virtio-net-pci",
1492 .property = "vectors",
1493 .value = stringify(0),
1494 },{
1495 .driver = "virtio-blk-pci",
1496 .property = "vectors",
1497 .value = stringify(0),
1498 },
1499 { /* end of list */ }
1500 },
1501 };
1502
1503 static QEMUMachine isapc_machine = {
1504 .name = "isapc",
1505 .desc = "ISA-only PC",
1506 .init = pc_init_isa,
1507 .max_cpus = 1,
1508 };
1509
1510 static void pc_machine_init(void)
1511 {
1512 qemu_register_machine(&pc_machine);
1513 qemu_register_machine(&pc_machine_v0_10);
1514 qemu_register_machine(&isapc_machine);
1515 }
1516
1517 machine_init(pc_machine_init);
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