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hw/ppc/spapr: Fix the selection of the processor features
[qemu/kevin.git] / hw / ppc / spapr.c
blob8654108061d7e9ce71cdf989e682a13b91cacbd8
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
31 #include "hw/hw.h"
32 #include "qemu/log.h"
33 #include "hw/fw-path-provider.h"
34 #include "elf.h"
35 #include "net/net.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/kvm.h"
40 #include "sysemu/device_tree.h"
41 #include "kvm_ppc.h"
42 #include "migration/migration.h"
43 #include "mmu-hash64.h"
44 #include "qom/cpu.h"
45
46 #include "hw/boards.h"
47 #include "hw/ppc/ppc.h"
48 #include "hw/loader.h"
49
50 #include "hw/ppc/fdt.h"
51 #include "hw/ppc/spapr.h"
52 #include "hw/ppc/spapr_vio.h"
53 #include "hw/pci-host/spapr.h"
54 #include "hw/ppc/xics.h"
55 #include "hw/pci/msi.h"
56
57 #include "hw/pci/pci.h"
58 #include "hw/scsi/scsi.h"
59 #include "hw/virtio/virtio-scsi.h"
60
61 #include "exec/address-spaces.h"
62 #include "hw/usb.h"
63 #include "qemu/config-file.h"
64 #include "qemu/error-report.h"
65 #include "trace.h"
66 #include "hw/nmi.h"
67
68 #include "hw/compat.h"
69 #include "qemu/cutils.h"
70 #include "hw/ppc/spapr_cpu_core.h"
71 #include "qmp-commands.h"
72
73 #include <libfdt.h>
74
75 /* SLOF memory layout:
76 *
77 * SLOF raw image loaded at 0, copies its romfs right below the flat
78 * device-tree, then position SLOF itself 31M below that
79 *
80 * So we set FW_OVERHEAD to 40MB which should account for all of that
81 * and more
82 *
83 * We load our kernel at 4M, leaving space for SLOF initial image
84 */
85 #define FDT_MAX_SIZE 0x100000
86 #define RTAS_MAX_SIZE 0x10000
87 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
88 #define FW_MAX_SIZE 0x400000
89 #define FW_FILE_NAME "slof.bin"
90 #define FW_OVERHEAD 0x2800000
91 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
92
93 #define MIN_RMA_SLOF 128UL
94
95 #define PHANDLE_XICP 0x00001111
96
97 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
98
99 static XICSState *try_create_xics(const char *type, int nr_servers,
100 int nr_irqs, Error **errp)
101 {
102 Error *err = NULL;
103 DeviceState *dev;
104
105 dev = qdev_create(NULL, type);
106 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
107 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
108 object_property_set_bool(OBJECT(dev), true, "realized", &err);
109 if (err) {
110 error_propagate(errp, err);
111 object_unparent(OBJECT(dev));
112 return NULL;
113 }
114 return XICS_COMMON(dev);
115 }
116
117 static XICSState *xics_system_init(MachineState *machine,
118 int nr_servers, int nr_irqs, Error **errp)
119 {
120 XICSState *xics = NULL;
121
122 if (kvm_enabled()) {
123 Error *err = NULL;
124
125 if (machine_kernel_irqchip_allowed(machine)) {
126 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
127 &err);
128 }
129 if (machine_kernel_irqchip_required(machine) && !xics) {
130 error_reportf_err(err,
131 "kernel_irqchip requested but unavailable: ");
132 } else {
133 error_free(err);
134 }
135 }
136
137 if (!xics) {
138 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
139 }
140
141 return xics;
142 }
143
144 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
145 int smt_threads)
146 {
147 int i, ret = 0;
148 uint32_t servers_prop[smt_threads];
149 uint32_t gservers_prop[smt_threads * 2];
150 int index = ppc_get_vcpu_dt_id(cpu);
151
152 if (cpu->cpu_version) {
153 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
154 if (ret < 0) {
155 return ret;
156 }
157 }
158
159 /* Build interrupt servers and gservers properties */
160 for (i = 0; i < smt_threads; i++) {
161 servers_prop[i] = cpu_to_be32(index + i);
162 /* Hack, direct the group queues back to cpu 0 */
163 gservers_prop[i*2] = cpu_to_be32(index + i);
164 gservers_prop[i*2 + 1] = 0;
165 }
166 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
167 servers_prop, sizeof(servers_prop));
168 if (ret < 0) {
169 return ret;
170 }
171 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
172 gservers_prop, sizeof(gservers_prop));
173
174 return ret;
175 }
176
177 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
178 {
179 int ret = 0;
180 PowerPCCPU *cpu = POWERPC_CPU(cs);
181 int index = ppc_get_vcpu_dt_id(cpu);
182 uint32_t associativity[] = {cpu_to_be32(0x5),
183 cpu_to_be32(0x0),
184 cpu_to_be32(0x0),
185 cpu_to_be32(0x0),
186 cpu_to_be32(cs->numa_node),
187 cpu_to_be32(index)};
188
189 /* Advertise NUMA via ibm,associativity */
190 if (nb_numa_nodes > 1) {
191 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
192 sizeof(associativity));
193 }
194
195 return ret;
196 }
197
198 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
199 {
200 int ret = 0, offset, cpus_offset;
201 CPUState *cs;
202 char cpu_model[32];
203 int smt = kvmppc_smt_threads();
204 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
205
206 CPU_FOREACH(cs) {
207 PowerPCCPU *cpu = POWERPC_CPU(cs);
208 DeviceClass *dc = DEVICE_GET_CLASS(cs);
209 int index = ppc_get_vcpu_dt_id(cpu);
210
211 if ((index % smt) != 0) {
212 continue;
213 }
214
215 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
216
217 cpus_offset = fdt_path_offset(fdt, "/cpus");
218 if (cpus_offset < 0) {
219 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
220 "cpus");
221 if (cpus_offset < 0) {
222 return cpus_offset;
223 }
224 }
225 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
226 if (offset < 0) {
227 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
228 if (offset < 0) {
229 return offset;
230 }
231 }
232
233 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
234 pft_size_prop, sizeof(pft_size_prop));
235 if (ret < 0) {
236 return ret;
237 }
238
239 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
240 if (ret < 0) {
241 return ret;
242 }
243
244 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
245 ppc_get_compat_smt_threads(cpu));
246 if (ret < 0) {
247 return ret;
248 }
249 }
250 return ret;
251 }
252
253 static hwaddr spapr_node0_size(void)
254 {
255 MachineState *machine = MACHINE(qdev_get_machine());
256
257 if (nb_numa_nodes) {
258 int i;
259 for (i = 0; i < nb_numa_nodes; ++i) {
260 if (numa_info[i].node_mem) {
261 return MIN(pow2floor(numa_info[i].node_mem),
262 machine->ram_size);
263 }
264 }
265 }
266 return machine->ram_size;
267 }
268
269 static void add_str(GString *s, const gchar *s1)
270 {
271 g_string_append_len(s, s1, strlen(s1) + 1);
272 }
273
274 static void *spapr_create_fdt_skel(hwaddr initrd_base,
275 hwaddr initrd_size,
276 hwaddr kernel_size,
277 bool little_endian,
278 const char *kernel_cmdline,
279 uint32_t epow_irq)
280 {
281 void *fdt;
282 uint32_t start_prop = cpu_to_be32(initrd_base);
283 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
284 GString *hypertas = g_string_sized_new(256);
285 GString *qemu_hypertas = g_string_sized_new(256);
286 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
287 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
288 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
289 char *buf;
290
291 add_str(hypertas, "hcall-pft");
292 add_str(hypertas, "hcall-term");
293 add_str(hypertas, "hcall-dabr");
294 add_str(hypertas, "hcall-interrupt");
295 add_str(hypertas, "hcall-tce");
296 add_str(hypertas, "hcall-vio");
297 add_str(hypertas, "hcall-splpar");
298 add_str(hypertas, "hcall-bulk");
299 add_str(hypertas, "hcall-set-mode");
300 add_str(hypertas, "hcall-sprg0");
301 add_str(hypertas, "hcall-copy");
302 add_str(hypertas, "hcall-debug");
303 add_str(qemu_hypertas, "hcall-memop1");
304
305 fdt = g_malloc0(FDT_MAX_SIZE);
306 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
307
308 if (kernel_size) {
309 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
310 }
311 if (initrd_size) {
312 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
313 }
314 _FDT((fdt_finish_reservemap(fdt)));
315
316 /* Root node */
317 _FDT((fdt_begin_node(fdt, "")));
318 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
319 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
320 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
321
322 /*
323 * Add info to guest to indentify which host is it being run on
324 * and what is the uuid of the guest
325 */
326 if (kvmppc_get_host_model(&buf)) {
327 _FDT((fdt_property_string(fdt, "host-model", buf)));
328 g_free(buf);
329 }
330 if (kvmppc_get_host_serial(&buf)) {
331 _FDT((fdt_property_string(fdt, "host-serial", buf)));
332 g_free(buf);
333 }
334
335 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
336
337 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
338 if (qemu_uuid_set) {
339 _FDT((fdt_property_string(fdt, "system-id", buf)));
340 }
341 g_free(buf);
342
343 if (qemu_get_vm_name()) {
344 _FDT((fdt_property_string(fdt, "ibm,partition-name",
345 qemu_get_vm_name())));
346 }
347
348 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
349 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
350
351 /* /chosen */
352 _FDT((fdt_begin_node(fdt, "chosen")));
353
354 /* Set Form1_affinity */
355 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
356
357 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
358 _FDT((fdt_property(fdt, "linux,initrd-start",
359 &start_prop, sizeof(start_prop))));
360 _FDT((fdt_property(fdt, "linux,initrd-end",
361 &end_prop, sizeof(end_prop))));
362 if (kernel_size) {
363 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
364 cpu_to_be64(kernel_size) };
365
366 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
367 if (little_endian) {
368 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
369 }
370 }
371 if (boot_menu) {
372 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
373 }
374 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
375 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
376 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
377
378 _FDT((fdt_end_node(fdt)));
379
380 /* RTAS */
381 _FDT((fdt_begin_node(fdt, "rtas")));
382
383 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
384 add_str(hypertas, "hcall-multi-tce");
385 }
386 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
387 hypertas->len)));
388 g_string_free(hypertas, TRUE);
389 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
390 qemu_hypertas->len)));
391 g_string_free(qemu_hypertas, TRUE);
392
393 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
394 refpoints, sizeof(refpoints))));
395
396 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
397 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
398 RTAS_EVENT_SCAN_RATE)));
399
400 if (msi_nonbroken) {
401 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
402 }
403
404 /*
405 * According to PAPR, rtas ibm,os-term does not guarantee a return
406 * back to the guest cpu.
407 *
408 * While an additional ibm,extended-os-term property indicates that
409 * rtas call return will always occur. Set this property.
410 */
411 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
412
413 _FDT((fdt_end_node(fdt)));
414
415 /* interrupt controller */
416 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
417
418 _FDT((fdt_property_string(fdt, "device_type",
419 "PowerPC-External-Interrupt-Presentation")));
420 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
421 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
422 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
423 interrupt_server_ranges_prop,
424 sizeof(interrupt_server_ranges_prop))));
425 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
426 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
427 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
428
429 _FDT((fdt_end_node(fdt)));
430
431 /* vdevice */
432 _FDT((fdt_begin_node(fdt, "vdevice")));
433
434 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
435 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
436 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
437 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
438 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
439 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
440
441 _FDT((fdt_end_node(fdt)));
442
443 /* event-sources */
444 spapr_events_fdt_skel(fdt, epow_irq);
445
446 /* /hypervisor node */
447 if (kvm_enabled()) {
448 uint8_t hypercall[16];
449
450 /* indicate KVM hypercall interface */
451 _FDT((fdt_begin_node(fdt, "hypervisor")));
452 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
453 if (kvmppc_has_cap_fixup_hcalls()) {
454 /*
455 * Older KVM versions with older guest kernels were broken with the
456 * magic page, don't allow the guest to map it.
457 */
458 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
459 sizeof(hypercall))) {
460 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
461 sizeof(hypercall))));
462 }
463 }
464 _FDT((fdt_end_node(fdt)));
465 }
466
467 _FDT((fdt_end_node(fdt))); /* close root node */
468 _FDT((fdt_finish(fdt)));
469
470 return fdt;
471 }
472
473 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
474 hwaddr size)
475 {
476 uint32_t associativity[] = {
477 cpu_to_be32(0x4), /* length */
478 cpu_to_be32(0x0), cpu_to_be32(0x0),
479 cpu_to_be32(0x0), cpu_to_be32(nodeid)
480 };
481 char mem_name[32];
482 uint64_t mem_reg_property[2];
483 int off;
484
485 mem_reg_property[0] = cpu_to_be64(start);
486 mem_reg_property[1] = cpu_to_be64(size);
487
488 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
489 off = fdt_add_subnode(fdt, 0, mem_name);
490 _FDT(off);
491 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
492 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
493 sizeof(mem_reg_property))));
494 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
495 sizeof(associativity))));
496 return off;
497 }
498
499 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
500 {
501 MachineState *machine = MACHINE(spapr);
502 hwaddr mem_start, node_size;
503 int i, nb_nodes = nb_numa_nodes;
504 NodeInfo *nodes = numa_info;
505 NodeInfo ramnode;
506
507 /* No NUMA nodes, assume there is just one node with whole RAM */
508 if (!nb_numa_nodes) {
509 nb_nodes = 1;
510 ramnode.node_mem = machine->ram_size;
511 nodes = &ramnode;
512 }
513
514 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
515 if (!nodes[i].node_mem) {
516 continue;
517 }
518 if (mem_start >= machine->ram_size) {
519 node_size = 0;
520 } else {
521 node_size = nodes[i].node_mem;
522 if (node_size > machine->ram_size - mem_start) {
523 node_size = machine->ram_size - mem_start;
524 }
525 }
526 if (!mem_start) {
527 /* ppc_spapr_init() checks for rma_size <= node0_size already */
528 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
529 mem_start += spapr->rma_size;
530 node_size -= spapr->rma_size;
531 }
532 for ( ; node_size; ) {
533 hwaddr sizetmp = pow2floor(node_size);
534
535 /* mem_start != 0 here */
536 if (ctzl(mem_start) < ctzl(sizetmp)) {
537 sizetmp = 1ULL << ctzl(mem_start);
538 }
539
540 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
541 node_size -= sizetmp;
542 mem_start += sizetmp;
543 }
544 }
545
546 return 0;
547 }
548
549 /* Populate the "ibm,pa-features" property */
550 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset)
551 {
552 uint8_t pa_features_206[] = { 6, 0,
553 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
554 uint8_t pa_features_207[] = { 24, 0,
555 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
556 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
557 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
558 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
559 uint8_t *pa_features;
560 size_t pa_size;
561
562 switch (env->mmu_model) {
563 case POWERPC_MMU_2_06:
564 case POWERPC_MMU_2_06a:
565 pa_features = pa_features_206;
566 pa_size = sizeof(pa_features_206);
567 break;
568 case POWERPC_MMU_2_07:
569 case POWERPC_MMU_2_07a:
570 pa_features = pa_features_207;
571 pa_size = sizeof(pa_features_207);
572 break;
573 default:
574 return;
575 }
576
577 if (env->ci_large_pages) {
578 /*
579 * Note: we keep CI large pages off by default because a 64K capable
580 * guest provisioned with large pages might otherwise try to map a qemu
581 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
582 * even if that qemu runs on a 4k host.
583 * We dd this bit back here if we are confident this is not an issue
584 */
585 pa_features[3] |= 0x20;
586 }
587
588 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
589 }
590
591 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
592 sPAPRMachineState *spapr)
593 {
594 PowerPCCPU *cpu = POWERPC_CPU(cs);
595 CPUPPCState *env = &cpu->env;
596 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
597 int index = ppc_get_vcpu_dt_id(cpu);
598 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
599 0xffffffff, 0xffffffff};
600 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
601 : SPAPR_TIMEBASE_FREQ;
602 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
603 uint32_t page_sizes_prop[64];
604 size_t page_sizes_prop_size;
605 uint32_t vcpus_per_socket = smp_threads * smp_cores;
606 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
607 sPAPRDRConnector *drc;
608 sPAPRDRConnectorClass *drck;
609 int drc_index;
610
611 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
612 if (drc) {
613 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
614 drc_index = drck->get_index(drc);
615 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
616 }
617
618 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
619 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
620
621 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
622 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
623 env->dcache_line_size)));
624 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
625 env->dcache_line_size)));
626 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
627 env->icache_line_size)));
628 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
629 env->icache_line_size)));
630
631 if (pcc->l1_dcache_size) {
632 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
633 pcc->l1_dcache_size)));
634 } else {
635 error_report("Warning: Unknown L1 dcache size for cpu");
636 }
637 if (pcc->l1_icache_size) {
638 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
639 pcc->l1_icache_size)));
640 } else {
641 error_report("Warning: Unknown L1 icache size for cpu");
642 }
643
644 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
645 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
646 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
647 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
648 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
649 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
650
651 if (env->spr_cb[SPR_PURR].oea_read) {
652 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
653 }
654
655 if (env->mmu_model & POWERPC_MMU_1TSEG) {
656 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
657 segs, sizeof(segs))));
658 }
659
660 /* Advertise VMX/VSX (vector extensions) if available
661 * 0 / no property == no vector extensions
662 * 1 == VMX / Altivec available
663 * 2 == VSX available */
664 if (env->insns_flags & PPC_ALTIVEC) {
665 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
666
667 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
668 }
669
670 /* Advertise DFP (Decimal Floating Point) if available
671 * 0 / no property == no DFP
672 * 1 == DFP available */
673 if (env->insns_flags2 & PPC2_DFP) {
674 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
675 }
676
677 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
678 sizeof(page_sizes_prop));
679 if (page_sizes_prop_size) {
680 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
681 page_sizes_prop, page_sizes_prop_size)));
682 }
683
684 spapr_populate_pa_features(env, fdt, offset);
685
686 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
687 cs->cpu_index / vcpus_per_socket)));
688
689 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
690 pft_size_prop, sizeof(pft_size_prop))));
691
692 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
693
694 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
695 ppc_get_compat_smt_threads(cpu)));
696 }
697
698 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
699 {
700 CPUState *cs;
701 int cpus_offset;
702 char *nodename;
703 int smt = kvmppc_smt_threads();
704
705 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
706 _FDT(cpus_offset);
707 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
708 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
709
710 /*
711 * We walk the CPUs in reverse order to ensure that CPU DT nodes
712 * created by fdt_add_subnode() end up in the right order in FDT
713 * for the guest kernel the enumerate the CPUs correctly.
714 */
715 CPU_FOREACH_REVERSE(cs) {
716 PowerPCCPU *cpu = POWERPC_CPU(cs);
717 int index = ppc_get_vcpu_dt_id(cpu);
718 DeviceClass *dc = DEVICE_GET_CLASS(cs);
719 int offset;
720
721 if ((index % smt) != 0) {
722 continue;
723 }
724
725 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
726 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
727 g_free(nodename);
728 _FDT(offset);
729 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
730 }
731
732 }
733
734 /*
735 * Adds ibm,dynamic-reconfiguration-memory node.
736 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
737 * of this device tree node.
738 */
739 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
740 {
741 MachineState *machine = MACHINE(spapr);
742 int ret, i, offset;
743 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
744 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
745 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
746 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
747 memory_region_size(&spapr->hotplug_memory.mr)) /
748 lmb_size;
749 uint32_t *int_buf, *cur_index, buf_len;
750 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
751
752 /*
753 * Don't create the node if there is no hotpluggable memory
754 */
755 if (machine->ram_size == machine->maxram_size) {
756 return 0;
757 }
758
759 /*
760 * Allocate enough buffer size to fit in ibm,dynamic-memory
761 * or ibm,associativity-lookup-arrays
762 */
763 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
764 * sizeof(uint32_t);
765 cur_index = int_buf = g_malloc0(buf_len);
766
767 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
768
769 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
770 sizeof(prop_lmb_size));
771 if (ret < 0) {
772 goto out;
773 }
774
775 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
776 if (ret < 0) {
777 goto out;
778 }
779
780 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
781 if (ret < 0) {
782 goto out;
783 }
784
785 /* ibm,dynamic-memory */
786 int_buf[0] = cpu_to_be32(nr_lmbs);
787 cur_index++;
788 for (i = 0; i < nr_lmbs; i++) {
789 uint64_t addr = i * lmb_size;
790 uint32_t *dynamic_memory = cur_index;
791
792 if (i >= hotplug_lmb_start) {
793 sPAPRDRConnector *drc;
794 sPAPRDRConnectorClass *drck;
795
796 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
797 g_assert(drc);
798 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
799
800 dynamic_memory[0] = cpu_to_be32(addr >> 32);
801 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
802 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
803 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
804 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
805 if (memory_region_present(get_system_memory(), addr)) {
806 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
807 } else {
808 dynamic_memory[5] = cpu_to_be32(0);
809 }
810 } else {
811 /*
812 * LMB information for RMA, boot time RAM and gap b/n RAM and
813 * hotplug memory region -- all these are marked as reserved
814 * and as having no valid DRC.
815 */
816 dynamic_memory[0] = cpu_to_be32(addr >> 32);
817 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
818 dynamic_memory[2] = cpu_to_be32(0);
819 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
820 dynamic_memory[4] = cpu_to_be32(-1);
821 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
822 SPAPR_LMB_FLAGS_DRC_INVALID);
823 }
824
825 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
826 }
827 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
828 if (ret < 0) {
829 goto out;
830 }
831
832 /* ibm,associativity-lookup-arrays */
833 cur_index = int_buf;
834 int_buf[0] = cpu_to_be32(nr_nodes);
835 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
836 cur_index += 2;
837 for (i = 0; i < nr_nodes; i++) {
838 uint32_t associativity[] = {
839 cpu_to_be32(0x0),
840 cpu_to_be32(0x0),
841 cpu_to_be32(0x0),
842 cpu_to_be32(i)
843 };
844 memcpy(cur_index, associativity, sizeof(associativity));
845 cur_index += 4;
846 }
847 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
848 (cur_index - int_buf) * sizeof(uint32_t));
849 out:
850 g_free(int_buf);
851 return ret;
852 }
853
854 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
855 target_ulong addr, target_ulong size,
856 bool cpu_update, bool memory_update)
857 {
858 void *fdt, *fdt_skel;
859 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
860 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
861
862 size -= sizeof(hdr);
863
864 /* Create sceleton */
865 fdt_skel = g_malloc0(size);
866 _FDT((fdt_create(fdt_skel, size)));
867 _FDT((fdt_begin_node(fdt_skel, "")));
868 _FDT((fdt_end_node(fdt_skel)));
869 _FDT((fdt_finish(fdt_skel)));
870 fdt = g_malloc0(size);
871 _FDT((fdt_open_into(fdt_skel, fdt, size)));
872 g_free(fdt_skel);
873
874 /* Fixup cpu nodes */
875 if (cpu_update) {
876 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
877 }
878
879 /* Generate ibm,dynamic-reconfiguration-memory node if required */
880 if (memory_update && smc->dr_lmb_enabled) {
881 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
882 }
883
884 /* Pack resulting tree */
885 _FDT((fdt_pack(fdt)));
886
887 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
888 trace_spapr_cas_failed(size);
889 return -1;
890 }
891
892 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
893 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
894 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
895 g_free(fdt);
896
897 return 0;
898 }
899
900 static void spapr_finalize_fdt(sPAPRMachineState *spapr,
901 hwaddr fdt_addr,
902 hwaddr rtas_addr,
903 hwaddr rtas_size)
904 {
905 MachineState *machine = MACHINE(qdev_get_machine());
906 MachineClass *mc = MACHINE_GET_CLASS(machine);
907 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
908 const char *boot_device = machine->boot_order;
909 int ret, i;
910 size_t cb = 0;
911 char *bootlist;
912 void *fdt;
913 sPAPRPHBState *phb;
914
915 fdt = g_malloc(FDT_MAX_SIZE);
916
917 /* open out the base tree into a temp buffer for the final tweaks */
918 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
919
920 ret = spapr_populate_memory(spapr, fdt);
921 if (ret < 0) {
922 error_report("couldn't setup memory nodes in fdt");
923 exit(1);
924 }
925
926 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
927 if (ret < 0) {
928 error_report("couldn't setup vio devices in fdt");
929 exit(1);
930 }
931
932 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
933 ret = spapr_rng_populate_dt(fdt);
934 if (ret < 0) {
935 error_report("could not set up rng device in the fdt");
936 exit(1);
937 }
938 }
939
940 QLIST_FOREACH(phb, &spapr->phbs, list) {
941 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
942 if (ret < 0) {
943 error_report("couldn't setup PCI devices in fdt");
944 exit(1);
945 }
946 }
947
948 /* RTAS */
949 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
950 if (ret < 0) {
951 error_report("Couldn't set up RTAS device tree properties");
952 }
953
954 /* cpus */
955 spapr_populate_cpus_dt_node(fdt, spapr);
956
957 bootlist = get_boot_devices_list(&cb, true);
958 if (cb && bootlist) {
959 int offset = fdt_path_offset(fdt, "/chosen");
960 if (offset < 0) {
961 exit(1);
962 }
963 for (i = 0; i < cb; i++) {
964 if (bootlist[i] == '\n') {
965 bootlist[i] = ' ';
966 }
967
968 }
969 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
970 }
971
972 if (boot_device && strlen(boot_device)) {
973 int offset = fdt_path_offset(fdt, "/chosen");
974
975 if (offset < 0) {
976 exit(1);
977 }
978 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
979 }
980
981 if (!spapr->has_graphics) {
982 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
983 }
984
985 if (smc->dr_lmb_enabled) {
986 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
987 }
988
989 if (mc->query_hotpluggable_cpus) {
990 int offset = fdt_path_offset(fdt, "/cpus");
991 ret = spapr_drc_populate_dt(fdt, offset, NULL,
992 SPAPR_DR_CONNECTOR_TYPE_CPU);
993 if (ret < 0) {
994 error_report("Couldn't set up CPU DR device tree properties");
995 exit(1);
996 }
997 }
998
999 _FDT((fdt_pack(fdt)));
1000
1001 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1002 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1003 fdt_totalsize(fdt), FDT_MAX_SIZE);
1004 exit(1);
1005 }
1006
1007 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1008 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1009
1010 g_free(bootlist);
1011 g_free(fdt);
1012 }
1013
1014 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1015 {
1016 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1017 }
1018
1019 static void emulate_spapr_hypercall(PowerPCCPU *cpu)
1020 {
1021 CPUPPCState *env = &cpu->env;
1022
1023 if (msr_pr) {
1024 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1025 env->gpr[3] = H_PRIVILEGE;
1026 } else {
1027 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1028 }
1029 }
1030
1031 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1032 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1033 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1034 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1035 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1036
1037 /*
1038 * Get the fd to access the kernel htab, re-opening it if necessary
1039 */
1040 static int get_htab_fd(sPAPRMachineState *spapr)
1041 {
1042 if (spapr->htab_fd >= 0) {
1043 return spapr->htab_fd;
1044 }
1045
1046 spapr->htab_fd = kvmppc_get_htab_fd(false);
1047 if (spapr->htab_fd < 0) {
1048 error_report("Unable to open fd for reading hash table from KVM: %s",
1049 strerror(errno));
1050 }
1051
1052 return spapr->htab_fd;
1053 }
1054
1055 static void close_htab_fd(sPAPRMachineState *spapr)
1056 {
1057 if (spapr->htab_fd >= 0) {
1058 close(spapr->htab_fd);
1059 }
1060 spapr->htab_fd = -1;
1061 }
1062
1063 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1064 {
1065 int shift;
1066
1067 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1068 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1069 * that's much more than is needed for Linux guests */
1070 shift = ctz64(pow2ceil(ramsize)) - 7;
1071 shift = MAX(shift, 18); /* Minimum architected size */
1072 shift = MIN(shift, 46); /* Maximum architected size */
1073 return shift;
1074 }
1075
1076 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1077 Error **errp)
1078 {
1079 long rc;
1080
1081 /* Clean up any HPT info from a previous boot */
1082 g_free(spapr->htab);
1083 spapr->htab = NULL;
1084 spapr->htab_shift = 0;
1085 close_htab_fd(spapr);
1086
1087 rc = kvmppc_reset_htab(shift);
1088 if (rc < 0) {
1089 /* kernel-side HPT needed, but couldn't allocate one */
1090 error_setg_errno(errp, errno,
1091 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1092 shift);
1093 /* This is almost certainly fatal, but if the caller really
1094 * wants to carry on with shift == 0, it's welcome to try */
1095 } else if (rc > 0) {
1096 /* kernel-side HPT allocated */
1097 if (rc != shift) {
1098 error_setg(errp,
1099 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1100 shift, rc);
1101 }
1102
1103 spapr->htab_shift = shift;
1104 spapr->htab = NULL;
1105 } else {
1106 /* kernel-side HPT not needed, allocate in userspace instead */
1107 size_t size = 1ULL << shift;
1108 int i;
1109
1110 spapr->htab = qemu_memalign(size, size);
1111 if (!spapr->htab) {
1112 error_setg_errno(errp, errno,
1113 "Could not allocate HPT of order %d", shift);
1114 return;
1115 }
1116
1117 memset(spapr->htab, 0, size);
1118 spapr->htab_shift = shift;
1119
1120 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1121 DIRTY_HPTE(HPTE(spapr->htab, i));
1122 }
1123 }
1124 }
1125
1126 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1127 {
1128 bool matched = false;
1129
1130 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1131 matched = true;
1132 }
1133
1134 if (!matched) {
1135 error_report("Device %s is not supported by this machine yet.",
1136 qdev_fw_name(DEVICE(sbdev)));
1137 exit(1);
1138 }
1139 }
1140
1141 static void ppc_spapr_reset(void)
1142 {
1143 MachineState *machine = MACHINE(qdev_get_machine());
1144 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1145 PowerPCCPU *first_ppc_cpu;
1146 uint32_t rtas_limit;
1147
1148 /* Check for unknown sysbus devices */
1149 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1150
1151 /* Allocate and/or reset the hash page table */
1152 spapr_reallocate_hpt(spapr,
1153 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1154 &error_fatal);
1155
1156 /* Update the RMA size if necessary */
1157 if (spapr->vrma_adjust) {
1158 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1159 spapr->htab_shift);
1160 }
1161
1162 qemu_devices_reset();
1163
1164 /*
1165 * We place the device tree and RTAS just below either the top of the RMA,
1166 * or just below 2GB, whichever is lowere, so that it can be
1167 * processed with 32-bit real mode code if necessary
1168 */
1169 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1170 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1171 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1172
1173 /* Load the fdt */
1174 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1175 spapr->rtas_size);
1176
1177 /* Copy RTAS over */
1178 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1179 spapr->rtas_size);
1180
1181 /* Set up the entry state */
1182 first_ppc_cpu = POWERPC_CPU(first_cpu);
1183 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1184 first_ppc_cpu->env.gpr[5] = 0;
1185 first_cpu->halted = 0;
1186 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1187
1188 }
1189
1190 static void spapr_create_nvram(sPAPRMachineState *spapr)
1191 {
1192 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1193 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1194
1195 if (dinfo) {
1196 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1197 &error_fatal);
1198 }
1199
1200 qdev_init_nofail(dev);
1201
1202 spapr->nvram = (struct sPAPRNVRAM *)dev;
1203 }
1204
1205 static void spapr_rtc_create(sPAPRMachineState *spapr)
1206 {
1207 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1208
1209 qdev_init_nofail(dev);
1210 spapr->rtc = dev;
1211
1212 object_property_add_alias(qdev_get_machine(), "rtc-time",
1213 OBJECT(spapr->rtc), "date", NULL);
1214 }
1215
1216 /* Returns whether we want to use VGA or not */
1217 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1218 {
1219 switch (vga_interface_type) {
1220 case VGA_NONE:
1221 return false;
1222 case VGA_DEVICE:
1223 return true;
1224 case VGA_STD:
1225 case VGA_VIRTIO:
1226 return pci_vga_init(pci_bus) != NULL;
1227 default:
1228 error_setg(errp,
1229 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1230 return false;
1231 }
1232 }
1233
1234 static int spapr_post_load(void *opaque, int version_id)
1235 {
1236 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1237 int err = 0;
1238
1239 /* In earlier versions, there was no separate qdev for the PAPR
1240 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1241 * So when migrating from those versions, poke the incoming offset
1242 * value into the RTC device */
1243 if (version_id < 3) {
1244 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1245 }
1246
1247 return err;
1248 }
1249
1250 static bool version_before_3(void *opaque, int version_id)
1251 {
1252 return version_id < 3;
1253 }
1254
1255 static const VMStateDescription vmstate_spapr = {
1256 .name = "spapr",
1257 .version_id = 3,
1258 .minimum_version_id = 1,
1259 .post_load = spapr_post_load,
1260 .fields = (VMStateField[]) {
1261 /* used to be @next_irq */
1262 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1263
1264 /* RTC offset */
1265 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1266
1267 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1268 VMSTATE_END_OF_LIST()
1269 },
1270 };
1271
1272 static int htab_save_setup(QEMUFile *f, void *opaque)
1273 {
1274 sPAPRMachineState *spapr = opaque;
1275
1276 /* "Iteration" header */
1277 qemu_put_be32(f, spapr->htab_shift);
1278
1279 if (spapr->htab) {
1280 spapr->htab_save_index = 0;
1281 spapr->htab_first_pass = true;
1282 } else {
1283 assert(kvm_enabled());
1284 }
1285
1286
1287 return 0;
1288 }
1289
1290 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1291 int64_t max_ns)
1292 {
1293 bool has_timeout = max_ns != -1;
1294 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1295 int index = spapr->htab_save_index;
1296 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1297
1298 assert(spapr->htab_first_pass);
1299
1300 do {
1301 int chunkstart;
1302
1303 /* Consume invalid HPTEs */
1304 while ((index < htabslots)
1305 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1306 index++;
1307 CLEAN_HPTE(HPTE(spapr->htab, index));
1308 }
1309
1310 /* Consume valid HPTEs */
1311 chunkstart = index;
1312 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1313 && HPTE_VALID(HPTE(spapr->htab, index))) {
1314 index++;
1315 CLEAN_HPTE(HPTE(spapr->htab, index));
1316 }
1317
1318 if (index > chunkstart) {
1319 int n_valid = index - chunkstart;
1320
1321 qemu_put_be32(f, chunkstart);
1322 qemu_put_be16(f, n_valid);
1323 qemu_put_be16(f, 0);
1324 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1325 HASH_PTE_SIZE_64 * n_valid);
1326
1327 if (has_timeout &&
1328 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1329 break;
1330 }
1331 }
1332 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1333
1334 if (index >= htabslots) {
1335 assert(index == htabslots);
1336 index = 0;
1337 spapr->htab_first_pass = false;
1338 }
1339 spapr->htab_save_index = index;
1340 }
1341
1342 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1343 int64_t max_ns)
1344 {
1345 bool final = max_ns < 0;
1346 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1347 int examined = 0, sent = 0;
1348 int index = spapr->htab_save_index;
1349 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1350
1351 assert(!spapr->htab_first_pass);
1352
1353 do {
1354 int chunkstart, invalidstart;
1355
1356 /* Consume non-dirty HPTEs */
1357 while ((index < htabslots)
1358 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1359 index++;
1360 examined++;
1361 }
1362
1363 chunkstart = index;
1364 /* Consume valid dirty HPTEs */
1365 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1366 && HPTE_DIRTY(HPTE(spapr->htab, index))
1367 && HPTE_VALID(HPTE(spapr->htab, index))) {
1368 CLEAN_HPTE(HPTE(spapr->htab, index));
1369 index++;
1370 examined++;
1371 }
1372
1373 invalidstart = index;
1374 /* Consume invalid dirty HPTEs */
1375 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1376 && HPTE_DIRTY(HPTE(spapr->htab, index))
1377 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1378 CLEAN_HPTE(HPTE(spapr->htab, index));
1379 index++;
1380 examined++;
1381 }
1382
1383 if (index > chunkstart) {
1384 int n_valid = invalidstart - chunkstart;
1385 int n_invalid = index - invalidstart;
1386
1387 qemu_put_be32(f, chunkstart);
1388 qemu_put_be16(f, n_valid);
1389 qemu_put_be16(f, n_invalid);
1390 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1391 HASH_PTE_SIZE_64 * n_valid);
1392 sent += index - chunkstart;
1393
1394 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1395 break;
1396 }
1397 }
1398
1399 if (examined >= htabslots) {
1400 break;
1401 }
1402
1403 if (index >= htabslots) {
1404 assert(index == htabslots);
1405 index = 0;
1406 }
1407 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1408
1409 if (index >= htabslots) {
1410 assert(index == htabslots);
1411 index = 0;
1412 }
1413
1414 spapr->htab_save_index = index;
1415
1416 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1417 }
1418
1419 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1420 #define MAX_KVM_BUF_SIZE 2048
1421
1422 static int htab_save_iterate(QEMUFile *f, void *opaque)
1423 {
1424 sPAPRMachineState *spapr = opaque;
1425 int fd;
1426 int rc = 0;
1427
1428 /* Iteration header */
1429 qemu_put_be32(f, 0);
1430
1431 if (!spapr->htab) {
1432 assert(kvm_enabled());
1433
1434 fd = get_htab_fd(spapr);
1435 if (fd < 0) {
1436 return fd;
1437 }
1438
1439 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1440 if (rc < 0) {
1441 return rc;
1442 }
1443 } else if (spapr->htab_first_pass) {
1444 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1445 } else {
1446 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1447 }
1448
1449 /* End marker */
1450 qemu_put_be32(f, 0);
1451 qemu_put_be16(f, 0);
1452 qemu_put_be16(f, 0);
1453
1454 return rc;
1455 }
1456
1457 static int htab_save_complete(QEMUFile *f, void *opaque)
1458 {
1459 sPAPRMachineState *spapr = opaque;
1460 int fd;
1461
1462 /* Iteration header */
1463 qemu_put_be32(f, 0);
1464
1465 if (!spapr->htab) {
1466 int rc;
1467
1468 assert(kvm_enabled());
1469
1470 fd = get_htab_fd(spapr);
1471 if (fd < 0) {
1472 return fd;
1473 }
1474
1475 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1476 if (rc < 0) {
1477 return rc;
1478 }
1479 } else {
1480 if (spapr->htab_first_pass) {
1481 htab_save_first_pass(f, spapr, -1);
1482 }
1483 htab_save_later_pass(f, spapr, -1);
1484 }
1485
1486 /* End marker */
1487 qemu_put_be32(f, 0);
1488 qemu_put_be16(f, 0);
1489 qemu_put_be16(f, 0);
1490
1491 return 0;
1492 }
1493
1494 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1495 {
1496 sPAPRMachineState *spapr = opaque;
1497 uint32_t section_hdr;
1498 int fd = -1;
1499
1500 if (version_id < 1 || version_id > 1) {
1501 error_report("htab_load() bad version");
1502 return -EINVAL;
1503 }
1504
1505 section_hdr = qemu_get_be32(f);
1506
1507 if (section_hdr) {
1508 Error *local_err = NULL;
1509
1510 /* First section gives the htab size */
1511 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1512 if (local_err) {
1513 error_report_err(local_err);
1514 return -EINVAL;
1515 }
1516 return 0;
1517 }
1518
1519 if (!spapr->htab) {
1520 assert(kvm_enabled());
1521
1522 fd = kvmppc_get_htab_fd(true);
1523 if (fd < 0) {
1524 error_report("Unable to open fd to restore KVM hash table: %s",
1525 strerror(errno));
1526 }
1527 }
1528
1529 while (true) {
1530 uint32_t index;
1531 uint16_t n_valid, n_invalid;
1532
1533 index = qemu_get_be32(f);
1534 n_valid = qemu_get_be16(f);
1535 n_invalid = qemu_get_be16(f);
1536
1537 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1538 /* End of Stream */
1539 break;
1540 }
1541
1542 if ((index + n_valid + n_invalid) >
1543 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1544 /* Bad index in stream */
1545 error_report(
1546 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1547 index, n_valid, n_invalid, spapr->htab_shift);
1548 return -EINVAL;
1549 }
1550
1551 if (spapr->htab) {
1552 if (n_valid) {
1553 qemu_get_buffer(f, HPTE(spapr->htab, index),
1554 HASH_PTE_SIZE_64 * n_valid);
1555 }
1556 if (n_invalid) {
1557 memset(HPTE(spapr->htab, index + n_valid), 0,
1558 HASH_PTE_SIZE_64 * n_invalid);
1559 }
1560 } else {
1561 int rc;
1562
1563 assert(fd >= 0);
1564
1565 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1566 if (rc < 0) {
1567 return rc;
1568 }
1569 }
1570 }
1571
1572 if (!spapr->htab) {
1573 assert(fd >= 0);
1574 close(fd);
1575 }
1576
1577 return 0;
1578 }
1579
1580 static void htab_cleanup(void *opaque)
1581 {
1582 sPAPRMachineState *spapr = opaque;
1583
1584 close_htab_fd(spapr);
1585 }
1586
1587 static SaveVMHandlers savevm_htab_handlers = {
1588 .save_live_setup = htab_save_setup,
1589 .save_live_iterate = htab_save_iterate,
1590 .save_live_complete_precopy = htab_save_complete,
1591 .cleanup = htab_cleanup,
1592 .load_state = htab_load,
1593 };
1594
1595 static void spapr_boot_set(void *opaque, const char *boot_device,
1596 Error **errp)
1597 {
1598 MachineState *machine = MACHINE(qdev_get_machine());
1599 machine->boot_order = g_strdup(boot_device);
1600 }
1601
1602 /*
1603 * Reset routine for LMB DR devices.
1604 *
1605 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1606 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1607 * when it walks all its children devices. LMB devices reset occurs
1608 * as part of spapr_ppc_reset().
1609 */
1610 static void spapr_drc_reset(void *opaque)
1611 {
1612 sPAPRDRConnector *drc = opaque;
1613 DeviceState *d = DEVICE(drc);
1614
1615 if (d) {
1616 device_reset(d);
1617 }
1618 }
1619
1620 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1621 {
1622 MachineState *machine = MACHINE(spapr);
1623 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1624 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1625 int i;
1626
1627 for (i = 0; i < nr_lmbs; i++) {
1628 sPAPRDRConnector *drc;
1629 uint64_t addr;
1630
1631 addr = i * lmb_size + spapr->hotplug_memory.base;
1632 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1633 addr/lmb_size);
1634 qemu_register_reset(spapr_drc_reset, drc);
1635 }
1636 }
1637
1638 /*
1639 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1640 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1641 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1642 */
1643 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1644 {
1645 int i;
1646
1647 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1648 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1649 " is not aligned to %llu MiB",
1650 machine->ram_size,
1651 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1652 return;
1653 }
1654
1655 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1656 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1657 " is not aligned to %llu MiB",
1658 machine->ram_size,
1659 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1660 return;
1661 }
1662
1663 for (i = 0; i < nb_numa_nodes; i++) {
1664 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1665 error_setg(errp,
1666 "Node %d memory size 0x%" PRIx64
1667 " is not aligned to %llu MiB",
1668 i, numa_info[i].node_mem,
1669 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1670 return;
1671 }
1672 }
1673 }
1674
1675 /* pSeries LPAR / sPAPR hardware init */
1676 static void ppc_spapr_init(MachineState *machine)
1677 {
1678 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1679 MachineClass *mc = MACHINE_GET_CLASS(machine);
1680 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1681 const char *kernel_filename = machine->kernel_filename;
1682 const char *kernel_cmdline = machine->kernel_cmdline;
1683 const char *initrd_filename = machine->initrd_filename;
1684 PCIHostState *phb;
1685 int i;
1686 MemoryRegion *sysmem = get_system_memory();
1687 MemoryRegion *ram = g_new(MemoryRegion, 1);
1688 MemoryRegion *rma_region;
1689 void *rma = NULL;
1690 hwaddr rma_alloc_size;
1691 hwaddr node0_size = spapr_node0_size();
1692 uint32_t initrd_base = 0;
1693 long kernel_size = 0, initrd_size = 0;
1694 long load_limit, fw_size;
1695 bool kernel_le = false;
1696 char *filename;
1697 int smt = kvmppc_smt_threads();
1698 int spapr_cores = smp_cpus / smp_threads;
1699 int spapr_max_cores = max_cpus / smp_threads;
1700
1701 if (mc->query_hotpluggable_cpus) {
1702 if (smp_cpus % smp_threads) {
1703 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1704 smp_cpus, smp_threads);
1705 exit(1);
1706 }
1707 if (max_cpus % smp_threads) {
1708 error_report("max_cpus (%u) must be multiple of threads (%u)",
1709 max_cpus, smp_threads);
1710 exit(1);
1711 }
1712 }
1713
1714 msi_nonbroken = true;
1715
1716 QLIST_INIT(&spapr->phbs);
1717
1718 cpu_ppc_hypercall = emulate_spapr_hypercall;
1719
1720 /* Allocate RMA if necessary */
1721 rma_alloc_size = kvmppc_alloc_rma(&rma);
1722
1723 if (rma_alloc_size == -1) {
1724 error_report("Unable to create RMA");
1725 exit(1);
1726 }
1727
1728 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1729 spapr->rma_size = rma_alloc_size;
1730 } else {
1731 spapr->rma_size = node0_size;
1732
1733 /* With KVM, we don't actually know whether KVM supports an
1734 * unbounded RMA (PR KVM) or is limited by the hash table size
1735 * (HV KVM using VRMA), so we always assume the latter
1736 *
1737 * In that case, we also limit the initial allocations for RTAS
1738 * etc... to 256M since we have no way to know what the VRMA size
1739 * is going to be as it depends on the size of the hash table
1740 * isn't determined yet.
1741 */
1742 if (kvm_enabled()) {
1743 spapr->vrma_adjust = 1;
1744 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1745 }
1746
1747 /* Actually we don't support unbounded RMA anymore since we
1748 * added proper emulation of HV mode. The max we can get is
1749 * 16G which also happens to be what we configure for PAPR
1750 * mode so make sure we don't do anything bigger than that
1751 */
1752 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
1753 }
1754
1755 if (spapr->rma_size > node0_size) {
1756 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1757 spapr->rma_size);
1758 exit(1);
1759 }
1760
1761 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1762 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
1763
1764 /* Set up Interrupt Controller before we create the VCPUs */
1765 spapr->xics = xics_system_init(machine,
1766 DIV_ROUND_UP(max_cpus * smt, smp_threads),
1767 XICS_IRQS_SPAPR, &error_fatal);
1768
1769 if (smc->dr_lmb_enabled) {
1770 spapr_validate_node_memory(machine, &error_fatal);
1771 }
1772
1773 /* init CPUs */
1774 if (machine->cpu_model == NULL) {
1775 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
1776 }
1777
1778 ppc_cpu_parse_features(machine->cpu_model);
1779
1780 if (mc->query_hotpluggable_cpus) {
1781 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1782
1783 if (type == NULL) {
1784 error_report("Unable to find sPAPR CPU Core definition");
1785 exit(1);
1786 }
1787
1788 spapr->cores = g_new0(Object *, spapr_max_cores);
1789 for (i = 0; i < spapr_max_cores; i++) {
1790 int core_id = i * smp_threads;
1791 sPAPRDRConnector *drc =
1792 spapr_dr_connector_new(OBJECT(spapr),
1793 SPAPR_DR_CONNECTOR_TYPE_CPU,
1794 (core_id / smp_threads) * smt);
1795
1796 qemu_register_reset(spapr_drc_reset, drc);
1797
1798 if (i < spapr_cores) {
1799 Object *core = object_new(type);
1800 object_property_set_int(core, smp_threads, "nr-threads",
1801 &error_fatal);
1802 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
1803 &error_fatal);
1804 object_property_set_bool(core, true, "realized", &error_fatal);
1805 }
1806 }
1807 g_free(type);
1808 } else {
1809 for (i = 0; i < smp_cpus; i++) {
1810 PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model);
1811 if (cpu == NULL) {
1812 error_report("Unable to find PowerPC CPU definition");
1813 exit(1);
1814 }
1815 spapr_cpu_init(spapr, cpu, &error_fatal);
1816 }
1817 }
1818
1819 if (kvm_enabled()) {
1820 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1821 kvmppc_enable_logical_ci_hcalls();
1822 kvmppc_enable_set_mode_hcall();
1823
1824 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
1825 kvmppc_enable_clear_ref_mod_hcalls();
1826 }
1827
1828 /* allocate RAM */
1829 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
1830 machine->ram_size);
1831 memory_region_add_subregion(sysmem, 0, ram);
1832
1833 if (rma_alloc_size && rma) {
1834 rma_region = g_new(MemoryRegion, 1);
1835 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1836 rma_alloc_size, rma);
1837 vmstate_register_ram_global(rma_region);
1838 memory_region_add_subregion(sysmem, 0, rma_region);
1839 }
1840
1841 /* initialize hotplug memory address space */
1842 if (machine->ram_size < machine->maxram_size) {
1843 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
1844 /*
1845 * Limit the number of hotpluggable memory slots to half the number
1846 * slots that KVM supports, leaving the other half for PCI and other
1847 * devices. However ensure that number of slots doesn't drop below 32.
1848 */
1849 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
1850 SPAPR_MAX_RAM_SLOTS;
1851
1852 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
1853 max_memslots = SPAPR_MAX_RAM_SLOTS;
1854 }
1855 if (machine->ram_slots > max_memslots) {
1856 error_report("Specified number of memory slots %"
1857 PRIu64" exceeds max supported %d",
1858 machine->ram_slots, max_memslots);
1859 exit(1);
1860 }
1861
1862 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1863 SPAPR_HOTPLUG_MEM_ALIGN);
1864 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1865 "hotplug-memory", hotplug_mem_size);
1866 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1867 &spapr->hotplug_memory.mr);
1868 }
1869
1870 if (smc->dr_lmb_enabled) {
1871 spapr_create_lmb_dr_connectors(spapr);
1872 }
1873
1874 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1875 if (!filename) {
1876 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
1877 exit(1);
1878 }
1879 spapr->rtas_size = get_image_size(filename);
1880 if (spapr->rtas_size < 0) {
1881 error_report("Could not get size of LPAR rtas '%s'", filename);
1882 exit(1);
1883 }
1884 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1885 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
1886 error_report("Could not load LPAR rtas '%s'", filename);
1887 exit(1);
1888 }
1889 if (spapr->rtas_size > RTAS_MAX_SIZE) {
1890 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1891 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
1892 exit(1);
1893 }
1894 g_free(filename);
1895
1896 /* Set up EPOW events infrastructure */
1897 spapr_events_init(spapr);
1898
1899 /* Set up the RTC RTAS interfaces */
1900 spapr_rtc_create(spapr);
1901
1902 /* Set up VIO bus */
1903 spapr->vio_bus = spapr_vio_bus_init();
1904
1905 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
1906 if (serial_hds[i]) {
1907 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
1908 }
1909 }
1910
1911 /* We always have at least the nvram device on VIO */
1912 spapr_create_nvram(spapr);
1913
1914 /* Set up PCI */
1915 spapr_pci_rtas_init();
1916
1917 phb = spapr_create_phb(spapr, 0);
1918
1919 for (i = 0; i < nb_nics; i++) {
1920 NICInfo *nd = &nd_table[i];
1921
1922 if (!nd->model) {
1923 nd->model = g_strdup("ibmveth");
1924 }
1925
1926 if (strcmp(nd->model, "ibmveth") == 0) {
1927 spapr_vlan_create(spapr->vio_bus, nd);
1928 } else {
1929 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
1930 }
1931 }
1932
1933 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
1934 spapr_vscsi_create(spapr->vio_bus);
1935 }
1936
1937 /* Graphics */
1938 if (spapr_vga_init(phb->bus, &error_fatal)) {
1939 spapr->has_graphics = true;
1940 machine->usb |= defaults_enabled() && !machine->usb_disabled;
1941 }
1942
1943 if (machine->usb) {
1944 if (smc->use_ohci_by_default) {
1945 pci_create_simple(phb->bus, -1, "pci-ohci");
1946 } else {
1947 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1948 }
1949
1950 if (spapr->has_graphics) {
1951 USBBus *usb_bus = usb_bus_find(-1);
1952
1953 usb_create_simple(usb_bus, "usb-kbd");
1954 usb_create_simple(usb_bus, "usb-mouse");
1955 }
1956 }
1957
1958 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
1959 error_report(
1960 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
1961 MIN_RMA_SLOF);
1962 exit(1);
1963 }
1964
1965 if (kernel_filename) {
1966 uint64_t lowaddr = 0;
1967
1968 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
1969 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
1970 0, 0);
1971 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
1972 kernel_size = load_elf(kernel_filename,
1973 translate_kernel_address, NULL,
1974 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE,
1975 0, 0);
1976 kernel_le = kernel_size > 0;
1977 }
1978 if (kernel_size < 0) {
1979 error_report("error loading %s: %s",
1980 kernel_filename, load_elf_strerror(kernel_size));
1981 exit(1);
1982 }
1983
1984 /* load initrd */
1985 if (initrd_filename) {
1986 /* Try to locate the initrd in the gap between the kernel
1987 * and the firmware. Add a bit of space just in case
1988 */
1989 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
1990 initrd_size = load_image_targphys(initrd_filename, initrd_base,
1991 load_limit - initrd_base);
1992 if (initrd_size < 0) {
1993 error_report("could not load initial ram disk '%s'",
1994 initrd_filename);
1995 exit(1);
1996 }
1997 } else {
1998 initrd_base = 0;
1999 initrd_size = 0;
2000 }
2001 }
2002
2003 if (bios_name == NULL) {
2004 bios_name = FW_FILE_NAME;
2005 }
2006 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2007 if (!filename) {
2008 error_report("Could not find LPAR firmware '%s'", bios_name);
2009 exit(1);
2010 }
2011 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2012 if (fw_size <= 0) {
2013 error_report("Could not load LPAR firmware '%s'", filename);
2014 exit(1);
2015 }
2016 g_free(filename);
2017
2018 /* FIXME: Should register things through the MachineState's qdev
2019 * interface, this is a legacy from the sPAPREnvironment structure
2020 * which predated MachineState but had a similar function */
2021 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2022 register_savevm_live(NULL, "spapr/htab", -1, 1,
2023 &savevm_htab_handlers, spapr);
2024
2025 /* Prepare the device tree */
2026 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
2027 kernel_size, kernel_le,
2028 kernel_cmdline,
2029 spapr->check_exception_irq);
2030 assert(spapr->fdt_skel != NULL);
2031
2032 /* used by RTAS */
2033 QTAILQ_INIT(&spapr->ccs_list);
2034 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2035
2036 qemu_register_boot_set(spapr_boot_set, spapr);
2037 }
2038
2039 static int spapr_kvm_type(const char *vm_type)
2040 {
2041 if (!vm_type) {
2042 return 0;
2043 }
2044
2045 if (!strcmp(vm_type, "HV")) {
2046 return 1;
2047 }
2048
2049 if (!strcmp(vm_type, "PR")) {
2050 return 2;
2051 }
2052
2053 error_report("Unknown kvm-type specified '%s'", vm_type);
2054 exit(1);
2055 }
2056
2057 /*
2058 * Implementation of an interface to adjust firmware path
2059 * for the bootindex property handling.
2060 */
2061 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2062 DeviceState *dev)
2063 {
2064 #define CAST(type, obj, name) \
2065 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2066 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2067 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2068
2069 if (d) {
2070 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2071 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2072 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2073
2074 if (spapr) {
2075 /*
2076 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2077 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2078 * in the top 16 bits of the 64-bit LUN
2079 */
2080 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2081 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2082 (uint64_t)id << 48);
2083 } else if (virtio) {
2084 /*
2085 * We use SRP luns of the form 01000000 | (target << 8) | lun
2086 * in the top 32 bits of the 64-bit LUN
2087 * Note: the quote above is from SLOF and it is wrong,
2088 * the actual binding is:
2089 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2090 */
2091 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2092 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2093 (uint64_t)id << 32);
2094 } else if (usb) {
2095 /*
2096 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2097 * in the top 32 bits of the 64-bit LUN
2098 */
2099 unsigned usb_port = atoi(usb->port->path);
2100 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2101 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2102 (uint64_t)id << 32);
2103 }
2104 }
2105
2106 if (phb) {
2107 /* Replace "pci" with "pci@800000020000000" */
2108 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2109 }
2110
2111 return NULL;
2112 }
2113
2114 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2115 {
2116 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2117
2118 return g_strdup(spapr->kvm_type);
2119 }
2120
2121 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2122 {
2123 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2124
2125 g_free(spapr->kvm_type);
2126 spapr->kvm_type = g_strdup(value);
2127 }
2128
2129 static void spapr_machine_initfn(Object *obj)
2130 {
2131 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2132
2133 spapr->htab_fd = -1;
2134 object_property_add_str(obj, "kvm-type",
2135 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2136 object_property_set_description(obj, "kvm-type",
2137 "Specifies the KVM virtualization mode (HV, PR)",
2138 NULL);
2139 }
2140
2141 static void spapr_machine_finalizefn(Object *obj)
2142 {
2143 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2144
2145 g_free(spapr->kvm_type);
2146 }
2147
2148 static void ppc_cpu_do_nmi_on_cpu(CPUState *cs, void *arg)
2149 {
2150 cpu_synchronize_state(cs);
2151 ppc_cpu_do_system_reset(cs);
2152 }
2153
2154 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2155 {
2156 CPUState *cs;
2157
2158 CPU_FOREACH(cs) {
2159 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, NULL);
2160 }
2161 }
2162
2163 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2164 uint32_t node, Error **errp)
2165 {
2166 sPAPRDRConnector *drc;
2167 sPAPRDRConnectorClass *drck;
2168 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2169 int i, fdt_offset, fdt_size;
2170 void *fdt;
2171
2172 for (i = 0; i < nr_lmbs; i++) {
2173 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2174 addr/SPAPR_MEMORY_BLOCK_SIZE);
2175 g_assert(drc);
2176
2177 fdt = create_device_tree(&fdt_size);
2178 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2179 SPAPR_MEMORY_BLOCK_SIZE);
2180
2181 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2182 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2183 addr += SPAPR_MEMORY_BLOCK_SIZE;
2184 }
2185 /* send hotplug notification to the
2186 * guest only in case of hotplugged memory
2187 */
2188 if (dev->hotplugged) {
2189 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2190 }
2191 }
2192
2193 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2194 uint32_t node, Error **errp)
2195 {
2196 Error *local_err = NULL;
2197 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2198 PCDIMMDevice *dimm = PC_DIMM(dev);
2199 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2200 MemoryRegion *mr = ddc->get_memory_region(dimm);
2201 uint64_t align = memory_region_get_alignment(mr);
2202 uint64_t size = memory_region_size(mr);
2203 uint64_t addr;
2204
2205 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2206 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2207 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2208 goto out;
2209 }
2210
2211 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2212 if (local_err) {
2213 goto out;
2214 }
2215
2216 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2217 if (local_err) {
2218 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2219 goto out;
2220 }
2221
2222 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2223
2224 out:
2225 error_propagate(errp, local_err);
2226 }
2227
2228 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2229 sPAPRMachineState *spapr)
2230 {
2231 PowerPCCPU *cpu = POWERPC_CPU(cs);
2232 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2233 int id = ppc_get_vcpu_dt_id(cpu);
2234 void *fdt;
2235 int offset, fdt_size;
2236 char *nodename;
2237
2238 fdt = create_device_tree(&fdt_size);
2239 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2240 offset = fdt_add_subnode(fdt, 0, nodename);
2241
2242 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2243 g_free(nodename);
2244
2245 *fdt_offset = offset;
2246 return fdt;
2247 }
2248
2249 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2250 DeviceState *dev, Error **errp)
2251 {
2252 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2253
2254 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2255 int node;
2256
2257 if (!smc->dr_lmb_enabled) {
2258 error_setg(errp, "Memory hotplug not supported for this machine");
2259 return;
2260 }
2261 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2262 if (*errp) {
2263 return;
2264 }
2265 if (node < 0 || node >= MAX_NODES) {
2266 error_setg(errp, "Invaild node %d", node);
2267 return;
2268 }
2269
2270 /*
2271 * Currently PowerPC kernel doesn't allow hot-adding memory to
2272 * memory-less node, but instead will silently add the memory
2273 * to the first node that has some memory. This causes two
2274 * unexpected behaviours for the user.
2275 *
2276 * - Memory gets hotplugged to a different node than what the user
2277 * specified.
2278 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2279 * to memory-less node, a reboot will set things accordingly
2280 * and the previously hotplugged memory now ends in the right node.
2281 * This appears as if some memory moved from one node to another.
2282 *
2283 * So until kernel starts supporting memory hotplug to memory-less
2284 * nodes, just prevent such attempts upfront in QEMU.
2285 */
2286 if (nb_numa_nodes && !numa_info[node].node_mem) {
2287 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2288 node);
2289 return;
2290 }
2291
2292 spapr_memory_plug(hotplug_dev, dev, node, errp);
2293 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2294 spapr_core_plug(hotplug_dev, dev, errp);
2295 }
2296 }
2297
2298 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2299 DeviceState *dev, Error **errp)
2300 {
2301 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2302
2303 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2304 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2305 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2306 if (!mc->query_hotpluggable_cpus) {
2307 error_setg(errp, "CPU hot unplug not supported on this machine");
2308 return;
2309 }
2310 spapr_core_unplug(hotplug_dev, dev, errp);
2311 }
2312 }
2313
2314 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2315 DeviceState *dev, Error **errp)
2316 {
2317 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2318 spapr_core_pre_plug(hotplug_dev, dev, errp);
2319 }
2320 }
2321
2322 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
2323 DeviceState *dev)
2324 {
2325 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2326 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2327 return HOTPLUG_HANDLER(machine);
2328 }
2329 return NULL;
2330 }
2331
2332 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2333 {
2334 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2335 * socket means much for the paravirtualized PAPR platform) */
2336 return cpu_index / smp_threads / smp_cores;
2337 }
2338
2339 static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
2340 {
2341 int i;
2342 HotpluggableCPUList *head = NULL;
2343 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2344 int spapr_max_cores = max_cpus / smp_threads;
2345
2346 for (i = 0; i < spapr_max_cores; i++) {
2347 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
2348 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
2349 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
2350
2351 cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model);
2352 cpu_item->vcpus_count = smp_threads;
2353 cpu_props->has_core_id = true;
2354 cpu_props->core_id = i * smp_threads;
2355 /* TODO: add 'has_node/node' here to describe
2356 to which node core belongs */
2357
2358 cpu_item->props = cpu_props;
2359 if (spapr->cores[i]) {
2360 cpu_item->has_qom_path = true;
2361 cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]);
2362 }
2363 list_item->value = cpu_item;
2364 list_item->next = head;
2365 head = list_item;
2366 }
2367 return head;
2368 }
2369
2370 static void spapr_machine_class_init(ObjectClass *oc, void *data)
2371 {
2372 MachineClass *mc = MACHINE_CLASS(oc);
2373 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2374 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
2375 NMIClass *nc = NMI_CLASS(oc);
2376 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2377
2378 mc->desc = "pSeries Logical Partition (PAPR compliant)";
2379
2380 /*
2381 * We set up the default / latest behaviour here. The class_init
2382 * functions for the specific versioned machine types can override
2383 * these details for backwards compatibility
2384 */
2385 mc->init = ppc_spapr_init;
2386 mc->reset = ppc_spapr_reset;
2387 mc->block_default_type = IF_SCSI;
2388 mc->max_cpus = MAX_CPUMASK_BITS;
2389 mc->no_parallel = 1;
2390 mc->default_boot_order = "";
2391 mc->default_ram_size = 512 * M_BYTE;
2392 mc->kvm_type = spapr_kvm_type;
2393 mc->has_dynamic_sysbus = true;
2394 mc->pci_allow_0_address = true;
2395 mc->get_hotplug_handler = spapr_get_hotplug_handler;
2396 hc->pre_plug = spapr_machine_device_pre_plug;
2397 hc->plug = spapr_machine_device_plug;
2398 hc->unplug = spapr_machine_device_unplug;
2399 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
2400
2401 smc->dr_lmb_enabled = true;
2402 mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus;
2403 fwc->get_dev_path = spapr_get_fw_dev_path;
2404 nc->nmi_monitor_handler = spapr_nmi;
2405 }
2406
2407 static const TypeInfo spapr_machine_info = {
2408 .name = TYPE_SPAPR_MACHINE,
2409 .parent = TYPE_MACHINE,
2410 .abstract = true,
2411 .instance_size = sizeof(sPAPRMachineState),
2412 .instance_init = spapr_machine_initfn,
2413 .instance_finalize = spapr_machine_finalizefn,
2414 .class_size = sizeof(sPAPRMachineClass),
2415 .class_init = spapr_machine_class_init,
2416 .interfaces = (InterfaceInfo[]) {
2417 { TYPE_FW_PATH_PROVIDER },
2418 { TYPE_NMI },
2419 { TYPE_HOTPLUG_HANDLER },
2420 { }
2421 },
2422 };
2423
2424 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
2425 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2426 void *data) \
2427 { \
2428 MachineClass *mc = MACHINE_CLASS(oc); \
2429 spapr_machine_##suffix##_class_options(mc); \
2430 if (latest) { \
2431 mc->alias = "pseries"; \
2432 mc->is_default = 1; \
2433 } \
2434 } \
2435 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2436 { \
2437 MachineState *machine = MACHINE(obj); \
2438 spapr_machine_##suffix##_instance_options(machine); \
2439 } \
2440 static const TypeInfo spapr_machine_##suffix##_info = { \
2441 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2442 .parent = TYPE_SPAPR_MACHINE, \
2443 .class_init = spapr_machine_##suffix##_class_init, \
2444 .instance_init = spapr_machine_##suffix##_instance_init, \
2445 }; \
2446 static void spapr_machine_register_##suffix(void) \
2447 { \
2448 type_register(&spapr_machine_##suffix##_info); \
2449 } \
2450 type_init(spapr_machine_register_##suffix)
2451
2452 /*
2453 * pseries-2.8
2454 */
2455 static void spapr_machine_2_8_instance_options(MachineState *machine)
2456 {
2457 }
2458
2459 static void spapr_machine_2_8_class_options(MachineClass *mc)
2460 {
2461 /* Defaults for the latest behaviour inherited from the base class */
2462 }
2463
2464 DEFINE_SPAPR_MACHINE(2_8, "2.8", true);
2465
2466 /*
2467 * pseries-2.7
2468 */
2469 #define SPAPR_COMPAT_2_7 \
2470 HW_COMPAT_2_7 \
2471
2472 static void spapr_machine_2_7_instance_options(MachineState *machine)
2473 {
2474 }
2475
2476 static void spapr_machine_2_7_class_options(MachineClass *mc)
2477 {
2478 spapr_machine_2_8_class_options(mc);
2479 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
2480 }
2481
2482 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
2483
2484 /*
2485 * pseries-2.6
2486 */
2487 #define SPAPR_COMPAT_2_6 \
2488 HW_COMPAT_2_6 \
2489 { \
2490 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2491 .property = "ddw",\
2492 .value = stringify(off),\
2493 },
2494
2495 static void spapr_machine_2_6_instance_options(MachineState *machine)
2496 {
2497 }
2498
2499 static void spapr_machine_2_6_class_options(MachineClass *mc)
2500 {
2501 spapr_machine_2_7_class_options(mc);
2502 mc->query_hotpluggable_cpus = NULL;
2503 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
2504 }
2505
2506 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
2507
2508 /*
2509 * pseries-2.5
2510 */
2511 #define SPAPR_COMPAT_2_5 \
2512 HW_COMPAT_2_5 \
2513 { \
2514 .driver = "spapr-vlan", \
2515 .property = "use-rx-buffer-pools", \
2516 .value = "off", \
2517 },
2518
2519 static void spapr_machine_2_5_instance_options(MachineState *machine)
2520 {
2521 }
2522
2523 static void spapr_machine_2_5_class_options(MachineClass *mc)
2524 {
2525 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2526
2527 spapr_machine_2_6_class_options(mc);
2528 smc->use_ohci_by_default = true;
2529 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
2530 }
2531
2532 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
2533
2534 /*
2535 * pseries-2.4
2536 */
2537 #define SPAPR_COMPAT_2_4 \
2538 HW_COMPAT_2_4
2539
2540 static void spapr_machine_2_4_instance_options(MachineState *machine)
2541 {
2542 spapr_machine_2_5_instance_options(machine);
2543 }
2544
2545 static void spapr_machine_2_4_class_options(MachineClass *mc)
2546 {
2547 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2548
2549 spapr_machine_2_5_class_options(mc);
2550 smc->dr_lmb_enabled = false;
2551 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
2552 }
2553
2554 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
2555
2556 /*
2557 * pseries-2.3
2558 */
2559 #define SPAPR_COMPAT_2_3 \
2560 HW_COMPAT_2_3 \
2561 {\
2562 .driver = "spapr-pci-host-bridge",\
2563 .property = "dynamic-reconfiguration",\
2564 .value = "off",\
2565 },
2566
2567 static void spapr_machine_2_3_instance_options(MachineState *machine)
2568 {
2569 spapr_machine_2_4_instance_options(machine);
2570 savevm_skip_section_footers();
2571 global_state_set_optional();
2572 savevm_skip_configuration();
2573 }
2574
2575 static void spapr_machine_2_3_class_options(MachineClass *mc)
2576 {
2577 spapr_machine_2_4_class_options(mc);
2578 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
2579 }
2580 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
2581
2582 /*
2583 * pseries-2.2
2584 */
2585
2586 #define SPAPR_COMPAT_2_2 \
2587 HW_COMPAT_2_2 \
2588 {\
2589 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2590 .property = "mem_win_size",\
2591 .value = "0x20000000",\
2592 },
2593
2594 static void spapr_machine_2_2_instance_options(MachineState *machine)
2595 {
2596 spapr_machine_2_3_instance_options(machine);
2597 machine->suppress_vmdesc = true;
2598 }
2599
2600 static void spapr_machine_2_2_class_options(MachineClass *mc)
2601 {
2602 spapr_machine_2_3_class_options(mc);
2603 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
2604 }
2605 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
2606
2607 /*
2608 * pseries-2.1
2609 */
2610 #define SPAPR_COMPAT_2_1 \
2611 HW_COMPAT_2_1
2612
2613 static void spapr_machine_2_1_instance_options(MachineState *machine)
2614 {
2615 spapr_machine_2_2_instance_options(machine);
2616 }
2617
2618 static void spapr_machine_2_1_class_options(MachineClass *mc)
2619 {
2620 spapr_machine_2_2_class_options(mc);
2621 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
2622 }
2623 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
2624
2625 static void spapr_machine_register_types(void)
2626 {
2627 type_register_static(&spapr_machine_info);
2628 }
2629
2630 type_init(spapr_machine_register_types)
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