target-i386/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "hw/i386/pc.h"
   4 #include "hw/isa/isa.h"
   5
   6 #include "cpu.h"
   7 #include "sysemu/kvm.h"
   8
   9 #include "qemu/error-report.h"
  10
  11 static const VMStateDescription vmstate_segment = {
  12     .name = "segment",
  13     .version_id = 1,
  14     .minimum_version_id = 1,
  15     .fields = (VMStateField[]) {
  16         VMSTATE_UINT32(selector, SegmentCache),
  17         VMSTATE_UINTTL(base, SegmentCache),
  18         VMSTATE_UINT32(limit, SegmentCache),
  19         VMSTATE_UINT32(flags, SegmentCache),
  20         VMSTATE_END_OF_LIST()
  21     }
  22 };
  23
  24 #define VMSTATE_SEGMENT(_field, _state) {                            \
  25     .name       = (stringify(_field)),                               \
  26     .size       = sizeof(SegmentCache),                              \
  27     .vmsd       = &vmstate_segment,                                  \
  28     .flags      = VMS_STRUCT,                                        \
  29     .offset     = offsetof(_state, _field)                           \
  30             + type_check(SegmentCache,typeof_field(_state, _field))  \
  31 }
  32
  33 #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n)                    \
  34     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
  35
  36 static const VMStateDescription vmstate_xmm_reg = {
  37     .name = "xmm_reg",
  38     .version_id = 1,
  39     .minimum_version_id = 1,
  40     .fields = (VMStateField[]) {
  41         VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
  42         VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
  43         VMSTATE_END_OF_LIST()
  44     }
  45 };
  46
  47 #define VMSTATE_XMM_REGS(_field, _state, _start)                         \
  48     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
  49                              vmstate_xmm_reg, ZMMReg)
  50
  51 /* YMMH format is the same as XMM, but for bits 128-255 */
  52 static const VMStateDescription vmstate_ymmh_reg = {
  53     .name = "ymmh_reg",
  54     .version_id = 1,
  55     .minimum_version_id = 1,
  56     .fields = (VMStateField[]) {
  57         VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
  58         VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
  59         VMSTATE_END_OF_LIST()
  60     }
  61 };
  62
  63 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v)               \
  64     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v,    \
  65                              vmstate_ymmh_reg, ZMMReg)
  66
  67 static const VMStateDescription vmstate_zmmh_reg = {
  68     .name = "zmmh_reg",
  69     .version_id = 1,
  70     .minimum_version_id = 1,
  71     .fields = (VMStateField[]) {
  72         VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
  73         VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
  74         VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
  75         VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
  76         VMSTATE_END_OF_LIST()
  77     }
  78 };
  79
  80 #define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start)                   \
  81     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
  82                              vmstate_zmmh_reg, ZMMReg)
  83
  84 #ifdef TARGET_X86_64
  85 static const VMStateDescription vmstate_hi16_zmm_reg = {
  86     .name = "hi16_zmm_reg",
  87     .version_id = 1,
  88     .minimum_version_id = 1,
  89     .fields = (VMStateField[]) {
  90         VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
  91         VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
  92         VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
  93         VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
  94         VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
  95         VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
  96         VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
  97         VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
  98         VMSTATE_END_OF_LIST()
  99     }
 100 };
 101
 102 #define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start)               \
 103     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
 104                              vmstate_hi16_zmm_reg, ZMMReg)
 105 #endif
 106
 107 static const VMStateDescription vmstate_bnd_regs = {
 108     .name = "bnd_regs",
 109     .version_id = 1,
 110     .minimum_version_id = 1,
 111     .fields = (VMStateField[]) {
 112         VMSTATE_UINT64(lb, BNDReg),
 113         VMSTATE_UINT64(ub, BNDReg),
 114         VMSTATE_END_OF_LIST()
 115     }
 116 };
 117
 118 #define VMSTATE_BND_REGS(_field, _state, _n)          \
 119     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg)
 120
 121 static const VMStateDescription vmstate_mtrr_var = {
 122     .name = "mtrr_var",
 123     .version_id = 1,
 124     .minimum_version_id = 1,
 125     .fields = (VMStateField[]) {
 126         VMSTATE_UINT64(base, MTRRVar),
 127         VMSTATE_UINT64(mask, MTRRVar),
 128         VMSTATE_END_OF_LIST()
 129     }
 130 };
 131
 132 #define VMSTATE_MTRR_VARS(_field, _state, _n, _v)                    \
 133     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
 134
 135 static void put_fpreg_error(QEMUFile *f, void *opaque, size_t size)
 136 {
 137     fprintf(stderr, "call put_fpreg() with invalid arguments\n");
 138     exit(0);
 139 }
 140
 141 /* XXX: add that in a FPU generic layer */
 142 union x86_longdouble {
 143     uint64_t mant;
 144     uint16_t exp;
 145 };
 146
 147 #define MANTD1(fp)      (fp & ((1LL << 52) - 1))
 148 #define EXPBIAS1 1023
 149 #define EXPD1(fp)       ((fp >> 52) & 0x7FF)
 150 #define SIGND1(fp)      ((fp >> 32) & 0x80000000)
 151
 152 static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
 153 {
 154     int e;
 155     /* mantissa */
 156     p->mant = (MANTD1(temp) << 11) | (1LL << 63);
 157     /* exponent + sign */
 158     e = EXPD1(temp) - EXPBIAS1 + 16383;
 159     e |= SIGND1(temp) >> 16;
 160     p->exp = e;
 161 }
 162
 163 static int get_fpreg(QEMUFile *f, void *opaque, size_t size)
 164 {
 165     FPReg *fp_reg = opaque;
 166     uint64_t mant;
 167     uint16_t exp;
 168
 169     qemu_get_be64s(f, &mant);
 170     qemu_get_be16s(f, &exp);
 171     fp_reg->d = cpu_set_fp80(mant, exp);
 172     return 0;
 173 }
 174
 175 static void put_fpreg(QEMUFile *f, void *opaque, size_t size)
 176 {
 177     FPReg *fp_reg = opaque;
 178     uint64_t mant;
 179     uint16_t exp;
 180     /* we save the real CPU data (in case of MMX usage only 'mant'
 181        contains the MMX register */
 182     cpu_get_fp80(&mant, &exp, fp_reg->d);
 183     qemu_put_be64s(f, &mant);
 184     qemu_put_be16s(f, &exp);
 185 }
 186
 187 static const VMStateInfo vmstate_fpreg = {
 188     .name = "fpreg",
 189     .get  = get_fpreg,
 190     .put  = put_fpreg,
 191 };
 192
 193 static int get_fpreg_1_mmx(QEMUFile *f, void *opaque, size_t size)
 194 {
 195     union x86_longdouble *p = opaque;
 196     uint64_t mant;
 197
 198     qemu_get_be64s(f, &mant);
 199     p->mant = mant;
 200     p->exp = 0xffff;
 201     return 0;
 202 }
 203
 204 static const VMStateInfo vmstate_fpreg_1_mmx = {
 205     .name = "fpreg_1_mmx",
 206     .get  = get_fpreg_1_mmx,
 207     .put  = put_fpreg_error,
 208 };
 209
 210 static int get_fpreg_1_no_mmx(QEMUFile *f, void *opaque, size_t size)
 211 {
 212     union x86_longdouble *p = opaque;
 213     uint64_t mant;
 214
 215     qemu_get_be64s(f, &mant);
 216     fp64_to_fp80(p, mant);
 217     return 0;
 218 }
 219
 220 static const VMStateInfo vmstate_fpreg_1_no_mmx = {
 221     .name = "fpreg_1_no_mmx",
 222     .get  = get_fpreg_1_no_mmx,
 223     .put  = put_fpreg_error,
 224 };
 225
 226 static bool fpregs_is_0(void *opaque, int version_id)
 227 {
 228     X86CPU *cpu = opaque;
 229     CPUX86State *env = &cpu->env;
 230
 231     return (env->fpregs_format_vmstate == 0);
 232 }
 233
 234 static bool fpregs_is_1_mmx(void *opaque, int version_id)
 235 {
 236     X86CPU *cpu = opaque;
 237     CPUX86State *env = &cpu->env;
 238     int guess_mmx;
 239
 240     guess_mmx = ((env->fptag_vmstate == 0xff) &&
 241                  (env->fpus_vmstate & 0x3800) == 0);
 242     return (guess_mmx && (env->fpregs_format_vmstate == 1));
 243 }
 244
 245 static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
 246 {
 247     X86CPU *cpu = opaque;
 248     CPUX86State *env = &cpu->env;
 249     int guess_mmx;
 250
 251     guess_mmx = ((env->fptag_vmstate == 0xff) &&
 252                  (env->fpus_vmstate & 0x3800) == 0);
 253     return (!guess_mmx && (env->fpregs_format_vmstate == 1));
 254 }
 255
 256 #define VMSTATE_FP_REGS(_field, _state, _n)                               \
 257     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \
 258     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \
 259     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg)
 260
 261 static bool version_is_5(void *opaque, int version_id)
 262 {
 263     return version_id == 5;
 264 }
 265
 266 #ifdef TARGET_X86_64
 267 static bool less_than_7(void *opaque, int version_id)
 268 {
 269     return version_id < 7;
 270 }
 271
 272 static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
 273 {
 274     uint64_t *v = pv;
 275     *v = qemu_get_be32(f);
 276     return 0;
 277 }
 278
 279 static void put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
 280 {
 281     uint64_t *v = pv;
 282     qemu_put_be32(f, *v);
 283 }
 284
 285 static const VMStateInfo vmstate_hack_uint64_as_uint32 = {
 286     .name = "uint64_as_uint32",
 287     .get  = get_uint64_as_uint32,
 288     .put  = put_uint64_as_uint32,
 289 };
 290
 291 #define VMSTATE_HACK_UINT32(_f, _s, _t)                                  \
 292     VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t)
 293 #endif
 294
 295 static void cpu_pre_save(void *opaque)
 296 {
 297     X86CPU *cpu = opaque;
 298     CPUX86State *env = &cpu->env;
 299     int i;
 300
 301     /* FPU */
 302     env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 303     env->fptag_vmstate = 0;
 304     for(i = 0; i < 8; i++) {
 305         env->fptag_vmstate |= ((!env->fptags[i]) << i);
 306     }
 307
 308     env->fpregs_format_vmstate = 0;
 309
 310     /*
 311      * Real mode guest segments register DPL should be zero.
 312      * Older KVM version were setting it wrongly.
 313      * Fixing it will allow live migration to host with unrestricted guest
 314      * support (otherwise the migration will fail with invalid guest state
 315      * error).
 316      */
 317     if (!(env->cr[0] & CR0_PE_MASK) &&
 318         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
 319         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
 320         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
 321         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
 322         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
 323         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
 324         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
 325     }
 326
 327 }
 328
 329 static int cpu_post_load(void *opaque, int version_id)
 330 {
 331     X86CPU *cpu = opaque;
 332     CPUState *cs = CPU(cpu);
 333     CPUX86State *env = &cpu->env;
 334     int i;
 335
 336     if (env->tsc_khz && env->user_tsc_khz &&
 337         env->tsc_khz != env->user_tsc_khz) {
 338         error_report("Mismatch between user-specified TSC frequency and "
 339                      "migrated TSC frequency");
 340         return -EINVAL;
 341     }
 342
 343     /*
 344      * Real mode guest segments register DPL should be zero.
 345      * Older KVM version were setting it wrongly.
 346      * Fixing it will allow live migration from such host that don't have
 347      * restricted guest support to a host with unrestricted guest support
 348      * (otherwise the migration will fail with invalid guest state
 349      * error).
 350      */
 351     if (!(env->cr[0] & CR0_PE_MASK) &&
 352         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
 353         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
 354         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
 355         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
 356         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
 357         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
 358         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
 359     }
 360
 361     /* Older versions of QEMU incorrectly used CS.DPL as the CPL when
 362      * running under KVM.  This is wrong for conforming code segments.
 363      * Luckily, in our implementation the CPL field of hflags is redundant
 364      * and we can get the right value from the SS descriptor privilege level.
 365      */
 366     env->hflags &= ~HF_CPL_MASK;
 367     env->hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 368
 369     env->fpstt = (env->fpus_vmstate >> 11) & 7;
 370     env->fpus = env->fpus_vmstate & ~0x3800;
 371     env->fptag_vmstate ^= 0xff;
 372     for(i = 0; i < 8; i++) {
 373         env->fptags[i] = (env->fptag_vmstate >> i) & 1;
 374     }
 375     update_fp_status(env);
 376
 377     cpu_breakpoint_remove_all(cs, BP_CPU);
 378     cpu_watchpoint_remove_all(cs, BP_CPU);
 379     {
 380         /* Indicate all breakpoints disabled, as they are, then
 381            let the helper re-enable them.  */
 382         target_ulong dr7 = env->dr[7];
 383         env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK);
 384         cpu_x86_update_dr7(env, dr7);
 385     }
 386     tlb_flush(cs, 1);
 387
 388     if (tcg_enabled()) {
 389         cpu_smm_update(cpu);
 390     }
 391     return 0;
 392 }
 393
 394 static bool async_pf_msr_needed(void *opaque)
 395 {
 396     X86CPU *cpu = opaque;
 397
 398     return cpu->env.async_pf_en_msr != 0;
 399 }
 400
 401 static bool pv_eoi_msr_needed(void *opaque)
 402 {
 403     X86CPU *cpu = opaque;
 404
 405     return cpu->env.pv_eoi_en_msr != 0;
 406 }
 407
 408 static bool steal_time_msr_needed(void *opaque)
 409 {
 410     X86CPU *cpu = opaque;
 411
 412     return cpu->env.steal_time_msr != 0;
 413 }
 414
 415 static const VMStateDescription vmstate_steal_time_msr = {
 416     .name = "cpu/steal_time_msr",
 417     .version_id = 1,
 418     .minimum_version_id = 1,
 419     .needed = steal_time_msr_needed,
 420     .fields = (VMStateField[]) {
 421         VMSTATE_UINT64(env.steal_time_msr, X86CPU),
 422         VMSTATE_END_OF_LIST()
 423     }
 424 };
 425
 426 static const VMStateDescription vmstate_async_pf_msr = {
 427     .name = "cpu/async_pf_msr",
 428     .version_id = 1,
 429     .minimum_version_id = 1,
 430     .needed = async_pf_msr_needed,
 431     .fields = (VMStateField[]) {
 432         VMSTATE_UINT64(env.async_pf_en_msr, X86CPU),
 433         VMSTATE_END_OF_LIST()
 434     }
 435 };
 436
 437 static const VMStateDescription vmstate_pv_eoi_msr = {
 438     .name = "cpu/async_pv_eoi_msr",
 439     .version_id = 1,
 440     .minimum_version_id = 1,
 441     .needed = pv_eoi_msr_needed,
 442     .fields = (VMStateField[]) {
 443         VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU),
 444         VMSTATE_END_OF_LIST()
 445     }
 446 };
 447
 448 static bool fpop_ip_dp_needed(void *opaque)
 449 {
 450     X86CPU *cpu = opaque;
 451     CPUX86State *env = &cpu->env;
 452
 453     return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
 454 }
 455
 456 static const VMStateDescription vmstate_fpop_ip_dp = {
 457     .name = "cpu/fpop_ip_dp",
 458     .version_id = 1,
 459     .minimum_version_id = 1,
 460     .needed = fpop_ip_dp_needed,
 461     .fields = (VMStateField[]) {
 462         VMSTATE_UINT16(env.fpop, X86CPU),
 463         VMSTATE_UINT64(env.fpip, X86CPU),
 464         VMSTATE_UINT64(env.fpdp, X86CPU),
 465         VMSTATE_END_OF_LIST()
 466     }
 467 };
 468
 469 static bool tsc_adjust_needed(void *opaque)
 470 {
 471     X86CPU *cpu = opaque;
 472     CPUX86State *env = &cpu->env;
 473
 474     return env->tsc_adjust != 0;
 475 }
 476
 477 static const VMStateDescription vmstate_msr_tsc_adjust = {
 478     .name = "cpu/msr_tsc_adjust",
 479     .version_id = 1,
 480     .minimum_version_id = 1,
 481     .needed = tsc_adjust_needed,
 482     .fields = (VMStateField[]) {
 483         VMSTATE_UINT64(env.tsc_adjust, X86CPU),
 484         VMSTATE_END_OF_LIST()
 485     }
 486 };
 487
 488 static bool tscdeadline_needed(void *opaque)
 489 {
 490     X86CPU *cpu = opaque;
 491     CPUX86State *env = &cpu->env;
 492
 493     return env->tsc_deadline != 0;
 494 }
 495
 496 static const VMStateDescription vmstate_msr_tscdeadline = {
 497     .name = "cpu/msr_tscdeadline",
 498     .version_id = 1,
 499     .minimum_version_id = 1,
 500     .needed = tscdeadline_needed,
 501     .fields = (VMStateField[]) {
 502         VMSTATE_UINT64(env.tsc_deadline, X86CPU),
 503         VMSTATE_END_OF_LIST()
 504     }
 505 };
 506
 507 static bool misc_enable_needed(void *opaque)
 508 {
 509     X86CPU *cpu = opaque;
 510     CPUX86State *env = &cpu->env;
 511
 512     return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
 513 }
 514
 515 static bool feature_control_needed(void *opaque)
 516 {
 517     X86CPU *cpu = opaque;
 518     CPUX86State *env = &cpu->env;
 519
 520     return env->msr_ia32_feature_control != 0;
 521 }
 522
 523 static const VMStateDescription vmstate_msr_ia32_misc_enable = {
 524     .name = "cpu/msr_ia32_misc_enable",
 525     .version_id = 1,
 526     .minimum_version_id = 1,
 527     .needed = misc_enable_needed,
 528     .fields = (VMStateField[]) {
 529         VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU),
 530         VMSTATE_END_OF_LIST()
 531     }
 532 };
 533
 534 static const VMStateDescription vmstate_msr_ia32_feature_control = {
 535     .name = "cpu/msr_ia32_feature_control",
 536     .version_id = 1,
 537     .minimum_version_id = 1,
 538     .needed = feature_control_needed,
 539     .fields = (VMStateField[]) {
 540         VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU),
 541         VMSTATE_END_OF_LIST()
 542     }
 543 };
 544
 545 static bool pmu_enable_needed(void *opaque)
 546 {
 547     X86CPU *cpu = opaque;
 548     CPUX86State *env = &cpu->env;
 549     int i;
 550
 551     if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl ||
 552         env->msr_global_status || env->msr_global_ovf_ctrl) {
 553         return true;
 554     }
 555     for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
 556         if (env->msr_fixed_counters[i]) {
 557             return true;
 558         }
 559     }
 560     for (i = 0; i < MAX_GP_COUNTERS; i++) {
 561         if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) {
 562             return true;
 563         }
 564     }
 565
 566     return false;
 567 }
 568
 569 static const VMStateDescription vmstate_msr_architectural_pmu = {
 570     .name = "cpu/msr_architectural_pmu",
 571     .version_id = 1,
 572     .minimum_version_id = 1,
 573     .needed = pmu_enable_needed,
 574     .fields = (VMStateField[]) {
 575         VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU),
 576         VMSTATE_UINT64(env.msr_global_ctrl, X86CPU),
 577         VMSTATE_UINT64(env.msr_global_status, X86CPU),
 578         VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU),
 579         VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS),
 580         VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS),
 581         VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS),
 582         VMSTATE_END_OF_LIST()
 583     }
 584 };
 585
 586 static bool mpx_needed(void *opaque)
 587 {
 588     X86CPU *cpu = opaque;
 589     CPUX86State *env = &cpu->env;
 590     unsigned int i;
 591
 592     for (i = 0; i < 4; i++) {
 593         if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) {
 594             return true;
 595         }
 596     }
 597
 598     if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) {
 599         return true;
 600     }
 601
 602     return !!env->msr_bndcfgs;
 603 }
 604
 605 static const VMStateDescription vmstate_mpx = {
 606     .name = "cpu/mpx",
 607     .version_id = 1,
 608     .minimum_version_id = 1,
 609     .needed = mpx_needed,
 610     .fields = (VMStateField[]) {
 611         VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4),
 612         VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU),
 613         VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU),
 614         VMSTATE_UINT64(env.msr_bndcfgs, X86CPU),
 615         VMSTATE_END_OF_LIST()
 616     }
 617 };
 618
 619 static bool hyperv_hypercall_enable_needed(void *opaque)
 620 {
 621     X86CPU *cpu = opaque;
 622     CPUX86State *env = &cpu->env;
 623
 624     return env->msr_hv_hypercall != 0 || env->msr_hv_guest_os_id != 0;
 625 }
 626
 627 static const VMStateDescription vmstate_msr_hypercall_hypercall = {
 628     .name = "cpu/msr_hyperv_hypercall",
 629     .version_id = 1,
 630     .minimum_version_id = 1,
 631     .needed = hyperv_hypercall_enable_needed,
 632     .fields = (VMStateField[]) {
 633         VMSTATE_UINT64(env.msr_hv_guest_os_id, X86CPU),
 634         VMSTATE_UINT64(env.msr_hv_hypercall, X86CPU),
 635         VMSTATE_END_OF_LIST()
 636     }
 637 };
 638
 639 static bool hyperv_vapic_enable_needed(void *opaque)
 640 {
 641     X86CPU *cpu = opaque;
 642     CPUX86State *env = &cpu->env;
 643
 644     return env->msr_hv_vapic != 0;
 645 }
 646
 647 static const VMStateDescription vmstate_msr_hyperv_vapic = {
 648     .name = "cpu/msr_hyperv_vapic",
 649     .version_id = 1,
 650     .minimum_version_id = 1,
 651     .needed = hyperv_vapic_enable_needed,
 652     .fields = (VMStateField[]) {
 653         VMSTATE_UINT64(env.msr_hv_vapic, X86CPU),
 654         VMSTATE_END_OF_LIST()
 655     }
 656 };
 657
 658 static bool hyperv_time_enable_needed(void *opaque)
 659 {
 660     X86CPU *cpu = opaque;
 661     CPUX86State *env = &cpu->env;
 662
 663     return env->msr_hv_tsc != 0;
 664 }
 665
 666 static const VMStateDescription vmstate_msr_hyperv_time = {
 667     .name = "cpu/msr_hyperv_time",
 668     .version_id = 1,
 669     .minimum_version_id = 1,
 670     .needed = hyperv_time_enable_needed,
 671     .fields = (VMStateField[]) {
 672         VMSTATE_UINT64(env.msr_hv_tsc, X86CPU),
 673         VMSTATE_END_OF_LIST()
 674     }
 675 };
 676
 677 static bool hyperv_crash_enable_needed(void *opaque)
 678 {
 679     X86CPU *cpu = opaque;
 680     CPUX86State *env = &cpu->env;
 681     int i;
 682
 683     for (i = 0; i < HV_X64_MSR_CRASH_PARAMS; i++) {
 684         if (env->msr_hv_crash_params[i]) {
 685             return true;
 686         }
 687     }
 688     return false;
 689 }
 690
 691 static const VMStateDescription vmstate_msr_hyperv_crash = {
 692     .name = "cpu/msr_hyperv_crash",
 693     .version_id = 1,
 694     .minimum_version_id = 1,
 695     .needed = hyperv_crash_enable_needed,
 696     .fields = (VMStateField[]) {
 697         VMSTATE_UINT64_ARRAY(env.msr_hv_crash_params,
 698                              X86CPU, HV_X64_MSR_CRASH_PARAMS),
 699         VMSTATE_END_OF_LIST()
 700     }
 701 };
 702
 703 static bool hyperv_runtime_enable_needed(void *opaque)
 704 {
 705     X86CPU *cpu = opaque;
 706     CPUX86State *env = &cpu->env;
 707
 708     return env->msr_hv_runtime != 0;
 709 }
 710
 711 static const VMStateDescription vmstate_msr_hyperv_runtime = {
 712     .name = "cpu/msr_hyperv_runtime",
 713     .version_id = 1,
 714     .minimum_version_id = 1,
 715     .needed = hyperv_runtime_enable_needed,
 716     .fields = (VMStateField[]) {
 717         VMSTATE_UINT64(env.msr_hv_runtime, X86CPU),
 718         VMSTATE_END_OF_LIST()
 719     }
 720 };
 721
 722 static bool hyperv_synic_enable_needed(void *opaque)
 723 {
 724     X86CPU *cpu = opaque;
 725     CPUX86State *env = &cpu->env;
 726     int i;
 727
 728     if (env->msr_hv_synic_control != 0 ||
 729         env->msr_hv_synic_evt_page != 0 ||
 730         env->msr_hv_synic_msg_page != 0) {
 731         return true;
 732     }
 733
 734     for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
 735         if (env->msr_hv_synic_sint[i] != 0) {
 736             return true;
 737         }
 738     }
 739
 740     return false;
 741 }
 742
 743 static const VMStateDescription vmstate_msr_hyperv_synic = {
 744     .name = "cpu/msr_hyperv_synic",
 745     .version_id = 1,
 746     .minimum_version_id = 1,
 747     .needed = hyperv_synic_enable_needed,
 748     .fields = (VMStateField[]) {
 749         VMSTATE_UINT64(env.msr_hv_synic_control, X86CPU),
 750         VMSTATE_UINT64(env.msr_hv_synic_evt_page, X86CPU),
 751         VMSTATE_UINT64(env.msr_hv_synic_msg_page, X86CPU),
 752         VMSTATE_UINT64_ARRAY(env.msr_hv_synic_sint, X86CPU,
 753                              HV_SYNIC_SINT_COUNT),
 754         VMSTATE_END_OF_LIST()
 755     }
 756 };
 757
 758 static bool hyperv_stimer_enable_needed(void *opaque)
 759 {
 760     X86CPU *cpu = opaque;
 761     CPUX86State *env = &cpu->env;
 762     int i;
 763
 764     for (i = 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) {
 765         if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i]) {
 766             return true;
 767         }
 768     }
 769     return false;
 770 }
 771
 772 static const VMStateDescription vmstate_msr_hyperv_stimer = {
 773     .name = "cpu/msr_hyperv_stimer",
 774     .version_id = 1,
 775     .minimum_version_id = 1,
 776     .needed = hyperv_stimer_enable_needed,
 777     .fields = (VMStateField[]) {
 778         VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_config,
 779                              X86CPU, HV_SYNIC_STIMER_COUNT),
 780         VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_count,
 781                              X86CPU, HV_SYNIC_STIMER_COUNT),
 782         VMSTATE_END_OF_LIST()
 783     }
 784 };
 785
 786 static bool avx512_needed(void *opaque)
 787 {
 788     X86CPU *cpu = opaque;
 789     CPUX86State *env = &cpu->env;
 790     unsigned int i;
 791
 792     for (i = 0; i < NB_OPMASK_REGS; i++) {
 793         if (env->opmask_regs[i]) {
 794             return true;
 795         }
 796     }
 797
 798     for (i = 0; i < CPU_NB_REGS; i++) {
 799 #define ENV_XMM(reg, field) (env->xmm_regs[reg].ZMM_Q(field))
 800         if (ENV_XMM(i, 4) || ENV_XMM(i, 6) ||
 801             ENV_XMM(i, 5) || ENV_XMM(i, 7)) {
 802             return true;
 803         }
 804 #ifdef TARGET_X86_64
 805         if (ENV_XMM(i+16, 0) || ENV_XMM(i+16, 1) ||
 806             ENV_XMM(i+16, 2) || ENV_XMM(i+16, 3) ||
 807             ENV_XMM(i+16, 4) || ENV_XMM(i+16, 5) ||
 808             ENV_XMM(i+16, 6) || ENV_XMM(i+16, 7)) {
 809             return true;
 810         }
 811 #endif
 812     }
 813
 814     return false;
 815 }
 816
 817 static const VMStateDescription vmstate_avx512 = {
 818     .name = "cpu/avx512",
 819     .version_id = 1,
 820     .minimum_version_id = 1,
 821     .needed = avx512_needed,
 822     .fields = (VMStateField[]) {
 823         VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS),
 824         VMSTATE_ZMMH_REGS_VARS(env.xmm_regs, X86CPU, 0),
 825 #ifdef TARGET_X86_64
 826         VMSTATE_Hi16_ZMM_REGS_VARS(env.xmm_regs, X86CPU, 16),
 827 #endif
 828         VMSTATE_END_OF_LIST()
 829     }
 830 };
 831
 832 static bool xss_needed(void *opaque)
 833 {
 834     X86CPU *cpu = opaque;
 835     CPUX86State *env = &cpu->env;
 836
 837     return env->xss != 0;
 838 }
 839
 840 static const VMStateDescription vmstate_xss = {
 841     .name = "cpu/xss",
 842     .version_id = 1,
 843     .minimum_version_id = 1,
 844     .needed = xss_needed,
 845     .fields = (VMStateField[]) {
 846         VMSTATE_UINT64(env.xss, X86CPU),
 847         VMSTATE_END_OF_LIST()
 848     }
 849 };
 850
 851 #ifdef TARGET_X86_64
 852 static bool pkru_needed(void *opaque)
 853 {
 854     X86CPU *cpu = opaque;
 855     CPUX86State *env = &cpu->env;
 856
 857     return env->pkru != 0;
 858 }
 859
 860 static const VMStateDescription vmstate_pkru = {
 861     .name = "cpu/pkru",
 862     .version_id = 1,
 863     .minimum_version_id = 1,
 864     .needed = pkru_needed,
 865     .fields = (VMStateField[]){
 866         VMSTATE_UINT32(env.pkru, X86CPU),
 867         VMSTATE_END_OF_LIST()
 868     }
 869 };
 870 #endif
 871
 872 static bool tsc_khz_needed(void *opaque)
 873 {
 874     X86CPU *cpu = opaque;
 875     CPUX86State *env = &cpu->env;
 876     MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
 877     PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
 878     return env->tsc_khz && pcmc->save_tsc_khz;
 879 }
 880
 881 static const VMStateDescription vmstate_tsc_khz = {
 882     .name = "cpu/tsc_khz",
 883     .version_id = 1,
 884     .minimum_version_id = 1,
 885     .needed = tsc_khz_needed,
 886     .fields = (VMStateField[]) {
 887         VMSTATE_INT64(env.tsc_khz, X86CPU),
 888         VMSTATE_END_OF_LIST()
 889     }
 890 };
 891
 892 VMStateDescription vmstate_x86_cpu = {
 893     .name = "cpu",
 894     .version_id = 12,
 895     .minimum_version_id = 3,
 896     .pre_save = cpu_pre_save,
 897     .post_load = cpu_post_load,
 898     .fields = (VMStateField[]) {
 899         VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS),
 900         VMSTATE_UINTTL(env.eip, X86CPU),
 901         VMSTATE_UINTTL(env.eflags, X86CPU),
 902         VMSTATE_UINT32(env.hflags, X86CPU),
 903         /* FPU */
 904         VMSTATE_UINT16(env.fpuc, X86CPU),
 905         VMSTATE_UINT16(env.fpus_vmstate, X86CPU),
 906         VMSTATE_UINT16(env.fptag_vmstate, X86CPU),
 907         VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),
 908         VMSTATE_FP_REGS(env.fpregs, X86CPU, 8),
 909
 910         VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
 911         VMSTATE_SEGMENT(env.ldt, X86CPU),
 912         VMSTATE_SEGMENT(env.tr, X86CPU),
 913         VMSTATE_SEGMENT(env.gdt, X86CPU),
 914         VMSTATE_SEGMENT(env.idt, X86CPU),
 915
 916         VMSTATE_UINT32(env.sysenter_cs, X86CPU),
 917 #ifdef TARGET_X86_64
 918         /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
 919         VMSTATE_HACK_UINT32(env.sysenter_esp, X86CPU, less_than_7),
 920         VMSTATE_HACK_UINT32(env.sysenter_eip, X86CPU, less_than_7),
 921         VMSTATE_UINTTL_V(env.sysenter_esp, X86CPU, 7),
 922         VMSTATE_UINTTL_V(env.sysenter_eip, X86CPU, 7),
 923 #else
 924         VMSTATE_UINTTL(env.sysenter_esp, X86CPU),
 925         VMSTATE_UINTTL(env.sysenter_eip, X86CPU),
 926 #endif
 927
 928         VMSTATE_UINTTL(env.cr[0], X86CPU),
 929         VMSTATE_UINTTL(env.cr[2], X86CPU),
 930         VMSTATE_UINTTL(env.cr[3], X86CPU),
 931         VMSTATE_UINTTL(env.cr[4], X86CPU),
 932         VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
 933         /* MMU */
 934         VMSTATE_INT32(env.a20_mask, X86CPU),
 935         /* XMM */
 936         VMSTATE_UINT32(env.mxcsr, X86CPU),
 937         VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, 0),
 938
 939 #ifdef TARGET_X86_64
 940         VMSTATE_UINT64(env.efer, X86CPU),
 941         VMSTATE_UINT64(env.star, X86CPU),
 942         VMSTATE_UINT64(env.lstar, X86CPU),
 943         VMSTATE_UINT64(env.cstar, X86CPU),
 944         VMSTATE_UINT64(env.fmask, X86CPU),
 945         VMSTATE_UINT64(env.kernelgsbase, X86CPU),
 946 #endif
 947         VMSTATE_UINT32_V(env.smbase, X86CPU, 4),
 948
 949         VMSTATE_UINT64_V(env.pat, X86CPU, 5),
 950         VMSTATE_UINT32_V(env.hflags2, X86CPU, 5),
 951
 952         VMSTATE_UINT32_TEST(parent_obj.halted, X86CPU, version_is_5),
 953         VMSTATE_UINT64_V(env.vm_hsave, X86CPU, 5),
 954         VMSTATE_UINT64_V(env.vm_vmcb, X86CPU, 5),
 955         VMSTATE_UINT64_V(env.tsc_offset, X86CPU, 5),
 956         VMSTATE_UINT64_V(env.intercept, X86CPU, 5),
 957         VMSTATE_UINT16_V(env.intercept_cr_read, X86CPU, 5),
 958         VMSTATE_UINT16_V(env.intercept_cr_write, X86CPU, 5),
 959         VMSTATE_UINT16_V(env.intercept_dr_read, X86CPU, 5),
 960         VMSTATE_UINT16_V(env.intercept_dr_write, X86CPU, 5),
 961         VMSTATE_UINT32_V(env.intercept_exceptions, X86CPU, 5),
 962         VMSTATE_UINT8_V(env.v_tpr, X86CPU, 5),
 963         /* MTRRs */
 964         VMSTATE_UINT64_ARRAY_V(env.mtrr_fixed, X86CPU, 11, 8),
 965         VMSTATE_UINT64_V(env.mtrr_deftype, X86CPU, 8),
 966         VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, MSR_MTRRcap_VCNT, 8),
 967         /* KVM-related states */
 968         VMSTATE_INT32_V(env.interrupt_injected, X86CPU, 9),
 969         VMSTATE_UINT32_V(env.mp_state, X86CPU, 9),
 970         VMSTATE_UINT64_V(env.tsc, X86CPU, 9),
 971         VMSTATE_INT32_V(env.exception_injected, X86CPU, 11),
 972         VMSTATE_UINT8_V(env.soft_interrupt, X86CPU, 11),
 973         VMSTATE_UINT8_V(env.nmi_injected, X86CPU, 11),
 974         VMSTATE_UINT8_V(env.nmi_pending, X86CPU, 11),
 975         VMSTATE_UINT8_V(env.has_error_code, X86CPU, 11),
 976         VMSTATE_UINT32_V(env.sipi_vector, X86CPU, 11),
 977         /* MCE */
 978         VMSTATE_UINT64_V(env.mcg_cap, X86CPU, 10),
 979         VMSTATE_UINT64_V(env.mcg_status, X86CPU, 10),
 980         VMSTATE_UINT64_V(env.mcg_ctl, X86CPU, 10),
 981         VMSTATE_UINT64_ARRAY_V(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4, 10),
 982         /* rdtscp */
 983         VMSTATE_UINT64_V(env.tsc_aux, X86CPU, 11),
 984         /* KVM pvclock msr */
 985         VMSTATE_UINT64_V(env.system_time_msr, X86CPU, 11),
 986         VMSTATE_UINT64_V(env.wall_clock_msr, X86CPU, 11),
 987         /* XSAVE related fields */
 988         VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
 989         VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
 990         VMSTATE_YMMH_REGS_VARS(env.xmm_regs, X86CPU, 0, 12),
 991         VMSTATE_END_OF_LIST()
 992         /* The above list is not sorted /wrt version numbers, watch out! */
 993     },
 994     .subsections = (const VMStateDescription*[]) {
 995         &vmstate_async_pf_msr,
 996         &vmstate_pv_eoi_msr,
 997         &vmstate_steal_time_msr,
 998         &vmstate_fpop_ip_dp,
 999         &vmstate_msr_tsc_adjust,
1000         &vmstate_msr_tscdeadline,
1001         &vmstate_msr_ia32_misc_enable,
1002         &vmstate_msr_ia32_feature_control,
1003         &vmstate_msr_architectural_pmu,
1004         &vmstate_mpx,
1005         &vmstate_msr_hypercall_hypercall,
1006         &vmstate_msr_hyperv_vapic,
1007         &vmstate_msr_hyperv_time,
1008         &vmstate_msr_hyperv_crash,
1009         &vmstate_msr_hyperv_runtime,
1010         &vmstate_msr_hyperv_synic,
1011         &vmstate_msr_hyperv_stimer,
1012         &vmstate_avx512,
1013         &vmstate_xss,
1014         &vmstate_tsc_khz,
1015 #ifdef TARGET_X86_64
1016         &vmstate_pkru,
1017 #endif
1018         NULL
1019     }
1020 };