block: Convert throttle_group_get_name() to BlockBackend
[qemu/kevin.git] / hw / acpi / nvdimm.c
blob9531340e56ffcf71cb60659dcc96d5e106d4448e
1 /*
2 * NVDIMM ACPI Implementation
4 * Copyright(C) 2015 Intel Corporation.
6 * Author:
7 * Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 * NFIT is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT)
10 * and the DSM specification can be found at:
11 * http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf
13 * Currently, it only supports PMEM Virtualization.
15 * This library is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU Lesser General Public
17 * License as published by the Free Software Foundation; either
18 * version 2 of the License, or (at your option) any later version.
20 * This library is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * Lesser General Public License for more details.
25 * You should have received a copy of the GNU Lesser General Public
26 * License along with this library; if not, see <http://www.gnu.org/licenses/>
29 #include "qemu/osdep.h"
30 #include "hw/acpi/acpi.h"
31 #include "hw/acpi/aml-build.h"
32 #include "hw/acpi/bios-linker-loader.h"
33 #include "hw/nvram/fw_cfg.h"
34 #include "hw/mem/nvdimm.h"
36 static int nvdimm_plugged_device_list(Object *obj, void *opaque)
38 GSList **list = opaque;
40 if (object_dynamic_cast(obj, TYPE_NVDIMM)) {
41 DeviceState *dev = DEVICE(obj);
43 if (dev->realized) { /* only realized NVDIMMs matter */
44 *list = g_slist_append(*list, DEVICE(obj));
48 object_child_foreach(obj, nvdimm_plugged_device_list, opaque);
49 return 0;
53 * inquire plugged NVDIMM devices and link them into the list which is
54 * returned to the caller.
56 * Note: it is the caller's responsibility to free the list to avoid
57 * memory leak.
59 static GSList *nvdimm_get_plugged_device_list(void)
61 GSList *list = NULL;
63 object_child_foreach(qdev_get_machine(), nvdimm_plugged_device_list,
64 &list);
65 return list;
68 #define NVDIMM_UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
69 { (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
70 (b) & 0xff, ((b) >> 8) & 0xff, (c) & 0xff, ((c) >> 8) & 0xff, \
71 (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }
74 * define Byte Addressable Persistent Memory (PM) Region according to
75 * ACPI 6.0: 5.2.25.1 System Physical Address Range Structure.
77 static const uint8_t nvdimm_nfit_spa_uuid[] =
78 NVDIMM_UUID_LE(0x66f0d379, 0xb4f3, 0x4074, 0xac, 0x43, 0x0d, 0x33,
79 0x18, 0xb7, 0x8c, 0xdb);
82 * NVDIMM Firmware Interface Table
83 * @signature: "NFIT"
85 * It provides information that allows OSPM to enumerate NVDIMM present in
86 * the platform and associate system physical address ranges created by the
87 * NVDIMMs.
89 * It is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT)
91 struct NvdimmNfitHeader {
92 ACPI_TABLE_HEADER_DEF
93 uint32_t reserved;
94 } QEMU_PACKED;
95 typedef struct NvdimmNfitHeader NvdimmNfitHeader;
98 * define NFIT structures according to ACPI 6.0: 5.2.25 NVDIMM Firmware
99 * Interface Table (NFIT).
103 * System Physical Address Range Structure
105 * It describes the system physical address ranges occupied by NVDIMMs and
106 * the types of the regions.
108 struct NvdimmNfitSpa {
109 uint16_t type;
110 uint16_t length;
111 uint16_t spa_index;
112 uint16_t flags;
113 uint32_t reserved;
114 uint32_t proximity_domain;
115 uint8_t type_guid[16];
116 uint64_t spa_base;
117 uint64_t spa_length;
118 uint64_t mem_attr;
119 } QEMU_PACKED;
120 typedef struct NvdimmNfitSpa NvdimmNfitSpa;
123 * Memory Device to System Physical Address Range Mapping Structure
125 * It enables identifying each NVDIMM region and the corresponding SPA
126 * describing the memory interleave
128 struct NvdimmNfitMemDev {
129 uint16_t type;
130 uint16_t length;
131 uint32_t nfit_handle;
132 uint16_t phys_id;
133 uint16_t region_id;
134 uint16_t spa_index;
135 uint16_t dcr_index;
136 uint64_t region_len;
137 uint64_t region_offset;
138 uint64_t region_dpa;
139 uint16_t interleave_index;
140 uint16_t interleave_ways;
141 uint16_t flags;
142 uint16_t reserved;
143 } QEMU_PACKED;
144 typedef struct NvdimmNfitMemDev NvdimmNfitMemDev;
147 * NVDIMM Control Region Structure
149 * It describes the NVDIMM and if applicable, Block Control Window.
151 struct NvdimmNfitControlRegion {
152 uint16_t type;
153 uint16_t length;
154 uint16_t dcr_index;
155 uint16_t vendor_id;
156 uint16_t device_id;
157 uint16_t revision_id;
158 uint16_t sub_vendor_id;
159 uint16_t sub_device_id;
160 uint16_t sub_revision_id;
161 uint8_t reserved[6];
162 uint32_t serial_number;
163 uint16_t fic;
164 uint16_t num_bcw;
165 uint64_t bcw_size;
166 uint64_t cmd_offset;
167 uint64_t cmd_size;
168 uint64_t status_offset;
169 uint64_t status_size;
170 uint16_t flags;
171 uint8_t reserved2[6];
172 } QEMU_PACKED;
173 typedef struct NvdimmNfitControlRegion NvdimmNfitControlRegion;
176 * Module serial number is a unique number for each device. We use the
177 * slot id of NVDIMM device to generate this number so that each device
178 * associates with a different number.
180 * 0x123456 is a magic number we arbitrarily chose.
182 static uint32_t nvdimm_slot_to_sn(int slot)
184 return 0x123456 + slot;
188 * handle is used to uniquely associate nfit_memdev structure with NVDIMM
189 * ACPI device - nfit_memdev.nfit_handle matches with the value returned
190 * by ACPI device _ADR method.
192 * We generate the handle with the slot id of NVDIMM device and reserve
193 * 0 for NVDIMM root device.
195 static uint32_t nvdimm_slot_to_handle(int slot)
197 return slot + 1;
201 * index uniquely identifies the structure, 0 is reserved which indicates
202 * that the structure is not valid or the associated structure is not
203 * present.
205 * Each NVDIMM device needs two indexes, one for nfit_spa and another for
206 * nfit_dc which are generated by the slot id of NVDIMM device.
208 static uint16_t nvdimm_slot_to_spa_index(int slot)
210 return (slot + 1) << 1;
213 /* See the comments of nvdimm_slot_to_spa_index(). */
214 static uint32_t nvdimm_slot_to_dcr_index(int slot)
216 return nvdimm_slot_to_spa_index(slot) + 1;
219 /* ACPI 6.0: 5.2.25.1 System Physical Address Range Structure */
220 static void
221 nvdimm_build_structure_spa(GArray *structures, DeviceState *dev)
223 NvdimmNfitSpa *nfit_spa;
224 uint64_t addr = object_property_get_int(OBJECT(dev), PC_DIMM_ADDR_PROP,
225 NULL);
226 uint64_t size = object_property_get_int(OBJECT(dev), PC_DIMM_SIZE_PROP,
227 NULL);
228 uint32_t node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP,
229 NULL);
230 int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
231 NULL);
233 nfit_spa = acpi_data_push(structures, sizeof(*nfit_spa));
235 nfit_spa->type = cpu_to_le16(0 /* System Physical Address Range
236 Structure */);
237 nfit_spa->length = cpu_to_le16(sizeof(*nfit_spa));
238 nfit_spa->spa_index = cpu_to_le16(nvdimm_slot_to_spa_index(slot));
241 * Control region is strict as all the device info, such as SN, index,
242 * is associated with slot id.
244 nfit_spa->flags = cpu_to_le16(1 /* Control region is strictly for
245 management during hot add/online
246 operation */ |
247 2 /* Data in Proximity Domain field is
248 valid*/);
250 /* NUMA node. */
251 nfit_spa->proximity_domain = cpu_to_le32(node);
252 /* the region reported as PMEM. */
253 memcpy(nfit_spa->type_guid, nvdimm_nfit_spa_uuid,
254 sizeof(nvdimm_nfit_spa_uuid));
256 nfit_spa->spa_base = cpu_to_le64(addr);
257 nfit_spa->spa_length = cpu_to_le64(size);
259 /* It is the PMEM and can be cached as writeback. */
260 nfit_spa->mem_attr = cpu_to_le64(0x8ULL /* EFI_MEMORY_WB */ |
261 0x8000ULL /* EFI_MEMORY_NV */);
265 * ACPI 6.0: 5.2.25.2 Memory Device to System Physical Address Range Mapping
266 * Structure
268 static void
269 nvdimm_build_structure_memdev(GArray *structures, DeviceState *dev)
271 NvdimmNfitMemDev *nfit_memdev;
272 uint64_t addr = object_property_get_int(OBJECT(dev), PC_DIMM_ADDR_PROP,
273 NULL);
274 uint64_t size = object_property_get_int(OBJECT(dev), PC_DIMM_SIZE_PROP,
275 NULL);
276 int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
277 NULL);
278 uint32_t handle = nvdimm_slot_to_handle(slot);
280 nfit_memdev = acpi_data_push(structures, sizeof(*nfit_memdev));
282 nfit_memdev->type = cpu_to_le16(1 /* Memory Device to System Address
283 Range Map Structure*/);
284 nfit_memdev->length = cpu_to_le16(sizeof(*nfit_memdev));
285 nfit_memdev->nfit_handle = cpu_to_le32(handle);
288 * associate memory device with System Physical Address Range
289 * Structure.
291 nfit_memdev->spa_index = cpu_to_le16(nvdimm_slot_to_spa_index(slot));
292 /* associate memory device with Control Region Structure. */
293 nfit_memdev->dcr_index = cpu_to_le16(nvdimm_slot_to_dcr_index(slot));
295 /* The memory region on the device. */
296 nfit_memdev->region_len = cpu_to_le64(size);
297 nfit_memdev->region_dpa = cpu_to_le64(addr);
299 /* Only one interleave for PMEM. */
300 nfit_memdev->interleave_ways = cpu_to_le16(1);
304 * ACPI 6.0: 5.2.25.5 NVDIMM Control Region Structure.
306 static void nvdimm_build_structure_dcr(GArray *structures, DeviceState *dev)
308 NvdimmNfitControlRegion *nfit_dcr;
309 int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
310 NULL);
311 uint32_t sn = nvdimm_slot_to_sn(slot);
313 nfit_dcr = acpi_data_push(structures, sizeof(*nfit_dcr));
315 nfit_dcr->type = cpu_to_le16(4 /* NVDIMM Control Region Structure */);
316 nfit_dcr->length = cpu_to_le16(sizeof(*nfit_dcr));
317 nfit_dcr->dcr_index = cpu_to_le16(nvdimm_slot_to_dcr_index(slot));
319 /* vendor: Intel. */
320 nfit_dcr->vendor_id = cpu_to_le16(0x8086);
321 nfit_dcr->device_id = cpu_to_le16(1);
323 /* The _DSM method is following Intel's DSM specification. */
324 nfit_dcr->revision_id = cpu_to_le16(1 /* Current Revision supported
325 in ACPI 6.0 is 1. */);
326 nfit_dcr->serial_number = cpu_to_le32(sn);
327 nfit_dcr->fic = cpu_to_le16(0x201 /* Format Interface Code. See Chapter
328 2: NVDIMM Device Specific Method
329 (DSM) in DSM Spec Rev1.*/);
332 static GArray *nvdimm_build_device_structure(GSList *device_list)
334 GArray *structures = g_array_new(false, true /* clear */, 1);
336 for (; device_list; device_list = device_list->next) {
337 DeviceState *dev = device_list->data;
339 /* build System Physical Address Range Structure. */
340 nvdimm_build_structure_spa(structures, dev);
343 * build Memory Device to System Physical Address Range Mapping
344 * Structure.
346 nvdimm_build_structure_memdev(structures, dev);
348 /* build NVDIMM Control Region Structure. */
349 nvdimm_build_structure_dcr(structures, dev);
352 return structures;
355 static void nvdimm_build_nfit(GSList *device_list, GArray *table_offsets,
356 GArray *table_data, GArray *linker)
358 GArray *structures = nvdimm_build_device_structure(device_list);
359 unsigned int header;
361 acpi_add_table(table_offsets, table_data);
363 /* NFIT header. */
364 header = table_data->len;
365 acpi_data_push(table_data, sizeof(NvdimmNfitHeader));
366 /* NVDIMM device structures. */
367 g_array_append_vals(table_data, structures->data, structures->len);
369 build_header(linker, table_data,
370 (void *)(table_data->data + header), "NFIT",
371 sizeof(NvdimmNfitHeader) + structures->len, 1, NULL, NULL);
372 g_array_free(structures, true);
375 struct NvdimmDsmIn {
376 uint32_t handle;
377 uint32_t revision;
378 uint32_t function;
379 /* the remaining size in the page is used by arg3. */
380 union {
381 uint8_t arg3[0];
383 } QEMU_PACKED;
384 typedef struct NvdimmDsmIn NvdimmDsmIn;
386 struct NvdimmDsmOut {
387 /* the size of buffer filled by QEMU. */
388 uint32_t len;
389 uint8_t data[0];
390 } QEMU_PACKED;
391 typedef struct NvdimmDsmOut NvdimmDsmOut;
393 struct NvdimmDsmFunc0Out {
394 /* the size of buffer filled by QEMU. */
395 uint32_t len;
396 uint32_t supported_func;
397 } QEMU_PACKED;
398 typedef struct NvdimmDsmFunc0Out NvdimmDsmFunc0Out;
400 struct NvdimmDsmFuncNoPayloadOut {
401 /* the size of buffer filled by QEMU. */
402 uint32_t len;
403 uint32_t func_ret_status;
404 } QEMU_PACKED;
405 typedef struct NvdimmDsmFuncNoPayloadOut NvdimmDsmFuncNoPayloadOut;
407 static uint64_t
408 nvdimm_dsm_read(void *opaque, hwaddr addr, unsigned size)
410 nvdimm_debug("BUG: we never read _DSM IO Port.\n");
411 return 0;
414 static void
415 nvdimm_dsm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
417 NvdimmDsmIn *in;
418 hwaddr dsm_mem_addr = val;
420 nvdimm_debug("dsm memory address %#" HWADDR_PRIx ".\n", dsm_mem_addr);
423 * The DSM memory is mapped to guest address space so an evil guest
424 * can change its content while we are doing DSM emulation. Avoid
425 * this by copying DSM memory to QEMU local memory.
427 in = g_malloc(TARGET_PAGE_SIZE);
428 cpu_physical_memory_read(dsm_mem_addr, in, TARGET_PAGE_SIZE);
430 le32_to_cpus(&in->revision);
431 le32_to_cpus(&in->function);
432 le32_to_cpus(&in->handle);
434 nvdimm_debug("Revision %#x Handler %#x Function %#x.\n", in->revision,
435 in->handle, in->function);
438 * function 0 is called to inquire which functions are supported by
439 * OSPM
441 if (in->function == 0) {
442 NvdimmDsmFunc0Out func0 = {
443 .len = cpu_to_le32(sizeof(func0)),
444 /* No function supported other than function 0 */
445 .supported_func = cpu_to_le32(0),
447 cpu_physical_memory_write(dsm_mem_addr, &func0, sizeof func0);
448 } else {
449 /* No function except function 0 is supported yet. */
450 NvdimmDsmFuncNoPayloadOut out = {
451 .len = cpu_to_le32(sizeof(out)),
452 .func_ret_status = cpu_to_le32(1) /* Not Supported */,
454 cpu_physical_memory_write(dsm_mem_addr, &out, sizeof(out));
457 g_free(in);
460 static const MemoryRegionOps nvdimm_dsm_ops = {
461 .read = nvdimm_dsm_read,
462 .write = nvdimm_dsm_write,
463 .endianness = DEVICE_LITTLE_ENDIAN,
464 .valid = {
465 .min_access_size = 4,
466 .max_access_size = 4,
470 void nvdimm_init_acpi_state(AcpiNVDIMMState *state, MemoryRegion *io,
471 FWCfgState *fw_cfg, Object *owner)
473 memory_region_init_io(&state->io_mr, owner, &nvdimm_dsm_ops, state,
474 "nvdimm-acpi-io", NVDIMM_ACPI_IO_LEN);
475 memory_region_add_subregion(io, NVDIMM_ACPI_IO_BASE, &state->io_mr);
477 state->dsm_mem = g_array_new(false, true /* clear */, 1);
478 acpi_data_push(state->dsm_mem, TARGET_PAGE_SIZE);
479 fw_cfg_add_file(fw_cfg, NVDIMM_DSM_MEM_FILE, state->dsm_mem->data,
480 state->dsm_mem->len);
483 #define NVDIMM_COMMON_DSM "NCAL"
484 #define NVDIMM_ACPI_MEM_ADDR "MEMA"
486 static void nvdimm_build_common_dsm(Aml *dev)
488 Aml *method, *ifctx, *function, *dsm_mem, *unpatched, *result_size;
489 uint8_t byte_list[1];
491 method = aml_method(NVDIMM_COMMON_DSM, 4, AML_SERIALIZED);
492 function = aml_arg(2);
493 dsm_mem = aml_name(NVDIMM_ACPI_MEM_ADDR);
496 * do not support any method if DSM memory address has not been
497 * patched.
499 unpatched = aml_if(aml_equal(dsm_mem, aml_int(0x0)));
502 * function 0 is called to inquire what functions are supported by
503 * OSPM
505 ifctx = aml_if(aml_equal(function, aml_int(0)));
506 byte_list[0] = 0 /* No function Supported */;
507 aml_append(ifctx, aml_return(aml_buffer(1, byte_list)));
508 aml_append(unpatched, ifctx);
510 /* No function is supported yet. */
511 byte_list[0] = 1 /* Not Supported */;
512 aml_append(unpatched, aml_return(aml_buffer(1, byte_list)));
513 aml_append(method, unpatched);
516 * The HDLE indicates the DSM function is issued from which device,
517 * it is not used at this time as no function is supported yet.
518 * Currently we make it always be 0 for all the devices and will set
519 * the appropriate value once real function is implemented.
521 aml_append(method, aml_store(aml_int(0x0), aml_name("HDLE")));
522 aml_append(method, aml_store(aml_arg(1), aml_name("REVS")));
523 aml_append(method, aml_store(aml_arg(2), aml_name("FUNC")));
526 * tell QEMU about the real address of DSM memory, then QEMU
527 * gets the control and fills the result in DSM memory.
529 aml_append(method, aml_store(dsm_mem, aml_name("NTFI")));
531 result_size = aml_local(1);
532 aml_append(method, aml_store(aml_name("RLEN"), result_size));
533 aml_append(method, aml_store(aml_shiftleft(result_size, aml_int(3)),
534 result_size));
535 aml_append(method, aml_create_field(aml_name("ODAT"), aml_int(0),
536 result_size, "OBUF"));
537 aml_append(method, aml_concatenate(aml_buffer(0, NULL), aml_name("OBUF"),
538 aml_arg(6)));
539 aml_append(method, aml_return(aml_arg(6)));
540 aml_append(dev, method);
543 static void nvdimm_build_device_dsm(Aml *dev)
545 Aml *method;
547 method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
548 aml_append(method, aml_return(aml_call4(NVDIMM_COMMON_DSM, aml_arg(0),
549 aml_arg(1), aml_arg(2), aml_arg(3))));
550 aml_append(dev, method);
553 static void nvdimm_build_nvdimm_devices(GSList *device_list, Aml *root_dev)
555 for (; device_list; device_list = device_list->next) {
556 DeviceState *dev = device_list->data;
557 int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
558 NULL);
559 uint32_t handle = nvdimm_slot_to_handle(slot);
560 Aml *nvdimm_dev;
562 nvdimm_dev = aml_device("NV%02X", slot);
565 * ACPI 6.0: 9.20 NVDIMM Devices:
567 * _ADR object that is used to supply OSPM with unique address
568 * of the NVDIMM device. This is done by returning the NFIT Device
569 * handle that is used to identify the associated entries in ACPI
570 * table NFIT or _FIT.
572 aml_append(nvdimm_dev, aml_name_decl("_ADR", aml_int(handle)));
574 nvdimm_build_device_dsm(nvdimm_dev);
575 aml_append(root_dev, nvdimm_dev);
579 static void nvdimm_build_ssdt(GSList *device_list, GArray *table_offsets,
580 GArray *table_data, GArray *linker)
582 Aml *ssdt, *sb_scope, *dev, *field;
583 int mem_addr_offset, nvdimm_ssdt;
585 acpi_add_table(table_offsets, table_data);
587 ssdt = init_aml_allocator();
588 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
590 sb_scope = aml_scope("\\_SB");
592 dev = aml_device("NVDR");
595 * ACPI 6.0: 9.20 NVDIMM Devices:
597 * The ACPI Name Space device uses _HID of ACPI0012 to identify the root
598 * NVDIMM interface device. Platform firmware is required to contain one
599 * such device in _SB scope if NVDIMMs support is exposed by platform to
600 * OSPM.
601 * For each NVDIMM present or intended to be supported by platform,
602 * platform firmware also exposes an ACPI Namespace Device under the
603 * root device.
605 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0012")));
607 /* map DSM memory and IO into ACPI namespace. */
608 aml_append(dev, aml_operation_region("NPIO", AML_SYSTEM_IO,
609 aml_int(NVDIMM_ACPI_IO_BASE), NVDIMM_ACPI_IO_LEN));
610 aml_append(dev, aml_operation_region("NRAM", AML_SYSTEM_MEMORY,
611 aml_name(NVDIMM_ACPI_MEM_ADDR), TARGET_PAGE_SIZE));
614 * DSM notifier:
615 * NTFI: write the address of DSM memory and notify QEMU to emulate
616 * the access.
618 * It is the IO port so that accessing them will cause VM-exit, the
619 * control will be transferred to QEMU.
621 field = aml_field("NPIO", AML_DWORD_ACC, AML_NOLOCK, AML_PRESERVE);
622 aml_append(field, aml_named_field("NTFI",
623 sizeof(uint32_t) * BITS_PER_BYTE));
624 aml_append(dev, field);
627 * DSM input:
628 * HDLE: store device's handle, it's zero if the _DSM call happens
629 * on NVDIMM Root Device.
630 * REVS: store the Arg1 of _DSM call.
631 * FUNC: store the Arg2 of _DSM call.
632 * ARG3: store the Arg3 of _DSM call.
634 * They are RAM mapping on host so that these accesses never cause
635 * VM-EXIT.
637 field = aml_field("NRAM", AML_DWORD_ACC, AML_NOLOCK, AML_PRESERVE);
638 aml_append(field, aml_named_field("HDLE",
639 sizeof(typeof_field(NvdimmDsmIn, handle)) * BITS_PER_BYTE));
640 aml_append(field, aml_named_field("REVS",
641 sizeof(typeof_field(NvdimmDsmIn, revision)) * BITS_PER_BYTE));
642 aml_append(field, aml_named_field("FUNC",
643 sizeof(typeof_field(NvdimmDsmIn, function)) * BITS_PER_BYTE));
644 aml_append(field, aml_named_field("ARG3",
645 (TARGET_PAGE_SIZE - offsetof(NvdimmDsmIn, arg3)) *
646 BITS_PER_BYTE));
647 aml_append(dev, field);
650 * DSM output:
651 * RLEN: the size of the buffer filled by QEMU.
652 * ODAT: the buffer QEMU uses to store the result.
654 * Since the page is reused by both input and out, the input data
655 * will be lost after storing new result into ODAT so we should fetch
656 * all the input data before writing the result.
658 field = aml_field("NRAM", AML_DWORD_ACC, AML_NOLOCK, AML_PRESERVE);
659 aml_append(field, aml_named_field("RLEN",
660 sizeof(typeof_field(NvdimmDsmOut, len)) * BITS_PER_BYTE));
661 aml_append(field, aml_named_field("ODAT",
662 (TARGET_PAGE_SIZE - offsetof(NvdimmDsmOut, data)) *
663 BITS_PER_BYTE));
664 aml_append(dev, field);
666 nvdimm_build_common_dsm(dev);
667 nvdimm_build_device_dsm(dev);
669 nvdimm_build_nvdimm_devices(device_list, dev);
671 aml_append(sb_scope, dev);
672 aml_append(ssdt, sb_scope);
674 nvdimm_ssdt = table_data->len;
676 /* copy AML table into ACPI tables blob and patch header there */
677 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
678 mem_addr_offset = build_append_named_dword(table_data,
679 NVDIMM_ACPI_MEM_ADDR);
681 bios_linker_loader_alloc(linker, NVDIMM_DSM_MEM_FILE, TARGET_PAGE_SIZE,
682 false /* high memory */);
683 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
684 NVDIMM_DSM_MEM_FILE, table_data,
685 table_data->data + mem_addr_offset,
686 sizeof(uint32_t));
687 build_header(linker, table_data,
688 (void *)(table_data->data + nvdimm_ssdt),
689 "SSDT", table_data->len - nvdimm_ssdt, 1, NULL, "NVDIMM");
690 free_aml_allocator();
693 void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data,
694 GArray *linker)
696 GSList *device_list;
698 /* no NVDIMM device is plugged. */
699 device_list = nvdimm_get_plugged_device_list();
700 if (!device_list) {
701 return;
703 nvdimm_build_nfit(device_list, table_offsets, table_data, linker);
704 nvdimm_build_ssdt(device_list, table_offsets, table_data, linker);
705 g_slist_free(device_list);