hw/ppc/spapr_cpu_core.c

   1 /*
   2  * sPAPR CPU core device, acts as container of CPU thread devices.
   3  *
   4  * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9 #include "hw/cpu/core.h"
  10 #include "hw/ppc/spapr_cpu_core.h"
  11 #include "target-ppc/cpu.h"
  12 #include "hw/ppc/spapr.h"
  13 #include "hw/boards.h"
  14 #include "qapi/error.h"
  15 #include "sysemu/cpus.h"
  16 #include "target-ppc/kvm_ppc.h"
  17 #include "hw/ppc/ppc.h"
  18 #include "target-ppc/mmu-hash64.h"
  19 #include "sysemu/numa.h"
  20
  21 static void spapr_cpu_reset(void *opaque)
  22 {
  23     sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
  24     PowerPCCPU *cpu = opaque;
  25     CPUState *cs = CPU(cpu);
  26     CPUPPCState *env = &cpu->env;
  27
  28     cpu_reset(cs);
  29
  30     /* All CPUs start halted.  CPU0 is unhalted from the machine level
  31      * reset code and the rest are explicitly started up by the guest
  32      * using an RTAS call */
  33     cs->halted = 1;
  34
  35     env->spr[SPR_HIOR] = 0;
  36
  37     ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift,
  38                                 &error_fatal);
  39 }
  40
  41 static void spapr_cpu_destroy(PowerPCCPU *cpu)
  42 {
  43     sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
  44
  45     xics_cpu_destroy(spapr->xics, cpu);
  46     qemu_unregister_reset(spapr_cpu_reset, cpu);
  47 }
  48
  49 void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp)
  50 {
  51     CPUPPCState *env = &cpu->env;
  52     CPUState *cs = CPU(cpu);
  53     int i;
  54
  55     /* Set time-base frequency to 512 MHz */
  56     cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
  57
  58     /* Enable PAPR mode in TCG or KVM */
  59     cpu_ppc_set_papr(cpu);
  60
  61     if (cpu->max_compat) {
  62         Error *local_err = NULL;
  63
  64         ppc_set_compat(cpu, cpu->max_compat, &local_err);
  65         if (local_err) {
  66             error_propagate(errp, local_err);
  67             return;
  68         }
  69     }
  70
  71     /* Set NUMA node for the added CPUs  */
  72     for (i = 0; i < nb_numa_nodes; i++) {
  73         if (test_bit(cs->cpu_index, numa_info[i].node_cpu)) {
  74             cs->numa_node = i;
  75             break;
  76         }
  77     }
  78
  79     xics_cpu_setup(spapr->xics, cpu);
  80
  81     qemu_register_reset(spapr_cpu_reset, cpu);
  82     spapr_cpu_reset(cpu);
  83 }
  84
  85 /*
  86  * Return the sPAPR CPU core type for @model which essentially is the CPU
  87  * model specified with -cpu cmdline option.
  88  */
  89 char *spapr_get_cpu_core_type(const char *model)
  90 {
  91     char *core_type;
  92     gchar **model_pieces = g_strsplit(model, ",", 2);
  93
  94     core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE);
  95
  96     /* Check whether it exists or whether we have to look up an alias name */
  97     if (!object_class_by_name(core_type)) {
  98         const char *realmodel;
  99
 100         g_free(core_type);
 101         core_type = NULL;
 102         realmodel = ppc_cpu_lookup_alias(model_pieces[0]);
 103         if (realmodel) {
 104             core_type = spapr_get_cpu_core_type(realmodel);
 105         }
 106     }
 107
 108     g_strfreev(model_pieces);
 109     return core_type;
 110 }
 111
 112 static void spapr_core_release(DeviceState *dev, void *opaque)
 113 {
 114     sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 115     sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
 116     const char *typename = object_class_get_name(scc->cpu_class);
 117     size_t size = object_type_get_instance_size(typename);
 118     sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
 119     CPUCore *cc = CPU_CORE(dev);
 120     int i;
 121
 122     for (i = 0; i < cc->nr_threads; i++) {
 123         void *obj = sc->threads + i * size;
 124         DeviceState *dev = DEVICE(obj);
 125         CPUState *cs = CPU(dev);
 126         PowerPCCPU *cpu = POWERPC_CPU(cs);
 127
 128         spapr_cpu_destroy(cpu);
 129         cpu_remove_sync(cs);
 130         object_unparent(obj);
 131     }
 132
 133     spapr->cores[cc->core_id / smp_threads] = NULL;
 134
 135     g_free(sc->threads);
 136     object_unparent(OBJECT(dev));
 137 }
 138
 139 void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
 140                        Error **errp)
 141 {
 142     CPUCore *cc = CPU_CORE(dev);
 143     int smt = kvmppc_smt_threads();
 144     int index = cc->core_id / smp_threads;
 145     sPAPRDRConnector *drc =
 146         spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
 147     sPAPRDRConnectorClass *drck;
 148     Error *local_err = NULL;
 149
 150     if (index == 0) {
 151         error_setg(errp, "Boot CPU core may not be unplugged");
 152         return;
 153     }
 154
 155     g_assert(drc);
 156
 157     drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
 158     drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
 159     if (local_err) {
 160         error_propagate(errp, local_err);
 161         return;
 162     }
 163
 164     spapr_hotplug_req_remove_by_index(drc);
 165 }
 166
 167 void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
 168                      Error **errp)
 169 {
 170     sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
 171     sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
 172     CPUCore *cc = CPU_CORE(dev);
 173     CPUState *cs = CPU(core->threads);
 174     sPAPRDRConnector *drc;
 175     sPAPRDRConnectorClass *drck;
 176     Error *local_err = NULL;
 177     void *fdt = NULL;
 178     int fdt_offset = 0;
 179     int index = cc->core_id / smp_threads;
 180     int smt = kvmppc_smt_threads();
 181
 182     drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
 183     spapr->cores[index] = OBJECT(dev);
 184
 185     g_assert(drc);
 186
 187     /*
 188      * Setup CPU DT entries only for hotplugged CPUs. For boot time or
 189      * coldplugged CPUs DT entries are setup in spapr_finalize_fdt().
 190      */
 191     if (dev->hotplugged) {
 192         fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
 193     }
 194
 195     drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
 196     drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
 197     if (local_err) {
 198         g_free(fdt);
 199         spapr->cores[index] = NULL;
 200         error_propagate(errp, local_err);
 201         return;
 202     }
 203
 204     if (dev->hotplugged) {
 205         /*
 206          * Send hotplug notification interrupt to the guest only in case
 207          * of hotplugged CPUs.
 208          */
 209         spapr_hotplug_req_add_by_index(drc);
 210     } else {
 211         /*
 212          * Set the right DRC states for cold plugged CPU.
 213          */
 214         drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
 215         drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
 216     }
 217 }
 218
 219 void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
 220                          Error **errp)
 221 {
 222     MachineState *machine = MACHINE(OBJECT(hotplug_dev));
 223     MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
 224     sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
 225     int spapr_max_cores = max_cpus / smp_threads;
 226     int index;
 227     Error *local_err = NULL;
 228     CPUCore *cc = CPU_CORE(dev);
 229     char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
 230     const char *type = object_get_typename(OBJECT(dev));
 231
 232     if (!mc->query_hotpluggable_cpus) {
 233         error_setg(&local_err, "CPU hotplug not supported for this machine");
 234         goto out;
 235     }
 236
 237     if (strcmp(base_core_type, type)) {
 238         error_setg(&local_err, "CPU core type should be %s", base_core_type);
 239         goto out;
 240     }
 241
 242     if (cc->nr_threads != smp_threads) {
 243         error_setg(&local_err, "threads must be %d", smp_threads);
 244         goto out;
 245     }
 246
 247     if (cc->core_id % smp_threads) {
 248         error_setg(&local_err, "invalid core id %d", cc->core_id);
 249         goto out;
 250     }
 251
 252     index = cc->core_id / smp_threads;
 253     if (index < 0 || index >= spapr_max_cores) {
 254         error_setg(&local_err, "core id %d out of range", cc->core_id);
 255         goto out;
 256     }
 257
 258     if (spapr->cores[index]) {
 259         error_setg(&local_err, "core %d already populated", cc->core_id);
 260         goto out;
 261     }
 262
 263 out:
 264     g_free(base_core_type);
 265     error_propagate(errp, local_err);
 266 }
 267
 268 static void spapr_cpu_core_realize_child(Object *child, Error **errp)
 269 {
 270     Error *local_err = NULL;
 271     sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
 272     CPUState *cs = CPU(child);
 273     PowerPCCPU *cpu = POWERPC_CPU(cs);
 274
 275     object_property_set_bool(child, true, "realized", &local_err);
 276     if (local_err) {
 277         error_propagate(errp, local_err);
 278         return;
 279     }
 280
 281     spapr_cpu_init(spapr, cpu, &local_err);
 282     if (local_err) {
 283         error_propagate(errp, local_err);
 284         return;
 285     }
 286 }
 287
 288 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
 289 {
 290     sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 291     sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
 292     CPUCore *cc = CPU_CORE(OBJECT(dev));
 293     const char *typename = object_class_get_name(scc->cpu_class);
 294     size_t size = object_type_get_instance_size(typename);
 295     Error *local_err = NULL;
 296     void *obj;
 297     int i, j;
 298
 299     sc->threads = g_malloc0(size * cc->nr_threads);
 300     for (i = 0; i < cc->nr_threads; i++) {
 301         char id[32];
 302         CPUState *cs;
 303
 304         obj = sc->threads + i * size;
 305
 306         object_initialize(obj, size, typename);
 307         cs = CPU(obj);
 308         cs->cpu_index = cc->core_id + i;
 309         snprintf(id, sizeof(id), "thread[%d]", i);
 310         object_property_add_child(OBJECT(sc), id, obj, &local_err);
 311         if (local_err) {
 312             goto err;
 313         }
 314         object_unref(obj);
 315     }
 316
 317     for (j = 0; j < cc->nr_threads; j++) {
 318         obj = sc->threads + j * size;
 319
 320         spapr_cpu_core_realize_child(obj, &local_err);
 321         if (local_err) {
 322             goto err;
 323         }
 324     }
 325     return;
 326
 327 err:
 328     while (--i >= 0) {
 329         obj = sc->threads + i * size;
 330         object_unparent(obj);
 331     }
 332     g_free(sc->threads);
 333     error_propagate(errp, local_err);
 334 }
 335
 336 static const char *spapr_core_models[] = {
 337     /* 970 */
 338     "970_v2.2",
 339
 340     /* 970MP variants */
 341     "970MP_v1.0",
 342     "970mp_v1.0",
 343     "970MP_v1.1",
 344     "970mp_v1.1",
 345
 346     /* POWER5+ */
 347     "POWER5+_v2.1",
 348
 349     /* POWER7 */
 350     "POWER7_v2.3",
 351
 352     /* POWER7+ */
 353     "POWER7+_v2.1",
 354
 355     /* POWER8 */
 356     "POWER8_v2.0",
 357
 358     /* POWER8E */
 359     "POWER8E_v2.1",
 360
 361     /* POWER8NVL */
 362     "POWER8NVL_v1.0",
 363 };
 364
 365 void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
 366 {
 367     DeviceClass *dc = DEVICE_CLASS(oc);
 368     sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
 369
 370     dc->realize = spapr_cpu_core_realize;
 371     scc->cpu_class = cpu_class_by_name(TYPE_POWERPC_CPU, data);
 372     g_assert(scc->cpu_class);
 373 }
 374
 375 static const TypeInfo spapr_cpu_core_type_info = {
 376     .name = TYPE_SPAPR_CPU_CORE,
 377     .parent = TYPE_CPU_CORE,
 378     .abstract = true,
 379     .instance_size = sizeof(sPAPRCPUCore),
 380     .class_size = sizeof(sPAPRCPUCoreClass),
 381 };
 382
 383 static void spapr_cpu_core_register_types(void)
 384 {
 385     int i;
 386
 387     type_register_static(&spapr_cpu_core_type_info);
 388
 389     for (i = 0; i < ARRAY_SIZE(spapr_core_models); i++) {
 390         TypeInfo type_info = {
 391             .parent = TYPE_SPAPR_CPU_CORE,
 392             .instance_size = sizeof(sPAPRCPUCore),
 393             .class_init = spapr_cpu_core_class_init,
 394             .class_data = (void *) spapr_core_models[i],
 395         };
 396
 397         type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE,
 398                                          spapr_core_models[i]);
 399         type_register(&type_info);
 400         g_free((void *)type_info.name);
 401     }
 402 }
 403
 404 type_init(spapr_cpu_core_register_types)