target/nios2/cpu.h

   1 /*
   2  * Altera Nios II virtual CPU header
   3  *
   4  * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20 #ifndef CPU_NIOS2_H
  21 #define CPU_NIOS2_H
  22
  23 #include "qemu/osdep.h"
  24 #include "qemu-common.h"
  25
  26 #define TARGET_LONG_BITS 32
  27
  28 #define CPUArchState struct CPUNios2State
  29
  30 #include "exec/cpu-defs.h"
  31 #include "fpu/softfloat.h"
  32 #include "qom/cpu.h"
  33 struct CPUNios2State;
  34 typedef struct CPUNios2State CPUNios2State;
  35 #if !defined(CONFIG_USER_ONLY)
  36 #include "mmu.h"
  37 #endif
  38
  39 #define TYPE_NIOS2_CPU "nios2-cpu"
  40
  41 #define NIOS2_CPU_CLASS(klass) \
  42     OBJECT_CLASS_CHECK(Nios2CPUClass, (klass), TYPE_NIOS2_CPU)
  43 #define NIOS2_CPU(obj) \
  44     OBJECT_CHECK(Nios2CPU, (obj), TYPE_NIOS2_CPU)
  45 #define NIOS2_CPU_GET_CLASS(obj) \
  46     OBJECT_GET_CLASS(Nios2CPUClass, (obj), TYPE_NIOS2_CPU)
  47
  48 /**
  49  * Nios2CPUClass:
  50  * @parent_reset: The parent class' reset handler.
  51  *
  52  * A Nios2 CPU model.
  53  */
  54 typedef struct Nios2CPUClass {
  55     /*< private >*/
  56     CPUClass parent_class;
  57     /*< public >*/
  58
  59     DeviceRealize parent_realize;
  60     void (*parent_reset)(CPUState *cpu);
  61 } Nios2CPUClass;
  62
  63 #define TARGET_HAS_ICE 1
  64
  65 /* Configuration options for Nios II */
  66 #define RESET_ADDRESS         0x00000000
  67 #define EXCEPTION_ADDRESS     0x00000004
  68 #define FAST_TLB_MISS_ADDRESS 0x00000008
  69
  70
  71 /* GP regs + CR regs + PC */
  72 #define NUM_CORE_REGS (32 + 32 + 1)
  73
  74 /* General purpose register aliases */
  75 #define R_ZERO   0
  76 #define R_AT     1
  77 #define R_RET0   2
  78 #define R_RET1   3
  79 #define R_ARG0   4
  80 #define R_ARG1   5
  81 #define R_ARG2   6
  82 #define R_ARG3   7
  83 #define R_ET     24
  84 #define R_BT     25
  85 #define R_GP     26
  86 #define R_SP     27
  87 #define R_FP     28
  88 #define R_EA     29
  89 #define R_BA     30
  90 #define R_RA     31
  91
  92 /* Control register aliases */
  93 #define CR_BASE  32
  94 #define CR_STATUS    (CR_BASE + 0)
  95 #define   CR_STATUS_PIE  (1 << 0)
  96 #define   CR_STATUS_U    (1 << 1)
  97 #define   CR_STATUS_EH   (1 << 2)
  98 #define   CR_STATUS_IH   (1 << 3)
  99 #define   CR_STATUS_IL   (63 << 4)
 100 #define   CR_STATUS_CRS  (63 << 10)
 101 #define   CR_STATUS_PRS  (63 << 16)
 102 #define   CR_STATUS_NMI  (1 << 22)
 103 #define   CR_STATUS_RSIE (1 << 23)
 104 #define CR_ESTATUS   (CR_BASE + 1)
 105 #define CR_BSTATUS   (CR_BASE + 2)
 106 #define CR_IENABLE   (CR_BASE + 3)
 107 #define CR_IPENDING  (CR_BASE + 4)
 108 #define CR_CPUID     (CR_BASE + 5)
 109 #define CR_CTL6      (CR_BASE + 6)
 110 #define CR_EXCEPTION (CR_BASE + 7)
 111 #define CR_PTEADDR   (CR_BASE + 8)
 112 #define   CR_PTEADDR_PTBASE_SHIFT 22
 113 #define   CR_PTEADDR_PTBASE_MASK  (0x3FF << CR_PTEADDR_PTBASE_SHIFT)
 114 #define   CR_PTEADDR_VPN_SHIFT    2
 115 #define   CR_PTEADDR_VPN_MASK     (0xFFFFF << CR_PTEADDR_VPN_SHIFT)
 116 #define CR_TLBACC    (CR_BASE + 9)
 117 #define   CR_TLBACC_IGN_SHIFT 25
 118 #define   CR_TLBACC_IGN_MASK  (0x7F << CR_TLBACC_IGN_SHIFT)
 119 #define   CR_TLBACC_C         (1 << 24)
 120 #define   CR_TLBACC_R         (1 << 23)
 121 #define   CR_TLBACC_W         (1 << 22)
 122 #define   CR_TLBACC_X         (1 << 21)
 123 #define   CR_TLBACC_G         (1 << 20)
 124 #define   CR_TLBACC_PFN_MASK  0x000FFFFF
 125 #define CR_TLBMISC   (CR_BASE + 10)
 126 #define   CR_TLBMISC_WAY_SHIFT 20
 127 #define   CR_TLBMISC_WAY_MASK  (0xF << CR_TLBMISC_WAY_SHIFT)
 128 #define   CR_TLBMISC_RD        (1 << 19)
 129 #define   CR_TLBMISC_WR        (1 << 18)
 130 #define   CR_TLBMISC_PID_SHIFT 4
 131 #define   CR_TLBMISC_PID_MASK  (0x3FFF << CR_TLBMISC_PID_SHIFT)
 132 #define   CR_TLBMISC_DBL       (1 << 3)
 133 #define   CR_TLBMISC_BAD       (1 << 2)
 134 #define   CR_TLBMISC_PERM      (1 << 1)
 135 #define   CR_TLBMISC_D         (1 << 0)
 136 #define CR_ENCINJ    (CR_BASE + 11)
 137 #define CR_BADADDR   (CR_BASE + 12)
 138 #define CR_CONFIG    (CR_BASE + 13)
 139 #define CR_MPUBASE   (CR_BASE + 14)
 140 #define CR_MPUACC    (CR_BASE + 15)
 141
 142 /* Other registers */
 143 #define R_PC         64
 144
 145 /* Exceptions */
 146 #define EXCP_BREAK    -1
 147 #define EXCP_RESET    0
 148 #define EXCP_PRESET   1
 149 #define EXCP_IRQ      2
 150 #define EXCP_TRAP     3
 151 #define EXCP_UNIMPL   4
 152 #define EXCP_ILLEGAL  5
 153 #define EXCP_UNALIGN  6
 154 #define EXCP_UNALIGND 7
 155 #define EXCP_DIV      8
 156 #define EXCP_SUPERA   9
 157 #define EXCP_SUPERI   10
 158 #define EXCP_SUPERD   11
 159 #define EXCP_TLBD     12
 160 #define EXCP_TLBX     13
 161 #define EXCP_TLBR     14
 162 #define EXCP_TLBW     15
 163 #define EXCP_MPUI     16
 164 #define EXCP_MPUD     17
 165
 166 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
 167
 168 #define NB_MMU_MODES 2
 169
 170 struct CPUNios2State {
 171     uint32_t regs[NUM_CORE_REGS];
 172
 173 #if !defined(CONFIG_USER_ONLY)
 174     Nios2MMU mmu;
 175
 176     uint32_t irq_pending;
 177 #endif
 178
 179     CPU_COMMON
 180 };
 181
 182 /**
 183  * Nios2CPU:
 184  * @env: #CPUNios2State
 185  *
 186  * A Nios2 CPU.
 187  */
 188 typedef struct Nios2CPU {
 189     /*< private >*/
 190     CPUState parent_obj;
 191     /*< public >*/
 192
 193     CPUNios2State env;
 194     bool mmu_present;
 195     uint32_t pid_num_bits;
 196     uint32_t tlb_num_ways;
 197     uint32_t tlb_num_entries;
 198
 199     /* Addresses that are hard-coded in the FPGA build settings */
 200     uint32_t reset_addr;
 201     uint32_t exception_addr;
 202     uint32_t fast_tlb_miss_addr;
 203 } Nios2CPU;
 204
 205 static inline Nios2CPU *nios2_env_get_cpu(CPUNios2State *env)
 206 {
 207     return NIOS2_CPU(container_of(env, Nios2CPU, env));
 208 }
 209
 210 #define ENV_GET_CPU(e) CPU(nios2_env_get_cpu(e))
 211
 212 #define ENV_OFFSET offsetof(Nios2CPU, env)
 213
 214 void nios2_tcg_init(void);
 215 Nios2CPU *cpu_nios2_init(const char *cpu_model);
 216 void nios2_cpu_do_interrupt(CPUState *cs);
 217 int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc);
 218 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUNios2State *env);
 219 void nios2_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 220                           int flags);
 221 hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 222 void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 223                                    MMUAccessType access_type,
 224                                    int mmu_idx, uintptr_t retaddr);
 225
 226 qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu);
 227 void nios2_check_interrupts(CPUNios2State *env);
 228
 229 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 230 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 231
 232 #define cpu_init(cpu_model) CPU(cpu_nios2_init(cpu_model))
 233
 234 #define cpu_gen_code cpu_nios2_gen_code
 235 #define cpu_signal_handler cpu_nios2_signal_handler
 236
 237 #define CPU_SAVE_VERSION 1
 238
 239 #define TARGET_PAGE_BITS 12
 240
 241 /* MMU modes definitions */
 242 #define MMU_MODE0_SUFFIX _kernel
 243 #define MMU_MODE1_SUFFIX _user
 244 #define MMU_SUPERVISOR_IDX  0
 245 #define MMU_USER_IDX        1
 246
 247 static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
 248 {
 249     return (env->regs[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX :
 250                                                   MMU_SUPERVISOR_IDX;
 251 }
 252
 253 int nios2_cpu_handle_mmu_fault(CPUState *env, vaddr address,
 254                                int rw, int mmu_idx);
 255
 256 static inline int cpu_interrupts_enabled(CPUNios2State *env)
 257 {
 258     return env->regs[CR_STATUS] & CR_STATUS_PIE;
 259 }
 260
 261 #include "exec/cpu-all.h"
 262 #include "exec/exec-all.h"
 263
 264 static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
 265                                         target_ulong *cs_base, uint32_t *flags)
 266 {
 267     *pc = env->regs[R_PC];
 268     *cs_base = 0;
 269     *flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U));
 270 }
 271
 272 #endif /* CPU_NIOS2_H */