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hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
[qemu/kevin.git] / hw / riscv / virt.c
blob86c4adc0c966dd27bf2e75d525bb9179fb219d62
1 /*
2 * QEMU RISC-V VirtIO Board
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * RISC-V machine with 16550a UART and VirtIO MMIO
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
25 #include "qapi/error.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/sysbus.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial.h"
31 #include "target/riscv/cpu.h"
32 #include "hw/core/sysbus-fdt.h"
33 #include "target/riscv/pmu.h"
34 #include "hw/riscv/riscv_hart.h"
35 #include "hw/riscv/virt.h"
36 #include "hw/riscv/boot.h"
37 #include "hw/riscv/numa.h"
38 #include "hw/intc/riscv_aclint.h"
39 #include "hw/intc/riscv_aplic.h"
40 #include "hw/intc/riscv_imsic.h"
41 #include "hw/intc/sifive_plic.h"
42 #include "hw/misc/sifive_test.h"
43 #include "hw/platform-bus.h"
44 #include "chardev/char.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/sysemu.h"
47 #include "sysemu/kvm.h"
48 #include "sysemu/tpm.h"
49 #include "hw/pci/pci.h"
50 #include "hw/pci-host/gpex.h"
51 #include "hw/display/ramfb.h"
52
53 /*
54 * The virt machine physical address space used by some of the devices
55 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
56 * number of CPUs, and number of IMSIC guest files.
57 *
58 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
59 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
60 * of virt machine physical address space.
61 */
62
63 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
64 #if VIRT_IMSIC_GROUP_MAX_SIZE < \
65 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
66 #error "Can't accomodate single IMSIC group in address space"
67 #endif
68
69 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \
70 VIRT_IMSIC_GROUP_MAX_SIZE)
71 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE
72 #error "Can't accomodate all IMSIC groups in address space"
73 #endif
74
75 static const MemMapEntry virt_memmap[] = {
76 [VIRT_DEBUG] = { 0x0, 0x100 },
77 [VIRT_MROM] = { 0x1000, 0xf000 },
78 [VIRT_TEST] = { 0x100000, 0x1000 },
79 [VIRT_RTC] = { 0x101000, 0x1000 },
80 [VIRT_CLINT] = { 0x2000000, 0x10000 },
81 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
82 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
83 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 },
84 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
85 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
86 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
87 [VIRT_UART0] = { 0x10000000, 0x100 },
88 [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
89 [VIRT_FW_CFG] = { 0x10100000, 0x18 },
90 [VIRT_FLASH] = { 0x20000000, 0x4000000 },
91 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
92 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE },
93 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
94 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
95 [VIRT_DRAM] = { 0x80000000, 0x0 },
96 };
97
98 /* PCIe high mmio is fixed for RV32 */
99 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
100 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
101
102 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
103 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
104
105 static MemMapEntry virt_high_pcie_memmap;
106
107 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
108
109 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
110 const char *name,
111 const char *alias_prop_name)
112 {
113 /*
114 * Create a single flash device. We use the same parameters as
115 * the flash devices on the ARM virt board.
116 */
117 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
118
119 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
120 qdev_prop_set_uint8(dev, "width", 4);
121 qdev_prop_set_uint8(dev, "device-width", 2);
122 qdev_prop_set_bit(dev, "big-endian", false);
123 qdev_prop_set_uint16(dev, "id0", 0x89);
124 qdev_prop_set_uint16(dev, "id1", 0x18);
125 qdev_prop_set_uint16(dev, "id2", 0x00);
126 qdev_prop_set_uint16(dev, "id3", 0x00);
127 qdev_prop_set_string(dev, "name", name);
128
129 object_property_add_child(OBJECT(s), name, OBJECT(dev));
130 object_property_add_alias(OBJECT(s), alias_prop_name,
131 OBJECT(dev), "drive");
132
133 return PFLASH_CFI01(dev);
134 }
135
136 static void virt_flash_create(RISCVVirtState *s)
137 {
138 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
139 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
140 }
141
142 static void virt_flash_map1(PFlashCFI01 *flash,
143 hwaddr base, hwaddr size,
144 MemoryRegion *sysmem)
145 {
146 DeviceState *dev = DEVICE(flash);
147
148 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
149 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
150 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
151 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
152
153 memory_region_add_subregion(sysmem, base,
154 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
155 0));
156 }
157
158 static void virt_flash_map(RISCVVirtState *s,
159 MemoryRegion *sysmem)
160 {
161 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
162 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
163
164 virt_flash_map1(s->flash[0], flashbase, flashsize,
165 sysmem);
166 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
167 sysmem);
168 }
169
170 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
171 uint32_t irqchip_phandle)
172 {
173 int pin, dev;
174 uint32_t irq_map_stride = 0;
175 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS *
176 FDT_MAX_INT_MAP_WIDTH] = {};
177 uint32_t *irq_map = full_irq_map;
178
179 /* This code creates a standard swizzle of interrupts such that
180 * each device's first interrupt is based on it's PCI_SLOT number.
181 * (See pci_swizzle_map_irq_fn())
182 *
183 * We only need one entry per interrupt in the table (not one per
184 * possible slot) seeing the interrupt-map-mask will allow the table
185 * to wrap to any number of devices.
186 */
187 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
188 int devfn = dev * 0x8;
189
190 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
191 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
192 int i = 0;
193
194 /* Fill PCI address cells */
195 irq_map[i] = cpu_to_be32(devfn << 8);
196 i += FDT_PCI_ADDR_CELLS;
197
198 /* Fill PCI Interrupt cells */
199 irq_map[i] = cpu_to_be32(pin + 1);
200 i += FDT_PCI_INT_CELLS;
201
202 /* Fill interrupt controller phandle and cells */
203 irq_map[i++] = cpu_to_be32(irqchip_phandle);
204 irq_map[i++] = cpu_to_be32(irq_nr);
205 if (s->aia_type != VIRT_AIA_TYPE_NONE) {
206 irq_map[i++] = cpu_to_be32(0x4);
207 }
208
209 if (!irq_map_stride) {
210 irq_map_stride = i;
211 }
212 irq_map += irq_map_stride;
213 }
214 }
215
216 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
217 GPEX_NUM_IRQS * GPEX_NUM_IRQS *
218 irq_map_stride * sizeof(uint32_t));
219
220 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
221 0x1800, 0, 0, 0x7);
222 }
223
224 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
225 char *clust_name, uint32_t *phandle,
226 uint32_t *intc_phandles)
227 {
228 int cpu;
229 uint32_t cpu_phandle;
230 MachineState *ms = MACHINE(s);
231 char *name, *cpu_name, *core_name, *intc_name;
232 bool is_32_bit = riscv_is_32bit(&s->soc[0]);
233
234 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
235 cpu_phandle = (*phandle)++;
236
237 cpu_name = g_strdup_printf("/cpus/cpu@%d",
238 s->soc[socket].hartid_base + cpu);
239 qemu_fdt_add_subnode(ms->fdt, cpu_name);
240 if (riscv_feature(&s->soc[socket].harts[cpu].env,
241 RISCV_FEATURE_MMU)) {
242 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
243 (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
244 } else {
245 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
246 "riscv,none");
247 }
248 name = riscv_isa_string(&s->soc[socket].harts[cpu]);
249 qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
250 g_free(name);
251 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
252 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay");
253 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg",
254 s->soc[socket].hartid_base + cpu);
255 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu");
256 riscv_socket_fdt_write_id(ms, cpu_name, socket);
257 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle);
258
259 intc_phandles[cpu] = (*phandle)++;
260
261 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
262 qemu_fdt_add_subnode(ms->fdt, intc_name);
263 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle",
264 intc_phandles[cpu]);
265 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible",
266 "riscv,cpu-intc");
267 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0);
268 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1);
269
270 core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
271 qemu_fdt_add_subnode(ms->fdt, core_name);
272 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle);
273
274 g_free(core_name);
275 g_free(intc_name);
276 g_free(cpu_name);
277 }
278 }
279
280 static void create_fdt_socket_memory(RISCVVirtState *s,
281 const MemMapEntry *memmap, int socket)
282 {
283 char *mem_name;
284 uint64_t addr, size;
285 MachineState *ms = MACHINE(s);
286
287 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket);
288 size = riscv_socket_mem_size(ms, socket);
289 mem_name = g_strdup_printf("/memory@%lx", (long)addr);
290 qemu_fdt_add_subnode(ms->fdt, mem_name);
291 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg",
292 addr >> 32, addr, size >> 32, size);
293 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory");
294 riscv_socket_fdt_write_id(ms, mem_name, socket);
295 g_free(mem_name);
296 }
297
298 static void create_fdt_socket_clint(RISCVVirtState *s,
299 const MemMapEntry *memmap, int socket,
300 uint32_t *intc_phandles)
301 {
302 int cpu;
303 char *clint_name;
304 uint32_t *clint_cells;
305 unsigned long clint_addr;
306 MachineState *ms = MACHINE(s);
307 static const char * const clint_compat[2] = {
308 "sifive,clint0", "riscv,clint0"
309 };
310
311 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
312
313 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
314 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
315 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
316 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
317 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
318 }
319
320 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
321 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
322 qemu_fdt_add_subnode(ms->fdt, clint_name);
323 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
324 (char **)&clint_compat,
325 ARRAY_SIZE(clint_compat));
326 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg",
327 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
328 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended",
329 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
330 riscv_socket_fdt_write_id(ms, clint_name, socket);
331 g_free(clint_name);
332
333 g_free(clint_cells);
334 }
335
336 static void create_fdt_socket_aclint(RISCVVirtState *s,
337 const MemMapEntry *memmap, int socket,
338 uint32_t *intc_phandles)
339 {
340 int cpu;
341 char *name;
342 unsigned long addr, size;
343 uint32_t aclint_cells_size;
344 uint32_t *aclint_mswi_cells;
345 uint32_t *aclint_sswi_cells;
346 uint32_t *aclint_mtimer_cells;
347 MachineState *ms = MACHINE(s);
348
349 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
350 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
351 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
352
353 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
354 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
355 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT);
356 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
357 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER);
358 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
359 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT);
360 }
361 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;
362
363 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
364 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
365 name = g_strdup_printf("/soc/mswi@%lx", addr);
366 qemu_fdt_add_subnode(ms->fdt, name);
367 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
368 "riscv,aclint-mswi");
369 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
370 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
371 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
372 aclint_mswi_cells, aclint_cells_size);
373 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
374 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
375 riscv_socket_fdt_write_id(ms, name, socket);
376 g_free(name);
377 }
378
379 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
380 addr = memmap[VIRT_CLINT].base +
381 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket);
382 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE;
383 } else {
384 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
385 (memmap[VIRT_CLINT].size * socket);
386 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE;
387 }
388 name = g_strdup_printf("/soc/mtimer@%lx", addr);
389 qemu_fdt_add_subnode(ms->fdt, name);
390 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
391 "riscv,aclint-mtimer");
392 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
393 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
394 0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
395 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
396 0x0, RISCV_ACLINT_DEFAULT_MTIME);
397 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
398 aclint_mtimer_cells, aclint_cells_size);
399 riscv_socket_fdt_write_id(ms, name, socket);
400 g_free(name);
401
402 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
403 addr = memmap[VIRT_ACLINT_SSWI].base +
404 (memmap[VIRT_ACLINT_SSWI].size * socket);
405 name = g_strdup_printf("/soc/sswi@%lx", addr);
406 qemu_fdt_add_subnode(ms->fdt, name);
407 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
408 "riscv,aclint-sswi");
409 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
410 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
411 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
412 aclint_sswi_cells, aclint_cells_size);
413 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
414 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
415 riscv_socket_fdt_write_id(ms, name, socket);
416 g_free(name);
417 }
418
419 g_free(aclint_mswi_cells);
420 g_free(aclint_mtimer_cells);
421 g_free(aclint_sswi_cells);
422 }
423
424 static void create_fdt_socket_plic(RISCVVirtState *s,
425 const MemMapEntry *memmap, int socket,
426 uint32_t *phandle, uint32_t *intc_phandles,
427 uint32_t *plic_phandles)
428 {
429 int cpu;
430 char *plic_name;
431 uint32_t *plic_cells;
432 unsigned long plic_addr;
433 MachineState *ms = MACHINE(s);
434 static const char * const plic_compat[2] = {
435 "sifive,plic-1.0.0", "riscv,plic0"
436 };
437
438 if (kvm_enabled()) {
439 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
440 } else {
441 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
442 }
443
444 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
445 if (kvm_enabled()) {
446 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
447 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
448 } else {
449 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
450 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
451 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
452 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
453 }
454 }
455
456 plic_phandles[socket] = (*phandle)++;
457 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
458 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
459 qemu_fdt_add_subnode(ms->fdt, plic_name);
460 qemu_fdt_setprop_cell(ms->fdt, plic_name,
461 "#interrupt-cells", FDT_PLIC_INT_CELLS);
462 qemu_fdt_setprop_cell(ms->fdt, plic_name,
463 "#address-cells", FDT_PLIC_ADDR_CELLS);
464 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible",
465 (char **)&plic_compat,
466 ARRAY_SIZE(plic_compat));
467 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0);
468 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended",
469 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
470 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg",
471 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
472 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev",
473 VIRT_IRQCHIP_NUM_SOURCES - 1);
474 riscv_socket_fdt_write_id(ms, plic_name, socket);
475 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle",
476 plic_phandles[socket]);
477
478 if (!socket) {
479 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name,
480 memmap[VIRT_PLATFORM_BUS].base,
481 memmap[VIRT_PLATFORM_BUS].size,
482 VIRT_PLATFORM_BUS_IRQ);
483 }
484
485 g_free(plic_name);
486
487 g_free(plic_cells);
488 }
489
490 static uint32_t imsic_num_bits(uint32_t count)
491 {
492 uint32_t ret = 0;
493
494 while (BIT(ret) < count) {
495 ret++;
496 }
497
498 return ret;
499 }
500
501 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
502 uint32_t *phandle, uint32_t *intc_phandles,
503 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
504 {
505 int cpu, socket;
506 char *imsic_name;
507 MachineState *ms = MACHINE(s);
508 int socket_count = riscv_socket_count(ms);
509 uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
510 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
511
512 *msi_m_phandle = (*phandle)++;
513 *msi_s_phandle = (*phandle)++;
514 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2);
515 imsic_regs = g_new0(uint32_t, socket_count * 4);
516
517 /* M-level IMSIC node */
518 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
519 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
520 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
521 }
522 imsic_max_hart_per_socket = 0;
523 for (socket = 0; socket < socket_count; socket++) {
524 imsic_addr = memmap[VIRT_IMSIC_M].base +
525 socket * VIRT_IMSIC_GROUP_MAX_SIZE;
526 imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts;
527 imsic_regs[socket * 4 + 0] = 0;
528 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
529 imsic_regs[socket * 4 + 2] = 0;
530 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
531 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
532 imsic_max_hart_per_socket = s->soc[socket].num_harts;
533 }
534 }
535 imsic_name = g_strdup_printf("/soc/imsics@%lx",
536 (unsigned long)memmap[VIRT_IMSIC_M].base);
537 qemu_fdt_add_subnode(ms->fdt, imsic_name);
538 qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
539 "riscv,imsics");
540 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
541 FDT_IMSIC_INT_CELLS);
542 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
543 NULL, 0);
544 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
545 NULL, 0);
546 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
547 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
548 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
549 socket_count * sizeof(uint32_t) * 4);
550 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
551 VIRT_IRQCHIP_NUM_MSIS);
552 if (socket_count > 1) {
553 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
554 imsic_num_bits(imsic_max_hart_per_socket));
555 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
556 imsic_num_bits(socket_count));
557 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
558 IMSIC_MMIO_GROUP_MIN_SHIFT);
559 }
560 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle);
561
562 g_free(imsic_name);
563
564 /* S-level IMSIC node */
565 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
566 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
567 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
568 }
569 imsic_guest_bits = imsic_num_bits(s->aia_guests + 1);
570 imsic_max_hart_per_socket = 0;
571 for (socket = 0; socket < socket_count; socket++) {
572 imsic_addr = memmap[VIRT_IMSIC_S].base +
573 socket * VIRT_IMSIC_GROUP_MAX_SIZE;
574 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
575 s->soc[socket].num_harts;
576 imsic_regs[socket * 4 + 0] = 0;
577 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
578 imsic_regs[socket * 4 + 2] = 0;
579 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
580 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
581 imsic_max_hart_per_socket = s->soc[socket].num_harts;
582 }
583 }
584 imsic_name = g_strdup_printf("/soc/imsics@%lx",
585 (unsigned long)memmap[VIRT_IMSIC_S].base);
586 qemu_fdt_add_subnode(ms->fdt, imsic_name);
587 qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
588 "riscv,imsics");
589 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
590 FDT_IMSIC_INT_CELLS);
591 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
592 NULL, 0);
593 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
594 NULL, 0);
595 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
596 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
597 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
598 socket_count * sizeof(uint32_t) * 4);
599 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
600 VIRT_IRQCHIP_NUM_MSIS);
601 if (imsic_guest_bits) {
602 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits",
603 imsic_guest_bits);
604 }
605 if (socket_count > 1) {
606 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
607 imsic_num_bits(imsic_max_hart_per_socket));
608 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
609 imsic_num_bits(socket_count));
610 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
611 IMSIC_MMIO_GROUP_MIN_SHIFT);
612 }
613 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle);
614 g_free(imsic_name);
615
616 g_free(imsic_regs);
617 g_free(imsic_cells);
618 }
619
620 static void create_fdt_socket_aplic(RISCVVirtState *s,
621 const MemMapEntry *memmap, int socket,
622 uint32_t msi_m_phandle,
623 uint32_t msi_s_phandle,
624 uint32_t *phandle,
625 uint32_t *intc_phandles,
626 uint32_t *aplic_phandles)
627 {
628 int cpu;
629 char *aplic_name;
630 uint32_t *aplic_cells;
631 unsigned long aplic_addr;
632 MachineState *ms = MACHINE(s);
633 uint32_t aplic_m_phandle, aplic_s_phandle;
634
635 aplic_m_phandle = (*phandle)++;
636 aplic_s_phandle = (*phandle)++;
637 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
638
639 /* M-level APLIC node */
640 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
641 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
642 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
643 }
644 aplic_addr = memmap[VIRT_APLIC_M].base +
645 (memmap[VIRT_APLIC_M].size * socket);
646 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
647 qemu_fdt_add_subnode(ms->fdt, aplic_name);
648 qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
649 qemu_fdt_setprop_cell(ms->fdt, aplic_name,
650 "#interrupt-cells", FDT_APLIC_INT_CELLS);
651 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
652 if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
653 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
654 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
655 } else {
656 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
657 msi_m_phandle);
658 }
659 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
660 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
661 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
662 VIRT_IRQCHIP_NUM_SOURCES);
663 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children",
664 aplic_s_phandle);
665 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
666 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
667 riscv_socket_fdt_write_id(ms, aplic_name, socket);
668 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle);
669 g_free(aplic_name);
670
671 /* S-level APLIC node */
672 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
673 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
674 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
675 }
676 aplic_addr = memmap[VIRT_APLIC_S].base +
677 (memmap[VIRT_APLIC_S].size * socket);
678 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
679 qemu_fdt_add_subnode(ms->fdt, aplic_name);
680 qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
681 qemu_fdt_setprop_cell(ms->fdt, aplic_name,
682 "#interrupt-cells", FDT_APLIC_INT_CELLS);
683 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
684 if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
685 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
686 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
687 } else {
688 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
689 msi_s_phandle);
690 }
691 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
692 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
693 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
694 VIRT_IRQCHIP_NUM_SOURCES);
695 riscv_socket_fdt_write_id(ms, aplic_name, socket);
696 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle);
697
698 if (!socket) {
699 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name,
700 memmap[VIRT_PLATFORM_BUS].base,
701 memmap[VIRT_PLATFORM_BUS].size,
702 VIRT_PLATFORM_BUS_IRQ);
703 }
704
705 g_free(aplic_name);
706
707 g_free(aplic_cells);
708 aplic_phandles[socket] = aplic_s_phandle;
709 }
710
711 static void create_fdt_pmu(RISCVVirtState *s)
712 {
713 char *pmu_name;
714 MachineState *ms = MACHINE(s);
715 RISCVCPU hart = s->soc[0].harts[0];
716
717 pmu_name = g_strdup_printf("/soc/pmu");
718 qemu_fdt_add_subnode(ms->fdt, pmu_name);
719 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu");
720 riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name);
721
722 g_free(pmu_name);
723 }
724
725 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
726 uint32_t *phandle,
727 uint32_t *irq_mmio_phandle,
728 uint32_t *irq_pcie_phandle,
729 uint32_t *irq_virtio_phandle,
730 uint32_t *msi_pcie_phandle)
731 {
732 char *clust_name;
733 int socket, phandle_pos;
734 MachineState *ms = MACHINE(s);
735 uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
736 uint32_t *intc_phandles, xplic_phandles[MAX_NODES];
737 int socket_count = riscv_socket_count(ms);
738
739 qemu_fdt_add_subnode(ms->fdt, "/cpus");
740 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency",
741 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
742 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
743 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
744 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
745
746 intc_phandles = g_new0(uint32_t, ms->smp.cpus);
747
748 phandle_pos = ms->smp.cpus;
749 for (socket = (socket_count - 1); socket >= 0; socket--) {
750 phandle_pos -= s->soc[socket].num_harts;
751
752 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
753 qemu_fdt_add_subnode(ms->fdt, clust_name);
754
755 create_fdt_socket_cpus(s, socket, clust_name, phandle,
756 &intc_phandles[phandle_pos]);
757
758 create_fdt_socket_memory(s, memmap, socket);
759
760 g_free(clust_name);
761
762 if (!kvm_enabled()) {
763 if (s->have_aclint) {
764 create_fdt_socket_aclint(s, memmap, socket,
765 &intc_phandles[phandle_pos]);
766 } else {
767 create_fdt_socket_clint(s, memmap, socket,
768 &intc_phandles[phandle_pos]);
769 }
770 }
771 }
772
773 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
774 create_fdt_imsic(s, memmap, phandle, intc_phandles,
775 &msi_m_phandle, &msi_s_phandle);
776 *msi_pcie_phandle = msi_s_phandle;
777 }
778
779 phandle_pos = ms->smp.cpus;
780 for (socket = (socket_count - 1); socket >= 0; socket--) {
781 phandle_pos -= s->soc[socket].num_harts;
782
783 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
784 create_fdt_socket_plic(s, memmap, socket, phandle,
785 &intc_phandles[phandle_pos], xplic_phandles);
786 } else {
787 create_fdt_socket_aplic(s, memmap, socket,
788 msi_m_phandle, msi_s_phandle, phandle,
789 &intc_phandles[phandle_pos], xplic_phandles);
790 }
791 }
792
793 g_free(intc_phandles);
794
795 for (socket = 0; socket < socket_count; socket++) {
796 if (socket == 0) {
797 *irq_mmio_phandle = xplic_phandles[socket];
798 *irq_virtio_phandle = xplic_phandles[socket];
799 *irq_pcie_phandle = xplic_phandles[socket];
800 }
801 if (socket == 1) {
802 *irq_virtio_phandle = xplic_phandles[socket];
803 *irq_pcie_phandle = xplic_phandles[socket];
804 }
805 if (socket == 2) {
806 *irq_pcie_phandle = xplic_phandles[socket];
807 }
808 }
809
810 riscv_socket_fdt_write_distance_matrix(ms);
811 }
812
813 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
814 uint32_t irq_virtio_phandle)
815 {
816 int i;
817 char *name;
818 MachineState *ms = MACHINE(s);
819
820 for (i = 0; i < VIRTIO_COUNT; i++) {
821 name = g_strdup_printf("/soc/virtio_mmio@%lx",
822 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
823 qemu_fdt_add_subnode(ms->fdt, name);
824 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio");
825 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
826 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
827 0x0, memmap[VIRT_VIRTIO].size);
828 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
829 irq_virtio_phandle);
830 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
831 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts",
832 VIRTIO_IRQ + i);
833 } else {
834 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts",
835 VIRTIO_IRQ + i, 0x4);
836 }
837 g_free(name);
838 }
839 }
840
841 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
842 uint32_t irq_pcie_phandle,
843 uint32_t msi_pcie_phandle)
844 {
845 char *name;
846 MachineState *ms = MACHINE(s);
847
848 name = g_strdup_printf("/soc/pci@%lx",
849 (long) memmap[VIRT_PCIE_ECAM].base);
850 qemu_fdt_add_subnode(ms->fdt, name);
851 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells",
852 FDT_PCI_ADDR_CELLS);
853 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells",
854 FDT_PCI_INT_CELLS);
855 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2);
856 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
857 "pci-host-ecam-generic");
858 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci");
859 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0);
860 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0,
861 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
862 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0);
863 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
864 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle);
865 }
866 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0,
867 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
868 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges",
869 1, FDT_PCI_RANGE_IOPORT, 2, 0,
870 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
871 1, FDT_PCI_RANGE_MMIO,
872 2, memmap[VIRT_PCIE_MMIO].base,
873 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,
874 1, FDT_PCI_RANGE_MMIO_64BIT,
875 2, virt_high_pcie_memmap.base,
876 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
877
878 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle);
879 g_free(name);
880 }
881
882 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap,
883 uint32_t *phandle)
884 {
885 char *name;
886 uint32_t test_phandle;
887 MachineState *ms = MACHINE(s);
888
889 test_phandle = (*phandle)++;
890 name = g_strdup_printf("/soc/test@%lx",
891 (long)memmap[VIRT_TEST].base);
892 qemu_fdt_add_subnode(ms->fdt, name);
893 {
894 static const char * const compat[3] = {
895 "sifive,test1", "sifive,test0", "syscon"
896 };
897 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible",
898 (char **)&compat, ARRAY_SIZE(compat));
899 }
900 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
901 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size);
902 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle);
903 test_phandle = qemu_fdt_get_phandle(ms->fdt, name);
904 g_free(name);
905
906 name = g_strdup_printf("/reboot");
907 qemu_fdt_add_subnode(ms->fdt, name);
908 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot");
909 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
910 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
911 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET);
912 g_free(name);
913
914 name = g_strdup_printf("/poweroff");
915 qemu_fdt_add_subnode(ms->fdt, name);
916 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff");
917 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
918 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
919 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS);
920 g_free(name);
921 }
922
923 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
924 uint32_t irq_mmio_phandle)
925 {
926 char *name;
927 MachineState *ms = MACHINE(s);
928
929 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base);
930 qemu_fdt_add_subnode(ms->fdt, name);
931 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a");
932 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
933 0x0, memmap[VIRT_UART0].base,
934 0x0, memmap[VIRT_UART0].size);
935 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400);
936 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle);
937 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
938 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ);
939 } else {
940 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4);
941 }
942
943 qemu_fdt_add_subnode(ms->fdt, "/chosen");
944 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name);
945 g_free(name);
946 }
947
948 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
949 uint32_t irq_mmio_phandle)
950 {
951 char *name;
952 MachineState *ms = MACHINE(s);
953
954 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
955 qemu_fdt_add_subnode(ms->fdt, name);
956 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
957 "google,goldfish-rtc");
958 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
959 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
960 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
961 irq_mmio_phandle);
962 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
963 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ);
964 } else {
965 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4);
966 }
967 g_free(name);
968 }
969
970 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap)
971 {
972 char *name;
973 MachineState *ms = MACHINE(s);
974 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
975 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
976
977 name = g_strdup_printf("/flash@%" PRIx64, flashbase);
978 qemu_fdt_add_subnode(ms->fdt, name);
979 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash");
980 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
981 2, flashbase, 2, flashsize,
982 2, flashbase + flashsize, 2, flashsize);
983 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4);
984 g_free(name);
985 }
986
987 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
988 {
989 char *nodename;
990 MachineState *ms = MACHINE(s);
991 hwaddr base = memmap[VIRT_FW_CFG].base;
992 hwaddr size = memmap[VIRT_FW_CFG].size;
993
994 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
995 qemu_fdt_add_subnode(ms->fdt, nodename);
996 qemu_fdt_setprop_string(ms->fdt, nodename,
997 "compatible", "qemu,fw-cfg-mmio");
998 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
999 2, base, 2, size);
1000 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1001 g_free(nodename);
1002 }
1003
1004 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
1005 {
1006 MachineState *ms = MACHINE(s);
1007 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
1008 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
1009 uint8_t rng_seed[32];
1010
1011 if (ms->dtb) {
1012 ms->fdt = load_device_tree(ms->dtb, &s->fdt_size);
1013 if (!ms->fdt) {
1014 error_report("load_device_tree() failed");
1015 exit(1);
1016 }
1017 } else {
1018 ms->fdt = create_device_tree(&s->fdt_size);
1019 if (!ms->fdt) {
1020 error_report("create_device_tree() failed");
1021 exit(1);
1022 }
1023 }
1024
1025 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu");
1026 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio");
1027 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2);
1028 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2);
1029
1030 qemu_fdt_add_subnode(ms->fdt, "/soc");
1031 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0);
1032 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus");
1033 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2);
1034 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2);
1035
1036 create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle,
1037 &irq_pcie_phandle, &irq_virtio_phandle,
1038 &msi_pcie_phandle);
1039
1040 create_fdt_virtio(s, memmap, irq_virtio_phandle);
1041
1042 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle);
1043
1044 create_fdt_reset(s, memmap, &phandle);
1045
1046 create_fdt_uart(s, memmap, irq_mmio_phandle);
1047
1048 create_fdt_rtc(s, memmap, irq_mmio_phandle);
1049
1050 create_fdt_flash(s, memmap);
1051 create_fdt_fw_cfg(s, memmap);
1052 create_fdt_pmu(s);
1053
1054 /* Pass seed to RNG */
1055 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
1056 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed",
1057 rng_seed, sizeof(rng_seed));
1058 }
1059
1060 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
1061 hwaddr ecam_base, hwaddr ecam_size,
1062 hwaddr mmio_base, hwaddr mmio_size,
1063 hwaddr high_mmio_base,
1064 hwaddr high_mmio_size,
1065 hwaddr pio_base,
1066 DeviceState *irqchip)
1067 {
1068 DeviceState *dev;
1069 MemoryRegion *ecam_alias, *ecam_reg;
1070 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
1071 qemu_irq irq;
1072 int i;
1073
1074 dev = qdev_new(TYPE_GPEX_HOST);
1075
1076 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1077
1078 ecam_alias = g_new0(MemoryRegion, 1);
1079 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1080 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1081 ecam_reg, 0, ecam_size);
1082 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
1083
1084 mmio_alias = g_new0(MemoryRegion, 1);
1085 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1086 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1087 mmio_reg, mmio_base, mmio_size);
1088 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
1089
1090 /* Map high MMIO space */
1091 high_mmio_alias = g_new0(MemoryRegion, 1);
1092 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1093 mmio_reg, high_mmio_base, high_mmio_size);
1094 memory_region_add_subregion(get_system_memory(), high_mmio_base,
1095 high_mmio_alias);
1096
1097 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
1098
1099 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1100 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i);
1101
1102 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
1103 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
1104 }
1105
1106 return dev;
1107 }
1108
1109 static FWCfgState *create_fw_cfg(const MachineState *ms)
1110 {
1111 hwaddr base = virt_memmap[VIRT_FW_CFG].base;
1112 FWCfgState *fw_cfg;
1113
1114 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
1115 &address_space_memory);
1116 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1117
1118 return fw_cfg;
1119 }
1120
1121 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
1122 int base_hartid, int hart_count)
1123 {
1124 DeviceState *ret;
1125 char *plic_hart_config;
1126
1127 /* Per-socket PLIC hart topology configuration string */
1128 plic_hart_config = riscv_plic_hart_config_string(hart_count);
1129
1130 /* Per-socket PLIC */
1131 ret = sifive_plic_create(
1132 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size,
1133 plic_hart_config, hart_count, base_hartid,
1134 VIRT_IRQCHIP_NUM_SOURCES,
1135 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1),
1136 VIRT_PLIC_PRIORITY_BASE,
1137 VIRT_PLIC_PENDING_BASE,
1138 VIRT_PLIC_ENABLE_BASE,
1139 VIRT_PLIC_ENABLE_STRIDE,
1140 VIRT_PLIC_CONTEXT_BASE,
1141 VIRT_PLIC_CONTEXT_STRIDE,
1142 memmap[VIRT_PLIC].size);
1143
1144 g_free(plic_hart_config);
1145
1146 return ret;
1147 }
1148
1149 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
1150 const MemMapEntry *memmap, int socket,
1151 int base_hartid, int hart_count)
1152 {
1153 int i;
1154 hwaddr addr;
1155 uint32_t guest_bits;
1156 DeviceState *aplic_m;
1157 bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false;
1158
1159 if (msimode) {
1160 /* Per-socket M-level IMSICs */
1161 addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
1162 for (i = 0; i < hart_count; i++) {
1163 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
1164 base_hartid + i, true, 1,
1165 VIRT_IRQCHIP_NUM_MSIS);
1166 }
1167
1168 /* Per-socket S-level IMSICs */
1169 guest_bits = imsic_num_bits(aia_guests + 1);
1170 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
1171 for (i = 0; i < hart_count; i++) {
1172 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),
1173 base_hartid + i, false, 1 + aia_guests,
1174 VIRT_IRQCHIP_NUM_MSIS);
1175 }
1176 }
1177
1178 /* Per-socket M-level APLIC */
1179 aplic_m = riscv_aplic_create(
1180 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size,
1181 memmap[VIRT_APLIC_M].size,
1182 (msimode) ? 0 : base_hartid,
1183 (msimode) ? 0 : hart_count,
1184 VIRT_IRQCHIP_NUM_SOURCES,
1185 VIRT_IRQCHIP_NUM_PRIO_BITS,
1186 msimode, true, NULL);
1187
1188 if (aplic_m) {
1189 /* Per-socket S-level APLIC */
1190 riscv_aplic_create(
1191 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size,
1192 memmap[VIRT_APLIC_S].size,
1193 (msimode) ? 0 : base_hartid,
1194 (msimode) ? 0 : hart_count,
1195 VIRT_IRQCHIP_NUM_SOURCES,
1196 VIRT_IRQCHIP_NUM_PRIO_BITS,
1197 msimode, false, aplic_m);
1198 }
1199
1200 return aplic_m;
1201 }
1202
1203 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip)
1204 {
1205 DeviceState *dev;
1206 SysBusDevice *sysbus;
1207 const MemMapEntry *memmap = virt_memmap;
1208 int i;
1209 MemoryRegion *sysmem = get_system_memory();
1210
1211 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1212 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1213 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS);
1214 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size);
1215 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1216 s->platform_bus_dev = dev;
1217
1218 sysbus = SYS_BUS_DEVICE(dev);
1219 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) {
1220 int irq = VIRT_PLATFORM_BUS_IRQ + i;
1221 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq));
1222 }
1223
1224 memory_region_add_subregion(sysmem,
1225 memmap[VIRT_PLATFORM_BUS].base,
1226 sysbus_mmio_get_region(sysbus, 0));
1227 }
1228
1229 static void virt_machine_done(Notifier *notifier, void *data)
1230 {
1231 RISCVVirtState *s = container_of(notifier, RISCVVirtState,
1232 machine_done);
1233 const MemMapEntry *memmap = virt_memmap;
1234 MachineState *machine = MACHINE(s);
1235 target_ulong start_addr = memmap[VIRT_DRAM].base;
1236 target_ulong firmware_end_addr, kernel_start_addr;
1237 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);
1238 uint32_t fdt_load_addr;
1239 uint64_t kernel_entry;
1240
1241 /*
1242 * Only direct boot kernel is currently supported for KVM VM,
1243 * so the "-bios" parameter is not supported when KVM is enabled.
1244 */
1245 if (kvm_enabled()) {
1246 if (machine->firmware) {
1247 if (strcmp(machine->firmware, "none")) {
1248 error_report("Machine mode firmware is not supported in "
1249 "combination with KVM.");
1250 exit(1);
1251 }
1252 } else {
1253 machine->firmware = g_strdup("none");
1254 }
1255 }
1256
1257 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
1258 start_addr, NULL);
1259
1260 if (drive_get(IF_PFLASH, 0, 1)) {
1261 /*
1262 * S-mode FW like EDK2 will be kept in second plash (unit 1).
1263 * When both kernel, initrd and pflash options are provided in the
1264 * command line, the kernel and initrd will be copied to the fw_cfg
1265 * table and opensbi will jump to the flash address which is the
1266 * entry point of S-mode FW. It is the job of the S-mode FW to load
1267 * the kernel and initrd using fw_cfg table.
1268 *
1269 * If only pflash is given but not -kernel, then it is the job of
1270 * of the S-mode firmware to locate and load the kernel.
1271 * In either case, the next_addr for opensbi will be the flash address.
1272 */
1273 riscv_setup_firmware_boot(machine);
1274 kernel_entry = virt_memmap[VIRT_FLASH].base +
1275 virt_memmap[VIRT_FLASH].size / 2;
1276 } else if (machine->kernel_filename) {
1277 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
1278 firmware_end_addr);
1279
1280 kernel_entry = riscv_load_kernel(machine, &s->soc[0],
1281 kernel_start_addr, true, NULL);
1282 } else {
1283 /*
1284 * If dynamic firmware is used, it doesn't know where is the next mode
1285 * if kernel argument is not set.
1286 */
1287 kernel_entry = 0;
1288 }
1289
1290 if (drive_get(IF_PFLASH, 0, 0)) {
1291 /*
1292 * Pflash was supplied, let's overwrite the address we jump to after
1293 * reset to the base of the flash.
1294 */
1295 start_addr = virt_memmap[VIRT_FLASH].base;
1296 }
1297
1298 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
1299 memmap[VIRT_DRAM].size,
1300 machine);
1301 riscv_load_fdt(fdt_load_addr, machine->fdt);
1302
1303 /* load the reset vector */
1304 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
1305 virt_memmap[VIRT_MROM].base,
1306 virt_memmap[VIRT_MROM].size, kernel_entry,
1307 fdt_load_addr);
1308
1309 /*
1310 * Only direct boot kernel is currently supported for KVM VM,
1311 * So here setup kernel start address and fdt address.
1312 * TODO:Support firmware loading and integrate to TCG start
1313 */
1314 if (kvm_enabled()) {
1315 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
1316 }
1317 }
1318
1319 static void virt_machine_init(MachineState *machine)
1320 {
1321 const MemMapEntry *memmap = virt_memmap;
1322 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
1323 MemoryRegion *system_memory = get_system_memory();
1324 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
1325 char *soc_name;
1326 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
1327 int i, base_hartid, hart_count;
1328 int socket_count = riscv_socket_count(machine);
1329
1330 /* Check socket count limit */
1331 if (VIRT_SOCKETS_MAX < socket_count) {
1332 error_report("number of sockets/nodes should be less than %d",
1333 VIRT_SOCKETS_MAX);
1334 exit(1);
1335 }
1336
1337 /* Initialize sockets */
1338 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
1339 for (i = 0; i < socket_count; i++) {
1340 if (!riscv_socket_check_hartids(machine, i)) {
1341 error_report("discontinuous hartids in socket%d", i);
1342 exit(1);
1343 }
1344
1345 base_hartid = riscv_socket_first_hartid(machine, i);
1346 if (base_hartid < 0) {
1347 error_report("can't find hartid base for socket%d", i);
1348 exit(1);
1349 }
1350
1351 hart_count = riscv_socket_hart_count(machine, i);
1352 if (hart_count < 0) {
1353 error_report("can't find hart count for socket%d", i);
1354 exit(1);
1355 }
1356
1357 soc_name = g_strdup_printf("soc%d", i);
1358 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
1359 TYPE_RISCV_HART_ARRAY);
1360 g_free(soc_name);
1361 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
1362 machine->cpu_type, &error_abort);
1363 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
1364 base_hartid, &error_abort);
1365 object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
1366 hart_count, &error_abort);
1367 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
1368
1369 if (!kvm_enabled()) {
1370 if (s->have_aclint) {
1371 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
1372 /* Per-socket ACLINT MTIMER */
1373 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1374 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1375 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1376 base_hartid, hart_count,
1377 RISCV_ACLINT_DEFAULT_MTIMECMP,
1378 RISCV_ACLINT_DEFAULT_MTIME,
1379 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1380 } else {
1381 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
1382 riscv_aclint_swi_create(memmap[VIRT_CLINT].base +
1383 i * memmap[VIRT_CLINT].size,
1384 base_hartid, hart_count, false);
1385 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1386 i * memmap[VIRT_CLINT].size +
1387 RISCV_ACLINT_SWI_SIZE,
1388 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1389 base_hartid, hart_count,
1390 RISCV_ACLINT_DEFAULT_MTIMECMP,
1391 RISCV_ACLINT_DEFAULT_MTIME,
1392 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1393 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base +
1394 i * memmap[VIRT_ACLINT_SSWI].size,
1395 base_hartid, hart_count, true);
1396 }
1397 } else {
1398 /* Per-socket SiFive CLINT */
1399 riscv_aclint_swi_create(
1400 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
1401 base_hartid, hart_count, false);
1402 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1403 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
1404 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
1405 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
1406 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1407 }
1408 }
1409
1410 /* Per-socket interrupt controller */
1411 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
1412 s->irqchip[i] = virt_create_plic(memmap, i,
1413 base_hartid, hart_count);
1414 } else {
1415 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests,
1416 memmap, i, base_hartid,
1417 hart_count);
1418 }
1419
1420 /* Try to use different IRQCHIP instance based device type */
1421 if (i == 0) {
1422 mmio_irqchip = s->irqchip[i];
1423 virtio_irqchip = s->irqchip[i];
1424 pcie_irqchip = s->irqchip[i];
1425 }
1426 if (i == 1) {
1427 virtio_irqchip = s->irqchip[i];
1428 pcie_irqchip = s->irqchip[i];
1429 }
1430 if (i == 2) {
1431 pcie_irqchip = s->irqchip[i];
1432 }
1433 }
1434
1435 if (riscv_is_32bit(&s->soc[0])) {
1436 #if HOST_LONG_BITS == 64
1437 /* limit RAM size in a 32-bit system */
1438 if (machine->ram_size > 10 * GiB) {
1439 machine->ram_size = 10 * GiB;
1440 error_report("Limiting RAM size to 10 GiB");
1441 }
1442 #endif
1443 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
1444 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
1445 } else {
1446 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
1447 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;
1448 virt_high_pcie_memmap.base =
1449 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
1450 }
1451
1452 /* register system main memory (actual RAM) */
1453 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
1454 machine->ram);
1455
1456 /* boot rom */
1457 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
1458 memmap[VIRT_MROM].size, &error_fatal);
1459 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
1460 mask_rom);
1461
1462 /*
1463 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the
1464 * device tree cannot be altered and we get FDT_ERR_NOSPACE.
1465 */
1466 s->fw_cfg = create_fw_cfg(machine);
1467 rom_set_fw(s->fw_cfg);
1468
1469 /* SiFive Test MMIO device */
1470 sifive_test_create(memmap[VIRT_TEST].base);
1471
1472 /* VirtIO MMIO devices */
1473 for (i = 0; i < VIRTIO_COUNT; i++) {
1474 sysbus_create_simple("virtio-mmio",
1475 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
1476 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i));
1477 }
1478
1479 gpex_pcie_init(system_memory,
1480 memmap[VIRT_PCIE_ECAM].base,
1481 memmap[VIRT_PCIE_ECAM].size,
1482 memmap[VIRT_PCIE_MMIO].base,
1483 memmap[VIRT_PCIE_MMIO].size,
1484 virt_high_pcie_memmap.base,
1485 virt_high_pcie_memmap.size,
1486 memmap[VIRT_PCIE_PIO].base,
1487 DEVICE(pcie_irqchip));
1488
1489 create_platform_bus(s, DEVICE(mmio_irqchip));
1490
1491 serial_mm_init(system_memory, memmap[VIRT_UART0].base,
1492 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
1493 serial_hd(0), DEVICE_LITTLE_ENDIAN);
1494
1495 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
1496 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ));
1497
1498 virt_flash_create(s);
1499
1500 for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
1501 /* Map legacy -drive if=pflash to machine properties */
1502 pflash_cfi01_legacy_drive(s->flash[i],
1503 drive_get(IF_PFLASH, 0, i));
1504 }
1505 virt_flash_map(s, system_memory);
1506
1507 /* create device tree */
1508 create_fdt(s, memmap);
1509
1510 s->machine_done.notify = virt_machine_done;
1511 qemu_add_machine_init_done_notifier(&s->machine_done);
1512 }
1513
1514 static void virt_machine_instance_init(Object *obj)
1515 {
1516 }
1517
1518 static char *virt_get_aia_guests(Object *obj, Error **errp)
1519 {
1520 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1521 char val[32];
1522
1523 sprintf(val, "%d", s->aia_guests);
1524 return g_strdup(val);
1525 }
1526
1527 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp)
1528 {
1529 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1530
1531 s->aia_guests = atoi(val);
1532 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) {
1533 error_setg(errp, "Invalid number of AIA IMSIC guests");
1534 error_append_hint(errp, "Valid values be between 0 and %d.\n",
1535 VIRT_IRQCHIP_MAX_GUESTS);
1536 }
1537 }
1538
1539 static char *virt_get_aia(Object *obj, Error **errp)
1540 {
1541 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1542 const char *val;
1543
1544 switch (s->aia_type) {
1545 case VIRT_AIA_TYPE_APLIC:
1546 val = "aplic";
1547 break;
1548 case VIRT_AIA_TYPE_APLIC_IMSIC:
1549 val = "aplic-imsic";
1550 break;
1551 default:
1552 val = "none";
1553 break;
1554 };
1555
1556 return g_strdup(val);
1557 }
1558
1559 static void virt_set_aia(Object *obj, const char *val, Error **errp)
1560 {
1561 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1562
1563 if (!strcmp(val, "none")) {
1564 s->aia_type = VIRT_AIA_TYPE_NONE;
1565 } else if (!strcmp(val, "aplic")) {
1566 s->aia_type = VIRT_AIA_TYPE_APLIC;
1567 } else if (!strcmp(val, "aplic-imsic")) {
1568 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC;
1569 } else {
1570 error_setg(errp, "Invalid AIA interrupt controller type");
1571 error_append_hint(errp, "Valid values are none, aplic, and "
1572 "aplic-imsic.\n");
1573 }
1574 }
1575
1576 static bool virt_get_aclint(Object *obj, Error **errp)
1577 {
1578 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1579
1580 return s->have_aclint;
1581 }
1582
1583 static void virt_set_aclint(Object *obj, bool value, Error **errp)
1584 {
1585 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1586
1587 s->have_aclint = value;
1588 }
1589
1590 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1591 DeviceState *dev)
1592 {
1593 MachineClass *mc = MACHINE_GET_CLASS(machine);
1594
1595 if (device_is_dynamic_sysbus(mc, dev)) {
1596 return HOTPLUG_HANDLER(machine);
1597 }
1598 return NULL;
1599 }
1600
1601 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1602 DeviceState *dev, Error **errp)
1603 {
1604 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev);
1605
1606 if (s->platform_bus_dev) {
1607 MachineClass *mc = MACHINE_GET_CLASS(s);
1608
1609 if (device_is_dynamic_sysbus(mc, dev)) {
1610 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev),
1611 SYS_BUS_DEVICE(dev));
1612 }
1613 }
1614 }
1615
1616 static void virt_machine_class_init(ObjectClass *oc, void *data)
1617 {
1618 char str[128];
1619 MachineClass *mc = MACHINE_CLASS(oc);
1620 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1621
1622 mc->desc = "RISC-V VirtIO board";
1623 mc->init = virt_machine_init;
1624 mc->max_cpus = VIRT_CPUS_MAX;
1625 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
1626 mc->pci_allow_0_address = true;
1627 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
1628 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
1629 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
1630 mc->numa_mem_supported = true;
1631 mc->default_ram_id = "riscv_virt_board.ram";
1632 assert(!mc->get_hotplug_handler);
1633 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1634
1635 hc->plug = virt_machine_device_plug_cb;
1636
1637 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1638 #ifdef CONFIG_TPM
1639 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
1640 #endif
1641
1642 object_class_property_add_bool(oc, "aclint", virt_get_aclint,
1643 virt_set_aclint);
1644 object_class_property_set_description(oc, "aclint",
1645 "Set on/off to enable/disable "
1646 "emulating ACLINT devices");
1647
1648 object_class_property_add_str(oc, "aia", virt_get_aia,
1649 virt_set_aia);
1650 object_class_property_set_description(oc, "aia",
1651 "Set type of AIA interrupt "
1652 "conttoller. Valid values are "
1653 "none, aplic, and aplic-imsic.");
1654
1655 object_class_property_add_str(oc, "aia-guests",
1656 virt_get_aia_guests,
1657 virt_set_aia_guests);
1658 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value "
1659 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS);
1660 object_class_property_set_description(oc, "aia-guests", str);
1661 }
1662
1663 static const TypeInfo virt_machine_typeinfo = {
1664 .name = MACHINE_TYPE_NAME("virt"),
1665 .parent = TYPE_MACHINE,
1666 .class_init = virt_machine_class_init,
1667 .instance_init = virt_machine_instance_init,
1668 .instance_size = sizeof(RISCVVirtState),
1669 .interfaces = (InterfaceInfo[]) {
1670 { TYPE_HOTPLUG_HANDLER },
1671 { }
1672 },
1673 };
1674
1675 static void virt_machine_init_register_types(void)
1676 {
1677 type_register_static(&virt_machine_typeinfo);
1678 }
1679
1680 type_init(virt_machine_init_register_types)
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