hw/arm/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu/datadir.h"
  27 #include "cpu.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/arm/boot.h"
  30 #include "hw/arm/primecell.h"
  31 #include "hw/net/lan9118.h"
  32 #include "hw/i2c/i2c.h"
  33 #include "net/net.h"
  34 #include "sysemu/sysemu.h"
  35 #include "hw/boards.h"
  36 #include "hw/loader.h"
  37 #include "hw/block/flash.h"
  38 #include "sysemu/device_tree.h"
  39 #include "qemu/error-report.h"
  40 #include <libfdt.h>
  41 #include "hw/char/pl011.h"
  42 #include "hw/cpu/a9mpcore.h"
  43 #include "hw/cpu/a15mpcore.h"
  44 #include "hw/i2c/arm_sbcon_i2c.h"
  45 #include "hw/sd/sd.h"
  46 #include "qom/object.h"
  47
  48 #define VEXPRESS_BOARD_ID 0x8e0
  49 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
  50 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
  51
  52 /* Number of virtio transports to create (0..8; limited by
  53  * number of available IRQ lines).
  54  */
  55 #define NUM_VIRTIO_TRANSPORTS 4
  56
  57 /* Address maps for peripherals:
  58  * the Versatile Express motherboard has two possible maps,
  59  * the "legacy" one (used for A9) and the "Cortex-A Series"
  60  * map (used for newer cores).
  61  * Individual daughterboards can also have different maps for
  62  * their peripherals.
  63  */
  64
  65 enum {
  66     VE_SYSREGS,
  67     VE_SP810,
  68     VE_SERIALPCI,
  69     VE_PL041,
  70     VE_MMCI,
  71     VE_KMI0,
  72     VE_KMI1,
  73     VE_UART0,
  74     VE_UART1,
  75     VE_UART2,
  76     VE_UART3,
  77     VE_WDT,
  78     VE_TIMER01,
  79     VE_TIMER23,
  80     VE_SERIALDVI,
  81     VE_RTC,
  82     VE_COMPACTFLASH,
  83     VE_CLCD,
  84     VE_NORFLASH0,
  85     VE_NORFLASH1,
  86     VE_NORFLASHALIAS,
  87     VE_SRAM,
  88     VE_VIDEORAM,
  89     VE_ETHERNET,
  90     VE_USB,
  91     VE_DAPROM,
  92     VE_VIRTIO,
  93 };
  94
  95 static hwaddr motherboard_legacy_map[] = {
  96     [VE_NORFLASHALIAS] = 0,
  97     /* CS7: 0x10000000 .. 0x10020000 */
  98     [VE_SYSREGS] = 0x10000000,
  99     [VE_SP810] = 0x10001000,
 100     [VE_SERIALPCI] = 0x10002000,
 101     [VE_PL041] = 0x10004000,
 102     [VE_MMCI] = 0x10005000,
 103     [VE_KMI0] = 0x10006000,
 104     [VE_KMI1] = 0x10007000,
 105     [VE_UART0] = 0x10009000,
 106     [VE_UART1] = 0x1000a000,
 107     [VE_UART2] = 0x1000b000,
 108     [VE_UART3] = 0x1000c000,
 109     [VE_WDT] = 0x1000f000,
 110     [VE_TIMER01] = 0x10011000,
 111     [VE_TIMER23] = 0x10012000,
 112     [VE_VIRTIO] = 0x10013000,
 113     [VE_SERIALDVI] = 0x10016000,
 114     [VE_RTC] = 0x10017000,
 115     [VE_COMPACTFLASH] = 0x1001a000,
 116     [VE_CLCD] = 0x1001f000,
 117     /* CS0: 0x40000000 .. 0x44000000 */
 118     [VE_NORFLASH0] = 0x40000000,
 119     /* CS1: 0x44000000 .. 0x48000000 */
 120     [VE_NORFLASH1] = 0x44000000,
 121     /* CS2: 0x48000000 .. 0x4a000000 */
 122     [VE_SRAM] = 0x48000000,
 123     /* CS3: 0x4c000000 .. 0x50000000 */
 124     [VE_VIDEORAM] = 0x4c000000,
 125     [VE_ETHERNET] = 0x4e000000,
 126     [VE_USB] = 0x4f000000,
 127 };
 128
 129 static hwaddr motherboard_aseries_map[] = {
 130     [VE_NORFLASHALIAS] = 0,
 131     /* CS0: 0x08000000 .. 0x0c000000 */
 132     [VE_NORFLASH0] = 0x08000000,
 133     /* CS4: 0x0c000000 .. 0x10000000 */
 134     [VE_NORFLASH1] = 0x0c000000,
 135     /* CS5: 0x10000000 .. 0x14000000 */
 136     /* CS1: 0x14000000 .. 0x18000000 */
 137     [VE_SRAM] = 0x14000000,
 138     /* CS2: 0x18000000 .. 0x1c000000 */
 139     [VE_VIDEORAM] = 0x18000000,
 140     [VE_ETHERNET] = 0x1a000000,
 141     [VE_USB] = 0x1b000000,
 142     /* CS3: 0x1c000000 .. 0x20000000 */
 143     [VE_DAPROM] = 0x1c000000,
 144     [VE_SYSREGS] = 0x1c010000,
 145     [VE_SP810] = 0x1c020000,
 146     [VE_SERIALPCI] = 0x1c030000,
 147     [VE_PL041] = 0x1c040000,
 148     [VE_MMCI] = 0x1c050000,
 149     [VE_KMI0] = 0x1c060000,
 150     [VE_KMI1] = 0x1c070000,
 151     [VE_UART0] = 0x1c090000,
 152     [VE_UART1] = 0x1c0a0000,
 153     [VE_UART2] = 0x1c0b0000,
 154     [VE_UART3] = 0x1c0c0000,
 155     [VE_WDT] = 0x1c0f0000,
 156     [VE_TIMER01] = 0x1c110000,
 157     [VE_TIMER23] = 0x1c120000,
 158     [VE_VIRTIO] = 0x1c130000,
 159     [VE_SERIALDVI] = 0x1c160000,
 160     [VE_RTC] = 0x1c170000,
 161     [VE_COMPACTFLASH] = 0x1c1a0000,
 162     [VE_CLCD] = 0x1c1f0000,
 163 };
 164
 165 /* Structure defining the peculiarities of a specific daughterboard */
 166
 167 typedef struct VEDBoardInfo VEDBoardInfo;
 168
 169 struct VexpressMachineClass {
 170     MachineClass parent;
 171     VEDBoardInfo *daughterboard;
 172 };
 173
 174 struct VexpressMachineState {
 175     MachineState parent;
 176     MemoryRegion vram;
 177     MemoryRegion sram;
 178     MemoryRegion flashalias;
 179     MemoryRegion lowram;
 180     MemoryRegion a15sram;
 181     bool secure;
 182     bool virt;
 183 };
 184
 185 #define TYPE_VEXPRESS_MACHINE   "vexpress"
 186 #define TYPE_VEXPRESS_A9_MACHINE   MACHINE_TYPE_NAME("vexpress-a9")
 187 #define TYPE_VEXPRESS_A15_MACHINE   MACHINE_TYPE_NAME("vexpress-a15")
 188 OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE)
 189
 190 typedef void DBoardInitFn(VexpressMachineState *machine,
 191                           ram_addr_t ram_size,
 192                           const char *cpu_type,
 193                           qemu_irq *pic);
 194
 195 struct VEDBoardInfo {
 196     struct arm_boot_info bootinfo;
 197     const hwaddr *motherboard_map;
 198     hwaddr loader_start;
 199     const hwaddr gic_cpu_if_addr;
 200     uint32_t proc_id;
 201     uint32_t num_voltage_sensors;
 202     const uint32_t *voltages;
 203     uint32_t num_clocks;
 204     const uint32_t *clocks;
 205     DBoardInitFn *init;
 206 };
 207
 208 static void init_cpus(MachineState *ms, const char *cpu_type,
 209                       const char *privdev, hwaddr periphbase,
 210                       qemu_irq *pic, bool secure, bool virt)
 211 {
 212     DeviceState *dev;
 213     SysBusDevice *busdev;
 214     int n;
 215     unsigned int smp_cpus = ms->smp.cpus;
 216
 217     /* Create the actual CPUs */
 218     for (n = 0; n < smp_cpus; n++) {
 219         Object *cpuobj = object_new(cpu_type);
 220
 221         if (!secure) {
 222             object_property_set_bool(cpuobj, "has_el3", false, NULL);
 223         }
 224         if (!virt) {
 225             if (object_property_find(cpuobj, "has_el2")) {
 226                 object_property_set_bool(cpuobj, "has_el2", false, NULL);
 227             }
 228         }
 229
 230         if (object_property_find(cpuobj, "reset-cbar")) {
 231             object_property_set_int(cpuobj, "reset-cbar", periphbase,
 232                                     &error_abort);
 233         }
 234         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
 235     }
 236
 237     /* Create the private peripheral devices (including the GIC);
 238      * this must happen after the CPUs are created because a15mpcore_priv
 239      * wires itself up to the CPU's generic_timer gpio out lines.
 240      */
 241     dev = qdev_new(privdev);
 242     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 243     busdev = SYS_BUS_DEVICE(dev);
 244     sysbus_realize_and_unref(busdev, &error_fatal);
 245     sysbus_mmio_map(busdev, 0, periphbase);
 246
 247     /* Interrupts [42:0] are from the motherboard;
 248      * [47:43] are reserved; [63:48] are daughterboard
 249      * peripherals. Note that some documentation numbers
 250      * external interrupts starting from 32 (because there
 251      * are internal interrupts 0..31).
 252      */
 253     for (n = 0; n < 64; n++) {
 254         pic[n] = qdev_get_gpio_in(dev, n);
 255     }
 256
 257     /* Connect the CPUs to the GIC */
 258     for (n = 0; n < smp_cpus; n++) {
 259         DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
 260
 261         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 262         sysbus_connect_irq(busdev, n + smp_cpus,
 263                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 264         sysbus_connect_irq(busdev, n + 2 * smp_cpus,
 265                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
 266         sysbus_connect_irq(busdev, n + 3 * smp_cpus,
 267                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
 268     }
 269 }
 270
 271 static void a9_daughterboard_init(VexpressMachineState *vms,
 272                                   ram_addr_t ram_size,
 273                                   const char *cpu_type,
 274                                   qemu_irq *pic)
 275 {
 276     MachineState *machine = MACHINE(vms);
 277     MemoryRegion *sysmem = get_system_memory();
 278     ram_addr_t low_ram_size;
 279
 280     if (ram_size > 0x40000000) {
 281         /* 1GB is the maximum the address space permits */
 282         error_report("vexpress-a9: cannot model more than 1GB RAM");
 283         exit(1);
 284     }
 285
 286     low_ram_size = ram_size;
 287     if (low_ram_size > 0x4000000) {
 288         low_ram_size = 0x4000000;
 289     }
 290     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
 291      * address space should in theory be remappable to various
 292      * things including ROM or RAM; we always map the RAM there.
 293      */
 294     memory_region_init_alias(&vms->lowram, NULL, "vexpress.lowmem",
 295                              machine->ram, 0, low_ram_size);
 296     memory_region_add_subregion(sysmem, 0x0, &vms->lowram);
 297     memory_region_add_subregion(sysmem, 0x60000000, machine->ram);
 298
 299     /* 0x1e000000 A9MPCore (SCU) private memory region */
 300     init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,
 301               vms->secure, vms->virt);
 302
 303     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 304
 305     /* 0x10020000 PL111 CLCD (daughterboard) */
 306     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 307
 308     /* 0x10060000 AXI RAM */
 309     /* 0x100e0000 PL341 Dynamic Memory Controller */
 310     /* 0x100e1000 PL354 Static Memory Controller */
 311     /* 0x100e2000 System Configuration Controller */
 312
 313     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 314     /* 0x100e5000 SP805 Watchdog module */
 315     /* 0x100e6000 BP147 TrustZone Protection Controller */
 316     /* 0x100e9000 PL301 'Fast' AXI matrix */
 317     /* 0x100ea000 PL301 'Slow' AXI matrix */
 318     /* 0x100ec000 TrustZone Address Space Controller */
 319     /* 0x10200000 CoreSight debug APB */
 320     /* 0x1e00a000 PL310 L2 Cache Controller */
 321     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
 322 }
 323
 324 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
 325  * values are in microvolts.
 326  */
 327 static const uint32_t a9_voltages[] = {
 328     1000000, /* VD10 : 1.0V : SoC internal logic voltage */
 329     1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
 330     1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
 331     1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
 332     900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
 333     3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
 334 };
 335
 336 /* Reset values for daughterboard oscillators (in Hz) */
 337 static const uint32_t a9_clocks[] = {
 338     45000000, /* AMBA AXI ACLK: 45MHz */
 339     23750000, /* daughterboard CLCD clock: 23.75MHz */
 340     66670000, /* Test chip reference clock: 66.67MHz */
 341 };
 342
 343 static VEDBoardInfo a9_daughterboard = {
 344     .motherboard_map = motherboard_legacy_map,
 345     .loader_start = 0x60000000,
 346     .gic_cpu_if_addr = 0x1e000100,
 347     .proc_id = 0x0c000191,
 348     .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
 349     .voltages = a9_voltages,
 350     .num_clocks = ARRAY_SIZE(a9_clocks),
 351     .clocks = a9_clocks,
 352     .init = a9_daughterboard_init,
 353 };
 354
 355 static void a15_daughterboard_init(VexpressMachineState *vms,
 356                                    ram_addr_t ram_size,
 357                                    const char *cpu_type,
 358                                    qemu_irq *pic)
 359 {
 360     MachineState *machine = MACHINE(vms);
 361     MemoryRegion *sysmem = get_system_memory();
 362
 363     {
 364         /* We have to use a separate 64 bit variable here to avoid the gcc
 365          * "comparison is always false due to limited range of data type"
 366          * warning if we are on a host where ram_addr_t is 32 bits.
 367          */
 368         uint64_t rsz = ram_size;
 369         if (rsz > (30ULL * 1024 * 1024 * 1024)) {
 370             error_report("vexpress-a15: cannot model more than 30GB RAM");
 371             exit(1);
 372         }
 373     }
 374
 375     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
 376     memory_region_add_subregion(sysmem, 0x80000000, machine->ram);
 377
 378     /* 0x2c000000 A15MPCore private memory region (GIC) */
 379     init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV,
 380               0x2c000000, pic, vms->secure, vms->virt);
 381
 382     /* A15 daughterboard peripherals: */
 383
 384     /* 0x20000000: CoreSight interfaces: not modelled */
 385     /* 0x2a000000: PL301 AXI interconnect: not modelled */
 386     /* 0x2a420000: SCC: not modelled */
 387     /* 0x2a430000: system counter: not modelled */
 388     /* 0x2b000000: HDLCD controller: not modelled */
 389     /* 0x2b060000: SP805 watchdog: not modelled */
 390     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
 391     /* 0x2e000000: system SRAM */
 392     memory_region_init_ram(&vms->a15sram, NULL, "vexpress.a15sram", 0x10000,
 393                            &error_fatal);
 394     memory_region_add_subregion(sysmem, 0x2e000000, &vms->a15sram);
 395
 396     /* 0x7ffb0000: DMA330 DMA controller: not modelled */
 397     /* 0x7ffd0000: PL354 static memory controller: not modelled */
 398 }
 399
 400 static const uint32_t a15_voltages[] = {
 401     900000, /* Vcore: 0.9V : CPU core voltage */
 402 };
 403
 404 static const uint32_t a15_clocks[] = {
 405     60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
 406     0, /* OSCCLK1: reserved */
 407     0, /* OSCCLK2: reserved */
 408     0, /* OSCCLK3: reserved */
 409     40000000, /* OSCCLK4: 40MHz : external AXI master clock */
 410     23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
 411     50000000, /* OSCCLK6: 50MHz : static memory controller clock */
 412     60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
 413     40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
 414 };
 415
 416 static VEDBoardInfo a15_daughterboard = {
 417     .motherboard_map = motherboard_aseries_map,
 418     .loader_start = 0x80000000,
 419     .gic_cpu_if_addr = 0x2c002000,
 420     .proc_id = 0x14000237,
 421     .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
 422     .voltages = a15_voltages,
 423     .num_clocks = ARRAY_SIZE(a15_clocks),
 424     .clocks = a15_clocks,
 425     .init = a15_daughterboard_init,
 426 };
 427
 428 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
 429                                 hwaddr addr, hwaddr size, uint32_t intc,
 430                                 int irq)
 431 {
 432     /* Add a virtio_mmio node to the device tree blob:
 433      *   virtio_mmio@ADDRESS {
 434      *       compatible = "virtio,mmio";
 435      *       reg = <ADDRESS, SIZE>;
 436      *       interrupt-parent = <&intc>;
 437      *       interrupts = <0, irq, 1>;
 438      *   }
 439      * (Note that the format of the interrupts property is dependent on the
 440      * interrupt controller that interrupt-parent points to; these are for
 441      * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
 442      */
 443     int rc;
 444     char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
 445
 446     rc = qemu_fdt_add_subnode(fdt, nodename);
 447     rc |= qemu_fdt_setprop_string(fdt, nodename,
 448                                   "compatible", "virtio,mmio");
 449     rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
 450                                        acells, addr, scells, size);
 451     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
 452     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
 453     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
 454     g_free(nodename);
 455     if (rc) {
 456         return -1;
 457     }
 458     return 0;
 459 }
 460
 461 static uint32_t find_int_controller(void *fdt)
 462 {
 463     /* Find the FDT node corresponding to the interrupt controller
 464      * for virtio-mmio devices. We do this by scanning the fdt for
 465      * a node with the right compatibility, since we know there is
 466      * only one GIC on a vexpress board.
 467      * We return the phandle of the node, or 0 if none was found.
 468      */
 469     const char *compat = "arm,cortex-a9-gic";
 470     int offset;
 471
 472     offset = fdt_node_offset_by_compatible(fdt, -1, compat);
 473     if (offset >= 0) {
 474         return fdt_get_phandle(fdt, offset);
 475     }
 476     return 0;
 477 }
 478
 479 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
 480 {
 481     uint32_t acells, scells, intc;
 482     const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
 483
 484     acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
 485                                    NULL, &error_fatal);
 486     scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
 487                                    NULL, &error_fatal);
 488     intc = find_int_controller(fdt);
 489     if (!intc) {
 490         /* Not fatal, we just won't provide virtio. This will
 491          * happen with older device tree blobs.
 492          */
 493         warn_report("couldn't find interrupt controller in "
 494                     "dtb; will not include virtio-mmio devices in the dtb");
 495     } else {
 496         int i;
 497         const hwaddr *map = daughterboard->motherboard_map;
 498
 499         /* We iterate backwards here because adding nodes
 500          * to the dtb puts them in last-first.
 501          */
 502         for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
 503             add_virtio_mmio_node(fdt, acells, scells,
 504                                  map[VE_VIRTIO] + 0x200 * i,
 505                                  0x200, intc, 40 + i);
 506         }
 507     }
 508 }
 509
 510
 511 /* Open code a private version of pflash registration since we
 512  * need to set non-default device width for VExpress platform.
 513  */
 514 static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name,
 515                                              DriveInfo *di)
 516 {
 517     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
 518
 519     if (di) {
 520         qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di));
 521     }
 522
 523     qdev_prop_set_uint32(dev, "num-blocks",
 524                          VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
 525     qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
 526     qdev_prop_set_uint8(dev, "width", 4);
 527     qdev_prop_set_uint8(dev, "device-width", 2);
 528     qdev_prop_set_bit(dev, "big-endian", false);
 529     qdev_prop_set_uint16(dev, "id0", 0x89);
 530     qdev_prop_set_uint16(dev, "id1", 0x18);
 531     qdev_prop_set_uint16(dev, "id2", 0x00);
 532     qdev_prop_set_uint16(dev, "id3", 0x00);
 533     qdev_prop_set_string(dev, "name", name);
 534     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 535
 536     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 537     return PFLASH_CFI01(dev);
 538 }
 539
 540 static void vexpress_common_init(MachineState *machine)
 541 {
 542     VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
 543     VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
 544     VEDBoardInfo *daughterboard = vmc->daughterboard;
 545     DeviceState *dev, *sysctl, *pl041;
 546     qemu_irq pic[64];
 547     uint32_t sys_id;
 548     DriveInfo *dinfo;
 549     PFlashCFI01 *pflash0;
 550     I2CBus *i2c;
 551     ram_addr_t vram_size, sram_size;
 552     MemoryRegion *sysmem = get_system_memory();
 553     const hwaddr *map = daughterboard->motherboard_map;
 554     int i;
 555
 556     daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);
 557
 558     /*
 559      * If a bios file was provided, attempt to map it into memory
 560      */
 561     if (machine->firmware) {
 562         char *fn;
 563         int image_size;
 564
 565         if (drive_get(IF_PFLASH, 0, 0)) {
 566             error_report("The contents of the first flash device may be "
 567                          "specified with -bios or with -drive if=pflash... "
 568                          "but you cannot use both options at once");
 569             exit(1);
 570         }
 571         fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
 572         if (!fn) {
 573             error_report("Could not find ROM image '%s'", machine->firmware);
 574             exit(1);
 575         }
 576         image_size = load_image_targphys(fn, map[VE_NORFLASH0],
 577                                          VEXPRESS_FLASH_SIZE);
 578         g_free(fn);
 579         if (image_size < 0) {
 580             error_report("Could not load ROM image '%s'", machine->firmware);
 581             exit(1);
 582         }
 583     }
 584
 585     /* Motherboard peripherals: the wiring is the same but the
 586      * addresses vary between the legacy and A-Series memory maps.
 587      */
 588
 589     sys_id = 0x1190f500;
 590
 591     sysctl = qdev_new("realview_sysctl");
 592     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 593     qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
 594     qdev_prop_set_uint32(sysctl, "len-db-voltage",
 595                          daughterboard->num_voltage_sensors);
 596     for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
 597         char *propname = g_strdup_printf("db-voltage[%d]", i);
 598         qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
 599         g_free(propname);
 600     }
 601     qdev_prop_set_uint32(sysctl, "len-db-clock",
 602                          daughterboard->num_clocks);
 603     for (i = 0; i < daughterboard->num_clocks; i++) {
 604         char *propname = g_strdup_printf("db-clock[%d]", i);
 605         qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
 606         g_free(propname);
 607     }
 608     sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
 609     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
 610
 611     /* VE_SP810: not modelled */
 612     /* VE_SERIALPCI: not modelled */
 613
 614     pl041 = qdev_new("pl041");
 615     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 616     sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
 617     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
 618     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
 619
 620     dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
 621     /* Wire up MMC card detect and read-only signals */
 622     qdev_connect_gpio_out_named(dev, "card-read-only", 0,
 623                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 624     qdev_connect_gpio_out_named(dev, "card-inserted", 0,
 625                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 626     dinfo = drive_get(IF_SD, 0, 0);
 627     if (dinfo) {
 628         DeviceState *card;
 629
 630         card = qdev_new(TYPE_SD_CARD);
 631         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 632                                 &error_fatal);
 633         qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
 634                                &error_fatal);
 635     }
 636
 637     sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
 638     sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
 639
 640     pl011_create(map[VE_UART0], pic[5], serial_hd(0));
 641     pl011_create(map[VE_UART1], pic[6], serial_hd(1));
 642     pl011_create(map[VE_UART2], pic[7], serial_hd(2));
 643     pl011_create(map[VE_UART3], pic[8], serial_hd(3));
 644
 645     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
 646     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 647
 648     dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, map[VE_SERIALDVI], NULL);
 649     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 650     i2c_slave_create_simple(i2c, "sii9022", 0x39);
 651
 652     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 653
 654     /* VE_COMPACTFLASH: not modelled */
 655
 656     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 657
 658     dinfo = drive_get(IF_PFLASH, 0, 0);
 659     pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
 660                                        dinfo);
 661
 662     if (map[VE_NORFLASHALIAS] != -1) {
 663         /* Map flash 0 as an alias into low memory */
 664         MemoryRegion *flash0mem;
 665         flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
 666         memory_region_init_alias(&vms->flashalias, NULL, "vexpress.flashalias",
 667                                  flash0mem, 0, VEXPRESS_FLASH_SIZE);
 668         memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], &vms->flashalias);
 669     }
 670
 671     dinfo = drive_get(IF_PFLASH, 0, 1);
 672     ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo);
 673
 674     sram_size = 0x2000000;
 675     memory_region_init_ram(&vms->sram, NULL, "vexpress.sram", sram_size,
 676                            &error_fatal);
 677     memory_region_add_subregion(sysmem, map[VE_SRAM], &vms->sram);
 678
 679     vram_size = 0x800000;
 680     memory_region_init_ram(&vms->vram, NULL, "vexpress.vram", vram_size,
 681                            &error_fatal);
 682     memory_region_add_subregion(sysmem, map[VE_VIDEORAM], &vms->vram);
 683
 684     /* 0x4e000000 LAN9118 Ethernet */
 685     if (nd_table[0].used) {
 686         lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
 687     }
 688
 689     /* VE_USB: not modelled */
 690
 691     /* VE_DAPROM: not modelled */
 692
 693     /* Create mmio transports, so the user can create virtio backends
 694      * (which will be automatically plugged in to the transports). If
 695      * no backend is created the transport will just sit harmlessly idle.
 696      */
 697     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
 698         sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
 699                              pic[40 + i]);
 700     }
 701
 702     daughterboard->bootinfo.ram_size = machine->ram_size;
 703     daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
 704     daughterboard->bootinfo.loader_start = daughterboard->loader_start;
 705     daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
 706     daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
 707     daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
 708     daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
 709     /* When booting Linux we should be in secure state if the CPU has one. */
 710     daughterboard->bootinfo.secure_boot = vms->secure;
 711     arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo);
 712 }
 713
 714 static bool vexpress_get_secure(Object *obj, Error **errp)
 715 {
 716     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 717
 718     return vms->secure;
 719 }
 720
 721 static void vexpress_set_secure(Object *obj, bool value, Error **errp)
 722 {
 723     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 724
 725     vms->secure = value;
 726 }
 727
 728 static bool vexpress_get_virt(Object *obj, Error **errp)
 729 {
 730     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 731
 732     return vms->virt;
 733 }
 734
 735 static void vexpress_set_virt(Object *obj, bool value, Error **errp)
 736 {
 737     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 738
 739     vms->virt = value;
 740 }
 741
 742 static void vexpress_instance_init(Object *obj)
 743 {
 744     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 745
 746     /* EL3 is enabled by default on vexpress */
 747     vms->secure = true;
 748 }
 749
 750 static void vexpress_a15_instance_init(Object *obj)
 751 {
 752     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 753
 754     /*
 755      * For the vexpress-a15, EL2 is by default enabled if EL3 is,
 756      * but can also be specifically set to on or off.
 757      */
 758     vms->virt = true;
 759 }
 760
 761 static void vexpress_a9_instance_init(Object *obj)
 762 {
 763     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 764
 765     /* The A9 doesn't have the virt extensions */
 766     vms->virt = false;
 767 }
 768
 769 static void vexpress_class_init(ObjectClass *oc, void *data)
 770 {
 771     MachineClass *mc = MACHINE_CLASS(oc);
 772
 773     mc->desc = "ARM Versatile Express";
 774     mc->init = vexpress_common_init;
 775     mc->max_cpus = 4;
 776     mc->ignore_memory_transaction_failures = true;
 777     mc->default_ram_id = "vexpress.highmem";
 778
 779     object_class_property_add_bool(oc, "secure", vexpress_get_secure,
 780                                    vexpress_set_secure);
 781     object_class_property_set_description(oc, "secure",
 782                                           "Set on/off to enable/disable the ARM "
 783                                           "Security Extensions (TrustZone)");
 784 }
 785
 786 static void vexpress_a9_class_init(ObjectClass *oc, void *data)
 787 {
 788     MachineClass *mc = MACHINE_CLASS(oc);
 789     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 790
 791     mc->desc = "ARM Versatile Express for Cortex-A9";
 792     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 793
 794     vmc->daughterboard = &a9_daughterboard;
 795 }
 796
 797 static void vexpress_a15_class_init(ObjectClass *oc, void *data)
 798 {
 799     MachineClass *mc = MACHINE_CLASS(oc);
 800     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 801
 802     mc->desc = "ARM Versatile Express for Cortex-A15";
 803     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
 804
 805     vmc->daughterboard = &a15_daughterboard;
 806
 807     object_class_property_add_bool(oc, "virtualization", vexpress_get_virt,
 808                                    vexpress_set_virt);
 809     object_class_property_set_description(oc, "virtualization",
 810                                           "Set on/off to enable/disable the ARM "
 811                                           "Virtualization Extensions "
 812                                           "(defaults to same as 'secure')");
 813
 814 }
 815
 816 static const TypeInfo vexpress_info = {
 817     .name = TYPE_VEXPRESS_MACHINE,
 818     .parent = TYPE_MACHINE,
 819     .abstract = true,
 820     .instance_size = sizeof(VexpressMachineState),
 821     .instance_init = vexpress_instance_init,
 822     .class_size = sizeof(VexpressMachineClass),
 823     .class_init = vexpress_class_init,
 824 };
 825
 826 static const TypeInfo vexpress_a9_info = {
 827     .name = TYPE_VEXPRESS_A9_MACHINE,
 828     .parent = TYPE_VEXPRESS_MACHINE,
 829     .class_init = vexpress_a9_class_init,
 830     .instance_init = vexpress_a9_instance_init,
 831 };
 832
 833 static const TypeInfo vexpress_a15_info = {
 834     .name = TYPE_VEXPRESS_A15_MACHINE,
 835     .parent = TYPE_VEXPRESS_MACHINE,
 836     .class_init = vexpress_a15_class_init,
 837     .instance_init = vexpress_a15_instance_init,
 838 };
 839
 840 static void vexpress_machine_init(void)
 841 {
 842     type_register_static(&vexpress_info);
 843     type_register_static(&vexpress_a9_info);
 844     type_register_static(&vexpress_a15_info);
 845 }
 846
 847 type_init(vexpress_machine_init);