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vga: Separate LE and BE conversion functions
[qemu/kevin.git] / hw / display / vga.c
blob451c3543bc881fd85544112077370c3ac60b2055
1 /*
2 * QEMU VGA Emulator.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "vga.h"
26 #include "ui/console.h"
27 #include "hw/i386/pc.h"
28 #include "hw/pci/pci.h"
29 #include "vga_int.h"
30 #include "ui/pixel_ops.h"
31 #include "qemu/timer.h"
32 #include "hw/xen/xen.h"
33 #include "trace.h"
34
35 //#define DEBUG_VGA
36 //#define DEBUG_VGA_MEM
37 //#define DEBUG_VGA_REG
38
39 //#define DEBUG_BOCHS_VBE
40
41 /* 16 state changes per vertical frame @60 Hz */
42 #define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
43
44 /*
45 * Video Graphics Array (VGA)
46 *
47 * Chipset docs for original IBM VGA:
48 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
49 *
50 * FreeVGA site:
51 * http://www.osdever.net/FreeVGA/home.htm
52 *
53 * Standard VGA features and Bochs VBE extensions are implemented.
54 */
55
56 /* force some bits to zero */
57 const uint8_t sr_mask[8] = {
58 0x03,
59 0x3d,
60 0x0f,
61 0x3f,
62 0x0e,
63 0x00,
64 0x00,
65 0xff,
66 };
67
68 const uint8_t gr_mask[16] = {
69 0x0f, /* 0x00 */
70 0x0f, /* 0x01 */
71 0x0f, /* 0x02 */
72 0x1f, /* 0x03 */
73 0x03, /* 0x04 */
74 0x7b, /* 0x05 */
75 0x0f, /* 0x06 */
76 0x0f, /* 0x07 */
77 0xff, /* 0x08 */
78 0x00, /* 0x09 */
79 0x00, /* 0x0a */
80 0x00, /* 0x0b */
81 0x00, /* 0x0c */
82 0x00, /* 0x0d */
83 0x00, /* 0x0e */
84 0x00, /* 0x0f */
85 };
86
87 #define cbswap_32(__x) \
88 ((uint32_t)( \
89 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
90 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
91 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
92 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
93
94 #ifdef HOST_WORDS_BIGENDIAN
95 #define PAT(x) cbswap_32(x)
96 #else
97 #define PAT(x) (x)
98 #endif
99
100 #ifdef HOST_WORDS_BIGENDIAN
101 #define BIG 1
102 #else
103 #define BIG 0
104 #endif
105
106 #ifdef HOST_WORDS_BIGENDIAN
107 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
108 #else
109 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
110 #endif
111
112 static const uint32_t mask16[16] = {
113 PAT(0x00000000),
114 PAT(0x000000ff),
115 PAT(0x0000ff00),
116 PAT(0x0000ffff),
117 PAT(0x00ff0000),
118 PAT(0x00ff00ff),
119 PAT(0x00ffff00),
120 PAT(0x00ffffff),
121 PAT(0xff000000),
122 PAT(0xff0000ff),
123 PAT(0xff00ff00),
124 PAT(0xff00ffff),
125 PAT(0xffff0000),
126 PAT(0xffff00ff),
127 PAT(0xffffff00),
128 PAT(0xffffffff),
129 };
130
131 #undef PAT
132
133 #ifdef HOST_WORDS_BIGENDIAN
134 #define PAT(x) (x)
135 #else
136 #define PAT(x) cbswap_32(x)
137 #endif
138
139 static const uint32_t dmask16[16] = {
140 PAT(0x00000000),
141 PAT(0x000000ff),
142 PAT(0x0000ff00),
143 PAT(0x0000ffff),
144 PAT(0x00ff0000),
145 PAT(0x00ff00ff),
146 PAT(0x00ffff00),
147 PAT(0x00ffffff),
148 PAT(0xff000000),
149 PAT(0xff0000ff),
150 PAT(0xff00ff00),
151 PAT(0xff00ffff),
152 PAT(0xffff0000),
153 PAT(0xffff00ff),
154 PAT(0xffffff00),
155 PAT(0xffffffff),
156 };
157
158 static const uint32_t dmask4[4] = {
159 PAT(0x00000000),
160 PAT(0x0000ffff),
161 PAT(0xffff0000),
162 PAT(0xffffffff),
163 };
164
165 static uint32_t expand4[256];
166 static uint16_t expand2[256];
167 static uint8_t expand4to8[16];
168
169 static void vga_update_memory_access(VGACommonState *s)
170 {
171 hwaddr base, offset, size;
172
173 if (s->legacy_address_space == NULL) {
174 return;
175 }
176
177 if (s->has_chain4_alias) {
178 memory_region_del_subregion(s->legacy_address_space, &s->chain4_alias);
179 object_unparent(OBJECT(&s->chain4_alias));
180 s->has_chain4_alias = false;
181 s->plane_updated = 0xf;
182 }
183 if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) ==
184 VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
185 offset = 0;
186 switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
187 case 0:
188 base = 0xa0000;
189 size = 0x20000;
190 break;
191 case 1:
192 base = 0xa0000;
193 size = 0x10000;
194 offset = s->bank_offset;
195 break;
196 case 2:
197 base = 0xb0000;
198 size = 0x8000;
199 break;
200 case 3:
201 default:
202 base = 0xb8000;
203 size = 0x8000;
204 break;
205 }
206 base += isa_mem_base;
207 memory_region_init_alias(&s->chain4_alias, memory_region_owner(&s->vram),
208 "vga.chain4", &s->vram, offset, size);
209 memory_region_add_subregion_overlap(s->legacy_address_space, base,
210 &s->chain4_alias, 2);
211 s->has_chain4_alias = true;
212 }
213 }
214
215 static void vga_dumb_update_retrace_info(VGACommonState *s)
216 {
217 (void) s;
218 }
219
220 static void vga_precise_update_retrace_info(VGACommonState *s)
221 {
222 int htotal_chars;
223 int hretr_start_char;
224 int hretr_skew_chars;
225 int hretr_end_char;
226
227 int vtotal_lines;
228 int vretr_start_line;
229 int vretr_end_line;
230
231 int dots;
232 #if 0
233 int div2, sldiv2;
234 #endif
235 int clocking_mode;
236 int clock_sel;
237 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
238 int64_t chars_per_sec;
239 struct vga_precise_retrace *r = &s->retrace_info.precise;
240
241 htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
242 hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
243 hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
244 hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
245
246 vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
247 (((s->cr[VGA_CRTC_OVERFLOW] & 1) |
248 ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
249 vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
250 ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
251 ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
252 vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
253
254 clocking_mode = (s->sr[VGA_SEQ_CLOCK_MODE] >> 3) & 1;
255 clock_sel = (s->msr >> 2) & 3;
256 dots = (s->msr & 1) ? 8 : 9;
257
258 chars_per_sec = clk_hz[clock_sel] / dots;
259
260 htotal_chars <<= clocking_mode;
261
262 r->total_chars = vtotal_lines * htotal_chars;
263 if (r->freq) {
264 r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq);
265 } else {
266 r->ticks_per_char = get_ticks_per_sec() / chars_per_sec;
267 }
268
269 r->vstart = vretr_start_line;
270 r->vend = r->vstart + vretr_end_line + 1;
271
272 r->hstart = hretr_start_char + hretr_skew_chars;
273 r->hend = r->hstart + hretr_end_char + 1;
274 r->htotal = htotal_chars;
275
276 #if 0
277 div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
278 sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
279 printf (
280 "hz=%f\n"
281 "htotal = %d\n"
282 "hretr_start = %d\n"
283 "hretr_skew = %d\n"
284 "hretr_end = %d\n"
285 "vtotal = %d\n"
286 "vretr_start = %d\n"
287 "vretr_end = %d\n"
288 "div2 = %d sldiv2 = %d\n"
289 "clocking_mode = %d\n"
290 "clock_sel = %d %d\n"
291 "dots = %d\n"
292 "ticks/char = %" PRId64 "\n"
293 "\n",
294 (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),
295 htotal_chars,
296 hretr_start_char,
297 hretr_skew_chars,
298 hretr_end_char,
299 vtotal_lines,
300 vretr_start_line,
301 vretr_end_line,
302 div2, sldiv2,
303 clocking_mode,
304 clock_sel,
305 clk_hz[clock_sel],
306 dots,
307 r->ticks_per_char
308 );
309 #endif
310 }
311
312 static uint8_t vga_precise_retrace(VGACommonState *s)
313 {
314 struct vga_precise_retrace *r = &s->retrace_info.precise;
315 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
316
317 if (r->total_chars) {
318 int cur_line, cur_line_char, cur_char;
319 int64_t cur_tick;
320
321 cur_tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
322
323 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
324 cur_line = cur_char / r->htotal;
325
326 if (cur_line >= r->vstart && cur_line <= r->vend) {
327 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
328 } else {
329 cur_line_char = cur_char % r->htotal;
330 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
331 val |= ST01_DISP_ENABLE;
332 }
333 }
334
335 return val;
336 } else {
337 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
338 }
339 }
340
341 static uint8_t vga_dumb_retrace(VGACommonState *s)
342 {
343 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
344 }
345
346 int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
347 {
348 if (s->msr & VGA_MIS_COLOR) {
349 /* Color */
350 return (addr >= 0x3b0 && addr <= 0x3bf);
351 } else {
352 /* Monochrome */
353 return (addr >= 0x3d0 && addr <= 0x3df);
354 }
355 }
356
357 uint32_t vga_ioport_read(void *opaque, uint32_t addr)
358 {
359 VGACommonState *s = opaque;
360 int val, index;
361
362 if (vga_ioport_invalid(s, addr)) {
363 val = 0xff;
364 } else {
365 switch(addr) {
366 case VGA_ATT_W:
367 if (s->ar_flip_flop == 0) {
368 val = s->ar_index;
369 } else {
370 val = 0;
371 }
372 break;
373 case VGA_ATT_R:
374 index = s->ar_index & 0x1f;
375 if (index < VGA_ATT_C) {
376 val = s->ar[index];
377 } else {
378 val = 0;
379 }
380 break;
381 case VGA_MIS_W:
382 val = s->st00;
383 break;
384 case VGA_SEQ_I:
385 val = s->sr_index;
386 break;
387 case VGA_SEQ_D:
388 val = s->sr[s->sr_index];
389 #ifdef DEBUG_VGA_REG
390 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
391 #endif
392 break;
393 case VGA_PEL_IR:
394 val = s->dac_state;
395 break;
396 case VGA_PEL_IW:
397 val = s->dac_write_index;
398 break;
399 case VGA_PEL_D:
400 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
401 if (++s->dac_sub_index == 3) {
402 s->dac_sub_index = 0;
403 s->dac_read_index++;
404 }
405 break;
406 case VGA_FTC_R:
407 val = s->fcr;
408 break;
409 case VGA_MIS_R:
410 val = s->msr;
411 break;
412 case VGA_GFX_I:
413 val = s->gr_index;
414 break;
415 case VGA_GFX_D:
416 val = s->gr[s->gr_index];
417 #ifdef DEBUG_VGA_REG
418 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
419 #endif
420 break;
421 case VGA_CRT_IM:
422 case VGA_CRT_IC:
423 val = s->cr_index;
424 break;
425 case VGA_CRT_DM:
426 case VGA_CRT_DC:
427 val = s->cr[s->cr_index];
428 #ifdef DEBUG_VGA_REG
429 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
430 #endif
431 break;
432 case VGA_IS1_RM:
433 case VGA_IS1_RC:
434 /* just toggle to fool polling */
435 val = s->st01 = s->retrace(s);
436 s->ar_flip_flop = 0;
437 break;
438 default:
439 val = 0x00;
440 break;
441 }
442 }
443 #if defined(DEBUG_VGA)
444 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
445 #endif
446 return val;
447 }
448
449 void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
450 {
451 VGACommonState *s = opaque;
452 int index;
453
454 /* check port range access depending on color/monochrome mode */
455 if (vga_ioport_invalid(s, addr)) {
456 return;
457 }
458 #ifdef DEBUG_VGA
459 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
460 #endif
461
462 switch(addr) {
463 case VGA_ATT_W:
464 if (s->ar_flip_flop == 0) {
465 val &= 0x3f;
466 s->ar_index = val;
467 } else {
468 index = s->ar_index & 0x1f;
469 switch(index) {
470 case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
471 s->ar[index] = val & 0x3f;
472 break;
473 case VGA_ATC_MODE:
474 s->ar[index] = val & ~0x10;
475 break;
476 case VGA_ATC_OVERSCAN:
477 s->ar[index] = val;
478 break;
479 case VGA_ATC_PLANE_ENABLE:
480 s->ar[index] = val & ~0xc0;
481 break;
482 case VGA_ATC_PEL:
483 s->ar[index] = val & ~0xf0;
484 break;
485 case VGA_ATC_COLOR_PAGE:
486 s->ar[index] = val & ~0xf0;
487 break;
488 default:
489 break;
490 }
491 }
492 s->ar_flip_flop ^= 1;
493 break;
494 case VGA_MIS_W:
495 s->msr = val & ~0x10;
496 s->update_retrace_info(s);
497 break;
498 case VGA_SEQ_I:
499 s->sr_index = val & 7;
500 break;
501 case VGA_SEQ_D:
502 #ifdef DEBUG_VGA_REG
503 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
504 #endif
505 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
506 if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
507 s->update_retrace_info(s);
508 }
509 vga_update_memory_access(s);
510 break;
511 case VGA_PEL_IR:
512 s->dac_read_index = val;
513 s->dac_sub_index = 0;
514 s->dac_state = 3;
515 break;
516 case VGA_PEL_IW:
517 s->dac_write_index = val;
518 s->dac_sub_index = 0;
519 s->dac_state = 0;
520 break;
521 case VGA_PEL_D:
522 s->dac_cache[s->dac_sub_index] = val;
523 if (++s->dac_sub_index == 3) {
524 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
525 s->dac_sub_index = 0;
526 s->dac_write_index++;
527 }
528 break;
529 case VGA_GFX_I:
530 s->gr_index = val & 0x0f;
531 break;
532 case VGA_GFX_D:
533 #ifdef DEBUG_VGA_REG
534 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
535 #endif
536 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
537 vga_update_memory_access(s);
538 break;
539 case VGA_CRT_IM:
540 case VGA_CRT_IC:
541 s->cr_index = val;
542 break;
543 case VGA_CRT_DM:
544 case VGA_CRT_DC:
545 #ifdef DEBUG_VGA_REG
546 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
547 #endif
548 /* handle CR0-7 protection */
549 if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&
550 s->cr_index <= VGA_CRTC_OVERFLOW) {
551 /* can always write bit 4 of CR7 */
552 if (s->cr_index == VGA_CRTC_OVERFLOW) {
553 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |
554 (val & 0x10);
555 }
556 return;
557 }
558 s->cr[s->cr_index] = val;
559
560 switch(s->cr_index) {
561 case VGA_CRTC_H_TOTAL:
562 case VGA_CRTC_H_SYNC_START:
563 case VGA_CRTC_H_SYNC_END:
564 case VGA_CRTC_V_TOTAL:
565 case VGA_CRTC_OVERFLOW:
566 case VGA_CRTC_V_SYNC_END:
567 case VGA_CRTC_MODE:
568 s->update_retrace_info(s);
569 break;
570 }
571 break;
572 case VGA_IS1_RM:
573 case VGA_IS1_RC:
574 s->fcr = val & 0x10;
575 break;
576 }
577 }
578
579 /*
580 * Sanity check vbe register writes.
581 *
582 * As we don't have a way to signal errors to the guest in the bochs
583 * dispi interface we'll go adjust the registers to the closest valid
584 * value.
585 */
586 static void vbe_fixup_regs(VGACommonState *s)
587 {
588 uint16_t *r = s->vbe_regs;
589 uint32_t bits, linelength, maxy, offset;
590
591 if (!(r[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
592 /* vbe is turned off -- nothing to do */
593 return;
594 }
595
596 /* check depth */
597 switch (r[VBE_DISPI_INDEX_BPP]) {
598 case 4:
599 case 8:
600 case 16:
601 case 24:
602 case 32:
603 bits = r[VBE_DISPI_INDEX_BPP];
604 break;
605 case 15:
606 bits = 16;
607 break;
608 default:
609 bits = r[VBE_DISPI_INDEX_BPP] = 8;
610 break;
611 }
612
613 /* check width */
614 r[VBE_DISPI_INDEX_XRES] &= ~7u;
615 if (r[VBE_DISPI_INDEX_XRES] == 0) {
616 r[VBE_DISPI_INDEX_XRES] = 8;
617 }
618 if (r[VBE_DISPI_INDEX_XRES] > VBE_DISPI_MAX_XRES) {
619 r[VBE_DISPI_INDEX_XRES] = VBE_DISPI_MAX_XRES;
620 }
621 r[VBE_DISPI_INDEX_VIRT_WIDTH] &= ~7u;
622 if (r[VBE_DISPI_INDEX_VIRT_WIDTH] > VBE_DISPI_MAX_XRES) {
623 r[VBE_DISPI_INDEX_VIRT_WIDTH] = VBE_DISPI_MAX_XRES;
624 }
625 if (r[VBE_DISPI_INDEX_VIRT_WIDTH] < r[VBE_DISPI_INDEX_XRES]) {
626 r[VBE_DISPI_INDEX_VIRT_WIDTH] = r[VBE_DISPI_INDEX_XRES];
627 }
628
629 /* check height */
630 linelength = r[VBE_DISPI_INDEX_VIRT_WIDTH] * bits / 8;
631 maxy = s->vbe_size / linelength;
632 if (r[VBE_DISPI_INDEX_YRES] == 0) {
633 r[VBE_DISPI_INDEX_YRES] = 1;
634 }
635 if (r[VBE_DISPI_INDEX_YRES] > VBE_DISPI_MAX_YRES) {
636 r[VBE_DISPI_INDEX_YRES] = VBE_DISPI_MAX_YRES;
637 }
638 if (r[VBE_DISPI_INDEX_YRES] > maxy) {
639 r[VBE_DISPI_INDEX_YRES] = maxy;
640 }
641
642 /* check offset */
643 if (r[VBE_DISPI_INDEX_X_OFFSET] > VBE_DISPI_MAX_XRES) {
644 r[VBE_DISPI_INDEX_X_OFFSET] = VBE_DISPI_MAX_XRES;
645 }
646 if (r[VBE_DISPI_INDEX_Y_OFFSET] > VBE_DISPI_MAX_YRES) {
647 r[VBE_DISPI_INDEX_Y_OFFSET] = VBE_DISPI_MAX_YRES;
648 }
649 offset = r[VBE_DISPI_INDEX_X_OFFSET] * bits / 8;
650 offset += r[VBE_DISPI_INDEX_Y_OFFSET] * linelength;
651 if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) {
652 r[VBE_DISPI_INDEX_Y_OFFSET] = 0;
653 offset = r[VBE_DISPI_INDEX_X_OFFSET] * bits / 8;
654 if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) {
655 r[VBE_DISPI_INDEX_X_OFFSET] = 0;
656 offset = 0;
657 }
658 }
659
660 /* update vga state */
661 r[VBE_DISPI_INDEX_VIRT_HEIGHT] = maxy;
662 s->vbe_line_offset = linelength;
663 s->vbe_start_addr = offset / 4;
664 }
665
666 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
667 {
668 VGACommonState *s = opaque;
669 uint32_t val;
670 val = s->vbe_index;
671 return val;
672 }
673
674 uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
675 {
676 VGACommonState *s = opaque;
677 uint32_t val;
678
679 if (s->vbe_index < VBE_DISPI_INDEX_NB) {
680 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
681 switch(s->vbe_index) {
682 /* XXX: do not hardcode ? */
683 case VBE_DISPI_INDEX_XRES:
684 val = VBE_DISPI_MAX_XRES;
685 break;
686 case VBE_DISPI_INDEX_YRES:
687 val = VBE_DISPI_MAX_YRES;
688 break;
689 case VBE_DISPI_INDEX_BPP:
690 val = VBE_DISPI_MAX_BPP;
691 break;
692 default:
693 val = s->vbe_regs[s->vbe_index];
694 break;
695 }
696 } else {
697 val = s->vbe_regs[s->vbe_index];
698 }
699 } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
700 val = s->vbe_size / (64 * 1024);
701 } else {
702 val = 0;
703 }
704 #ifdef DEBUG_BOCHS_VBE
705 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
706 #endif
707 return val;
708 }
709
710 void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
711 {
712 VGACommonState *s = opaque;
713 s->vbe_index = val;
714 }
715
716 void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
717 {
718 VGACommonState *s = opaque;
719
720 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
721 #ifdef DEBUG_BOCHS_VBE
722 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
723 #endif
724 switch(s->vbe_index) {
725 case VBE_DISPI_INDEX_ID:
726 if (val == VBE_DISPI_ID0 ||
727 val == VBE_DISPI_ID1 ||
728 val == VBE_DISPI_ID2 ||
729 val == VBE_DISPI_ID3 ||
730 val == VBE_DISPI_ID4) {
731 s->vbe_regs[s->vbe_index] = val;
732 }
733 break;
734 case VBE_DISPI_INDEX_XRES:
735 case VBE_DISPI_INDEX_YRES:
736 case VBE_DISPI_INDEX_BPP:
737 case VBE_DISPI_INDEX_VIRT_WIDTH:
738 case VBE_DISPI_INDEX_X_OFFSET:
739 case VBE_DISPI_INDEX_Y_OFFSET:
740 s->vbe_regs[s->vbe_index] = val;
741 vbe_fixup_regs(s);
742 break;
743 case VBE_DISPI_INDEX_BANK:
744 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
745 val &= (s->vbe_bank_mask >> 2);
746 } else {
747 val &= s->vbe_bank_mask;
748 }
749 s->vbe_regs[s->vbe_index] = val;
750 s->bank_offset = (val << 16);
751 vga_update_memory_access(s);
752 break;
753 case VBE_DISPI_INDEX_ENABLE:
754 if ((val & VBE_DISPI_ENABLED) &&
755 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
756 int h, shift_control;
757
758 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = 0;
759 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
760 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
761 s->vbe_regs[VBE_DISPI_INDEX_ENABLE] |= VBE_DISPI_ENABLED;
762 vbe_fixup_regs(s);
763
764 /* clear the screen (should be done in BIOS) */
765 if (!(val & VBE_DISPI_NOCLEARMEM)) {
766 memset(s->vram_ptr, 0,
767 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
768 }
769
770 /* we initialize the VGA graphic mode (should be done
771 in BIOS) */
772 /* graphic mode + memory map 1 */
773 s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
774 VGA_GR06_GRAPHICS_MODE;
775 s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
776 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
777 /* width */
778 s->cr[VGA_CRTC_H_DISP] =
779 (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
780 /* height (only meaningful if < 1024) */
781 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
782 s->cr[VGA_CRTC_V_DISP_END] = h;
783 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
784 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
785 /* line compare to 1023 */
786 s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
787 s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
788 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
789
790 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
791 shift_control = 0;
792 s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
793 } else {
794 shift_control = 2;
795 /* set chain 4 mode */
796 s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
797 /* activate all planes */
798 s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
799 }
800 s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
801 (shift_control << 5);
802 s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
803 } else {
804 /* XXX: the bios should do that */
805 s->bank_offset = 0;
806 }
807 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
808 s->vbe_regs[s->vbe_index] = val;
809 vga_update_memory_access(s);
810 break;
811 default:
812 break;
813 }
814 }
815 }
816
817 /* called for accesses between 0xa0000 and 0xc0000 */
818 uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
819 {
820 int memory_map_mode, plane;
821 uint32_t ret;
822
823 /* convert to VGA memory offset */
824 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
825 addr &= 0x1ffff;
826 switch(memory_map_mode) {
827 case 0:
828 break;
829 case 1:
830 if (addr >= 0x10000)
831 return 0xff;
832 addr += s->bank_offset;
833 break;
834 case 2:
835 addr -= 0x10000;
836 if (addr >= 0x8000)
837 return 0xff;
838 break;
839 default:
840 case 3:
841 addr -= 0x18000;
842 if (addr >= 0x8000)
843 return 0xff;
844 break;
845 }
846
847 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
848 /* chain 4 mode : simplest access */
849 ret = s->vram_ptr[addr];
850 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
851 /* odd/even mode (aka text mode mapping) */
852 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
853 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
854 } else {
855 /* standard VGA latched access */
856 s->latch = ((uint32_t *)s->vram_ptr)[addr];
857
858 if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
859 /* read mode 0 */
860 plane = s->gr[VGA_GFX_PLANE_READ];
861 ret = GET_PLANE(s->latch, plane);
862 } else {
863 /* read mode 1 */
864 ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
865 mask16[s->gr[VGA_GFX_COMPARE_MASK]];
866 ret |= ret >> 16;
867 ret |= ret >> 8;
868 ret = (~ret) & 0xff;
869 }
870 }
871 return ret;
872 }
873
874 /* called for accesses between 0xa0000 and 0xc0000 */
875 void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
876 {
877 int memory_map_mode, plane, write_mode, b, func_select, mask;
878 uint32_t write_mask, bit_mask, set_mask;
879
880 #ifdef DEBUG_VGA_MEM
881 printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
882 #endif
883 /* convert to VGA memory offset */
884 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
885 addr &= 0x1ffff;
886 switch(memory_map_mode) {
887 case 0:
888 break;
889 case 1:
890 if (addr >= 0x10000)
891 return;
892 addr += s->bank_offset;
893 break;
894 case 2:
895 addr -= 0x10000;
896 if (addr >= 0x8000)
897 return;
898 break;
899 default:
900 case 3:
901 addr -= 0x18000;
902 if (addr >= 0x8000)
903 return;
904 break;
905 }
906
907 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
908 /* chain 4 mode : simplest access */
909 plane = addr & 3;
910 mask = (1 << plane);
911 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
912 s->vram_ptr[addr] = val;
913 #ifdef DEBUG_VGA_MEM
914 printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
915 #endif
916 s->plane_updated |= mask; /* only used to detect font change */
917 memory_region_set_dirty(&s->vram, addr, 1);
918 }
919 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
920 /* odd/even mode (aka text mode mapping) */
921 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
922 mask = (1 << plane);
923 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
924 addr = ((addr & ~1) << 1) | plane;
925 s->vram_ptr[addr] = val;
926 #ifdef DEBUG_VGA_MEM
927 printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
928 #endif
929 s->plane_updated |= mask; /* only used to detect font change */
930 memory_region_set_dirty(&s->vram, addr, 1);
931 }
932 } else {
933 /* standard VGA latched access */
934 write_mode = s->gr[VGA_GFX_MODE] & 3;
935 switch(write_mode) {
936 default:
937 case 0:
938 /* rotate */
939 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
940 val = ((val >> b) | (val << (8 - b))) & 0xff;
941 val |= val << 8;
942 val |= val << 16;
943
944 /* apply set/reset mask */
945 set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
946 val = (val & ~set_mask) |
947 (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
948 bit_mask = s->gr[VGA_GFX_BIT_MASK];
949 break;
950 case 1:
951 val = s->latch;
952 goto do_write;
953 case 2:
954 val = mask16[val & 0x0f];
955 bit_mask = s->gr[VGA_GFX_BIT_MASK];
956 break;
957 case 3:
958 /* rotate */
959 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
960 val = (val >> b) | (val << (8 - b));
961
962 bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
963 val = mask16[s->gr[VGA_GFX_SR_VALUE]];
964 break;
965 }
966
967 /* apply logical operation */
968 func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
969 switch(func_select) {
970 case 0:
971 default:
972 /* nothing to do */
973 break;
974 case 1:
975 /* and */
976 val &= s->latch;
977 break;
978 case 2:
979 /* or */
980 val |= s->latch;
981 break;
982 case 3:
983 /* xor */
984 val ^= s->latch;
985 break;
986 }
987
988 /* apply bit mask */
989 bit_mask |= bit_mask << 8;
990 bit_mask |= bit_mask << 16;
991 val = (val & bit_mask) | (s->latch & ~bit_mask);
992
993 do_write:
994 /* mask data according to sr[2] */
995 mask = s->sr[VGA_SEQ_PLANE_WRITE];
996 s->plane_updated |= mask; /* only used to detect font change */
997 write_mask = mask16[mask];
998 ((uint32_t *)s->vram_ptr)[addr] =
999 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
1000 (val & write_mask);
1001 #ifdef DEBUG_VGA_MEM
1002 printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
1003 addr * 4, write_mask, val);
1004 #endif
1005 memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
1006 }
1007 }
1008
1009 typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
1010 const uint8_t *s, int width);
1011
1012 #include "vga_template.h"
1013
1014 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1015 {
1016 unsigned int col;
1017 col = rgb_to_pixel32(r, g, b);
1018 return col;
1019 }
1020
1021 /* return true if the palette was modified */
1022 static int update_palette16(VGACommonState *s)
1023 {
1024 int full_update, i;
1025 uint32_t v, col, *palette;
1026
1027 full_update = 0;
1028 palette = s->last_palette;
1029 for(i = 0; i < 16; i++) {
1030 v = s->ar[i];
1031 if (s->ar[VGA_ATC_MODE] & 0x80) {
1032 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
1033 } else {
1034 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
1035 }
1036 v = v * 3;
1037 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1038 c6_to_8(s->palette[v + 1]),
1039 c6_to_8(s->palette[v + 2]));
1040 if (col != palette[i]) {
1041 full_update = 1;
1042 palette[i] = col;
1043 }
1044 }
1045 return full_update;
1046 }
1047
1048 /* return true if the palette was modified */
1049 static int update_palette256(VGACommonState *s)
1050 {
1051 int full_update, i;
1052 uint32_t v, col, *palette;
1053
1054 full_update = 0;
1055 palette = s->last_palette;
1056 v = 0;
1057 for(i = 0; i < 256; i++) {
1058 if (s->dac_8bit) {
1059 col = s->rgb_to_pixel(s->palette[v],
1060 s->palette[v + 1],
1061 s->palette[v + 2]);
1062 } else {
1063 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1064 c6_to_8(s->palette[v + 1]),
1065 c6_to_8(s->palette[v + 2]));
1066 }
1067 if (col != palette[i]) {
1068 full_update = 1;
1069 palette[i] = col;
1070 }
1071 v += 3;
1072 }
1073 return full_update;
1074 }
1075
1076 static void vga_get_offsets(VGACommonState *s,
1077 uint32_t *pline_offset,
1078 uint32_t *pstart_addr,
1079 uint32_t *pline_compare)
1080 {
1081 uint32_t start_addr, line_offset, line_compare;
1082
1083 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1084 line_offset = s->vbe_line_offset;
1085 start_addr = s->vbe_start_addr;
1086 line_compare = 65535;
1087 } else {
1088 /* compute line_offset in bytes */
1089 line_offset = s->cr[VGA_CRTC_OFFSET];
1090 line_offset <<= 3;
1091
1092 /* starting address */
1093 start_addr = s->cr[VGA_CRTC_START_LO] |
1094 (s->cr[VGA_CRTC_START_HI] << 8);
1095
1096 /* line compare */
1097 line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
1098 ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
1099 ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
1100 }
1101 *pline_offset = line_offset;
1102 *pstart_addr = start_addr;
1103 *pline_compare = line_compare;
1104 }
1105
1106 /* update start_addr and line_offset. Return TRUE if modified */
1107 static int update_basic_params(VGACommonState *s)
1108 {
1109 int full_update;
1110 uint32_t start_addr, line_offset, line_compare;
1111
1112 full_update = 0;
1113
1114 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1115
1116 if (line_offset != s->line_offset ||
1117 start_addr != s->start_addr ||
1118 line_compare != s->line_compare) {
1119 s->line_offset = line_offset;
1120 s->start_addr = start_addr;
1121 s->line_compare = line_compare;
1122 full_update = 1;
1123 }
1124 return full_update;
1125 }
1126
1127
1128 static const uint8_t cursor_glyph[32 * 4] = {
1129 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1130 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1131 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1132 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1133 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1134 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1135 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1136 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1137 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1138 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1139 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1140 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1141 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1142 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1143 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1144 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1145 };
1146
1147 static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
1148 int *pcwidth, int *pcheight)
1149 {
1150 int width, cwidth, height, cheight;
1151
1152 /* total width & height */
1153 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
1154 cwidth = 8;
1155 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
1156 cwidth = 9;
1157 }
1158 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
1159 cwidth = 16; /* NOTE: no 18 pixel wide */
1160 }
1161 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1162 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
1163 /* ugly hack for CGA 160x100x16 - explain me the logic */
1164 height = 100;
1165 } else {
1166 height = s->cr[VGA_CRTC_V_DISP_END] |
1167 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1168 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1169 height = (height + 1) / cheight;
1170 }
1171
1172 *pwidth = width;
1173 *pheight = height;
1174 *pcwidth = cwidth;
1175 *pcheight = cheight;
1176 }
1177
1178 /*
1179 * Text mode update
1180 * Missing:
1181 * - double scan
1182 * - double width
1183 * - underline
1184 * - flashing
1185 */
1186 static void vga_draw_text(VGACommonState *s, int full_update)
1187 {
1188 DisplaySurface *surface = qemu_console_surface(s->con);
1189 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1190 int cx_min, cx_max, linesize, x_incr, line, line1;
1191 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1192 uint8_t *d1, *d, *src, *dest, *cursor_ptr;
1193 const uint8_t *font_ptr, *font_base[2];
1194 int dup9, line_offset;
1195 uint32_t *palette;
1196 uint32_t *ch_attr_ptr;
1197 int64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1198
1199 /* compute font data address (in plane 2) */
1200 v = s->sr[VGA_SEQ_CHARACTER_MAP];
1201 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1202 if (offset != s->font_offsets[0]) {
1203 s->font_offsets[0] = offset;
1204 full_update = 1;
1205 }
1206 font_base[0] = s->vram_ptr + offset;
1207
1208 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1209 font_base[1] = s->vram_ptr + offset;
1210 if (offset != s->font_offsets[1]) {
1211 s->font_offsets[1] = offset;
1212 full_update = 1;
1213 }
1214 if (s->plane_updated & (1 << 2) || s->has_chain4_alias) {
1215 /* if the plane 2 was modified since the last display, it
1216 indicates the font may have been modified */
1217 s->plane_updated = 0;
1218 full_update = 1;
1219 }
1220 full_update |= update_basic_params(s);
1221
1222 line_offset = s->line_offset;
1223
1224 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1225 if ((height * width) <= 1) {
1226 /* better than nothing: exit if transient size is too small */
1227 return;
1228 }
1229 if ((height * width) > CH_ATTR_SIZE) {
1230 /* better than nothing: exit if transient size is too big */
1231 return;
1232 }
1233
1234 if (width != s->last_width || height != s->last_height ||
1235 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1236 s->last_scr_width = width * cw;
1237 s->last_scr_height = height * cheight;
1238 qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
1239 surface = qemu_console_surface(s->con);
1240 dpy_text_resize(s->con, width, height);
1241 s->last_depth = 0;
1242 s->last_width = width;
1243 s->last_height = height;
1244 s->last_ch = cheight;
1245 s->last_cw = cw;
1246 full_update = 1;
1247 }
1248 s->rgb_to_pixel = rgb_to_pixel32_dup;
1249 full_update |= update_palette16(s);
1250 palette = s->last_palette;
1251 x_incr = cw * surface_bytes_per_pixel(surface);
1252
1253 if (full_update) {
1254 s->full_update_text = 1;
1255 }
1256 if (s->full_update_gfx) {
1257 s->full_update_gfx = 0;
1258 full_update |= 1;
1259 }
1260
1261 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1262 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
1263 if (cursor_offset != s->cursor_offset ||
1264 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1265 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
1266 /* if the cursor position changed, we update the old and new
1267 chars */
1268 if (s->cursor_offset < CH_ATTR_SIZE)
1269 s->last_ch_attr[s->cursor_offset] = -1;
1270 if (cursor_offset < CH_ATTR_SIZE)
1271 s->last_ch_attr[cursor_offset] = -1;
1272 s->cursor_offset = cursor_offset;
1273 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1274 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
1275 }
1276 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1277 if (now >= s->cursor_blink_time) {
1278 s->cursor_blink_time = now + VGA_TEXT_CURSOR_PERIOD_MS / 2;
1279 s->cursor_visible_phase = !s->cursor_visible_phase;
1280 }
1281
1282 dest = surface_data(surface);
1283 linesize = surface_stride(surface);
1284 ch_attr_ptr = s->last_ch_attr;
1285 line = 0;
1286 offset = s->start_addr * 4;
1287 for(cy = 0; cy < height; cy++) {
1288 d1 = dest;
1289 src = s->vram_ptr + offset;
1290 cx_min = width;
1291 cx_max = -1;
1292 for(cx = 0; cx < width; cx++) {
1293 ch_attr = *(uint16_t *)src;
1294 if (full_update || ch_attr != *ch_attr_ptr || src == cursor_ptr) {
1295 if (cx < cx_min)
1296 cx_min = cx;
1297 if (cx > cx_max)
1298 cx_max = cx;
1299 *ch_attr_ptr = ch_attr;
1300 #ifdef HOST_WORDS_BIGENDIAN
1301 ch = ch_attr >> 8;
1302 cattr = ch_attr & 0xff;
1303 #else
1304 ch = ch_attr & 0xff;
1305 cattr = ch_attr >> 8;
1306 #endif
1307 font_ptr = font_base[(cattr >> 3) & 1];
1308 font_ptr += 32 * 4 * ch;
1309 bgcol = palette[cattr >> 4];
1310 fgcol = palette[cattr & 0x0f];
1311 if (cw == 16) {
1312 vga_draw_glyph16(d1, linesize,
1313 font_ptr, cheight, fgcol, bgcol);
1314 } else if (cw != 9) {
1315 vga_draw_glyph8(d1, linesize,
1316 font_ptr, cheight, fgcol, bgcol);
1317 } else {
1318 dup9 = 0;
1319 if (ch >= 0xb0 && ch <= 0xdf &&
1320 (s->ar[VGA_ATC_MODE] & 0x04)) {
1321 dup9 = 1;
1322 }
1323 vga_draw_glyph9(d1, linesize,
1324 font_ptr, cheight, fgcol, bgcol, dup9);
1325 }
1326 if (src == cursor_ptr &&
1327 !(s->cr[VGA_CRTC_CURSOR_START] & 0x20) &&
1328 s->cursor_visible_phase) {
1329 int line_start, line_last, h;
1330 /* draw the cursor */
1331 line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
1332 line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
1333 /* XXX: check that */
1334 if (line_last > cheight - 1)
1335 line_last = cheight - 1;
1336 if (line_last >= line_start && line_start < cheight) {
1337 h = line_last - line_start + 1;
1338 d = d1 + linesize * line_start;
1339 if (cw == 16) {
1340 vga_draw_glyph16(d, linesize,
1341 cursor_glyph, h, fgcol, bgcol);
1342 } else if (cw != 9) {
1343 vga_draw_glyph8(d, linesize,
1344 cursor_glyph, h, fgcol, bgcol);
1345 } else {
1346 vga_draw_glyph9(d, linesize,
1347 cursor_glyph, h, fgcol, bgcol, 1);
1348 }
1349 }
1350 }
1351 }
1352 d1 += x_incr;
1353 src += 4;
1354 ch_attr_ptr++;
1355 }
1356 if (cx_max != -1) {
1357 dpy_gfx_update(s->con, cx_min * cw, cy * cheight,
1358 (cx_max - cx_min + 1) * cw, cheight);
1359 }
1360 dest += linesize * cheight;
1361 line1 = line + cheight;
1362 offset += line_offset;
1363 if (line < s->line_compare && line1 >= s->line_compare) {
1364 offset = 0;
1365 }
1366 line = line1;
1367 }
1368 }
1369
1370 enum {
1371 VGA_DRAW_LINE2,
1372 VGA_DRAW_LINE2D2,
1373 VGA_DRAW_LINE4,
1374 VGA_DRAW_LINE4D2,
1375 VGA_DRAW_LINE8D2,
1376 VGA_DRAW_LINE8,
1377 VGA_DRAW_LINE15_LE,
1378 VGA_DRAW_LINE16_LE,
1379 VGA_DRAW_LINE24_LE,
1380 VGA_DRAW_LINE32_LE,
1381 VGA_DRAW_LINE15_BE,
1382 VGA_DRAW_LINE16_BE,
1383 VGA_DRAW_LINE24_BE,
1384 VGA_DRAW_LINE32_BE,
1385 VGA_DRAW_LINE_NB,
1386 };
1387
1388 static vga_draw_line_func * const vga_draw_line_table[VGA_DRAW_LINE_NB] = {
1389 vga_draw_line2,
1390 vga_draw_line2d2,
1391 vga_draw_line4,
1392 vga_draw_line4d2,
1393 vga_draw_line8d2,
1394 vga_draw_line8,
1395 vga_draw_line15_le,
1396 vga_draw_line16_le,
1397 vga_draw_line24_le,
1398 vga_draw_line32_le,
1399 vga_draw_line15_be,
1400 vga_draw_line16_be,
1401 vga_draw_line24_be,
1402 vga_draw_line32_be,
1403 };
1404
1405 static int vga_get_bpp(VGACommonState *s)
1406 {
1407 int ret;
1408
1409 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1410 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1411 } else {
1412 ret = 0;
1413 }
1414 return ret;
1415 }
1416
1417 static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1418 {
1419 int width, height;
1420
1421 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1422 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1423 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1424 } else {
1425 width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
1426 height = s->cr[VGA_CRTC_V_DISP_END] |
1427 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1428 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1429 height = (height + 1);
1430 }
1431 *pwidth = width;
1432 *pheight = height;
1433 }
1434
1435 void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
1436 {
1437 int y;
1438 if (y1 >= VGA_MAX_HEIGHT)
1439 return;
1440 if (y2 >= VGA_MAX_HEIGHT)
1441 y2 = VGA_MAX_HEIGHT;
1442 for(y = y1; y < y2; y++) {
1443 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1444 }
1445 }
1446
1447 void vga_sync_dirty_bitmap(VGACommonState *s)
1448 {
1449 memory_region_sync_dirty_bitmap(&s->vram);
1450 }
1451
1452 void vga_dirty_log_start(VGACommonState *s)
1453 {
1454 memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
1455 }
1456
1457 void vga_dirty_log_stop(VGACommonState *s)
1458 {
1459 memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
1460 }
1461
1462 /*
1463 * graphic modes
1464 */
1465 static void vga_draw_graphic(VGACommonState *s, int full_update)
1466 {
1467 DisplaySurface *surface = qemu_console_surface(s->con);
1468 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1469 int width, height, shift_control, line_offset, bwidth, bits;
1470 ram_addr_t page0, page1, page_min, page_max;
1471 int disp_width, multi_scan, multi_run;
1472 uint8_t *d;
1473 uint32_t v, addr1, addr;
1474 vga_draw_line_func *vga_draw_line;
1475 #if defined(TARGET_WORDS_BIGENDIAN)
1476 static const bool big_endian_fb = true;
1477 #else
1478 static const bool big_endian_fb = false;
1479 #endif
1480 #if defined(HOST_WORDS_BIGENDIAN)
1481 static const bool byteswap = !big_endian_fb;
1482 #else
1483 static const bool byteswap = big_endian_fb;
1484 #endif
1485
1486 full_update |= update_basic_params(s);
1487
1488 if (!full_update)
1489 vga_sync_dirty_bitmap(s);
1490
1491 s->get_resolution(s, &width, &height);
1492 disp_width = width;
1493
1494 shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
1495 double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
1496 if (shift_control != 1) {
1497 multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
1498 - 1;
1499 } else {
1500 /* in CGA modes, multi_scan is ignored */
1501 /* XXX: is it correct ? */
1502 multi_scan = double_scan;
1503 }
1504 multi_run = multi_scan;
1505 if (shift_control != s->shift_control ||
1506 double_scan != s->double_scan) {
1507 full_update = 1;
1508 s->shift_control = shift_control;
1509 s->double_scan = double_scan;
1510 }
1511
1512 if (shift_control == 0) {
1513 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1514 disp_width <<= 1;
1515 }
1516 } else if (shift_control == 1) {
1517 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1518 disp_width <<= 1;
1519 }
1520 }
1521
1522 depth = s->get_bpp(s);
1523 if (s->line_offset != s->last_line_offset ||
1524 disp_width != s->last_width ||
1525 height != s->last_height ||
1526 s->last_depth != depth) {
1527 if (depth == 32 || (depth == 16 && !byteswap)) {
1528 pixman_format_code_t format =
1529 qemu_default_pixman_format(depth, !byteswap);
1530 surface = qemu_create_displaysurface_from(disp_width,
1531 height, format, s->line_offset,
1532 s->vram_ptr + (s->start_addr * 4));
1533 dpy_gfx_replace_surface(s->con, surface);
1534 } else {
1535 qemu_console_resize(s->con, disp_width, height);
1536 surface = qemu_console_surface(s->con);
1537 }
1538 s->last_scr_width = disp_width;
1539 s->last_scr_height = height;
1540 s->last_width = disp_width;
1541 s->last_height = height;
1542 s->last_line_offset = s->line_offset;
1543 s->last_depth = depth;
1544 full_update = 1;
1545 } else if (is_buffer_shared(surface) &&
1546 (full_update || surface_data(surface) != s->vram_ptr
1547 + (s->start_addr * 4))) {
1548 pixman_format_code_t format =
1549 qemu_default_pixman_format(depth, !byteswap);
1550 surface = qemu_create_displaysurface_from(disp_width,
1551 height, format, s->line_offset,
1552 s->vram_ptr + (s->start_addr * 4));
1553 dpy_gfx_replace_surface(s->con, surface);
1554 }
1555
1556 s->rgb_to_pixel = rgb_to_pixel32_dup;
1557
1558 if (shift_control == 0) {
1559 full_update |= update_palette16(s);
1560 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1561 v = VGA_DRAW_LINE4D2;
1562 } else {
1563 v = VGA_DRAW_LINE4;
1564 }
1565 bits = 4;
1566 } else if (shift_control == 1) {
1567 full_update |= update_palette16(s);
1568 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1569 v = VGA_DRAW_LINE2D2;
1570 } else {
1571 v = VGA_DRAW_LINE2;
1572 }
1573 bits = 4;
1574 } else {
1575 switch(s->get_bpp(s)) {
1576 default:
1577 case 0:
1578 full_update |= update_palette256(s);
1579 v = VGA_DRAW_LINE8D2;
1580 bits = 4;
1581 break;
1582 case 8:
1583 full_update |= update_palette256(s);
1584 v = VGA_DRAW_LINE8;
1585 bits = 8;
1586 break;
1587 case 15:
1588 v = big_endian_fb ? VGA_DRAW_LINE15_BE : VGA_DRAW_LINE15_LE;
1589 bits = 16;
1590 break;
1591 case 16:
1592 v = big_endian_fb ? VGA_DRAW_LINE16_BE : VGA_DRAW_LINE16_LE;
1593 bits = 16;
1594 break;
1595 case 24:
1596 v = big_endian_fb ? VGA_DRAW_LINE24_BE : VGA_DRAW_LINE24_LE;
1597 bits = 24;
1598 break;
1599 case 32:
1600 v = big_endian_fb ? VGA_DRAW_LINE32_BE : VGA_DRAW_LINE32_LE;
1601 bits = 32;
1602 break;
1603 }
1604 }
1605 vga_draw_line = vga_draw_line_table[v];
1606
1607 if (!is_buffer_shared(surface) && s->cursor_invalidate) {
1608 s->cursor_invalidate(s);
1609 }
1610
1611 line_offset = s->line_offset;
1612 #if 0
1613 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1614 width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
1615 s->line_compare, s->sr[VGA_SEQ_CLOCK_MODE]);
1616 #endif
1617 addr1 = (s->start_addr * 4);
1618 bwidth = (width * bits + 7) / 8;
1619 y_start = -1;
1620 page_min = -1;
1621 page_max = 0;
1622 d = surface_data(surface);
1623 linesize = surface_stride(surface);
1624 y1 = 0;
1625 for(y = 0; y < height; y++) {
1626 addr = addr1;
1627 if (!(s->cr[VGA_CRTC_MODE] & 1)) {
1628 int shift;
1629 /* CGA compatibility handling */
1630 shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
1631 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1632 }
1633 if (!(s->cr[VGA_CRTC_MODE] & 2)) {
1634 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1635 }
1636 update = full_update;
1637 page0 = addr;
1638 page1 = addr + bwidth - 1;
1639 update |= memory_region_get_dirty(&s->vram, page0, page1 - page0,
1640 DIRTY_MEMORY_VGA);
1641 /* explicit invalidation for the hardware cursor */
1642 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1643 if (update) {
1644 if (y_start < 0)
1645 y_start = y;
1646 if (page0 < page_min)
1647 page_min = page0;
1648 if (page1 > page_max)
1649 page_max = page1;
1650 if (!(is_buffer_shared(surface))) {
1651 vga_draw_line(s, d, s->vram_ptr + addr, width);
1652 if (s->cursor_draw_line)
1653 s->cursor_draw_line(s, d, y);
1654 }
1655 } else {
1656 if (y_start >= 0) {
1657 /* flush to display */
1658 dpy_gfx_update(s->con, 0, y_start,
1659 disp_width, y - y_start);
1660 y_start = -1;
1661 }
1662 }
1663 if (!multi_run) {
1664 mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
1665 if ((y1 & mask) == mask)
1666 addr1 += line_offset;
1667 y1++;
1668 multi_run = multi_scan;
1669 } else {
1670 multi_run--;
1671 }
1672 /* line compare acts on the displayed lines */
1673 if (y == s->line_compare)
1674 addr1 = 0;
1675 d += linesize;
1676 }
1677 if (y_start >= 0) {
1678 /* flush to display */
1679 dpy_gfx_update(s->con, 0, y_start,
1680 disp_width, y - y_start);
1681 }
1682 /* reset modified pages */
1683 if (page_max >= page_min) {
1684 memory_region_reset_dirty(&s->vram,
1685 page_min,
1686 page_max - page_min,
1687 DIRTY_MEMORY_VGA);
1688 }
1689 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1690 }
1691
1692 static void vga_draw_blank(VGACommonState *s, int full_update)
1693 {
1694 DisplaySurface *surface = qemu_console_surface(s->con);
1695 int i, w, val;
1696 uint8_t *d;
1697
1698 if (!full_update)
1699 return;
1700 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1701 return;
1702
1703 s->rgb_to_pixel = rgb_to_pixel32_dup;
1704 if (surface_bits_per_pixel(surface) == 8) {
1705 val = s->rgb_to_pixel(0, 0, 0);
1706 } else {
1707 val = 0;
1708 }
1709 w = s->last_scr_width * surface_bytes_per_pixel(surface);
1710 d = surface_data(surface);
1711 for(i = 0; i < s->last_scr_height; i++) {
1712 memset(d, val, w);
1713 d += surface_stride(surface);
1714 }
1715 dpy_gfx_update(s->con, 0, 0,
1716 s->last_scr_width, s->last_scr_height);
1717 }
1718
1719 #define GMODE_TEXT 0
1720 #define GMODE_GRAPH 1
1721 #define GMODE_BLANK 2
1722
1723 static void vga_update_display(void *opaque)
1724 {
1725 VGACommonState *s = opaque;
1726 DisplaySurface *surface = qemu_console_surface(s->con);
1727 int full_update, graphic_mode;
1728
1729 qemu_flush_coalesced_mmio_buffer();
1730
1731 if (surface_bits_per_pixel(surface) == 0) {
1732 /* nothing to do */
1733 } else {
1734 full_update = 0;
1735 if (!(s->ar_index & 0x20)) {
1736 graphic_mode = GMODE_BLANK;
1737 } else {
1738 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1739 }
1740 if (graphic_mode != s->graphic_mode) {
1741 s->graphic_mode = graphic_mode;
1742 s->cursor_blink_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1743 full_update = 1;
1744 }
1745 switch(graphic_mode) {
1746 case GMODE_TEXT:
1747 vga_draw_text(s, full_update);
1748 break;
1749 case GMODE_GRAPH:
1750 vga_draw_graphic(s, full_update);
1751 break;
1752 case GMODE_BLANK:
1753 default:
1754 vga_draw_blank(s, full_update);
1755 break;
1756 }
1757 }
1758 }
1759
1760 /* force a full display refresh */
1761 static void vga_invalidate_display(void *opaque)
1762 {
1763 VGACommonState *s = opaque;
1764
1765 s->last_width = -1;
1766 s->last_height = -1;
1767 }
1768
1769 void vga_common_reset(VGACommonState *s)
1770 {
1771 s->sr_index = 0;
1772 memset(s->sr, '\0', sizeof(s->sr));
1773 s->gr_index = 0;
1774 memset(s->gr, '\0', sizeof(s->gr));
1775 s->ar_index = 0;
1776 memset(s->ar, '\0', sizeof(s->ar));
1777 s->ar_flip_flop = 0;
1778 s->cr_index = 0;
1779 memset(s->cr, '\0', sizeof(s->cr));
1780 s->msr = 0;
1781 s->fcr = 0;
1782 s->st00 = 0;
1783 s->st01 = 0;
1784 s->dac_state = 0;
1785 s->dac_sub_index = 0;
1786 s->dac_read_index = 0;
1787 s->dac_write_index = 0;
1788 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1789 s->dac_8bit = 0;
1790 memset(s->palette, '\0', sizeof(s->palette));
1791 s->bank_offset = 0;
1792 s->vbe_index = 0;
1793 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1794 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
1795 s->vbe_start_addr = 0;
1796 s->vbe_line_offset = 0;
1797 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1798 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1799 s->graphic_mode = -1; /* force full update */
1800 s->shift_control = 0;
1801 s->double_scan = 0;
1802 s->line_offset = 0;
1803 s->line_compare = 0;
1804 s->start_addr = 0;
1805 s->plane_updated = 0;
1806 s->last_cw = 0;
1807 s->last_ch = 0;
1808 s->last_width = 0;
1809 s->last_height = 0;
1810 s->last_scr_width = 0;
1811 s->last_scr_height = 0;
1812 s->cursor_start = 0;
1813 s->cursor_end = 0;
1814 s->cursor_offset = 0;
1815 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1816 memset(s->last_palette, '\0', sizeof(s->last_palette));
1817 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1818 switch (vga_retrace_method) {
1819 case VGA_RETRACE_DUMB:
1820 break;
1821 case VGA_RETRACE_PRECISE:
1822 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1823 break;
1824 }
1825 vga_update_memory_access(s);
1826 }
1827
1828 static void vga_reset(void *opaque)
1829 {
1830 VGACommonState *s = opaque;
1831 vga_common_reset(s);
1832 }
1833
1834 #define TEXTMODE_X(x) ((x) % width)
1835 #define TEXTMODE_Y(x) ((x) / width)
1836 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1837 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1838 /* relay text rendering to the display driver
1839 * instead of doing a full vga_update_display() */
1840 static void vga_update_text(void *opaque, console_ch_t *chardata)
1841 {
1842 VGACommonState *s = opaque;
1843 int graphic_mode, i, cursor_offset, cursor_visible;
1844 int cw, cheight, width, height, size, c_min, c_max;
1845 uint32_t *src;
1846 console_ch_t *dst, val;
1847 char msg_buffer[80];
1848 int full_update = 0;
1849
1850 qemu_flush_coalesced_mmio_buffer();
1851
1852 if (!(s->ar_index & 0x20)) {
1853 graphic_mode = GMODE_BLANK;
1854 } else {
1855 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1856 }
1857 if (graphic_mode != s->graphic_mode) {
1858 s->graphic_mode = graphic_mode;
1859 full_update = 1;
1860 }
1861 if (s->last_width == -1) {
1862 s->last_width = 0;
1863 full_update = 1;
1864 }
1865
1866 switch (graphic_mode) {
1867 case GMODE_TEXT:
1868 /* TODO: update palette */
1869 full_update |= update_basic_params(s);
1870
1871 /* total width & height */
1872 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
1873 cw = 8;
1874 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
1875 cw = 9;
1876 }
1877 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
1878 cw = 16; /* NOTE: no 18 pixel wide */
1879 }
1880 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1881 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
1882 /* ugly hack for CGA 160x100x16 - explain me the logic */
1883 height = 100;
1884 } else {
1885 height = s->cr[VGA_CRTC_V_DISP_END] |
1886 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1887 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1888 height = (height + 1) / cheight;
1889 }
1890
1891 size = (height * width);
1892 if (size > CH_ATTR_SIZE) {
1893 if (!full_update)
1894 return;
1895
1896 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
1897 width, height);
1898 break;
1899 }
1900
1901 if (width != s->last_width || height != s->last_height ||
1902 cw != s->last_cw || cheight != s->last_ch) {
1903 s->last_scr_width = width * cw;
1904 s->last_scr_height = height * cheight;
1905 qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
1906 dpy_text_resize(s->con, width, height);
1907 s->last_depth = 0;
1908 s->last_width = width;
1909 s->last_height = height;
1910 s->last_ch = cheight;
1911 s->last_cw = cw;
1912 full_update = 1;
1913 }
1914
1915 if (full_update) {
1916 s->full_update_gfx = 1;
1917 }
1918 if (s->full_update_text) {
1919 s->full_update_text = 0;
1920 full_update |= 1;
1921 }
1922
1923 /* Update "hardware" cursor */
1924 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1925 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
1926 if (cursor_offset != s->cursor_offset ||
1927 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1928 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
1929 cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
1930 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
1931 dpy_text_cursor(s->con,
1932 TEXTMODE_X(cursor_offset),
1933 TEXTMODE_Y(cursor_offset));
1934 else
1935 dpy_text_cursor(s->con, -1, -1);
1936 s->cursor_offset = cursor_offset;
1937 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1938 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
1939 }
1940
1941 src = (uint32_t *) s->vram_ptr + s->start_addr;
1942 dst = chardata;
1943
1944 if (full_update) {
1945 for (i = 0; i < size; src ++, dst ++, i ++)
1946 console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
1947
1948 dpy_text_update(s->con, 0, 0, width, height);
1949 } else {
1950 c_max = 0;
1951
1952 for (i = 0; i < size; src ++, dst ++, i ++) {
1953 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
1954 if (*dst != val) {
1955 *dst = val;
1956 c_max = i;
1957 break;
1958 }
1959 }
1960 c_min = i;
1961 for (; i < size; src ++, dst ++, i ++) {
1962 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
1963 if (*dst != val) {
1964 *dst = val;
1965 c_max = i;
1966 }
1967 }
1968
1969 if (c_min <= c_max) {
1970 i = TEXTMODE_Y(c_min);
1971 dpy_text_update(s->con, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
1972 }
1973 }
1974
1975 return;
1976 case GMODE_GRAPH:
1977 if (!full_update)
1978 return;
1979
1980 s->get_resolution(s, &width, &height);
1981 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
1982 width, height);
1983 break;
1984 case GMODE_BLANK:
1985 default:
1986 if (!full_update)
1987 return;
1988
1989 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
1990 break;
1991 }
1992
1993 /* Display a message */
1994 s->last_width = 60;
1995 s->last_height = height = 3;
1996 dpy_text_cursor(s->con, -1, -1);
1997 dpy_text_resize(s->con, s->last_width, height);
1998
1999 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2000 console_write_ch(dst ++, ' ');
2001
2002 size = strlen(msg_buffer);
2003 width = (s->last_width - size) / 2;
2004 dst = chardata + s->last_width + width;
2005 for (i = 0; i < size; i ++)
2006 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2007
2008 dpy_text_update(s->con, 0, 0, s->last_width, height);
2009 }
2010
2011 static uint64_t vga_mem_read(void *opaque, hwaddr addr,
2012 unsigned size)
2013 {
2014 VGACommonState *s = opaque;
2015
2016 return vga_mem_readb(s, addr);
2017 }
2018
2019 static void vga_mem_write(void *opaque, hwaddr addr,
2020 uint64_t data, unsigned size)
2021 {
2022 VGACommonState *s = opaque;
2023
2024 return vga_mem_writeb(s, addr, data);
2025 }
2026
2027 const MemoryRegionOps vga_mem_ops = {
2028 .read = vga_mem_read,
2029 .write = vga_mem_write,
2030 .endianness = DEVICE_LITTLE_ENDIAN,
2031 .impl = {
2032 .min_access_size = 1,
2033 .max_access_size = 1,
2034 },
2035 };
2036
2037 static int vga_common_post_load(void *opaque, int version_id)
2038 {
2039 VGACommonState *s = opaque;
2040
2041 /* force refresh */
2042 s->graphic_mode = -1;
2043 return 0;
2044 }
2045
2046 const VMStateDescription vmstate_vga_common = {
2047 .name = "vga",
2048 .version_id = 2,
2049 .minimum_version_id = 2,
2050 .post_load = vga_common_post_load,
2051 .fields = (VMStateField[]) {
2052 VMSTATE_UINT32(latch, VGACommonState),
2053 VMSTATE_UINT8(sr_index, VGACommonState),
2054 VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
2055 VMSTATE_UINT8(gr_index, VGACommonState),
2056 VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
2057 VMSTATE_UINT8(ar_index, VGACommonState),
2058 VMSTATE_BUFFER(ar, VGACommonState),
2059 VMSTATE_INT32(ar_flip_flop, VGACommonState),
2060 VMSTATE_UINT8(cr_index, VGACommonState),
2061 VMSTATE_BUFFER(cr, VGACommonState),
2062 VMSTATE_UINT8(msr, VGACommonState),
2063 VMSTATE_UINT8(fcr, VGACommonState),
2064 VMSTATE_UINT8(st00, VGACommonState),
2065 VMSTATE_UINT8(st01, VGACommonState),
2066
2067 VMSTATE_UINT8(dac_state, VGACommonState),
2068 VMSTATE_UINT8(dac_sub_index, VGACommonState),
2069 VMSTATE_UINT8(dac_read_index, VGACommonState),
2070 VMSTATE_UINT8(dac_write_index, VGACommonState),
2071 VMSTATE_BUFFER(dac_cache, VGACommonState),
2072 VMSTATE_BUFFER(palette, VGACommonState),
2073
2074 VMSTATE_INT32(bank_offset, VGACommonState),
2075 VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
2076 VMSTATE_UINT16(vbe_index, VGACommonState),
2077 VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
2078 VMSTATE_UINT32(vbe_start_addr, VGACommonState),
2079 VMSTATE_UINT32(vbe_line_offset, VGACommonState),
2080 VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
2081 VMSTATE_END_OF_LIST()
2082 }
2083 };
2084
2085 static const GraphicHwOps vga_ops = {
2086 .invalidate = vga_invalidate_display,
2087 .gfx_update = vga_update_display,
2088 .text_update = vga_update_text,
2089 };
2090
2091 void vga_common_init(VGACommonState *s, Object *obj, bool global_vmstate)
2092 {
2093 int i, j, v, b;
2094
2095 for(i = 0;i < 256; i++) {
2096 v = 0;
2097 for(j = 0; j < 8; j++) {
2098 v |= ((i >> j) & 1) << (j * 4);
2099 }
2100 expand4[i] = v;
2101
2102 v = 0;
2103 for(j = 0; j < 4; j++) {
2104 v |= ((i >> (2 * j)) & 3) << (j * 4);
2105 }
2106 expand2[i] = v;
2107 }
2108 for(i = 0; i < 16; i++) {
2109 v = 0;
2110 for(j = 0; j < 4; j++) {
2111 b = ((i >> j) & 1);
2112 v |= b << (2 * j);
2113 v |= b << (2 * j + 1);
2114 }
2115 expand4to8[i] = v;
2116 }
2117
2118 /* valid range: 1 MB -> 256 MB */
2119 s->vram_size = 1024 * 1024;
2120 while (s->vram_size < (s->vram_size_mb << 20) &&
2121 s->vram_size < (256 << 20)) {
2122 s->vram_size <<= 1;
2123 }
2124 s->vram_size_mb = s->vram_size >> 20;
2125 if (!s->vbe_size) {
2126 s->vbe_size = s->vram_size;
2127 }
2128
2129 s->is_vbe_vmstate = 1;
2130 memory_region_init_ram(&s->vram, obj, "vga.vram", s->vram_size,
2131 &error_abort);
2132 vmstate_register_ram(&s->vram, global_vmstate ? NULL : DEVICE(obj));
2133 xen_register_framebuffer(&s->vram);
2134 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
2135 s->get_bpp = vga_get_bpp;
2136 s->get_offsets = vga_get_offsets;
2137 s->get_resolution = vga_get_resolution;
2138 s->hw_ops = &vga_ops;
2139 switch (vga_retrace_method) {
2140 case VGA_RETRACE_DUMB:
2141 s->retrace = vga_dumb_retrace;
2142 s->update_retrace_info = vga_dumb_update_retrace_info;
2143 break;
2144
2145 case VGA_RETRACE_PRECISE:
2146 s->retrace = vga_precise_retrace;
2147 s->update_retrace_info = vga_precise_update_retrace_info;
2148 break;
2149 }
2150 vga_dirty_log_start(s);
2151 }
2152
2153 static const MemoryRegionPortio vga_portio_list[] = {
2154 { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
2155 { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
2156 { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
2157 { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
2158 { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
2159 PORTIO_END_OF_LIST(),
2160 };
2161
2162 static const MemoryRegionPortio vbe_portio_list[] = {
2163 { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
2164 # ifdef TARGET_I386
2165 { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2166 # endif
2167 { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2168 PORTIO_END_OF_LIST(),
2169 };
2170
2171 /* Used by both ISA and PCI */
2172 MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
2173 const MemoryRegionPortio **vga_ports,
2174 const MemoryRegionPortio **vbe_ports)
2175 {
2176 MemoryRegion *vga_mem;
2177
2178 *vga_ports = vga_portio_list;
2179 *vbe_ports = vbe_portio_list;
2180
2181 vga_mem = g_malloc(sizeof(*vga_mem));
2182 memory_region_init_io(vga_mem, obj, &vga_mem_ops, s,
2183 "vga-lowmem", 0x20000);
2184 memory_region_set_flush_coalesced(vga_mem);
2185
2186 return vga_mem;
2187 }
2188
2189 void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
2190 MemoryRegion *address_space_io, bool init_vga_ports)
2191 {
2192 MemoryRegion *vga_io_memory;
2193 const MemoryRegionPortio *vga_ports, *vbe_ports;
2194
2195 qemu_register_reset(vga_reset, s);
2196
2197 s->bank_offset = 0;
2198
2199 s->legacy_address_space = address_space;
2200
2201 vga_io_memory = vga_init_io(s, obj, &vga_ports, &vbe_ports);
2202 memory_region_add_subregion_overlap(address_space,
2203 isa_mem_base + 0x000a0000,
2204 vga_io_memory,
2205 1);
2206 memory_region_set_coalescing(vga_io_memory);
2207 if (init_vga_ports) {
2208 portio_list_init(&s->vga_port_list, obj, vga_ports, s, "vga");
2209 portio_list_set_flush_coalesced(&s->vga_port_list);
2210 portio_list_add(&s->vga_port_list, address_space_io, 0x3b0);
2211 }
2212 if (vbe_ports) {
2213 portio_list_init(&s->vbe_port_list, obj, vbe_ports, s, "vbe");
2214 portio_list_add(&s->vbe_port_list, address_space_io, 0x1ce);
2215 }
2216 }
2217
2218 void vga_init_vbe(VGACommonState *s, Object *obj, MemoryRegion *system_memory)
2219 {
2220 /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
2221 * so use an alias to avoid double-mapping the same region.
2222 */
2223 memory_region_init_alias(&s->vram_vbe, obj, "vram.vbe",
2224 &s->vram, 0, memory_region_size(&s->vram));
2225 /* XXX: use optimized standard vga accesses */
2226 memory_region_add_subregion(system_memory,
2227 VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2228 &s->vram_vbe);
2229 s->vbe_mapped = 1;
2230 }
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