hw/char/cadence_uart.c

   1 /*
   2  * Device model for Cadence UART
   3  *
   4  * Reference: Xilinx Zynq 7000 reference manual
   5  *   - http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
   6  *   - Chapter 19 UART Controller
   7  *   - Appendix B for Register details
   8  *
   9  * Copyright (c) 2010 Xilinx Inc.
  10  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
  11  * Copyright (c) 2012 PetaLogix Pty Ltd.
  12  * Written by Haibing Ma
  13  *            M.Habib
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version
  18  * 2 of the License, or (at your option) any later version.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, see <http://www.gnu.org/licenses/>.
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "hw/sysbus.h"
  26 #include "sysemu/char.h"
  27 #include "qemu/timer.h"
  28 #include "qemu/log.h"
  29 #include "hw/char/cadence_uart.h"
  30
  31 #ifdef CADENCE_UART_ERR_DEBUG
  32 #define DB_PRINT(...) do { \
  33     fprintf(stderr,  ": %s: ", __func__); \
  34     fprintf(stderr, ## __VA_ARGS__); \
  35     } while (0);
  36 #else
  37     #define DB_PRINT(...)
  38 #endif
  39
  40 #define UART_SR_INTR_RTRIG     0x00000001
  41 #define UART_SR_INTR_REMPTY    0x00000002
  42 #define UART_SR_INTR_RFUL      0x00000004
  43 #define UART_SR_INTR_TEMPTY    0x00000008
  44 #define UART_SR_INTR_TFUL      0x00000010
  45 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */
  46 #define UART_SR_TTRIG          0x00002000
  47 #define UART_INTR_TTRIG        0x00000400
  48 /* bits fields in CSR that correlate to CISR. If any of these bits are set in
  49  * SR, then the same bit in CISR is set high too */
  50 #define UART_SR_TO_CISR_MASK   0x0000001F
  51
  52 #define UART_INTR_ROVR         0x00000020
  53 #define UART_INTR_FRAME        0x00000040
  54 #define UART_INTR_PARE         0x00000080
  55 #define UART_INTR_TIMEOUT      0x00000100
  56 #define UART_INTR_DMSI         0x00000200
  57 #define UART_INTR_TOVR         0x00001000
  58
  59 #define UART_SR_RACTIVE    0x00000400
  60 #define UART_SR_TACTIVE    0x00000800
  61 #define UART_SR_FDELT      0x00001000
  62
  63 #define UART_CR_RXRST       0x00000001
  64 #define UART_CR_TXRST       0x00000002
  65 #define UART_CR_RX_EN       0x00000004
  66 #define UART_CR_RX_DIS      0x00000008
  67 #define UART_CR_TX_EN       0x00000010
  68 #define UART_CR_TX_DIS      0x00000020
  69 #define UART_CR_RST_TO      0x00000040
  70 #define UART_CR_STARTBRK    0x00000080
  71 #define UART_CR_STOPBRK     0x00000100
  72
  73 #define UART_MR_CLKS            0x00000001
  74 #define UART_MR_CHRL            0x00000006
  75 #define UART_MR_CHRL_SH         1
  76 #define UART_MR_PAR             0x00000038
  77 #define UART_MR_PAR_SH          3
  78 #define UART_MR_NBSTOP          0x000000C0
  79 #define UART_MR_NBSTOP_SH       6
  80 #define UART_MR_CHMODE          0x00000300
  81 #define UART_MR_CHMODE_SH       8
  82 #define UART_MR_UCLKEN          0x00000400
  83 #define UART_MR_IRMODE          0x00000800
  84
  85 #define UART_DATA_BITS_6       (0x3 << UART_MR_CHRL_SH)
  86 #define UART_DATA_BITS_7       (0x2 << UART_MR_CHRL_SH)
  87 #define UART_PARITY_ODD        (0x1 << UART_MR_PAR_SH)
  88 #define UART_PARITY_EVEN       (0x0 << UART_MR_PAR_SH)
  89 #define UART_STOP_BITS_1       (0x3 << UART_MR_NBSTOP_SH)
  90 #define UART_STOP_BITS_2       (0x2 << UART_MR_NBSTOP_SH)
  91 #define NORMAL_MODE            (0x0 << UART_MR_CHMODE_SH)
  92 #define ECHO_MODE              (0x1 << UART_MR_CHMODE_SH)
  93 #define LOCAL_LOOPBACK         (0x2 << UART_MR_CHMODE_SH)
  94 #define REMOTE_LOOPBACK        (0x3 << UART_MR_CHMODE_SH)
  95
  96 #define UART_INPUT_CLK         50000000
  97
  98 #define R_CR       (0x00/4)
  99 #define R_MR       (0x04/4)
 100 #define R_IER      (0x08/4)
 101 #define R_IDR      (0x0C/4)
 102 #define R_IMR      (0x10/4)
 103 #define R_CISR     (0x14/4)
 104 #define R_BRGR     (0x18/4)
 105 #define R_RTOR     (0x1C/4)
 106 #define R_RTRIG    (0x20/4)
 107 #define R_MCR      (0x24/4)
 108 #define R_MSR      (0x28/4)
 109 #define R_SR       (0x2C/4)
 110 #define R_TX_RX    (0x30/4)
 111 #define R_BDIV     (0x34/4)
 112 #define R_FDEL     (0x38/4)
 113 #define R_PMIN     (0x3C/4)
 114 #define R_PWID     (0x40/4)
 115 #define R_TTRIG    (0x44/4)
 116
 117
 118 static void uart_update_status(CadenceUARTState *s)
 119 {
 120     s->r[R_SR] = 0;
 121
 122     s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
 123                                                            : 0;
 124     s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
 125     s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
 126
 127     s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL
 128                                                            : 0;
 129     s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
 130     s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
 131
 132     s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
 133     s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
 134     qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
 135 }
 136
 137 static void fifo_trigger_update(void *opaque)
 138 {
 139     CadenceUARTState *s = opaque;
 140
 141     s->r[R_CISR] |= UART_INTR_TIMEOUT;
 142
 143     uart_update_status(s);
 144 }
 145
 146 static void uart_rx_reset(CadenceUARTState *s)
 147 {
 148     s->rx_wpos = 0;
 149     s->rx_count = 0;
 150     qemu_chr_fe_accept_input(&s->chr);
 151 }
 152
 153 static void uart_tx_reset(CadenceUARTState *s)
 154 {
 155     s->tx_count = 0;
 156 }
 157
 158 static void uart_send_breaks(CadenceUARTState *s)
 159 {
 160     int break_enabled = 1;
 161
 162     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 163                       &break_enabled);
 164 }
 165
 166 static void uart_parameters_setup(CadenceUARTState *s)
 167 {
 168     QEMUSerialSetParams ssp;
 169     unsigned int baud_rate, packet_size;
 170
 171     baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
 172             UART_INPUT_CLK / 8 : UART_INPUT_CLK;
 173
 174     ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
 175     packet_size = 1;
 176
 177     switch (s->r[R_MR] & UART_MR_PAR) {
 178     case UART_PARITY_EVEN:
 179         ssp.parity = 'E';
 180         packet_size++;
 181         break;
 182     case UART_PARITY_ODD:
 183         ssp.parity = 'O';
 184         packet_size++;
 185         break;
 186     default:
 187         ssp.parity = 'N';
 188         break;
 189     }
 190
 191     switch (s->r[R_MR] & UART_MR_CHRL) {
 192     case UART_DATA_BITS_6:
 193         ssp.data_bits = 6;
 194         break;
 195     case UART_DATA_BITS_7:
 196         ssp.data_bits = 7;
 197         break;
 198     default:
 199         ssp.data_bits = 8;
 200         break;
 201     }
 202
 203     switch (s->r[R_MR] & UART_MR_NBSTOP) {
 204     case UART_STOP_BITS_1:
 205         ssp.stop_bits = 1;
 206         break;
 207     default:
 208         ssp.stop_bits = 2;
 209         break;
 210     }
 211
 212     packet_size += ssp.data_bits + ssp.stop_bits;
 213     s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
 214     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 215 }
 216
 217 static int uart_can_receive(void *opaque)
 218 {
 219     CadenceUARTState *s = opaque;
 220     int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
 221     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
 222
 223     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
 224         ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
 225     }
 226     if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
 227         ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);
 228     }
 229     return ret;
 230 }
 231
 232 static void uart_ctrl_update(CadenceUARTState *s)
 233 {
 234     if (s->r[R_CR] & UART_CR_TXRST) {
 235         uart_tx_reset(s);
 236     }
 237
 238     if (s->r[R_CR] & UART_CR_RXRST) {
 239         uart_rx_reset(s);
 240     }
 241
 242     s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
 243
 244     if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
 245         uart_send_breaks(s);
 246     }
 247 }
 248
 249 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
 250 {
 251     CadenceUARTState *s = opaque;
 252     uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 253     int i;
 254
 255     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
 256         return;
 257     }
 258
 259     if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
 260         s->r[R_CISR] |= UART_INTR_ROVR;
 261     } else {
 262         for (i = 0; i < size; i++) {
 263             s->rx_fifo[s->rx_wpos] = buf[i];
 264             s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE;
 265             s->rx_count++;
 266         }
 267         timer_mod(s->fifo_trigger_handle, new_rx_time +
 268                                                 (s->char_tx_time * 4));
 269     }
 270     uart_update_status(s);
 271 }
 272
 273 static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
 274                                   void *opaque)
 275 {
 276     CadenceUARTState *s = opaque;
 277     int ret;
 278
 279     /* instant drain the fifo when there's no back-end */
 280     if (!qemu_chr_fe_get_driver(&s->chr)) {
 281         s->tx_count = 0;
 282         return FALSE;
 283     }
 284
 285     if (!s->tx_count) {
 286         return FALSE;
 287     }
 288
 289     ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count);
 290
 291     if (ret >= 0) {
 292         s->tx_count -= ret;
 293         memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count);
 294     }
 295
 296     if (s->tx_count) {
 297         guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 298                                         cadence_uart_xmit, s);
 299         if (!r) {
 300             s->tx_count = 0;
 301             return FALSE;
 302         }
 303     }
 304
 305     uart_update_status(s);
 306     return FALSE;
 307 }
 308
 309 static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
 310                                int size)
 311 {
 312     if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
 313         return;
 314     }
 315
 316     if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {
 317         size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
 318         /*
 319          * This can only be a guest error via a bad tx fifo register push,
 320          * as can_receive() should stop remote loop and echo modes ever getting
 321          * us to here.
 322          */
 323         qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow");
 324         s->r[R_CISR] |= UART_INTR_ROVR;
 325     }
 326
 327     memcpy(s->tx_fifo + s->tx_count, buf, size);
 328     s->tx_count += size;
 329
 330     cadence_uart_xmit(NULL, G_IO_OUT, s);
 331 }
 332
 333 static void uart_receive(void *opaque, const uint8_t *buf, int size)
 334 {
 335     CadenceUARTState *s = opaque;
 336     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
 337
 338     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
 339         uart_write_rx_fifo(opaque, buf, size);
 340     }
 341     if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
 342         uart_write_tx_fifo(s, buf, size);
 343     }
 344 }
 345
 346 static void uart_event(void *opaque, int event)
 347 {
 348     CadenceUARTState *s = opaque;
 349     uint8_t buf = '\0';
 350
 351     if (event == CHR_EVENT_BREAK) {
 352         uart_write_rx_fifo(opaque, &buf, 1);
 353     }
 354
 355     uart_update_status(s);
 356 }
 357
 358 static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
 359 {
 360     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
 361         return;
 362     }
 363
 364     if (s->rx_count) {
 365         uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos -
 366                             s->rx_count) % CADENCE_UART_RX_FIFO_SIZE;
 367         *c = s->rx_fifo[rx_rpos];
 368         s->rx_count--;
 369
 370         qemu_chr_fe_accept_input(&s->chr);
 371     } else {
 372         *c = 0;
 373     }
 374
 375     uart_update_status(s);
 376 }
 377
 378 static void uart_write(void *opaque, hwaddr offset,
 379                           uint64_t value, unsigned size)
 380 {
 381     CadenceUARTState *s = opaque;
 382
 383     DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
 384     offset >>= 2;
 385     if (offset >= CADENCE_UART_R_MAX) {
 386         return;
 387     }
 388     switch (offset) {
 389     case R_IER: /* ier (wts imr) */
 390         s->r[R_IMR] |= value;
 391         break;
 392     case R_IDR: /* idr (wtc imr) */
 393         s->r[R_IMR] &= ~value;
 394         break;
 395     case R_IMR: /* imr (read only) */
 396         break;
 397     case R_CISR: /* cisr (wtc) */
 398         s->r[R_CISR] &= ~value;
 399         break;
 400     case R_TX_RX: /* UARTDR */
 401         switch (s->r[R_MR] & UART_MR_CHMODE) {
 402         case NORMAL_MODE:
 403             uart_write_tx_fifo(s, (uint8_t *) &value, 1);
 404             break;
 405         case LOCAL_LOOPBACK:
 406             uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
 407             break;
 408         }
 409         break;
 410     case R_BRGR: /* Baud rate generator */
 411         if (value >= 0x01) {
 412             s->r[offset] = value & 0xFFFF;
 413         }
 414         break;
 415     case R_BDIV:    /* Baud rate divider */
 416         if (value >= 0x04) {
 417             s->r[offset] = value & 0xFF;
 418         }
 419         break;
 420     default:
 421         s->r[offset] = value;
 422     }
 423
 424     switch (offset) {
 425     case R_CR:
 426         uart_ctrl_update(s);
 427         break;
 428     case R_MR:
 429         uart_parameters_setup(s);
 430         break;
 431     }
 432     uart_update_status(s);
 433 }
 434
 435 static uint64_t uart_read(void *opaque, hwaddr offset,
 436         unsigned size)
 437 {
 438     CadenceUARTState *s = opaque;
 439     uint32_t c = 0;
 440
 441     offset >>= 2;
 442     if (offset >= CADENCE_UART_R_MAX) {
 443         c = 0;
 444     } else if (offset == R_TX_RX) {
 445         uart_read_rx_fifo(s, &c);
 446     } else {
 447        c = s->r[offset];
 448     }
 449
 450     DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
 451     return c;
 452 }
 453
 454 static const MemoryRegionOps uart_ops = {
 455     .read = uart_read,
 456     .write = uart_write,
 457     .endianness = DEVICE_NATIVE_ENDIAN,
 458 };
 459
 460 static void cadence_uart_reset(DeviceState *dev)
 461 {
 462     CadenceUARTState *s = CADENCE_UART(dev);
 463
 464     s->r[R_CR] = 0x00000128;
 465     s->r[R_IMR] = 0;
 466     s->r[R_CISR] = 0;
 467     s->r[R_RTRIG] = 0x00000020;
 468     s->r[R_BRGR] = 0x0000028B;
 469     s->r[R_BDIV] = 0x0000000F;
 470     s->r[R_TTRIG] = 0x00000020;
 471
 472     uart_rx_reset(s);
 473     uart_tx_reset(s);
 474
 475     uart_update_status(s);
 476 }
 477
 478 static void cadence_uart_realize(DeviceState *dev, Error **errp)
 479 {
 480     CadenceUARTState *s = CADENCE_UART(dev);
 481
 482     s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 483                                           fifo_trigger_update, s);
 484
 485     qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
 486                              uart_event, s, NULL, true);
 487 }
 488
 489 static void cadence_uart_init(Object *obj)
 490 {
 491     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 492     CadenceUARTState *s = CADENCE_UART(obj);
 493
 494     memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
 495     sysbus_init_mmio(sbd, &s->iomem);
 496     sysbus_init_irq(sbd, &s->irq);
 497
 498     s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
 499 }
 500
 501 static int cadence_uart_post_load(void *opaque, int version_id)
 502 {
 503     CadenceUARTState *s = opaque;
 504
 505     /* Ensure these two aren't invalid numbers */
 506     if (s->r[R_BRGR] < 1 || s->r[R_BRGR] & ~0xFFFF ||
 507         s->r[R_BDIV] <= 3 || s->r[R_BDIV] & ~0xFF) {
 508         /* Value is invalid, abort */
 509         return 1;
 510     }
 511
 512     uart_parameters_setup(s);
 513     uart_update_status(s);
 514     return 0;
 515 }
 516
 517 static const VMStateDescription vmstate_cadence_uart = {
 518     .name = "cadence_uart",
 519     .version_id = 2,
 520     .minimum_version_id = 2,
 521     .post_load = cadence_uart_post_load,
 522     .fields = (VMStateField[]) {
 523         VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
 524         VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
 525                             CADENCE_UART_RX_FIFO_SIZE),
 526         VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
 527                             CADENCE_UART_TX_FIFO_SIZE),
 528         VMSTATE_UINT32(rx_count, CadenceUARTState),
 529         VMSTATE_UINT32(tx_count, CadenceUARTState),
 530         VMSTATE_UINT32(rx_wpos, CadenceUARTState),
 531         VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
 532         VMSTATE_END_OF_LIST()
 533     }
 534 };
 535
 536 static Property cadence_uart_properties[] = {
 537     DEFINE_PROP_CHR("chardev", CadenceUARTState, chr),
 538     DEFINE_PROP_END_OF_LIST(),
 539 };
 540
 541 static void cadence_uart_class_init(ObjectClass *klass, void *data)
 542 {
 543     DeviceClass *dc = DEVICE_CLASS(klass);
 544
 545     dc->realize = cadence_uart_realize;
 546     dc->vmsd = &vmstate_cadence_uart;
 547     dc->reset = cadence_uart_reset;
 548     dc->props = cadence_uart_properties;
 549   }
 550
 551 static const TypeInfo cadence_uart_info = {
 552     .name          = TYPE_CADENCE_UART,
 553     .parent        = TYPE_SYS_BUS_DEVICE,
 554     .instance_size = sizeof(CadenceUARTState),
 555     .instance_init = cadence_uart_init,
 556     .class_init    = cadence_uart_class_init,
 557 };
 558
 559 static void cadence_uart_register_types(void)
 560 {
 561     type_register_static(&cadence_uart_info);
 562 }
 563
 564 type_init(cadence_uart_register_types)