hw/isa/piix3.c

   1 /*
   2  * QEMU PIIX PCI ISA Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/range.h"
  27 #include "qapi/error.h"
  28 #include "hw/dma/i8257.h"
  29 #include "hw/southbridge/piix.h"
  30 #include "hw/irq.h"
  31 #include "hw/isa/isa.h"
  32 #include "hw/xen/xen.h"
  33 #include "sysemu/runstate.h"
  34 #include "migration/vmstate.h"
  35 #include "hw/acpi/acpi_aml_interface.h"
  36
  37 #define XEN_PIIX_NUM_PIRQS      128ULL
  38
  39 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
  40 {
  41     qemu_set_irq(piix3->pic[pic_irq],
  42                  !!(piix3->pic_levels &
  43                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
  44                      (pic_irq * PIIX_NUM_PIRQS))));
  45 }
  46
  47 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
  48 {
  49     int pic_irq;
  50     uint64_t mask;
  51
  52     pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
  53     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
  54         return;
  55     }
  56
  57     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
  58     piix3->pic_levels &= ~mask;
  59     piix3->pic_levels |= mask * !!level;
  60 }
  61
  62 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
  63 {
  64     int pic_irq;
  65
  66     pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
  67     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
  68         return;
  69     }
  70
  71     piix3_set_irq_level_internal(piix3, pirq, level);
  72
  73     piix3_set_irq_pic(piix3, pic_irq);
  74 }
  75
  76 static void piix3_set_irq(void *opaque, int pirq, int level)
  77 {
  78     PIIX3State *piix3 = opaque;
  79     piix3_set_irq_level(piix3, pirq, level);
  80 }
  81
  82 /*
  83  * Return the global irq number corresponding to a given device irq
  84  * pin. We could also use the bus number to have a more precise mapping.
  85  */
  86 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
  87 {
  88     int slot_addend;
  89     slot_addend = PCI_SLOT(pci_dev->devfn) - 1;
  90     return (pci_intx + slot_addend) & 3;
  91 }
  92
  93 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
  94 {
  95     PIIX3State *piix3 = opaque;
  96     int irq = piix3->dev.config[PIIX_PIRQCA + pin];
  97     PCIINTxRoute route;
  98
  99     if (irq < PIIX_NUM_PIC_IRQS) {
 100         route.mode = PCI_INTX_ENABLED;
 101         route.irq = irq;
 102     } else {
 103         route.mode = PCI_INTX_DISABLED;
 104         route.irq = -1;
 105     }
 106     return route;
 107 }
 108
 109 /* irq routing is changed. so rebuild bitmap */
 110 static void piix3_update_irq_levels(PIIX3State *piix3)
 111 {
 112     PCIBus *bus = pci_get_bus(&piix3->dev);
 113     int pirq;
 114
 115     piix3->pic_levels = 0;
 116     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 117         piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
 118     }
 119 }
 120
 121 static void piix3_write_config(PCIDevice *dev,
 122                                uint32_t address, uint32_t val, int len)
 123 {
 124     pci_default_write_config(dev, address, val, len);
 125     if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
 126         PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
 127         int pic_irq;
 128
 129         pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
 130         piix3_update_irq_levels(piix3);
 131         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 132             piix3_set_irq_pic(piix3, pic_irq);
 133         }
 134     }
 135 }
 136
 137 static void piix3_write_config_xen(PCIDevice *dev,
 138                                    uint32_t address, uint32_t val, int len)
 139 {
 140     int i;
 141
 142     /* Scan for updates to PCI link routes (0x60-0x63). */
 143     for (i = 0; i < len; i++) {
 144         uint8_t v = (val >> (8 * i)) & 0xff;
 145         if (v & 0x80) {
 146             v = 0;
 147         }
 148         v &= 0xf;
 149         if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
 150             xen_set_pci_link_route(address + i - PIIX_PIRQCA, v);
 151         }
 152     }
 153
 154     piix3_write_config(dev, address, val, len);
 155 }
 156
 157 static void piix3_reset(DeviceState *dev)
 158 {
 159     PIIX3State *d = PIIX3_PCI_DEVICE(dev);
 160     uint8_t *pci_conf = d->dev.config;
 161
 162     pci_conf[0x04] = 0x07; /* master, memory and I/O */
 163     pci_conf[0x05] = 0x00;
 164     pci_conf[0x06] = 0x00;
 165     pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
 166     pci_conf[0x4c] = 0x4d;
 167     pci_conf[0x4e] = 0x03;
 168     pci_conf[0x4f] = 0x00;
 169     pci_conf[0x60] = 0x80;
 170     pci_conf[0x61] = 0x80;
 171     pci_conf[0x62] = 0x80;
 172     pci_conf[0x63] = 0x80;
 173     pci_conf[0x69] = 0x02;
 174     pci_conf[0x70] = 0x80;
 175     pci_conf[0x76] = 0x0c;
 176     pci_conf[0x77] = 0x0c;
 177     pci_conf[0x78] = 0x02;
 178     pci_conf[0x79] = 0x00;
 179     pci_conf[0x80] = 0x00;
 180     pci_conf[0x82] = 0x00;
 181     pci_conf[0xa0] = 0x08;
 182     pci_conf[0xa2] = 0x00;
 183     pci_conf[0xa3] = 0x00;
 184     pci_conf[0xa4] = 0x00;
 185     pci_conf[0xa5] = 0x00;
 186     pci_conf[0xa6] = 0x00;
 187     pci_conf[0xa7] = 0x00;
 188     pci_conf[0xa8] = 0x0f;
 189     pci_conf[0xaa] = 0x00;
 190     pci_conf[0xab] = 0x00;
 191     pci_conf[0xac] = 0x00;
 192     pci_conf[0xae] = 0x00;
 193
 194     d->pic_levels = 0;
 195     d->rcr = 0;
 196 }
 197
 198 static int piix3_post_load(void *opaque, int version_id)
 199 {
 200     PIIX3State *piix3 = opaque;
 201     int pirq;
 202
 203     /*
 204      * Because the i8259 has not been deserialized yet, qemu_irq_raise
 205      * might bring the system to a different state than the saved one;
 206      * for example, the interrupt could be masked but the i8259 would
 207      * not know that yet and would trigger an interrupt in the CPU.
 208      *
 209      * Here, we update irq levels without raising the interrupt.
 210      * Interrupt state will be deserialized separately through the i8259.
 211      */
 212     piix3->pic_levels = 0;
 213     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 214         piix3_set_irq_level_internal(piix3, pirq,
 215             pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
 216     }
 217     return 0;
 218 }
 219
 220 static int piix3_pre_save(void *opaque)
 221 {
 222     int i;
 223     PIIX3State *piix3 = opaque;
 224
 225     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 226         piix3->pci_irq_levels_vmstate[i] =
 227             pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
 228     }
 229
 230     return 0;
 231 }
 232
 233 static bool piix3_rcr_needed(void *opaque)
 234 {
 235     PIIX3State *piix3 = opaque;
 236
 237     return (piix3->rcr != 0);
 238 }
 239
 240 static const VMStateDescription vmstate_piix3_rcr = {
 241     .name = "PIIX3/rcr",
 242     .version_id = 1,
 243     .minimum_version_id = 1,
 244     .needed = piix3_rcr_needed,
 245     .fields = (VMStateField[]) {
 246         VMSTATE_UINT8(rcr, PIIX3State),
 247         VMSTATE_END_OF_LIST()
 248     }
 249 };
 250
 251 static const VMStateDescription vmstate_piix3 = {
 252     .name = "PIIX3",
 253     .version_id = 3,
 254     .minimum_version_id = 2,
 255     .post_load = piix3_post_load,
 256     .pre_save = piix3_pre_save,
 257     .fields = (VMStateField[]) {
 258         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 259         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 260                               PIIX_NUM_PIRQS, 3),
 261         VMSTATE_END_OF_LIST()
 262     },
 263     .subsections = (const VMStateDescription*[]) {
 264         &vmstate_piix3_rcr,
 265         NULL
 266     }
 267 };
 268
 269
 270 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
 271 {
 272     PIIX3State *d = opaque;
 273
 274     if (val & 4) {
 275         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 276         return;
 277     }
 278     d->rcr = val & 2; /* keep System Reset type only */
 279 }
 280
 281 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
 282 {
 283     PIIX3State *d = opaque;
 284
 285     return d->rcr;
 286 }
 287
 288 static const MemoryRegionOps rcr_ops = {
 289     .read = rcr_read,
 290     .write = rcr_write,
 291     .endianness = DEVICE_LITTLE_ENDIAN,
 292     .impl = {
 293         .min_access_size = 1,
 294         .max_access_size = 1,
 295     },
 296 };
 297
 298 static void pci_piix3_realize(PCIDevice *dev, Error **errp)
 299 {
 300     PIIX3State *d = PIIX3_PCI_DEVICE(dev);
 301     ISABus *isa_bus;
 302
 303     isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev),
 304                           pci_address_space_io(dev), errp);
 305     if (!isa_bus) {
 306         return;
 307     }
 308
 309     memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
 310                           "piix3-reset-control", 1);
 311     memory_region_add_subregion_overlap(pci_address_space_io(dev),
 312                                         PIIX_RCR_IOPORT, &d->rcr_mem, 1);
 313
 314     i8257_dma_init(isa_bus, 0);
 315 }
 316
 317 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
 318 {
 319     Aml *field;
 320     BusChild *kid;
 321     Aml *sb_scope = aml_scope("\\_SB");
 322     BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0");
 323
 324     /* PIIX PCI to ISA irq remapping */
 325     aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG,
 326                                            aml_int(0x60), 0x04));
 327     /* Fields declarion has to happen *after* operation region */
 328     field = aml_field("PCI0.S08.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
 329     aml_append(field, aml_named_field("PRQ0", 8));
 330     aml_append(field, aml_named_field("PRQ1", 8));
 331     aml_append(field, aml_named_field("PRQ2", 8));
 332     aml_append(field, aml_named_field("PRQ3", 8));
 333     aml_append(sb_scope, field);
 334     aml_append(scope, sb_scope);
 335
 336     QTAILQ_FOREACH(kid, &bus->children, sibling) {
 337         call_dev_aml_func(DEVICE(kid->child), scope);
 338     }
 339 }
 340
 341 static void pci_piix3_class_init(ObjectClass *klass, void *data)
 342 {
 343     DeviceClass *dc = DEVICE_CLASS(klass);
 344     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 345     AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 346
 347     dc->reset       = piix3_reset;
 348     dc->desc        = "ISA bridge";
 349     dc->vmsd        = &vmstate_piix3;
 350     dc->hotpluggable   = false;
 351     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 352     /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
 353     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
 354     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 355     /*
 356      * Reason: part of PIIX3 southbridge, needs to be wired up by
 357      * pc_piix.c's pc_init1()
 358      */
 359     dc->user_creatable = false;
 360     adevc->build_dev_aml = build_pci_isa_aml;
 361 }
 362
 363 static const TypeInfo piix3_pci_type_info = {
 364     .name = TYPE_PIIX3_PCI_DEVICE,
 365     .parent = TYPE_PCI_DEVICE,
 366     .instance_size = sizeof(PIIX3State),
 367     .abstract = true,
 368     .class_init = pci_piix3_class_init,
 369     .interfaces = (InterfaceInfo[]) {
 370         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 371         { TYPE_ACPI_DEV_AML_IF },
 372         { },
 373     },
 374 };
 375
 376 static void piix3_realize(PCIDevice *dev, Error **errp)
 377 {
 378     ERRP_GUARD();
 379     PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
 380     PCIBus *pci_bus = pci_get_bus(dev);
 381
 382     pci_piix3_realize(dev, errp);
 383     if (*errp) {
 384         return;
 385     }
 386
 387     pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
 388                  piix3, PIIX_NUM_PIRQS);
 389     pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
 390 }
 391
 392 static void piix3_class_init(ObjectClass *klass, void *data)
 393 {
 394     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 395
 396     k->config_write = piix3_write_config;
 397     k->realize = piix3_realize;
 398 }
 399
 400 static const TypeInfo piix3_info = {
 401     .name          = TYPE_PIIX3_DEVICE,
 402     .parent        = TYPE_PIIX3_PCI_DEVICE,
 403     .class_init    = piix3_class_init,
 404 };
 405
 406 static void piix3_xen_realize(PCIDevice *dev, Error **errp)
 407 {
 408     ERRP_GUARD();
 409     PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
 410     PCIBus *pci_bus = pci_get_bus(dev);
 411
 412     pci_piix3_realize(dev, errp);
 413     if (*errp) {
 414         return;
 415     }
 416
 417     /*
 418      * Xen supports additional interrupt routes from the PCI devices to
 419      * the IOAPIC: the four pins of each PCI device on the bus are also
 420      * connected to the IOAPIC directly.
 421      * These additional routes can be discovered through ACPI.
 422      */
 423     pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 424                  piix3, XEN_PIIX_NUM_PIRQS);
 425 }
 426
 427 static void piix3_xen_class_init(ObjectClass *klass, void *data)
 428 {
 429     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 430
 431     k->config_write = piix3_write_config_xen;
 432     k->realize = piix3_xen_realize;
 433 }
 434
 435 static const TypeInfo piix3_xen_info = {
 436     .name          = TYPE_PIIX3_XEN_DEVICE,
 437     .parent        = TYPE_PIIX3_PCI_DEVICE,
 438     .class_init    = piix3_xen_class_init,
 439 };
 440
 441 static void piix3_register_types(void)
 442 {
 443     type_register_static(&piix3_pci_type_info);
 444     type_register_static(&piix3_info);
 445     type_register_static(&piix3_xen_info);
 446 }
 447
 448 type_init(piix3_register_types)