target-tilegx/cpu.c

   1 /*
   2  * QEMU TILE-Gx CPU
   3  *
   4  *  Copyright (c) 2015 Chen Gang
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #include "hw/qdev-properties.h"
  24 #include "migration/vmstate.h"
  25 #include "linux-user/syscall_defs.h"
  26
  27 static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
  28                                   fprintf_function cpu_fprintf, int flags)
  29 {
  30     static const char * const reg_names[TILEGX_R_COUNT] = {
  31          "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
  32          "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  33         "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  34         "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
  35         "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  36         "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
  37         "r48", "r49", "r50", "r51",  "bp",  "tp",  "sp",  "lr"
  38     };
  39
  40     TileGXCPU *cpu = TILEGX_CPU(cs);
  41     CPUTLGState *env = &cpu->env;
  42     int i;
  43
  44     for (i = 0; i < TILEGX_R_COUNT; i++) {
  45         cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s",
  46                     reg_names[i], env->regs[i],
  47                     (i % 4) == 3 ? "\n" : " ");
  48     }
  49     cpu_fprintf(f, "PC  " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n",
  50                 env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
  51 }
  52
  53 TileGXCPU *cpu_tilegx_init(const char *cpu_model)
  54 {
  55     TileGXCPU *cpu;
  56
  57     cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
  58
  59     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
  60
  61     return cpu;
  62 }
  63
  64 static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
  65 {
  66     TileGXCPU *cpu = TILEGX_CPU(cs);
  67
  68     cpu->env.pc = value;
  69 }
  70
  71 static bool tilegx_cpu_has_work(CPUState *cs)
  72 {
  73     return true;
  74 }
  75
  76 static void tilegx_cpu_reset(CPUState *s)
  77 {
  78     TileGXCPU *cpu = TILEGX_CPU(s);
  79     TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
  80     CPUTLGState *env = &cpu->env;
  81
  82     tcc->parent_reset(s);
  83
  84     memset(env, 0, sizeof(CPUTLGState));
  85     tlb_flush(s, 1);
  86 }
  87
  88 static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
  89 {
  90     CPUState *cs = CPU(dev);
  91     TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
  92
  93     cpu_reset(cs);
  94     qemu_init_vcpu(cs);
  95
  96     tcc->parent_realize(dev, errp);
  97 }
  98
  99 static void tilegx_cpu_initfn(Object *obj)
 100 {
 101     CPUState *cs = CPU(obj);
 102     TileGXCPU *cpu = TILEGX_CPU(obj);
 103     CPUTLGState *env = &cpu->env;
 104     static bool tcg_initialized;
 105
 106     cs->env_ptr = env;
 107     cpu_exec_init(cs, &error_abort);
 108
 109     if (tcg_enabled() && !tcg_initialized) {
 110         tcg_initialized = true;
 111         tilegx_tcg_init();
 112     }
 113 }
 114
 115 static void tilegx_cpu_do_interrupt(CPUState *cs)
 116 {
 117     cs->exception_index = -1;
 118 }
 119
 120 static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 121                                        int mmu_idx)
 122 {
 123     TileGXCPU *cpu = TILEGX_CPU(cs);
 124
 125     /* The sigcode field will be filled in by do_signal in main.c.  */
 126     cs->exception_index = TILEGX_EXCP_SIGNAL;
 127     cpu->env.excaddr = address;
 128     cpu->env.signo = TARGET_SIGSEGV;
 129     cpu->env.sigcode = 0;
 130
 131     return 1;
 132 }
 133
 134 static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 135 {
 136     if (interrupt_request & CPU_INTERRUPT_HARD) {
 137         tilegx_cpu_do_interrupt(cs);
 138         return true;
 139     }
 140     return false;
 141 }
 142
 143 static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
 144 {
 145     DeviceClass *dc = DEVICE_CLASS(oc);
 146     CPUClass *cc = CPU_CLASS(oc);
 147     TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
 148
 149     tcc->parent_realize = dc->realize;
 150     dc->realize = tilegx_cpu_realizefn;
 151
 152     tcc->parent_reset = cc->reset;
 153     cc->reset = tilegx_cpu_reset;
 154
 155     cc->has_work = tilegx_cpu_has_work;
 156     cc->do_interrupt = tilegx_cpu_do_interrupt;
 157     cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
 158     cc->dump_state = tilegx_cpu_dump_state;
 159     cc->set_pc = tilegx_cpu_set_pc;
 160     cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
 161     cc->gdb_num_core_regs = 0;
 162
 163     /*
 164      * Reason: tilegx_cpu_initfn() calls cpu_exec_init(), which saves
 165      * the object in cpus -> dangling pointer after final
 166      * object_unref().
 167      */
 168     dc->cannot_destroy_with_object_finalize_yet = true;
 169 }
 170
 171 static const TypeInfo tilegx_cpu_type_info = {
 172     .name = TYPE_TILEGX_CPU,
 173     .parent = TYPE_CPU,
 174     .instance_size = sizeof(TileGXCPU),
 175     .instance_init = tilegx_cpu_initfn,
 176     .class_size = sizeof(TileGXCPUClass),
 177     .class_init = tilegx_cpu_class_init,
 178 };
 179
 180 static void tilegx_cpu_register_types(void)
 181 {
 182     type_register_static(&tilegx_cpu_type_info);
 183 }
 184
 185 type_init(tilegx_cpu_register_types)