hw/intc/arm_gic.c

   1 /*
   2  * ARM Generic/Distributed Interrupt Controller
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 /* This file contains implementation code for the RealView EB interrupt
  11  * controller, MPCore distributed interrupt controller and ARMv7-M
  12  * Nested Vectored Interrupt Controller.
  13  * It is compiled in two ways:
  14  *  (1) as a standalone file to produce a sysbus device which is a GIC
  15  *  that can be used on the realview board and as one of the builtin
  16  *  private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
  17  *  (2) by being directly #included into armv7m_nvic.c to produce the
  18  *  armv7m_nvic device.
  19  */
  20
  21 #include "hw/sysbus.h"
  22 #include "gic_internal.h"
  23 #include "qom/cpu.h"
  24
  25 //#define DEBUG_GIC
  26
  27 #ifdef DEBUG_GIC
  28 #define DPRINTF(fmt, ...) \
  29 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0)
  30 #else
  31 #define DPRINTF(fmt, ...) do {} while(0)
  32 #endif
  33
  34 static const uint8_t gic_id[] = {
  35     0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
  36 };
  37
  38 #define NUM_CPU(s) ((s)->num_cpu)
  39
  40 static inline int gic_get_current_cpu(GICState *s)
  41 {
  42     if (s->num_cpu > 1) {
  43         return current_cpu->cpu_index;
  44     }
  45     return 0;
  46 }
  47
  48 /* TODO: Many places that call this routine could be optimized.  */
  49 /* Update interrupt status after enabled or pending bits have been changed.  */
  50 void gic_update(GICState *s)
  51 {
  52     int best_irq;
  53     int best_prio;
  54     int irq;
  55     int level;
  56     int cpu;
  57     int cm;
  58
  59     for (cpu = 0; cpu < NUM_CPU(s); cpu++) {
  60         cm = 1 << cpu;
  61         s->current_pending[cpu] = 1023;
  62         if (!s->enabled || !s->cpu_enabled[cpu]) {
  63             qemu_irq_lower(s->parent_irq[cpu]);
  64             return;
  65         }
  66         best_prio = 0x100;
  67         best_irq = 1023;
  68         for (irq = 0; irq < s->num_irq; irq++) {
  69             if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) {
  70                 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
  71                     best_prio = GIC_GET_PRIORITY(irq, cpu);
  72                     best_irq = irq;
  73                 }
  74             }
  75         }
  76         level = 0;
  77         if (best_prio < s->priority_mask[cpu]) {
  78             s->current_pending[cpu] = best_irq;
  79             if (best_prio < s->running_priority[cpu]) {
  80                 DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu);
  81                 level = 1;
  82             }
  83         }
  84         qemu_set_irq(s->parent_irq[cpu], level);
  85     }
  86 }
  87
  88 void gic_set_pending_private(GICState *s, int cpu, int irq)
  89 {
  90     int cm = 1 << cpu;
  91
  92     if (GIC_TEST_PENDING(irq, cm))
  93         return;
  94
  95     DPRINTF("Set %d pending cpu %d\n", irq, cpu);
  96     GIC_SET_PENDING(irq, cm);
  97     gic_update(s);
  98 }
  99
 100 /* Process a change in an external IRQ input.  */
 101 static void gic_set_irq(void *opaque, int irq, int level)
 102 {
 103     /* Meaning of the 'irq' parameter:
 104      *  [0..N-1] : external interrupts
 105      *  [N..N+31] : PPI (internal) interrupts for CPU 0
 106      *  [N+32..N+63] : PPI (internal interrupts for CPU 1
 107      *  ...
 108      */
 109     GICState *s = (GICState *)opaque;
 110     int cm, target;
 111     if (irq < (s->num_irq - GIC_INTERNAL)) {
 112         /* The first external input line is internal interrupt 32.  */
 113         cm = ALL_CPU_MASK;
 114         irq += GIC_INTERNAL;
 115         target = GIC_TARGET(irq);
 116     } else {
 117         int cpu;
 118         irq -= (s->num_irq - GIC_INTERNAL);
 119         cpu = irq / GIC_INTERNAL;
 120         irq %= GIC_INTERNAL;
 121         cm = 1 << cpu;
 122         target = cm;
 123     }
 124
 125     if (level == GIC_TEST_LEVEL(irq, cm)) {
 126         return;
 127     }
 128
 129     if (level) {
 130         GIC_SET_LEVEL(irq, cm);
 131         if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) {
 132             DPRINTF("Set %d pending mask %x\n", irq, target);
 133             GIC_SET_PENDING(irq, target);
 134         }
 135     } else {
 136         GIC_CLEAR_LEVEL(irq, cm);
 137     }
 138     gic_update(s);
 139 }
 140
 141 static void gic_set_running_irq(GICState *s, int cpu, int irq)
 142 {
 143     s->running_irq[cpu] = irq;
 144     if (irq == 1023) {
 145         s->running_priority[cpu] = 0x100;
 146     } else {
 147         s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu);
 148     }
 149     gic_update(s);
 150 }
 151
 152 uint32_t gic_acknowledge_irq(GICState *s, int cpu)
 153 {
 154     int new_irq;
 155     int cm = 1 << cpu;
 156     new_irq = s->current_pending[cpu];
 157     if (new_irq == 1023
 158             || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) {
 159         DPRINTF("ACK no pending IRQ\n");
 160         return 1023;
 161     }
 162     s->last_active[new_irq][cpu] = s->running_irq[cpu];
 163     /* Clear pending flags for both level and edge triggered interrupts.
 164        Level triggered IRQs will be reasserted once they become inactive.  */
 165     GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm);
 166     gic_set_running_irq(s, cpu, new_irq);
 167     DPRINTF("ACK %d\n", new_irq);
 168     return new_irq;
 169 }
 170
 171 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val)
 172 {
 173     if (irq < GIC_INTERNAL) {
 174         s->priority1[irq][cpu] = val;
 175     } else {
 176         s->priority2[(irq) - GIC_INTERNAL] = val;
 177     }
 178 }
 179
 180 void gic_complete_irq(GICState *s, int cpu, int irq)
 181 {
 182     int update = 0;
 183     int cm = 1 << cpu;
 184     DPRINTF("EOI %d\n", irq);
 185     if (irq >= s->num_irq) {
 186         /* This handles two cases:
 187          * 1. If software writes the ID of a spurious interrupt [ie 1023]
 188          * to the GICC_EOIR, the GIC ignores that write.
 189          * 2. If software writes the number of a non-existent interrupt
 190          * this must be a subcase of "value written does not match the last
 191          * valid interrupt value read from the Interrupt Acknowledge
 192          * register" and so this is UNPREDICTABLE. We choose to ignore it.
 193          */
 194         return;
 195     }
 196     if (s->running_irq[cpu] == 1023)
 197         return; /* No active IRQ.  */
 198     /* Mark level triggered interrupts as pending if they are still
 199        raised.  */
 200     if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
 201         && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
 202         DPRINTF("Set %d pending mask %x\n", irq, cm);
 203         GIC_SET_PENDING(irq, cm);
 204         update = 1;
 205     }
 206     if (irq != s->running_irq[cpu]) {
 207         /* Complete an IRQ that is not currently running.  */
 208         int tmp = s->running_irq[cpu];
 209         while (s->last_active[tmp][cpu] != 1023) {
 210             if (s->last_active[tmp][cpu] == irq) {
 211                 s->last_active[tmp][cpu] = s->last_active[irq][cpu];
 212                 break;
 213             }
 214             tmp = s->last_active[tmp][cpu];
 215         }
 216         if (update) {
 217             gic_update(s);
 218         }
 219     } else {
 220         /* Complete the current running IRQ.  */
 221         gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]);
 222     }
 223 }
 224
 225 static uint32_t gic_dist_readb(void *opaque, hwaddr offset)
 226 {
 227     GICState *s = (GICState *)opaque;
 228     uint32_t res;
 229     int irq;
 230     int i;
 231     int cpu;
 232     int cm;
 233     int mask;
 234
 235     cpu = gic_get_current_cpu(s);
 236     cm = 1 << cpu;
 237     if (offset < 0x100) {
 238         if (offset == 0)
 239             return s->enabled;
 240         if (offset == 4)
 241             return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
 242         if (offset < 0x08)
 243             return 0;
 244         if (offset >= 0x80) {
 245             /* Interrupt Security , RAZ/WI */
 246             return 0;
 247         }
 248         goto bad_reg;
 249     } else if (offset < 0x200) {
 250         /* Interrupt Set/Clear Enable.  */
 251         if (offset < 0x180)
 252             irq = (offset - 0x100) * 8;
 253         else
 254             irq = (offset - 0x180) * 8;
 255         irq += GIC_BASE_IRQ;
 256         if (irq >= s->num_irq)
 257             goto bad_reg;
 258         res = 0;
 259         for (i = 0; i < 8; i++) {
 260             if (GIC_TEST_ENABLED(irq + i, cm)) {
 261                 res |= (1 << i);
 262             }
 263         }
 264     } else if (offset < 0x300) {
 265         /* Interrupt Set/Clear Pending.  */
 266         if (offset < 0x280)
 267             irq = (offset - 0x200) * 8;
 268         else
 269             irq = (offset - 0x280) * 8;
 270         irq += GIC_BASE_IRQ;
 271         if (irq >= s->num_irq)
 272             goto bad_reg;
 273         res = 0;
 274         mask = (irq < GIC_INTERNAL) ?  cm : ALL_CPU_MASK;
 275         for (i = 0; i < 8; i++) {
 276             if (GIC_TEST_PENDING(irq + i, mask)) {
 277                 res |= (1 << i);
 278             }
 279         }
 280     } else if (offset < 0x400) {
 281         /* Interrupt Active.  */
 282         irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
 283         if (irq >= s->num_irq)
 284             goto bad_reg;
 285         res = 0;
 286         mask = (irq < GIC_INTERNAL) ?  cm : ALL_CPU_MASK;
 287         for (i = 0; i < 8; i++) {
 288             if (GIC_TEST_ACTIVE(irq + i, mask)) {
 289                 res |= (1 << i);
 290             }
 291         }
 292     } else if (offset < 0x800) {
 293         /* Interrupt Priority.  */
 294         irq = (offset - 0x400) + GIC_BASE_IRQ;
 295         if (irq >= s->num_irq)
 296             goto bad_reg;
 297         res = GIC_GET_PRIORITY(irq, cpu);
 298     } else if (offset < 0xc00) {
 299         /* Interrupt CPU Target.  */
 300         if (s->num_cpu == 1 && s->revision != REV_11MPCORE) {
 301             /* For uniprocessor GICs these RAZ/WI */
 302             res = 0;
 303         } else {
 304             irq = (offset - 0x800) + GIC_BASE_IRQ;
 305             if (irq >= s->num_irq) {
 306                 goto bad_reg;
 307             }
 308             if (irq >= 29 && irq <= 31) {
 309                 res = cm;
 310             } else {
 311                 res = GIC_TARGET(irq);
 312             }
 313         }
 314     } else if (offset < 0xf00) {
 315         /* Interrupt Configuration.  */
 316         irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ;
 317         if (irq >= s->num_irq)
 318             goto bad_reg;
 319         res = 0;
 320         for (i = 0; i < 4; i++) {
 321             if (GIC_TEST_MODEL(irq + i))
 322                 res |= (1 << (i * 2));
 323             if (GIC_TEST_EDGE_TRIGGER(irq + i))
 324                 res |= (2 << (i * 2));
 325         }
 326     } else if (offset < 0xfe0) {
 327         goto bad_reg;
 328     } else /* offset >= 0xfe0 */ {
 329         if (offset & 3) {
 330             res = 0;
 331         } else {
 332             res = gic_id[(offset - 0xfe0) >> 2];
 333         }
 334     }
 335     return res;
 336 bad_reg:
 337     qemu_log_mask(LOG_GUEST_ERROR,
 338                   "gic_dist_readb: Bad offset %x\n", (int)offset);
 339     return 0;
 340 }
 341
 342 static uint32_t gic_dist_readw(void *opaque, hwaddr offset)
 343 {
 344     uint32_t val;
 345     val = gic_dist_readb(opaque, offset);
 346     val |= gic_dist_readb(opaque, offset + 1) << 8;
 347     return val;
 348 }
 349
 350 static uint32_t gic_dist_readl(void *opaque, hwaddr offset)
 351 {
 352     uint32_t val;
 353     val = gic_dist_readw(opaque, offset);
 354     val |= gic_dist_readw(opaque, offset + 2) << 16;
 355     return val;
 356 }
 357
 358 static void gic_dist_writeb(void *opaque, hwaddr offset,
 359                             uint32_t value)
 360 {
 361     GICState *s = (GICState *)opaque;
 362     int irq;
 363     int i;
 364     int cpu;
 365
 366     cpu = gic_get_current_cpu(s);
 367     if (offset < 0x100) {
 368         if (offset == 0) {
 369             s->enabled = (value & 1);
 370             DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
 371         } else if (offset < 4) {
 372             /* ignored.  */
 373         } else if (offset >= 0x80) {
 374             /* Interrupt Security Registers, RAZ/WI */
 375         } else {
 376             goto bad_reg;
 377         }
 378     } else if (offset < 0x180) {
 379         /* Interrupt Set Enable.  */
 380         irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
 381         if (irq >= s->num_irq)
 382             goto bad_reg;
 383         if (irq < GIC_NR_SGIS) {
 384             value = 0xff;
 385         }
 386
 387         for (i = 0; i < 8; i++) {
 388             if (value & (1 << i)) {
 389                 int mask =
 390                     (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i);
 391                 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 392
 393                 if (!GIC_TEST_ENABLED(irq + i, cm)) {
 394                     DPRINTF("Enabled IRQ %d\n", irq + i);
 395                 }
 396                 GIC_SET_ENABLED(irq + i, cm);
 397                 /* If a raised level triggered IRQ enabled then mark
 398                    is as pending.  */
 399                 if (GIC_TEST_LEVEL(irq + i, mask)
 400                         && !GIC_TEST_EDGE_TRIGGER(irq + i)) {
 401                     DPRINTF("Set %d pending mask %x\n", irq + i, mask);
 402                     GIC_SET_PENDING(irq + i, mask);
 403                 }
 404             }
 405         }
 406     } else if (offset < 0x200) {
 407         /* Interrupt Clear Enable.  */
 408         irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;
 409         if (irq >= s->num_irq)
 410             goto bad_reg;
 411         if (irq < GIC_NR_SGIS) {
 412             value = 0;
 413         }
 414
 415         for (i = 0; i < 8; i++) {
 416             if (value & (1 << i)) {
 417                 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 418
 419                 if (GIC_TEST_ENABLED(irq + i, cm)) {
 420                     DPRINTF("Disabled IRQ %d\n", irq + i);
 421                 }
 422                 GIC_CLEAR_ENABLED(irq + i, cm);
 423             }
 424         }
 425     } else if (offset < 0x280) {
 426         /* Interrupt Set Pending.  */
 427         irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;
 428         if (irq >= s->num_irq)
 429             goto bad_reg;
 430         if (irq < GIC_NR_SGIS) {
 431             irq = 0;
 432         }
 433
 434         for (i = 0; i < 8; i++) {
 435             if (value & (1 << i)) {
 436                 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i));
 437             }
 438         }
 439     } else if (offset < 0x300) {
 440         /* Interrupt Clear Pending.  */
 441         irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
 442         if (irq >= s->num_irq)
 443             goto bad_reg;
 444         for (i = 0; i < 8; i++) {
 445             /* ??? This currently clears the pending bit for all CPUs, even
 446                for per-CPU interrupts.  It's unclear whether this is the
 447                corect behavior.  */
 448             if (value & (1 << i)) {
 449                 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
 450             }
 451         }
 452     } else if (offset < 0x400) {
 453         /* Interrupt Active.  */
 454         goto bad_reg;
 455     } else if (offset < 0x800) {
 456         /* Interrupt Priority.  */
 457         irq = (offset - 0x400) + GIC_BASE_IRQ;
 458         if (irq >= s->num_irq)
 459             goto bad_reg;
 460         gic_set_priority(s, cpu, irq, value);
 461     } else if (offset < 0xc00) {
 462         /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
 463          * annoying exception of the 11MPCore's GIC.
 464          */
 465         if (s->num_cpu != 1 || s->revision == REV_11MPCORE) {
 466             irq = (offset - 0x800) + GIC_BASE_IRQ;
 467             if (irq >= s->num_irq) {
 468                 goto bad_reg;
 469             }
 470             if (irq < 29) {
 471                 value = 0;
 472             } else if (irq < GIC_INTERNAL) {
 473                 value = ALL_CPU_MASK;
 474             }
 475             s->irq_target[irq] = value & ALL_CPU_MASK;
 476         }
 477     } else if (offset < 0xf00) {
 478         /* Interrupt Configuration.  */
 479         irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
 480         if (irq >= s->num_irq)
 481             goto bad_reg;
 482         if (irq < GIC_INTERNAL)
 483             value |= 0xaa;
 484         for (i = 0; i < 4; i++) {
 485             if (value & (1 << (i * 2))) {
 486                 GIC_SET_MODEL(irq + i);
 487             } else {
 488                 GIC_CLEAR_MODEL(irq + i);
 489             }
 490             if (value & (2 << (i * 2))) {
 491                 GIC_SET_EDGE_TRIGGER(irq + i);
 492             } else {
 493                 GIC_CLEAR_EDGE_TRIGGER(irq + i);
 494             }
 495         }
 496     } else {
 497         /* 0xf00 is only handled for 32-bit writes.  */
 498         goto bad_reg;
 499     }
 500     gic_update(s);
 501     return;
 502 bad_reg:
 503     qemu_log_mask(LOG_GUEST_ERROR,
 504                   "gic_dist_writeb: Bad offset %x\n", (int)offset);
 505 }
 506
 507 static void gic_dist_writew(void *opaque, hwaddr offset,
 508                             uint32_t value)
 509 {
 510     gic_dist_writeb(opaque, offset, value & 0xff);
 511     gic_dist_writeb(opaque, offset + 1, value >> 8);
 512 }
 513
 514 static void gic_dist_writel(void *opaque, hwaddr offset,
 515                             uint32_t value)
 516 {
 517     GICState *s = (GICState *)opaque;
 518     if (offset == 0xf00) {
 519         int cpu;
 520         int irq;
 521         int mask;
 522
 523         cpu = gic_get_current_cpu(s);
 524         irq = value & 0x3ff;
 525         switch ((value >> 24) & 3) {
 526         case 0:
 527             mask = (value >> 16) & ALL_CPU_MASK;
 528             break;
 529         case 1:
 530             mask = ALL_CPU_MASK ^ (1 << cpu);
 531             break;
 532         case 2:
 533             mask = 1 << cpu;
 534             break;
 535         default:
 536             DPRINTF("Bad Soft Int target filter\n");
 537             mask = ALL_CPU_MASK;
 538             break;
 539         }
 540         GIC_SET_PENDING(irq, mask);
 541         gic_update(s);
 542         return;
 543     }
 544     gic_dist_writew(opaque, offset, value & 0xffff);
 545     gic_dist_writew(opaque, offset + 2, value >> 16);
 546 }
 547
 548 static const MemoryRegionOps gic_dist_ops = {
 549     .old_mmio = {
 550         .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, },
 551         .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, },
 552     },
 553     .endianness = DEVICE_NATIVE_ENDIAN,
 554 };
 555
 556 static uint32_t gic_cpu_read(GICState *s, int cpu, int offset)
 557 {
 558     switch (offset) {
 559     case 0x00: /* Control */
 560         return s->cpu_enabled[cpu];
 561     case 0x04: /* Priority mask */
 562         return s->priority_mask[cpu];
 563     case 0x08: /* Binary Point */
 564         /* ??? Not implemented.  */
 565         return 0;
 566     case 0x0c: /* Acknowledge */
 567         return gic_acknowledge_irq(s, cpu);
 568     case 0x14: /* Running Priority */
 569         return s->running_priority[cpu];
 570     case 0x18: /* Highest Pending Interrupt */
 571         return s->current_pending[cpu];
 572     default:
 573         qemu_log_mask(LOG_GUEST_ERROR,
 574                       "gic_cpu_read: Bad offset %x\n", (int)offset);
 575         return 0;
 576     }
 577 }
 578
 579 static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value)
 580 {
 581     switch (offset) {
 582     case 0x00: /* Control */
 583         s->cpu_enabled[cpu] = (value & 1);
 584         DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled[cpu] ? "En" : "Dis");
 585         break;
 586     case 0x04: /* Priority mask */
 587         s->priority_mask[cpu] = (value & 0xff);
 588         break;
 589     case 0x08: /* Binary Point */
 590         /* ??? Not implemented.  */
 591         break;
 592     case 0x10: /* End Of Interrupt */
 593         return gic_complete_irq(s, cpu, value & 0x3ff);
 594     default:
 595         qemu_log_mask(LOG_GUEST_ERROR,
 596                       "gic_cpu_write: Bad offset %x\n", (int)offset);
 597         return;
 598     }
 599     gic_update(s);
 600 }
 601
 602 /* Wrappers to read/write the GIC CPU interface for the current CPU */
 603 static uint64_t gic_thiscpu_read(void *opaque, hwaddr addr,
 604                                  unsigned size)
 605 {
 606     GICState *s = (GICState *)opaque;
 607     return gic_cpu_read(s, gic_get_current_cpu(s), addr);
 608 }
 609
 610 static void gic_thiscpu_write(void *opaque, hwaddr addr,
 611                               uint64_t value, unsigned size)
 612 {
 613     GICState *s = (GICState *)opaque;
 614     gic_cpu_write(s, gic_get_current_cpu(s), addr, value);
 615 }
 616
 617 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
 618  * These just decode the opaque pointer into GICState* + cpu id.
 619  */
 620 static uint64_t gic_do_cpu_read(void *opaque, hwaddr addr,
 621                                 unsigned size)
 622 {
 623     GICState **backref = (GICState **)opaque;
 624     GICState *s = *backref;
 625     int id = (backref - s->backref);
 626     return gic_cpu_read(s, id, addr);
 627 }
 628
 629 static void gic_do_cpu_write(void *opaque, hwaddr addr,
 630                              uint64_t value, unsigned size)
 631 {
 632     GICState **backref = (GICState **)opaque;
 633     GICState *s = *backref;
 634     int id = (backref - s->backref);
 635     gic_cpu_write(s, id, addr, value);
 636 }
 637
 638 static const MemoryRegionOps gic_thiscpu_ops = {
 639     .read = gic_thiscpu_read,
 640     .write = gic_thiscpu_write,
 641     .endianness = DEVICE_NATIVE_ENDIAN,
 642 };
 643
 644 static const MemoryRegionOps gic_cpu_ops = {
 645     .read = gic_do_cpu_read,
 646     .write = gic_do_cpu_write,
 647     .endianness = DEVICE_NATIVE_ENDIAN,
 648 };
 649
 650 void gic_init_irqs_and_distributor(GICState *s, int num_irq)
 651 {
 652     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
 653     int i;
 654
 655     i = s->num_irq - GIC_INTERNAL;
 656     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
 657      * GPIO array layout is thus:
 658      *  [0..N-1] SPIs
 659      *  [N..N+31] PPIs for CPU 0
 660      *  [N+32..N+63] PPIs for CPU 1
 661      *   ...
 662      */
 663     if (s->revision != REV_NVIC) {
 664         i += (GIC_INTERNAL * s->num_cpu);
 665     }
 666     qdev_init_gpio_in(DEVICE(s), gic_set_irq, i);
 667     for (i = 0; i < NUM_CPU(s); i++) {
 668         sysbus_init_irq(sbd, &s->parent_irq[i]);
 669     }
 670     memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s,
 671                           "gic_dist", 0x1000);
 672 }
 673
 674 static void arm_gic_realize(DeviceState *dev, Error **errp)
 675 {
 676     /* Device instance realize function for the GIC sysbus device */
 677     int i;
 678     GICState *s = ARM_GIC(dev);
 679     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 680     ARMGICClass *agc = ARM_GIC_GET_CLASS(s);
 681
 682     agc->parent_realize(dev, errp);
 683     if (error_is_set(errp)) {
 684         return;
 685     }
 686
 687     gic_init_irqs_and_distributor(s, s->num_irq);
 688
 689     /* Memory regions for the CPU interfaces (NVIC doesn't have these):
 690      * a region for "CPU interface for this core", then a region for
 691      * "CPU interface for core 0", "for core 1", ...
 692      * NB that the memory region size of 0x100 applies for the 11MPCore
 693      * and also cores following the GIC v1 spec (ie A9).
 694      * GIC v2 defines a larger memory region (0x1000) so this will need
 695      * to be extended when we implement A15.
 696      */
 697     memory_region_init_io(&s->cpuiomem[0], OBJECT(s), &gic_thiscpu_ops, s,
 698                           "gic_cpu", 0x100);
 699     for (i = 0; i < NUM_CPU(s); i++) {
 700         s->backref[i] = s;
 701         memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops,
 702                               &s->backref[i], "gic_cpu", 0x100);
 703     }
 704     /* Distributor */
 705     sysbus_init_mmio(sbd, &s->iomem);
 706     /* cpu interfaces (one for "current cpu" plus one per cpu) */
 707     for (i = 0; i <= NUM_CPU(s); i++) {
 708         sysbus_init_mmio(sbd, &s->cpuiomem[i]);
 709     }
 710 }
 711
 712 static void arm_gic_class_init(ObjectClass *klass, void *data)
 713 {
 714     DeviceClass *dc = DEVICE_CLASS(klass);
 715     ARMGICClass *agc = ARM_GIC_CLASS(klass);
 716
 717     agc->parent_realize = dc->realize;
 718     dc->realize = arm_gic_realize;
 719 }
 720
 721 static const TypeInfo arm_gic_info = {
 722     .name = TYPE_ARM_GIC,
 723     .parent = TYPE_ARM_GIC_COMMON,
 724     .instance_size = sizeof(GICState),
 725     .class_init = arm_gic_class_init,
 726     .class_size = sizeof(ARMGICClass),
 727 };
 728
 729 static void arm_gic_register_types(void)
 730 {
 731     type_register_static(&arm_gic_info);
 732 }
 733
 734 type_init(arm_gic_register_types)