include/hw/intc/arm_gic_common.h

   1 /*
   2  * ARM GIC support
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef HW_ARM_GIC_COMMON_H
  22 #define HW_ARM_GIC_COMMON_H
  23
  24 #include "hw/sysbus.h"
  25
  26 /* Maximum number of possible interrupts, determined by the GIC architecture */
  27 #define GIC_MAXIRQ 1020
  28 /* First 32 are private to each CPU (SGIs and PPIs). */
  29 #define GIC_INTERNAL 32
  30 #define GIC_NR_SGIS 16
  31 /* Maximum number of possible CPU interfaces, determined by GIC architecture */
  32 #define GIC_NCPU 8
  33
  34 typedef struct gic_irq_state {
  35     /* The enable bits are only banked for per-cpu interrupts.  */
  36     uint8_t enabled;
  37     uint8_t pending;
  38     uint8_t active;
  39     uint8_t level;
  40     bool model; /* 0 = N:N, 1 = 1:N */
  41     bool edge_trigger; /* true: edge-triggered, false: level-triggered  */
  42 } gic_irq_state;
  43
  44 typedef struct GICState {
  45     /*< private >*/
  46     SysBusDevice parent_obj;
  47     /*< public >*/
  48
  49     qemu_irq parent_irq[GIC_NCPU];
  50     bool enabled;
  51     bool cpu_enabled[GIC_NCPU];
  52
  53     gic_irq_state irq_state[GIC_MAXIRQ];
  54     uint8_t irq_target[GIC_MAXIRQ];
  55     uint8_t priority1[GIC_INTERNAL][GIC_NCPU];
  56     uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
  57     uint16_t last_active[GIC_MAXIRQ][GIC_NCPU];
  58     /* For each SGI on the target CPU, we store 8 bits
  59      * indicating which source CPUs have made this SGI
  60      * pending on the target CPU. These correspond to
  61      * the bytes in the GIC_SPENDSGIR* registers as
  62      * read by the target CPU.
  63      */
  64     uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
  65
  66     uint16_t priority_mask[GIC_NCPU];
  67     uint16_t running_irq[GIC_NCPU];
  68     uint16_t running_priority[GIC_NCPU];
  69     uint16_t current_pending[GIC_NCPU];
  70
  71     uint32_t num_cpu;
  72
  73     MemoryRegion iomem; /* Distributor */
  74     /* This is just so we can have an opaque pointer which identifies
  75      * both this GIC and which CPU interface we should be accessing.
  76      */
  77     struct GICState *backref[GIC_NCPU];
  78     MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */
  79     uint32_t num_irq;
  80     uint32_t revision;
  81 } GICState;
  82
  83 #define TYPE_ARM_GIC_COMMON "arm_gic_common"
  84 #define ARM_GIC_COMMON(obj) \
  85      OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON)
  86 #define ARM_GIC_COMMON_CLASS(klass) \
  87      OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON)
  88 #define ARM_GIC_COMMON_GET_CLASS(obj) \
  89      OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON)
  90
  91 typedef struct ARMGICCommonClass {
  92     /*< private >*/
  93     SysBusDeviceClass parent_class;
  94     /*< public >*/
  95
  96     void (*pre_save)(GICState *s);
  97     void (*post_load)(GICState *s);
  98 } ARMGICCommonClass;
  99
 100 #endif