target-lm32/cpu.h

   1 /*
   2  *  LatticeMico32 virtual CPU header.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef CPU_LM32_H
  21 #define CPU_LM32_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define CPUArchState struct CPULM32State
  26
  27 #include "config.h"
  28 #include "qemu-common.h"
  29 #include "exec/cpu-defs.h"
  30 struct CPULM32State;
  31 typedef struct CPULM32State CPULM32State;
  32
  33 #define TARGET_HAS_ICE 1
  34
  35 #define ELF_MACHINE EM_LATTICEMICO32
  36
  37 #define NB_MMU_MODES 1
  38 #define TARGET_PAGE_BITS 12
  39 static inline int cpu_mmu_index(CPULM32State *env)
  40 {
  41     return 0;
  42 }
  43
  44 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  45 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  46
  47 /* Exceptions indices */
  48 enum {
  49     EXCP_RESET = 0,
  50     EXCP_BREAKPOINT,
  51     EXCP_INSN_BUS_ERROR,
  52     EXCP_WATCHPOINT,
  53     EXCP_DATA_BUS_ERROR,
  54     EXCP_DIVIDE_BY_ZERO,
  55     EXCP_IRQ,
  56     EXCP_SYSTEMCALL
  57 };
  58
  59 /* Registers */
  60 enum {
  61     R_R0 = 0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R10,
  62     R_R11, R_R12, R_R13, R_R14, R_R15, R_R16, R_R17, R_R18, R_R19, R_R20,
  63     R_R21, R_R22, R_R23, R_R24, R_R25, R_R26, R_R27, R_R28, R_R29, R_R30,
  64     R_R31
  65 };
  66
  67 /* Register aliases */
  68 enum {
  69     R_GP = R_R26,
  70     R_FP = R_R27,
  71     R_SP = R_R28,
  72     R_RA = R_R29,
  73     R_EA = R_R30,
  74     R_BA = R_R31
  75 };
  76
  77 /* IE flags */
  78 enum {
  79     IE_IE  = (1<<0),
  80     IE_EIE = (1<<1),
  81     IE_BIE = (1<<2),
  82 };
  83
  84 /* DC flags */
  85 enum {
  86     DC_SS  = (1<<0),
  87     DC_RE  = (1<<1),
  88     DC_C0  = (1<<2),
  89     DC_C1  = (1<<3),
  90     DC_C2  = (1<<4),
  91     DC_C3  = (1<<5),
  92 };
  93
  94 /* CFG mask */
  95 enum {
  96     CFG_M         = (1<<0),
  97     CFG_D         = (1<<1),
  98     CFG_S         = (1<<2),
  99     CFG_U         = (1<<3),
 100     CFG_X         = (1<<4),
 101     CFG_CC        = (1<<5),
 102     CFG_IC        = (1<<6),
 103     CFG_DC        = (1<<7),
 104     CFG_G         = (1<<8),
 105     CFG_H         = (1<<9),
 106     CFG_R         = (1<<10),
 107     CFG_J         = (1<<11),
 108     CFG_INT_SHIFT = 12,
 109     CFG_BP_SHIFT  = 18,
 110     CFG_WP_SHIFT  = 22,
 111     CFG_REV_SHIFT = 26,
 112 };
 113
 114 /* CSRs */
 115 enum {
 116     CSR_IE   = 0x00,
 117     CSR_IM   = 0x01,
 118     CSR_IP   = 0x02,
 119     CSR_ICC  = 0x03,
 120     CSR_DCC  = 0x04,
 121     CSR_CC   = 0x05,
 122     CSR_CFG  = 0x06,
 123     CSR_EBA  = 0x07,
 124     CSR_DC   = 0x08,
 125     CSR_DEBA = 0x09,
 126     CSR_JTX  = 0x0e,
 127     CSR_JRX  = 0x0f,
 128     CSR_BP0  = 0x10,
 129     CSR_BP1  = 0x11,
 130     CSR_BP2  = 0x12,
 131     CSR_BP3  = 0x13,
 132     CSR_WP0  = 0x18,
 133     CSR_WP1  = 0x19,
 134     CSR_WP2  = 0x1a,
 135     CSR_WP3  = 0x1b,
 136 };
 137
 138 enum {
 139     LM32_FEATURE_MULTIPLY     =  1,
 140     LM32_FEATURE_DIVIDE       =  2,
 141     LM32_FEATURE_SHIFT        =  4,
 142     LM32_FEATURE_SIGN_EXTEND  =  8,
 143     LM32_FEATURE_I_CACHE      = 16,
 144     LM32_FEATURE_D_CACHE      = 32,
 145     LM32_FEATURE_CYCLE_COUNT  = 64,
 146 };
 147
 148 enum {
 149     LM32_FLAG_IGNORE_MSB = 1,
 150 };
 151
 152 struct CPULM32State {
 153     /* general registers */
 154     uint32_t regs[32];
 155
 156     /* special registers */
 157     uint32_t pc;        /* program counter */
 158     uint32_t ie;        /* interrupt enable */
 159     uint32_t icc;       /* instruction cache control */
 160     uint32_t dcc;       /* data cache control */
 161     uint32_t cc;        /* cycle counter */
 162     uint32_t cfg;       /* configuration */
 163
 164     /* debug registers */
 165     uint32_t dc;        /* debug control */
 166     uint32_t bp[4];     /* breakpoints */
 167     uint32_t wp[4];     /* watchpoints */
 168
 169     struct CPUBreakpoint *cpu_breakpoint[4];
 170     struct CPUWatchpoint *cpu_watchpoint[4];
 171
 172     CPU_COMMON
 173
 174     /* Fields from here on are preserved across CPU reset. */
 175     uint32_t eba;       /* exception base address */
 176     uint32_t deba;      /* debug exception base address */
 177
 178     /* interrupt controller handle for callbacks */
 179     DeviceState *pic_state;
 180     /* JTAG UART handle for callbacks */
 181     DeviceState *juart_state;
 182
 183     /* processor core features */
 184     uint32_t flags;
 185
 186 };
 187
 188 typedef enum {
 189     LM32_WP_DISABLED = 0,
 190     LM32_WP_READ,
 191     LM32_WP_WRITE,
 192     LM32_WP_READ_WRITE,
 193 } lm32_wp_t;
 194
 195 static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx)
 196 {
 197     assert(idx < 4);
 198     return (dc >> (idx+1)*2) & 0x3;
 199 }
 200
 201 #include "cpu-qom.h"
 202
 203 LM32CPU *cpu_lm32_init(const char *cpu_model);
 204 int cpu_lm32_exec(CPULM32State *s);
 205 /* you can call this signal handler from your SIGBUS and SIGSEGV
 206    signal handlers to inform the virtual CPU of exceptions. non zero
 207    is returned if the signal was handled by the virtual CPU.  */
 208 int cpu_lm32_signal_handler(int host_signum, void *pinfo,
 209                           void *puc);
 210 void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 211 void lm32_translate_init(void);
 212 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);
 213 void QEMU_NORETURN raise_exception(CPULM32State *env, int index);
 214 void lm32_debug_excp_handler(CPULM32State *env);
 215 void lm32_breakpoint_insert(CPULM32State *env, int index, target_ulong address);
 216 void lm32_breakpoint_remove(CPULM32State *env, int index);
 217 void lm32_watchpoint_insert(CPULM32State *env, int index, target_ulong address,
 218         lm32_wp_t wp_type);
 219 void lm32_watchpoint_remove(CPULM32State *env, int index);
 220 bool lm32_cpu_do_semihosting(CPUState *cs);
 221
 222 static inline CPULM32State *cpu_init(const char *cpu_model)
 223 {
 224     LM32CPU *cpu = cpu_lm32_init(cpu_model);
 225     if (cpu == NULL) {
 226         return NULL;
 227     }
 228     return &cpu->env;
 229 }
 230
 231 #define cpu_list lm32_cpu_list
 232 #define cpu_exec cpu_lm32_exec
 233 #define cpu_gen_code cpu_lm32_gen_code
 234 #define cpu_signal_handler cpu_lm32_signal_handler
 235
 236 int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 237                               int mmu_idx);
 238
 239 #include "exec/cpu-all.h"
 240
 241 static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
 242                                         target_ulong *cs_base, int *flags)
 243 {
 244     *pc = env->pc;
 245     *cs_base = 0;
 246     *flags = 0;
 247 }
 248
 249 #include "exec/exec-all.h"
 250
 251 #endif