target/arm: Restore SPSEL to correct CONTROL register on exception return
[qemu/kevin.git] / include / hw / unicore32 / puv3.h
blob5a4839f8df728c20c5de4bf65acbb4e02a2d5134
1 /*
2 * Misc PKUnity SoC declarations
4 * Copyright (C) 2010-2012 Guan Xuetao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or any later version.
9 * See the COPYING file in the top-level directory.
12 #ifndef QEMU_HW_PUV3_H
13 #define QEMU_HW_PUV3_H
15 #define PUV3_REGS_OFFSET (0x1000) /* 4K is reasonable */
17 /* PKUnity System bus (AHB): 0xc0000000 - 0xedffffff (640MB) */
18 #define PUV3_DMA_BASE (0xc0200000) /* AHB-4 */
20 /* PKUnity Peripheral bus (APB): 0xee000000 - 0xefffffff (128MB) */
21 #define PUV3_GPIO_BASE (0xee500000) /* APB-5 */
22 #define PUV3_INTC_BASE (0xee600000) /* APB-6 */
23 #define PUV3_OST_BASE (0xee800000) /* APB-8 */
24 #define PUV3_PM_BASE (0xeea00000) /* APB-10 */
25 #define PUV3_PS2_BASE (0xeeb00000) /* APB-11 */
27 /* Hardware interrupts */
28 #define PUV3_IRQS_NR (32)
30 #define PUV3_IRQS_GPIOLOW0 (0)
31 #define PUV3_IRQS_GPIOLOW1 (1)
32 #define PUV3_IRQS_GPIOLOW2 (2)
33 #define PUV3_IRQS_GPIOLOW3 (3)
34 #define PUV3_IRQS_GPIOLOW4 (4)
35 #define PUV3_IRQS_GPIOLOW5 (5)
36 #define PUV3_IRQS_GPIOLOW6 (6)
37 #define PUV3_IRQS_GPIOLOW7 (7)
38 #define PUV3_IRQS_GPIOHIGH (8)
39 #define PUV3_IRQS_PS2_KBD (22)
40 #define PUV3_IRQS_PS2_AUX (23)
41 #define PUV3_IRQS_OST0 (26)
43 /* All puv3_*.c use DPRINTF for debug. */
44 #ifdef DEBUG_PUV3
45 #define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
46 #else
47 #define DPRINTF(fmt, ...) do {} while (0)
48 #endif
50 #endif /* QEMU_HW_PUV3_H */