hw/arm/mps2.c

   1 /*
   2  * ARM V2M MPS2 board emulation.
   3  *
   4  * Copyright (c) 2017 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 or
   9  *  (at your option) any later version.
  10  */
  11
  12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
  13  * FPGA but is otherwise the same as the 2). Since the CPU itself
  14  * and most of the devices are in the FPGA, the details of the board
  15  * as seen by the guest depend significantly on the FPGA image.
  16  * We model the following FPGA images:
  17  *  "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
  18  *  "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
  19  *  "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500
  20  *  "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
  21  *
  22  * Links to the TRM for the board itself and to the various Application
  23  * Notes which document the FPGA images can be found here:
  24  *   https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "qemu/units.h"
  29 #include "qemu/cutils.h"
  30 #include "qapi/error.h"
  31 #include "qemu/error-report.h"
  32 #include "hw/arm/boot.h"
  33 #include "hw/arm/armv7m.h"
  34 #include "hw/or-irq.h"
  35 #include "hw/boards.h"
  36 #include "exec/address-spaces.h"
  37 #include "sysemu/sysemu.h"
  38 #include "hw/qdev-properties.h"
  39 #include "hw/misc/unimp.h"
  40 #include "hw/char/cmsdk-apb-uart.h"
  41 #include "hw/timer/cmsdk-apb-timer.h"
  42 #include "hw/timer/cmsdk-apb-dualtimer.h"
  43 #include "hw/misc/mps2-scc.h"
  44 #include "hw/misc/mps2-fpgaio.h"
  45 #include "hw/ssi/pl022.h"
  46 #include "hw/i2c/arm_sbcon_i2c.h"
  47 #include "hw/net/lan9118.h"
  48 #include "net/net.h"
  49 #include "hw/watchdog/cmsdk-apb-watchdog.h"
  50 #include "hw/qdev-clock.h"
  51 #include "qapi/qmp/qlist.h"
  52 #include "qom/object.h"
  53
  54 typedef enum MPS2FPGAType {
  55     FPGA_AN385,
  56     FPGA_AN386,
  57     FPGA_AN500,
  58     FPGA_AN511,
  59 } MPS2FPGAType;
  60
  61 struct MPS2MachineClass {
  62     MachineClass parent;
  63     MPS2FPGAType fpga_type;
  64     uint32_t scc_id;
  65     bool has_block_ram;
  66     hwaddr ethernet_base;
  67     hwaddr psram_base;
  68 };
  69
  70 struct MPS2MachineState {
  71     MachineState parent;
  72
  73     ARMv7MState armv7m;
  74     MemoryRegion ssram1;
  75     MemoryRegion ssram1_m;
  76     MemoryRegion ssram23;
  77     MemoryRegion ssram23_m;
  78     MemoryRegion blockram;
  79     MemoryRegion blockram_m1;
  80     MemoryRegion blockram_m2;
  81     MemoryRegion blockram_m3;
  82     MemoryRegion sram;
  83     /* FPGA APB subsystem */
  84     MPS2SCC scc;
  85     MPS2FPGAIO fpgaio;
  86     /* CMSDK APB subsystem */
  87     CMSDKAPBDualTimer dualtimer;
  88     CMSDKAPBWatchdog watchdog;
  89     CMSDKAPBTimer timer[2];
  90     Clock *sysclk;
  91     Clock *refclk;
  92 };
  93
  94 #define TYPE_MPS2_MACHINE "mps2"
  95 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
  96 #define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386")
  97 #define TYPE_MPS2_AN500_MACHINE MACHINE_TYPE_NAME("mps2-an500")
  98 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
  99
 100 OBJECT_DECLARE_TYPE(MPS2MachineState, MPS2MachineClass, MPS2_MACHINE)
 101
 102 /* Main SYSCLK frequency in Hz */
 103 #define SYSCLK_FRQ 25000000
 104
 105 /*
 106  * The Application Notes don't say anything about how the
 107  * systick reference clock is configured. (Quite possibly
 108  * they don't have one at all.) This 1MHz clock matches the
 109  * pre-existing behaviour that used to be hardcoded in the
 110  * armv7m_systick implementation.
 111  */
 112 #define REFCLK_FRQ (1 * 1000 * 1000)
 113
 114 /* Initialize the auxiliary RAM region @mr and map it into
 115  * the memory map at @base.
 116  */
 117 static void make_ram(MemoryRegion *mr, const char *name,
 118                      hwaddr base, hwaddr size)
 119 {
 120     memory_region_init_ram(mr, NULL, name, size, &error_fatal);
 121     memory_region_add_subregion(get_system_memory(), base, mr);
 122 }
 123
 124 /* Create an alias of an entire original MemoryRegion @orig
 125  * located at @base in the memory map.
 126  */
 127 static void make_ram_alias(MemoryRegion *mr, const char *name,
 128                            MemoryRegion *orig, hwaddr base)
 129 {
 130     memory_region_init_alias(mr, NULL, name, orig, 0,
 131                              memory_region_size(orig));
 132     memory_region_add_subregion(get_system_memory(), base, mr);
 133 }
 134
 135 static void mps2_common_init(MachineState *machine)
 136 {
 137     MPS2MachineState *mms = MPS2_MACHINE(machine);
 138     MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
 139     MemoryRegion *system_memory = get_system_memory();
 140     MachineClass *mc = MACHINE_GET_CLASS(machine);
 141     DeviceState *armv7m, *sccdev;
 142     QList *oscclk;
 143     int i;
 144
 145     if (machine->ram_size != mc->default_ram_size) {
 146         char *sz = size_to_str(mc->default_ram_size);
 147         error_report("Invalid RAM size, should be %s", sz);
 148         g_free(sz);
 149         exit(EXIT_FAILURE);
 150     }
 151
 152     /* This clock doesn't need migration because it is fixed-frequency */
 153     mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
 154     clock_set_hz(mms->sysclk, SYSCLK_FRQ);
 155
 156     mms->refclk = clock_new(OBJECT(machine), "REFCLK");
 157     clock_set_hz(mms->refclk, REFCLK_FRQ);
 158
 159     /* The FPGA images have an odd combination of different RAMs,
 160      * because in hardware they are different implementations and
 161      * connected to different buses, giving varying performance/size
 162      * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
 163      * call the 16MB our "system memory", as it's the largest lump.
 164      *
 165      * AN385/AN386/AN511:
 166      *  0x21000000 .. 0x21ffffff : PSRAM (16MB)
 167      * AN385/AN386/AN500:
 168      *  0x00000000 .. 0x003fffff : ZBT SSRAM1
 169      *  0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
 170      *  0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
 171      *  0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
 172      * AN385/AN386 only:
 173      *  0x01000000 .. 0x01003fff : block RAM (16K)
 174      *  0x01004000 .. 0x01007fff : mirror of above
 175      *  0x01008000 .. 0x0100bfff : mirror of above
 176      *  0x0100c000 .. 0x0100ffff : mirror of above
 177      * AN511 only:
 178      *  0x00000000 .. 0x0003ffff : FPGA block RAM
 179      *  0x00400000 .. 0x007fffff : ZBT SSRAM1
 180      *  0x20000000 .. 0x2001ffff : SRAM
 181      *  0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
 182      * AN500 only:
 183      *  0x60000000 .. 0x60ffffff : PSRAM (16MB)
 184      *
 185      * The AN385/AN386 has a feature where the lowest 16K can be mapped
 186      * either to the bottom of the ZBT SSRAM1 or to the block RAM.
 187      * This is of no use for QEMU so we don't implement it (as if
 188      * zbt_boot_ctrl is always zero).
 189      */
 190     memory_region_add_subregion(system_memory, mmc->psram_base, machine->ram);
 191
 192     if (mmc->has_block_ram) {
 193         make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000);
 194         make_ram_alias(&mms->blockram_m1, "mps.blockram_m1",
 195                        &mms->blockram, 0x01004000);
 196         make_ram_alias(&mms->blockram_m2, "mps.blockram_m2",
 197                        &mms->blockram, 0x01008000);
 198         make_ram_alias(&mms->blockram_m3, "mps.blockram_m3",
 199                        &mms->blockram, 0x0100c000);
 200     }
 201
 202     switch (mmc->fpga_type) {
 203     case FPGA_AN385:
 204     case FPGA_AN386:
 205     case FPGA_AN500:
 206         make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
 207         make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
 208         make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
 209         make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
 210                        &mms->ssram23, 0x20400000);
 211         break;
 212     case FPGA_AN511:
 213         make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000);
 214         make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000);
 215         make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000);
 216         make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000);
 217         break;
 218     default:
 219         g_assert_not_reached();
 220     }
 221
 222     object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M);
 223     armv7m = DEVICE(&mms->armv7m);
 224     switch (mmc->fpga_type) {
 225     case FPGA_AN385:
 226     case FPGA_AN386:
 227     case FPGA_AN500:
 228         qdev_prop_set_uint32(armv7m, "num-irq", 32);
 229         break;
 230     case FPGA_AN511:
 231         qdev_prop_set_uint32(armv7m, "num-irq", 64);
 232         break;
 233     default:
 234         g_assert_not_reached();
 235     }
 236     qdev_connect_clock_in(armv7m, "cpuclk", mms->sysclk);
 237     qdev_connect_clock_in(armv7m, "refclk", mms->refclk);
 238     qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
 239     qdev_prop_set_bit(armv7m, "enable-bitband", true);
 240     object_property_set_link(OBJECT(&mms->armv7m), "memory",
 241                              OBJECT(system_memory), &error_abort);
 242     sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal);
 243
 244     create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
 245     create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
 246     create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);
 247     create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000);
 248     create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000);
 249     create_unimplemented_device("PSRAM", 0x21000000, 0x01000000);
 250     /* These three ranges all cover multiple devices; we may implement
 251      * some of them below (in which case the real device takes precedence
 252      * over the unimplemented-region mapping).
 253      */
 254     create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
 255                                 0x40000000, 0x00010000);
 256     create_unimplemented_device("CMSDK AHB peripheral region @0x40010000",
 257                                 0x40010000, 0x00010000);
 258     create_unimplemented_device("Extra peripheral region @0x40020000",
 259                                 0x40020000, 0x00010000);
 260
 261     create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
 262     create_unimplemented_device("VGA", 0x41000000, 0x0200000);
 263
 264     switch (mmc->fpga_type) {
 265     case FPGA_AN385:
 266     case FPGA_AN386:
 267     case FPGA_AN500:
 268     {
 269         /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
 270          * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
 271          */
 272         Object *orgate;
 273         DeviceState *orgate_dev;
 274
 275         orgate = object_new(TYPE_OR_IRQ);
 276         object_property_set_int(orgate, "num-lines", 6, &error_fatal);
 277         qdev_realize(DEVICE(orgate), NULL, &error_fatal);
 278         orgate_dev = DEVICE(orgate);
 279         qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
 280
 281         for (i = 0; i < 5; i++) {
 282             DeviceState *dev;
 283             SysBusDevice *s;
 284
 285             static const hwaddr uartbase[] = {0x40004000, 0x40005000,
 286                                               0x40006000, 0x40007000,
 287                                               0x40009000};
 288             /* RX irq number; TX irq is always one greater */
 289             static const int uartirq[] = {0, 2, 4, 18, 20};
 290             qemu_irq txovrint = NULL, rxovrint = NULL;
 291
 292             if (i < 3) {
 293                 txovrint = qdev_get_gpio_in(orgate_dev, i * 2);
 294                 rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
 295             }
 296
 297             dev = qdev_new(TYPE_CMSDK_APB_UART);
 298             s = SYS_BUS_DEVICE(dev);
 299             qdev_prop_set_chr(dev, "chardev", serial_hd(i));
 300             qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ);
 301             sysbus_realize_and_unref(s, &error_fatal);
 302             sysbus_mmio_map(s, 0, uartbase[i]);
 303             sysbus_connect_irq(s, 0, qdev_get_gpio_in(armv7m, uartirq[i] + 1));
 304             sysbus_connect_irq(s, 1, qdev_get_gpio_in(armv7m, uartirq[i]));
 305             sysbus_connect_irq(s, 2, txovrint);
 306             sysbus_connect_irq(s, 3, rxovrint);
 307         }
 308         break;
 309     }
 310     case FPGA_AN511:
 311     {
 312         /* The overflow IRQs for all UARTs are ORed together.
 313          * Tx and Rx IRQs for each UART are ORed together.
 314          */
 315         Object *orgate;
 316         DeviceState *orgate_dev;
 317
 318         orgate = object_new(TYPE_OR_IRQ);
 319         object_property_set_int(orgate, "num-lines", 10, &error_fatal);
 320         qdev_realize(DEVICE(orgate), NULL, &error_fatal);
 321         orgate_dev = DEVICE(orgate);
 322         qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
 323
 324         for (i = 0; i < 5; i++) {
 325             /* system irq numbers for the combined tx/rx for each UART */
 326             static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56};
 327             static const hwaddr uartbase[] = {0x40004000, 0x40005000,
 328                                               0x4002c000, 0x4002d000,
 329                                               0x4002e000};
 330             Object *txrx_orgate;
 331             DeviceState *txrx_orgate_dev, *dev;
 332             SysBusDevice *s;
 333
 334             txrx_orgate = object_new(TYPE_OR_IRQ);
 335             object_property_set_int(txrx_orgate, "num-lines", 2, &error_fatal);
 336             qdev_realize(DEVICE(txrx_orgate), NULL, &error_fatal);
 337             txrx_orgate_dev = DEVICE(txrx_orgate);
 338             qdev_connect_gpio_out(txrx_orgate_dev, 0,
 339                                   qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
 340
 341             dev = qdev_new(TYPE_CMSDK_APB_UART);
 342             s = SYS_BUS_DEVICE(dev);
 343             qdev_prop_set_chr(dev, "chardev", serial_hd(i));
 344             qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ);
 345             sysbus_realize_and_unref(s, &error_fatal);
 346             sysbus_mmio_map(s, 0, uartbase[i]);
 347             sysbus_connect_irq(s, 0, qdev_get_gpio_in(txrx_orgate_dev, 0));
 348             sysbus_connect_irq(s, 1, qdev_get_gpio_in(txrx_orgate_dev, 1));
 349             sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
 350             sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
 351         }
 352         break;
 353     }
 354     default:
 355         g_assert_not_reached();
 356     }
 357     for (i = 0; i < 4; i++) {
 358         static const hwaddr gpiobase[] = {0x40010000, 0x40011000,
 359                                           0x40012000, 0x40013000};
 360         create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000);
 361     }
 362
 363     /* CMSDK APB subsystem */
 364     for (i = 0; i < ARRAY_SIZE(mms->timer); i++) {
 365         g_autofree char *name = g_strdup_printf("timer%d", i);
 366         hwaddr base = 0x40000000 + i * 0x1000;
 367         int irqno = 8 + i;
 368         SysBusDevice *sbd;
 369
 370         object_initialize_child(OBJECT(mms), name, &mms->timer[i],
 371                                 TYPE_CMSDK_APB_TIMER);
 372         sbd = SYS_BUS_DEVICE(&mms->timer[i]);
 373         qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk);
 374         sysbus_realize_and_unref(sbd, &error_fatal);
 375         sysbus_mmio_map(sbd, 0, base);
 376         sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno));
 377     }
 378
 379     object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
 380                             TYPE_CMSDK_APB_DUALTIMER);
 381     qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk);
 382     sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
 383     sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
 384                        qdev_get_gpio_in(armv7m, 10));
 385     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
 386     object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
 387                             TYPE_CMSDK_APB_WATCHDOG);
 388     qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk);
 389     sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
 390     sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
 391                        qdev_get_gpio_in_named(armv7m, "NMI", 0));
 392     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0x40008000);
 393
 394     /* FPGA APB subsystem */
 395     object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
 396     sccdev = DEVICE(&mms->scc);
 397     qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
 398     qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
 399     qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
 400     /* All these FPGA images have the same OSCCLK configuration */
 401     oscclk = qlist_new();
 402     qlist_append_int(oscclk, 50000000);
 403     qlist_append_int(oscclk, 24576000);
 404     qlist_append_int(oscclk, 25000000);
 405     qdev_prop_set_array(sccdev, "oscclk", oscclk);
 406
 407     sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
 408     sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
 409     object_initialize_child(OBJECT(mms), "fpgaio",
 410                             &mms->fpgaio, TYPE_MPS2_FPGAIO);
 411     qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000);
 412     sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
 413     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000);
 414     sysbus_create_simple(TYPE_PL022, 0x40025000,        /* External ADC */
 415                          qdev_get_gpio_in(armv7m, 22));
 416     for (i = 0; i < 2; i++) {
 417         static const int spi_irqno[] = {11, 24};
 418         static const hwaddr spibase[] = {0x40020000,    /* APB */
 419                                          0x40021000,    /* LCD */
 420                                          0x40026000,    /* Shield0 */
 421                                          0x40027000};   /* Shield1 */
 422         DeviceState *orgate_dev;
 423         Object *orgate;
 424         int j;
 425
 426         orgate = object_new(TYPE_OR_IRQ);
 427         object_property_set_int(orgate, "num-lines", 2, &error_fatal);
 428         orgate_dev = DEVICE(orgate);
 429         qdev_realize(orgate_dev, NULL, &error_fatal);
 430         qdev_connect_gpio_out(orgate_dev, 0,
 431                               qdev_get_gpio_in(armv7m, spi_irqno[i]));
 432         for (j = 0; j < 2; j++) {
 433             sysbus_create_simple(TYPE_PL022, spibase[2 * i + j],
 434                                  qdev_get_gpio_in(orgate_dev, j));
 435         }
 436     }
 437     for (i = 0; i < 4; i++) {
 438         static const hwaddr i2cbase[] = {0x40022000,    /* Touch */
 439                                          0x40023000,    /* Audio */
 440                                          0x40029000,    /* Shield0 */
 441                                          0x4002a000};   /* Shield1 */
 442         DeviceState *dev;
 443
 444         dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL);
 445         if (i < 2) {
 446             /*
 447              * internal-only bus: mark it full to avoid user-created
 448              * i2c devices being plugged into it.
 449              */
 450             BusState *qbus = qdev_get_child_bus(dev, "i2c");
 451             qbus_mark_full(qbus);
 452         }
 453     }
 454     create_unimplemented_device("i2s", 0x40024000, 0x400);
 455
 456     /* In hardware this is a LAN9220; the LAN9118 is software compatible
 457      * except that it doesn't support the checksum-offload feature.
 458      */
 459     lan9118_init(mmc->ethernet_base,
 460                  qdev_get_gpio_in(armv7m,
 461                                   mmc->fpga_type == FPGA_AN511 ? 47 : 13));
 462
 463     armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
 464                        0, 0x400000);
 465 }
 466
 467 static void mps2_class_init(ObjectClass *oc, void *data)
 468 {
 469     MachineClass *mc = MACHINE_CLASS(oc);
 470
 471     mc->init = mps2_common_init;
 472     mc->max_cpus = 1;
 473     mc->default_ram_size = 16 * MiB;
 474     mc->default_ram_id = "mps.ram";
 475 }
 476
 477 static void mps2_an385_class_init(ObjectClass *oc, void *data)
 478 {
 479     MachineClass *mc = MACHINE_CLASS(oc);
 480     MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
 481     static const char * const valid_cpu_types[] = {
 482         ARM_CPU_TYPE_NAME("cortex-m3"),
 483         NULL
 484     };
 485
 486     mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
 487     mmc->fpga_type = FPGA_AN385;
 488     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
 489     mc->valid_cpu_types = valid_cpu_types;
 490     mmc->scc_id = 0x41043850;
 491     mmc->psram_base = 0x21000000;
 492     mmc->ethernet_base = 0x40200000;
 493     mmc->has_block_ram = true;
 494 }
 495
 496 static void mps2_an386_class_init(ObjectClass *oc, void *data)
 497 {
 498     MachineClass *mc = MACHINE_CLASS(oc);
 499     MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
 500     static const char * const valid_cpu_types[] = {
 501         ARM_CPU_TYPE_NAME("cortex-m4"),
 502         NULL
 503     };
 504
 505     mc->desc = "ARM MPS2 with AN386 FPGA image for Cortex-M4";
 506     mmc->fpga_type = FPGA_AN386;
 507     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
 508     mc->valid_cpu_types = valid_cpu_types;
 509     mmc->scc_id = 0x41043860;
 510     mmc->psram_base = 0x21000000;
 511     mmc->ethernet_base = 0x40200000;
 512     mmc->has_block_ram = true;
 513 }
 514
 515 static void mps2_an500_class_init(ObjectClass *oc, void *data)
 516 {
 517     MachineClass *mc = MACHINE_CLASS(oc);
 518     MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
 519     static const char * const valid_cpu_types[] = {
 520         ARM_CPU_TYPE_NAME("cortex-m7"),
 521         NULL
 522     };
 523
 524     mc->desc = "ARM MPS2 with AN500 FPGA image for Cortex-M7";
 525     mmc->fpga_type = FPGA_AN500;
 526     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m7");
 527     mc->valid_cpu_types = valid_cpu_types;
 528     mmc->scc_id = 0x41045000;
 529     mmc->psram_base = 0x60000000;
 530     mmc->ethernet_base = 0xa0000000;
 531     mmc->has_block_ram = false;
 532 }
 533
 534 static void mps2_an511_class_init(ObjectClass *oc, void *data)
 535 {
 536     MachineClass *mc = MACHINE_CLASS(oc);
 537     MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
 538     static const char * const valid_cpu_types[] = {
 539         ARM_CPU_TYPE_NAME("cortex-m3"),
 540         NULL
 541     };
 542
 543     mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
 544     mmc->fpga_type = FPGA_AN511;
 545     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
 546     mc->valid_cpu_types = valid_cpu_types;
 547     mmc->scc_id = 0x41045110;
 548     mmc->psram_base = 0x21000000;
 549     mmc->ethernet_base = 0x40200000;
 550     mmc->has_block_ram = false;
 551 }
 552
 553 static const TypeInfo mps2_info = {
 554     .name = TYPE_MPS2_MACHINE,
 555     .parent = TYPE_MACHINE,
 556     .abstract = true,
 557     .instance_size = sizeof(MPS2MachineState),
 558     .class_size = sizeof(MPS2MachineClass),
 559     .class_init = mps2_class_init,
 560 };
 561
 562 static const TypeInfo mps2_an385_info = {
 563     .name = TYPE_MPS2_AN385_MACHINE,
 564     .parent = TYPE_MPS2_MACHINE,
 565     .class_init = mps2_an385_class_init,
 566 };
 567
 568 static const TypeInfo mps2_an386_info = {
 569     .name = TYPE_MPS2_AN386_MACHINE,
 570     .parent = TYPE_MPS2_MACHINE,
 571     .class_init = mps2_an386_class_init,
 572 };
 573
 574 static const TypeInfo mps2_an500_info = {
 575     .name = TYPE_MPS2_AN500_MACHINE,
 576     .parent = TYPE_MPS2_MACHINE,
 577     .class_init = mps2_an500_class_init,
 578 };
 579
 580 static const TypeInfo mps2_an511_info = {
 581     .name = TYPE_MPS2_AN511_MACHINE,
 582     .parent = TYPE_MPS2_MACHINE,
 583     .class_init = mps2_an511_class_init,
 584 };
 585
 586 static void mps2_machine_init(void)
 587 {
 588     type_register_static(&mps2_info);
 589     type_register_static(&mps2_an385_info);
 590     type_register_static(&mps2_an386_info);
 591     type_register_static(&mps2_an500_info);
 592     type_register_static(&mps2_an511_info);
 593 }
 594
 595 type_init(mps2_machine_init);