?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
vmxnet3: iPXE compatibility fixes
[qemu/kevin.git] / target-ppc / translate_init.c
blob781170fb05f5044c4d0744607ef265b303c2853d
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include <sysemu/kvm.h>
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30
31 //#define PPC_DUMP_CPU
32 //#define PPC_DEBUG_SPR
33 //#define PPC_DUMP_SPR_ACCESSES
34
35 /* For user-mode emulation, we don't emulate any IRQ controller */
36 #if defined(CONFIG_USER_ONLY)
37 #define PPC_IRQ_INIT_FN(name) \
38 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
39 { \
40 }
41 #else
42 #define PPC_IRQ_INIT_FN(name) \
43 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
44 #endif
45
46 PPC_IRQ_INIT_FN(40x);
47 PPC_IRQ_INIT_FN(6xx);
48 PPC_IRQ_INIT_FN(970);
49 PPC_IRQ_INIT_FN(POWER7);
50 PPC_IRQ_INIT_FN(e500);
51
52 /* Generic callbacks:
53 * do nothing but store/retrieve spr value
54 */
55 static void spr_load_dump_spr(int sprn)
56 {
57 #ifdef PPC_DUMP_SPR_ACCESSES
58 TCGv_i32 t0 = tcg_const_i32(sprn);
59 gen_helper_load_dump_spr(cpu_env, t0);
60 tcg_temp_free_i32(t0);
61 #endif
62 }
63
64 static void spr_read_generic (void *opaque, int gprn, int sprn)
65 {
66 gen_load_spr(cpu_gpr[gprn], sprn);
67 spr_load_dump_spr(sprn);
68 }
69
70 static void spr_store_dump_spr(int sprn)
71 {
72 #ifdef PPC_DUMP_SPR_ACCESSES
73 TCGv_i32 t0 = tcg_const_i32(sprn);
74 gen_helper_store_dump_spr(cpu_env, t0);
75 tcg_temp_free_i32(t0);
76 #endif
77 }
78
79 static void spr_write_generic (void *opaque, int sprn, int gprn)
80 {
81 gen_store_spr(sprn, cpu_gpr[gprn]);
82 spr_store_dump_spr(sprn);
83 }
84
85 #if !defined(CONFIG_USER_ONLY)
86 static void spr_write_generic32(void *opaque, int sprn, int gprn)
87 {
88 #ifdef TARGET_PPC64
89 TCGv t0 = tcg_temp_new();
90 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
91 gen_store_spr(sprn, t0);
92 tcg_temp_free(t0);
93 spr_store_dump_spr(sprn);
94 #else
95 spr_write_generic(opaque, sprn, gprn);
96 #endif
97 }
98
99 static void spr_write_clear (void *opaque, int sprn, int gprn)
100 {
101 TCGv t0 = tcg_temp_new();
102 TCGv t1 = tcg_temp_new();
103 gen_load_spr(t0, sprn);
104 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
105 tcg_gen_and_tl(t0, t0, t1);
106 gen_store_spr(sprn, t0);
107 tcg_temp_free(t0);
108 tcg_temp_free(t1);
109 }
110 #endif
111
112 /* SPR common to all PowerPC */
113 /* XER */
114 static void spr_read_xer (void *opaque, int gprn, int sprn)
115 {
116 gen_read_xer(cpu_gpr[gprn]);
117 }
118
119 static void spr_write_xer (void *opaque, int sprn, int gprn)
120 {
121 gen_write_xer(cpu_gpr[gprn]);
122 }
123
124 /* LR */
125 static void spr_read_lr (void *opaque, int gprn, int sprn)
126 {
127 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
128 }
129
130 static void spr_write_lr (void *opaque, int sprn, int gprn)
131 {
132 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
133 }
134
135 /* CFAR */
136 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
137 static void spr_read_cfar (void *opaque, int gprn, int sprn)
138 {
139 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
140 }
141
142 static void spr_write_cfar (void *opaque, int sprn, int gprn)
143 {
144 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
145 }
146 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
147
148 /* CTR */
149 static void spr_read_ctr (void *opaque, int gprn, int sprn)
150 {
151 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
152 }
153
154 static void spr_write_ctr (void *opaque, int sprn, int gprn)
155 {
156 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
157 }
158
159 /* User read access to SPR */
160 /* USPRx */
161 /* UMMCRx */
162 /* UPMCx */
163 /* USIA */
164 /* UDECR */
165 static void spr_read_ureg (void *opaque, int gprn, int sprn)
166 {
167 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
168 }
169
170 /* SPR common to all non-embedded PowerPC */
171 /* DECR */
172 #if !defined(CONFIG_USER_ONLY)
173 static void spr_read_decr (void *opaque, int gprn, int sprn)
174 {
175 if (use_icount) {
176 gen_io_start();
177 }
178 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
179 if (use_icount) {
180 gen_io_end();
181 gen_stop_exception(opaque);
182 }
183 }
184
185 static void spr_write_decr (void *opaque, int sprn, int gprn)
186 {
187 if (use_icount) {
188 gen_io_start();
189 }
190 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
191 if (use_icount) {
192 gen_io_end();
193 gen_stop_exception(opaque);
194 }
195 }
196 #endif
197
198 /* SPR common to all non-embedded PowerPC, except 601 */
199 /* Time base */
200 static void spr_read_tbl (void *opaque, int gprn, int sprn)
201 {
202 if (use_icount) {
203 gen_io_start();
204 }
205 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
206 if (use_icount) {
207 gen_io_end();
208 gen_stop_exception(opaque);
209 }
210 }
211
212 static void spr_read_tbu (void *opaque, int gprn, int sprn)
213 {
214 if (use_icount) {
215 gen_io_start();
216 }
217 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
218 if (use_icount) {
219 gen_io_end();
220 gen_stop_exception(opaque);
221 }
222 }
223
224 __attribute__ (( unused ))
225 static void spr_read_atbl (void *opaque, int gprn, int sprn)
226 {
227 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
228 }
229
230 __attribute__ (( unused ))
231 static void spr_read_atbu (void *opaque, int gprn, int sprn)
232 {
233 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
234 }
235
236 #if !defined(CONFIG_USER_ONLY)
237 static void spr_write_tbl (void *opaque, int sprn, int gprn)
238 {
239 if (use_icount) {
240 gen_io_start();
241 }
242 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
243 if (use_icount) {
244 gen_io_end();
245 gen_stop_exception(opaque);
246 }
247 }
248
249 static void spr_write_tbu (void *opaque, int sprn, int gprn)
250 {
251 if (use_icount) {
252 gen_io_start();
253 }
254 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
255 if (use_icount) {
256 gen_io_end();
257 gen_stop_exception(opaque);
258 }
259 }
260
261 __attribute__ (( unused ))
262 static void spr_write_atbl (void *opaque, int sprn, int gprn)
263 {
264 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
265 }
266
267 __attribute__ (( unused ))
268 static void spr_write_atbu (void *opaque, int sprn, int gprn)
269 {
270 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
271 }
272
273 #if defined(TARGET_PPC64)
274 __attribute__ (( unused ))
275 static void spr_read_purr (void *opaque, int gprn, int sprn)
276 {
277 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
278 }
279 #endif
280 #endif
281
282 #if !defined(CONFIG_USER_ONLY)
283 /* IBAT0U...IBAT0U */
284 /* IBAT0L...IBAT7L */
285 static void spr_read_ibat (void *opaque, int gprn, int sprn)
286 {
287 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
288 }
289
290 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
291 {
292 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
293 }
294
295 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
296 {
297 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
298 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
299 tcg_temp_free_i32(t0);
300 }
301
302 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
303 {
304 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
305 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
306 tcg_temp_free_i32(t0);
307 }
308
309 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
310 {
311 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
312 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
313 tcg_temp_free_i32(t0);
314 }
315
316 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
317 {
318 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
319 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
320 tcg_temp_free_i32(t0);
321 }
322
323 /* DBAT0U...DBAT7U */
324 /* DBAT0L...DBAT7L */
325 static void spr_read_dbat (void *opaque, int gprn, int sprn)
326 {
327 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
328 }
329
330 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
331 {
332 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
333 }
334
335 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
336 {
337 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
338 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
339 tcg_temp_free_i32(t0);
340 }
341
342 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
343 {
344 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
345 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
346 tcg_temp_free_i32(t0);
347 }
348
349 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
350 {
351 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
352 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
353 tcg_temp_free_i32(t0);
354 }
355
356 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
357 {
358 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
359 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
360 tcg_temp_free_i32(t0);
361 }
362
363 /* SDR1 */
364 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
365 {
366 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
367 }
368
369 /* 64 bits PowerPC specific SPRs */
370 #if defined(TARGET_PPC64)
371 static void spr_read_hior (void *opaque, int gprn, int sprn)
372 {
373 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
374 }
375
376 static void spr_write_hior (void *opaque, int sprn, int gprn)
377 {
378 TCGv t0 = tcg_temp_new();
379 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
380 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
381 tcg_temp_free(t0);
382 }
383 #endif
384 #endif
385
386 /* PowerPC 601 specific registers */
387 /* RTC */
388 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
389 {
390 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
391 }
392
393 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
394 {
395 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
396 }
397
398 #if !defined(CONFIG_USER_ONLY)
399 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
400 {
401 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
402 }
403
404 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
405 {
406 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
407 }
408
409 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
410 {
411 DisasContext *ctx = opaque;
412
413 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
414 /* Must stop the translation as endianness may have changed */
415 gen_stop_exception(ctx);
416 }
417 #endif
418
419 /* Unified bats */
420 #if !defined(CONFIG_USER_ONLY)
421 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
422 {
423 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
424 }
425
426 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
427 {
428 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
429 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
430 tcg_temp_free_i32(t0);
431 }
432
433 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
434 {
435 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
436 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
437 tcg_temp_free_i32(t0);
438 }
439 #endif
440
441 /* PowerPC 40x specific registers */
442 #if !defined(CONFIG_USER_ONLY)
443 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
444 {
445 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
446 }
447
448 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
449 {
450 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
451 }
452
453 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
454 {
455 DisasContext *ctx = opaque;
456
457 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
458 /* We must stop translation as we may have rebooted */
459 gen_stop_exception(ctx);
460 }
461
462 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
463 {
464 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
465 }
466
467 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
468 {
469 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
470 }
471
472 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
473 {
474 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
475 }
476 #endif
477
478 /* PowerPC 403 specific registers */
479 /* PBL1 / PBU1 / PBL2 / PBU2 */
480 #if !defined(CONFIG_USER_ONLY)
481 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
482 {
483 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
484 }
485
486 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
487 {
488 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
489 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
490 tcg_temp_free_i32(t0);
491 }
492
493 static void spr_write_pir (void *opaque, int sprn, int gprn)
494 {
495 TCGv t0 = tcg_temp_new();
496 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
497 gen_store_spr(SPR_PIR, t0);
498 tcg_temp_free(t0);
499 }
500 #endif
501
502 /* SPE specific registers */
503 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
504 {
505 TCGv_i32 t0 = tcg_temp_new_i32();
506 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
507 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
508 tcg_temp_free_i32(t0);
509 }
510
511 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
512 {
513 TCGv_i32 t0 = tcg_temp_new_i32();
514 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
515 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
516 tcg_temp_free_i32(t0);
517 }
518
519 #if !defined(CONFIG_USER_ONLY)
520 /* Callback used to write the exception vector base */
521 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
522 {
523 TCGv t0 = tcg_temp_new();
524 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
525 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
526 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
527 gen_store_spr(sprn, t0);
528 tcg_temp_free(t0);
529 }
530
531 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
532 {
533 DisasContext *ctx = opaque;
534 int sprn_offs;
535
536 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
537 sprn_offs = sprn - SPR_BOOKE_IVOR0;
538 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
539 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
540 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
541 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
542 } else {
543 printf("Trying to write an unknown exception vector %d %03x\n",
544 sprn, sprn);
545 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
546 return;
547 }
548
549 TCGv t0 = tcg_temp_new();
550 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
551 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
552 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
553 gen_store_spr(sprn, t0);
554 tcg_temp_free(t0);
555 }
556 #endif
557
558 static inline void vscr_init (CPUPPCState *env, uint32_t val)
559 {
560 env->vscr = val;
561 /* Altivec always uses round-to-nearest */
562 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
563 set_flush_to_zero(vscr_nj, &env->vec_status);
564 }
565
566 #ifdef CONFIG_USER_ONLY
567 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
568 oea_read, oea_write, one_reg_id, initial_value) \
569 _spr_register(env, num, name, uea_read, uea_write, initial_value)
570 #else
571 #if !defined(CONFIG_KVM)
572 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
573 oea_read, oea_write, one_reg_id, initial_value) \
574 _spr_register(env, num, name, uea_read, uea_write, \
575 oea_read, oea_write, initial_value)
576 #else
577 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
578 oea_read, oea_write, one_reg_id, initial_value) \
579 _spr_register(env, num, name, uea_read, uea_write, \
580 oea_read, oea_write, one_reg_id, initial_value)
581 #endif
582 #endif
583
584 #define spr_register(env, num, name, uea_read, uea_write, \
585 oea_read, oea_write, initial_value) \
586 spr_register_kvm(env, num, name, uea_read, uea_write, \
587 oea_read, oea_write, 0, initial_value)
588
589 static inline void _spr_register(CPUPPCState *env, int num,
590 const char *name,
591 void (*uea_read)(void *opaque, int gprn, int sprn),
592 void (*uea_write)(void *opaque, int sprn, int gprn),
593 #if !defined(CONFIG_USER_ONLY)
594
595 void (*oea_read)(void *opaque, int gprn, int sprn),
596 void (*oea_write)(void *opaque, int sprn, int gprn),
597 #endif
598 #if defined(CONFIG_KVM)
599 uint64_t one_reg_id,
600 #endif
601 target_ulong initial_value)
602 {
603 ppc_spr_t *spr;
604
605 spr = &env->spr_cb[num];
606 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
607 #if !defined(CONFIG_USER_ONLY)
608 spr->oea_read != NULL || spr->oea_write != NULL ||
609 #endif
610 spr->uea_read != NULL || spr->uea_write != NULL) {
611 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
612 exit(1);
613 }
614 #if defined(PPC_DEBUG_SPR)
615 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
616 name, initial_value);
617 #endif
618 spr->name = name;
619 spr->uea_read = uea_read;
620 spr->uea_write = uea_write;
621 #if !defined(CONFIG_USER_ONLY)
622 spr->oea_read = oea_read;
623 spr->oea_write = oea_write;
624 #endif
625 env->spr[num] = initial_value;
626 }
627
628 /* Generic PowerPC SPRs */
629 static void gen_spr_generic (CPUPPCState *env)
630 {
631 /* Integer processing */
632 spr_register(env, SPR_XER, "XER",
633 &spr_read_xer, &spr_write_xer,
634 &spr_read_xer, &spr_write_xer,
635 0x00000000);
636 /* Branch contol */
637 spr_register(env, SPR_LR, "LR",
638 &spr_read_lr, &spr_write_lr,
639 &spr_read_lr, &spr_write_lr,
640 0x00000000);
641 spr_register(env, SPR_CTR, "CTR",
642 &spr_read_ctr, &spr_write_ctr,
643 &spr_read_ctr, &spr_write_ctr,
644 0x00000000);
645 /* Interrupt processing */
646 spr_register(env, SPR_SRR0, "SRR0",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650 spr_register(env, SPR_SRR1, "SRR1",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_generic, &spr_write_generic,
653 0x00000000);
654 /* Processor control */
655 spr_register(env, SPR_SPRG0, "SPRG0",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_SPRG1, "SPRG1",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 spr_register(env, SPR_SPRG2, "SPRG2",
664 SPR_NOACCESS, SPR_NOACCESS,
665 &spr_read_generic, &spr_write_generic,
666 0x00000000);
667 spr_register(env, SPR_SPRG3, "SPRG3",
668 SPR_NOACCESS, SPR_NOACCESS,
669 &spr_read_generic, &spr_write_generic,
670 0x00000000);
671 }
672
673 /* SPR common to all non-embedded PowerPC, including 601 */
674 static void gen_spr_ne_601 (CPUPPCState *env)
675 {
676 /* Exception processing */
677 spr_register_kvm(env, SPR_DSISR, "DSISR",
678 SPR_NOACCESS, SPR_NOACCESS,
679 &spr_read_generic, &spr_write_generic,
680 KVM_REG_PPC_DSISR, 0x00000000);
681 spr_register_kvm(env, SPR_DAR, "DAR",
682 SPR_NOACCESS, SPR_NOACCESS,
683 &spr_read_generic, &spr_write_generic,
684 KVM_REG_PPC_DAR, 0x00000000);
685 /* Timer */
686 spr_register(env, SPR_DECR, "DECR",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_decr, &spr_write_decr,
689 0x00000000);
690 /* Memory management */
691 spr_register(env, SPR_SDR1, "SDR1",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_generic, &spr_write_sdr1,
694 0x00000000);
695 }
696
697 /* BATs 0-3 */
698 static void gen_low_BATs (CPUPPCState *env)
699 {
700 #if !defined(CONFIG_USER_ONLY)
701 spr_register(env, SPR_IBAT0U, "IBAT0U",
702 SPR_NOACCESS, SPR_NOACCESS,
703 &spr_read_ibat, &spr_write_ibatu,
704 0x00000000);
705 spr_register(env, SPR_IBAT0L, "IBAT0L",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_ibat, &spr_write_ibatl,
708 0x00000000);
709 spr_register(env, SPR_IBAT1U, "IBAT1U",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_ibat, &spr_write_ibatu,
712 0x00000000);
713 spr_register(env, SPR_IBAT1L, "IBAT1L",
714 SPR_NOACCESS, SPR_NOACCESS,
715 &spr_read_ibat, &spr_write_ibatl,
716 0x00000000);
717 spr_register(env, SPR_IBAT2U, "IBAT2U",
718 SPR_NOACCESS, SPR_NOACCESS,
719 &spr_read_ibat, &spr_write_ibatu,
720 0x00000000);
721 spr_register(env, SPR_IBAT2L, "IBAT2L",
722 SPR_NOACCESS, SPR_NOACCESS,
723 &spr_read_ibat, &spr_write_ibatl,
724 0x00000000);
725 spr_register(env, SPR_IBAT3U, "IBAT3U",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_ibat, &spr_write_ibatu,
728 0x00000000);
729 spr_register(env, SPR_IBAT3L, "IBAT3L",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_ibat, &spr_write_ibatl,
732 0x00000000);
733 spr_register(env, SPR_DBAT0U, "DBAT0U",
734 SPR_NOACCESS, SPR_NOACCESS,
735 &spr_read_dbat, &spr_write_dbatu,
736 0x00000000);
737 spr_register(env, SPR_DBAT0L, "DBAT0L",
738 SPR_NOACCESS, SPR_NOACCESS,
739 &spr_read_dbat, &spr_write_dbatl,
740 0x00000000);
741 spr_register(env, SPR_DBAT1U, "DBAT1U",
742 SPR_NOACCESS, SPR_NOACCESS,
743 &spr_read_dbat, &spr_write_dbatu,
744 0x00000000);
745 spr_register(env, SPR_DBAT1L, "DBAT1L",
746 SPR_NOACCESS, SPR_NOACCESS,
747 &spr_read_dbat, &spr_write_dbatl,
748 0x00000000);
749 spr_register(env, SPR_DBAT2U, "DBAT2U",
750 SPR_NOACCESS, SPR_NOACCESS,
751 &spr_read_dbat, &spr_write_dbatu,
752 0x00000000);
753 spr_register(env, SPR_DBAT2L, "DBAT2L",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_dbat, &spr_write_dbatl,
756 0x00000000);
757 spr_register(env, SPR_DBAT3U, "DBAT3U",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_dbat, &spr_write_dbatu,
760 0x00000000);
761 spr_register(env, SPR_DBAT3L, "DBAT3L",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_dbat, &spr_write_dbatl,
764 0x00000000);
765 env->nb_BATs += 4;
766 #endif
767 }
768
769 /* BATs 4-7 */
770 static void gen_high_BATs (CPUPPCState *env)
771 {
772 #if !defined(CONFIG_USER_ONLY)
773 spr_register(env, SPR_IBAT4U, "IBAT4U",
774 SPR_NOACCESS, SPR_NOACCESS,
775 &spr_read_ibat_h, &spr_write_ibatu_h,
776 0x00000000);
777 spr_register(env, SPR_IBAT4L, "IBAT4L",
778 SPR_NOACCESS, SPR_NOACCESS,
779 &spr_read_ibat_h, &spr_write_ibatl_h,
780 0x00000000);
781 spr_register(env, SPR_IBAT5U, "IBAT5U",
782 SPR_NOACCESS, SPR_NOACCESS,
783 &spr_read_ibat_h, &spr_write_ibatu_h,
784 0x00000000);
785 spr_register(env, SPR_IBAT5L, "IBAT5L",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_ibat_h, &spr_write_ibatl_h,
788 0x00000000);
789 spr_register(env, SPR_IBAT6U, "IBAT6U",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_ibat_h, &spr_write_ibatu_h,
792 0x00000000);
793 spr_register(env, SPR_IBAT6L, "IBAT6L",
794 SPR_NOACCESS, SPR_NOACCESS,
795 &spr_read_ibat_h, &spr_write_ibatl_h,
796 0x00000000);
797 spr_register(env, SPR_IBAT7U, "IBAT7U",
798 SPR_NOACCESS, SPR_NOACCESS,
799 &spr_read_ibat_h, &spr_write_ibatu_h,
800 0x00000000);
801 spr_register(env, SPR_IBAT7L, "IBAT7L",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_ibat_h, &spr_write_ibatl_h,
804 0x00000000);
805 spr_register(env, SPR_DBAT4U, "DBAT4U",
806 SPR_NOACCESS, SPR_NOACCESS,
807 &spr_read_dbat_h, &spr_write_dbatu_h,
808 0x00000000);
809 spr_register(env, SPR_DBAT4L, "DBAT4L",
810 SPR_NOACCESS, SPR_NOACCESS,
811 &spr_read_dbat_h, &spr_write_dbatl_h,
812 0x00000000);
813 spr_register(env, SPR_DBAT5U, "DBAT5U",
814 SPR_NOACCESS, SPR_NOACCESS,
815 &spr_read_dbat_h, &spr_write_dbatu_h,
816 0x00000000);
817 spr_register(env, SPR_DBAT5L, "DBAT5L",
818 SPR_NOACCESS, SPR_NOACCESS,
819 &spr_read_dbat_h, &spr_write_dbatl_h,
820 0x00000000);
821 spr_register(env, SPR_DBAT6U, "DBAT6U",
822 SPR_NOACCESS, SPR_NOACCESS,
823 &spr_read_dbat_h, &spr_write_dbatu_h,
824 0x00000000);
825 spr_register(env, SPR_DBAT6L, "DBAT6L",
826 SPR_NOACCESS, SPR_NOACCESS,
827 &spr_read_dbat_h, &spr_write_dbatl_h,
828 0x00000000);
829 spr_register(env, SPR_DBAT7U, "DBAT7U",
830 SPR_NOACCESS, SPR_NOACCESS,
831 &spr_read_dbat_h, &spr_write_dbatu_h,
832 0x00000000);
833 spr_register(env, SPR_DBAT7L, "DBAT7L",
834 SPR_NOACCESS, SPR_NOACCESS,
835 &spr_read_dbat_h, &spr_write_dbatl_h,
836 0x00000000);
837 env->nb_BATs += 4;
838 #endif
839 }
840
841 /* Generic PowerPC time base */
842 static void gen_tbl (CPUPPCState *env)
843 {
844 spr_register(env, SPR_VTBL, "TBL",
845 &spr_read_tbl, SPR_NOACCESS,
846 &spr_read_tbl, SPR_NOACCESS,
847 0x00000000);
848 spr_register(env, SPR_TBL, "TBL",
849 &spr_read_tbl, SPR_NOACCESS,
850 &spr_read_tbl, &spr_write_tbl,
851 0x00000000);
852 spr_register(env, SPR_VTBU, "TBU",
853 &spr_read_tbu, SPR_NOACCESS,
854 &spr_read_tbu, SPR_NOACCESS,
855 0x00000000);
856 spr_register(env, SPR_TBU, "TBU",
857 &spr_read_tbu, SPR_NOACCESS,
858 &spr_read_tbu, &spr_write_tbu,
859 0x00000000);
860 }
861
862 /* Softare table search registers */
863 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
864 {
865 #if !defined(CONFIG_USER_ONLY)
866 env->nb_tlb = nb_tlbs;
867 env->nb_ways = nb_ways;
868 env->id_tlbs = 1;
869 env->tlb_type = TLB_6XX;
870 spr_register(env, SPR_DMISS, "DMISS",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic, SPR_NOACCESS,
873 0x00000000);
874 spr_register(env, SPR_DCMP, "DCMP",
875 SPR_NOACCESS, SPR_NOACCESS,
876 &spr_read_generic, SPR_NOACCESS,
877 0x00000000);
878 spr_register(env, SPR_HASH1, "HASH1",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, SPR_NOACCESS,
881 0x00000000);
882 spr_register(env, SPR_HASH2, "HASH2",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, SPR_NOACCESS,
885 0x00000000);
886 spr_register(env, SPR_IMISS, "IMISS",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_generic, SPR_NOACCESS,
889 0x00000000);
890 spr_register(env, SPR_ICMP, "ICMP",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, SPR_NOACCESS,
893 0x00000000);
894 spr_register(env, SPR_RPA, "RPA",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_generic, &spr_write_generic,
897 0x00000000);
898 #endif
899 }
900
901 /* SPR common to MPC755 and G2 */
902 static void gen_spr_G2_755 (CPUPPCState *env)
903 {
904 /* SGPRs */
905 spr_register(env, SPR_SPRG4, "SPRG4",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_generic,
908 0x00000000);
909 spr_register(env, SPR_SPRG5, "SPRG5",
910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_generic, &spr_write_generic,
912 0x00000000);
913 spr_register(env, SPR_SPRG6, "SPRG6",
914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_generic, &spr_write_generic,
916 0x00000000);
917 spr_register(env, SPR_SPRG7, "SPRG7",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, &spr_write_generic,
920 0x00000000);
921 }
922
923 /* SPR common to all 7xx PowerPC implementations */
924 static void gen_spr_7xx (CPUPPCState *env)
925 {
926 /* Breakpoints */
927 /* XXX : not implemented */
928 spr_register_kvm(env, SPR_DABR, "DABR",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 KVM_REG_PPC_DABR, 0x00000000);
932 /* XXX : not implemented */
933 spr_register(env, SPR_IABR, "IABR",
934 SPR_NOACCESS, SPR_NOACCESS,
935 &spr_read_generic, &spr_write_generic,
936 0x00000000);
937 /* Cache management */
938 /* XXX : not implemented */
939 spr_register(env, SPR_ICTC, "ICTC",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 /* Performance monitors */
944 /* XXX : not implemented */
945 spr_register(env, SPR_MMCR0, "MMCR0",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
948 0x00000000);
949 /* XXX : not implemented */
950 spr_register(env, SPR_MMCR1, "MMCR1",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954 /* XXX : not implemented */
955 spr_register(env, SPR_PMC1, "PMC1",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959 /* XXX : not implemented */
960 spr_register(env, SPR_PMC2, "PMC2",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964 /* XXX : not implemented */
965 spr_register(env, SPR_PMC3, "PMC3",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* XXX : not implemented */
970 spr_register(env, SPR_PMC4, "PMC4",
971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, &spr_write_generic,
973 0x00000000);
974 /* XXX : not implemented */
975 spr_register(env, SPR_SIAR, "SIAR",
976 SPR_NOACCESS, SPR_NOACCESS,
977 &spr_read_generic, SPR_NOACCESS,
978 0x00000000);
979 /* XXX : not implemented */
980 spr_register(env, SPR_UMMCR0, "UMMCR0",
981 &spr_read_ureg, SPR_NOACCESS,
982 &spr_read_ureg, SPR_NOACCESS,
983 0x00000000);
984 /* XXX : not implemented */
985 spr_register(env, SPR_UMMCR1, "UMMCR1",
986 &spr_read_ureg, SPR_NOACCESS,
987 &spr_read_ureg, SPR_NOACCESS,
988 0x00000000);
989 /* XXX : not implemented */
990 spr_register(env, SPR_UPMC1, "UPMC1",
991 &spr_read_ureg, SPR_NOACCESS,
992 &spr_read_ureg, SPR_NOACCESS,
993 0x00000000);
994 /* XXX : not implemented */
995 spr_register(env, SPR_UPMC2, "UPMC2",
996 &spr_read_ureg, SPR_NOACCESS,
997 &spr_read_ureg, SPR_NOACCESS,
998 0x00000000);
999 /* XXX : not implemented */
1000 spr_register(env, SPR_UPMC3, "UPMC3",
1001 &spr_read_ureg, SPR_NOACCESS,
1002 &spr_read_ureg, SPR_NOACCESS,
1003 0x00000000);
1004 /* XXX : not implemented */
1005 spr_register(env, SPR_UPMC4, "UPMC4",
1006 &spr_read_ureg, SPR_NOACCESS,
1007 &spr_read_ureg, SPR_NOACCESS,
1008 0x00000000);
1009 /* XXX : not implemented */
1010 spr_register(env, SPR_USIAR, "USIAR",
1011 &spr_read_ureg, SPR_NOACCESS,
1012 &spr_read_ureg, SPR_NOACCESS,
1013 0x00000000);
1014 /* External access control */
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_EAR, "EAR",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020 }
1021
1022 #ifdef TARGET_PPC64
1023 #ifndef CONFIG_USER_ONLY
1024 static void spr_read_uamr (void *opaque, int gprn, int sprn)
1025 {
1026 gen_load_spr(cpu_gpr[gprn], SPR_AMR);
1027 spr_load_dump_spr(SPR_AMR);
1028 }
1029
1030 static void spr_write_uamr (void *opaque, int sprn, int gprn)
1031 {
1032 gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
1033 spr_store_dump_spr(SPR_AMR);
1034 }
1035
1036 static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
1037 {
1038 TCGv t0 = tcg_temp_new();
1039
1040 gen_load_spr(t0, SPR_UAMOR);
1041 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1042 gen_store_spr(SPR_AMR, t0);
1043 spr_store_dump_spr(SPR_AMR);
1044 }
1045 #endif /* CONFIG_USER_ONLY */
1046
1047 static void gen_spr_amr (CPUPPCState *env)
1048 {
1049 #ifndef CONFIG_USER_ONLY
1050 /* Virtual Page Class Key protection */
1051 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1052 * userspace accessible, 29 is privileged. So we only need to set
1053 * the kvm ONE_REG id on one of them, we use 29 */
1054 spr_register(env, SPR_UAMR, "UAMR",
1055 &spr_read_uamr, &spr_write_uamr_pr,
1056 &spr_read_uamr, &spr_write_uamr,
1057 0);
1058 spr_register_kvm(env, SPR_AMR, "AMR",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_generic,
1061 KVM_REG_PPC_AMR, 0xffffffffffffffffULL);
1062 spr_register_kvm(env, SPR_UAMOR, "UAMOR",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, &spr_write_generic,
1065 KVM_REG_PPC_UAMOR, 0);
1066 #endif /* !CONFIG_USER_ONLY */
1067 }
1068 #endif /* TARGET_PPC64 */
1069
1070 static void gen_spr_thrm (CPUPPCState *env)
1071 {
1072 /* Thermal management */
1073 /* XXX : not implemented */
1074 spr_register(env, SPR_THRM1, "THRM1",
1075 SPR_NOACCESS, SPR_NOACCESS,
1076 &spr_read_generic, &spr_write_generic,
1077 0x00000000);
1078 /* XXX : not implemented */
1079 spr_register(env, SPR_THRM2, "THRM2",
1080 SPR_NOACCESS, SPR_NOACCESS,
1081 &spr_read_generic, &spr_write_generic,
1082 0x00000000);
1083 /* XXX : not implemented */
1084 spr_register(env, SPR_THRM3, "THRM3",
1085 SPR_NOACCESS, SPR_NOACCESS,
1086 &spr_read_generic, &spr_write_generic,
1087 0x00000000);
1088 }
1089
1090 /* SPR specific to PowerPC 604 implementation */
1091 static void gen_spr_604 (CPUPPCState *env)
1092 {
1093 /* Processor identification */
1094 spr_register(env, SPR_PIR, "PIR",
1095 SPR_NOACCESS, SPR_NOACCESS,
1096 &spr_read_generic, &spr_write_pir,
1097 0x00000000);
1098 /* Breakpoints */
1099 /* XXX : not implemented */
1100 spr_register(env, SPR_IABR, "IABR",
1101 SPR_NOACCESS, SPR_NOACCESS,
1102 &spr_read_generic, &spr_write_generic,
1103 0x00000000);
1104 /* XXX : not implemented */
1105 spr_register_kvm(env, SPR_DABR, "DABR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, &spr_write_generic,
1108 KVM_REG_PPC_DABR, 0x00000000);
1109 /* Performance counters */
1110 /* XXX : not implemented */
1111 spr_register(env, SPR_MMCR0, "MMCR0",
1112 SPR_NOACCESS, SPR_NOACCESS,
1113 &spr_read_generic, &spr_write_generic,
1114 0x00000000);
1115 /* XXX : not implemented */
1116 spr_register(env, SPR_PMC1, "PMC1",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, &spr_write_generic,
1119 0x00000000);
1120 /* XXX : not implemented */
1121 spr_register(env, SPR_PMC2, "PMC2",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_generic, &spr_write_generic,
1124 0x00000000);
1125 /* XXX : not implemented */
1126 spr_register(env, SPR_SIAR, "SIAR",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, SPR_NOACCESS,
1129 0x00000000);
1130 /* XXX : not implemented */
1131 spr_register(env, SPR_SDA, "SDA",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_generic, SPR_NOACCESS,
1134 0x00000000);
1135 /* External access control */
1136 /* XXX : not implemented */
1137 spr_register(env, SPR_EAR, "EAR",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, &spr_write_generic,
1140 0x00000000);
1141 }
1142
1143 /* SPR specific to PowerPC 603 implementation */
1144 static void gen_spr_603 (CPUPPCState *env)
1145 {
1146 /* External access control */
1147 /* XXX : not implemented */
1148 spr_register(env, SPR_EAR, "EAR",
1149 SPR_NOACCESS, SPR_NOACCESS,
1150 &spr_read_generic, &spr_write_generic,
1151 0x00000000);
1152 }
1153
1154 /* SPR specific to PowerPC G2 implementation */
1155 static void gen_spr_G2 (CPUPPCState *env)
1156 {
1157 /* Memory base address */
1158 /* MBAR */
1159 /* XXX : not implemented */
1160 spr_register(env, SPR_MBAR, "MBAR",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_generic, &spr_write_generic,
1163 0x00000000);
1164 /* Exception processing */
1165 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1166 SPR_NOACCESS, SPR_NOACCESS,
1167 &spr_read_generic, &spr_write_generic,
1168 0x00000000);
1169 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_generic,
1172 0x00000000);
1173 /* Breakpoints */
1174 /* XXX : not implemented */
1175 spr_register(env, SPR_DABR, "DABR",
1176 SPR_NOACCESS, SPR_NOACCESS,
1177 &spr_read_generic, &spr_write_generic,
1178 0x00000000);
1179 /* XXX : not implemented */
1180 spr_register(env, SPR_DABR2, "DABR2",
1181 SPR_NOACCESS, SPR_NOACCESS,
1182 &spr_read_generic, &spr_write_generic,
1183 0x00000000);
1184 /* XXX : not implemented */
1185 spr_register(env, SPR_IABR, "IABR",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 /* XXX : not implemented */
1190 spr_register(env, SPR_IABR2, "IABR2",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 /* XXX : not implemented */
1195 spr_register(env, SPR_IBCR, "IBCR",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199 /* XXX : not implemented */
1200 spr_register(env, SPR_DBCR, "DBCR",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_generic,
1203 0x00000000);
1204 }
1205
1206 /* SPR specific to PowerPC 602 implementation */
1207 static void gen_spr_602 (CPUPPCState *env)
1208 {
1209 /* ESA registers */
1210 /* XXX : not implemented */
1211 spr_register(env, SPR_SER, "SER",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* XXX : not implemented */
1216 spr_register(env, SPR_SEBR, "SEBR",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_generic,
1219 0x00000000);
1220 /* XXX : not implemented */
1221 spr_register(env, SPR_ESASRR, "ESASRR",
1222 SPR_NOACCESS, SPR_NOACCESS,
1223 &spr_read_generic, &spr_write_generic,
1224 0x00000000);
1225 /* Floating point status */
1226 /* XXX : not implemented */
1227 spr_register(env, SPR_SP, "SP",
1228 SPR_NOACCESS, SPR_NOACCESS,
1229 &spr_read_generic, &spr_write_generic,
1230 0x00000000);
1231 /* XXX : not implemented */
1232 spr_register(env, SPR_LT, "LT",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 /* Watchdog timer */
1237 /* XXX : not implemented */
1238 spr_register(env, SPR_TCR, "TCR",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 &spr_read_generic, &spr_write_generic,
1241 0x00000000);
1242 /* Interrupt base */
1243 spr_register(env, SPR_IBR, "IBR",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 &spr_read_generic, &spr_write_generic,
1246 0x00000000);
1247 /* XXX : not implemented */
1248 spr_register(env, SPR_IABR, "IABR",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_generic, &spr_write_generic,
1251 0x00000000);
1252 }
1253
1254 /* SPR specific to PowerPC 601 implementation */
1255 static void gen_spr_601 (CPUPPCState *env)
1256 {
1257 /* Multiplication/division register */
1258 /* MQ */
1259 spr_register(env, SPR_MQ, "MQ",
1260 &spr_read_generic, &spr_write_generic,
1261 &spr_read_generic, &spr_write_generic,
1262 0x00000000);
1263 /* RTC registers */
1264 spr_register(env, SPR_601_RTCU, "RTCU",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 SPR_NOACCESS, &spr_write_601_rtcu,
1267 0x00000000);
1268 spr_register(env, SPR_601_VRTCU, "RTCU",
1269 &spr_read_601_rtcu, SPR_NOACCESS,
1270 &spr_read_601_rtcu, SPR_NOACCESS,
1271 0x00000000);
1272 spr_register(env, SPR_601_RTCL, "RTCL",
1273 SPR_NOACCESS, SPR_NOACCESS,
1274 SPR_NOACCESS, &spr_write_601_rtcl,
1275 0x00000000);
1276 spr_register(env, SPR_601_VRTCL, "RTCL",
1277 &spr_read_601_rtcl, SPR_NOACCESS,
1278 &spr_read_601_rtcl, SPR_NOACCESS,
1279 0x00000000);
1280 /* Timer */
1281 #if 0 /* ? */
1282 spr_register(env, SPR_601_UDECR, "UDECR",
1283 &spr_read_decr, SPR_NOACCESS,
1284 &spr_read_decr, SPR_NOACCESS,
1285 0x00000000);
1286 #endif
1287 /* External access control */
1288 /* XXX : not implemented */
1289 spr_register(env, SPR_EAR, "EAR",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293 /* Memory management */
1294 #if !defined(CONFIG_USER_ONLY)
1295 spr_register(env, SPR_IBAT0U, "IBAT0U",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_601_ubat, &spr_write_601_ubatu,
1298 0x00000000);
1299 spr_register(env, SPR_IBAT0L, "IBAT0L",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_601_ubat, &spr_write_601_ubatl,
1302 0x00000000);
1303 spr_register(env, SPR_IBAT1U, "IBAT1U",
1304 SPR_NOACCESS, SPR_NOACCESS,
1305 &spr_read_601_ubat, &spr_write_601_ubatu,
1306 0x00000000);
1307 spr_register(env, SPR_IBAT1L, "IBAT1L",
1308 SPR_NOACCESS, SPR_NOACCESS,
1309 &spr_read_601_ubat, &spr_write_601_ubatl,
1310 0x00000000);
1311 spr_register(env, SPR_IBAT2U, "IBAT2U",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_601_ubat, &spr_write_601_ubatu,
1314 0x00000000);
1315 spr_register(env, SPR_IBAT2L, "IBAT2L",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_601_ubat, &spr_write_601_ubatl,
1318 0x00000000);
1319 spr_register(env, SPR_IBAT3U, "IBAT3U",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_601_ubat, &spr_write_601_ubatu,
1322 0x00000000);
1323 spr_register(env, SPR_IBAT3L, "IBAT3L",
1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_601_ubat, &spr_write_601_ubatl,
1326 0x00000000);
1327 env->nb_BATs = 4;
1328 #endif
1329 }
1330
1331 static void gen_spr_74xx (CPUPPCState *env)
1332 {
1333 /* Processor identification */
1334 spr_register(env, SPR_PIR, "PIR",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_pir,
1337 0x00000000);
1338 /* XXX : not implemented */
1339 spr_register(env, SPR_MMCR2, "MMCR2",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, &spr_write_generic,
1342 0x00000000);
1343 /* XXX : not implemented */
1344 spr_register(env, SPR_UMMCR2, "UMMCR2",
1345 &spr_read_ureg, SPR_NOACCESS,
1346 &spr_read_ureg, SPR_NOACCESS,
1347 0x00000000);
1348 /* XXX: not implemented */
1349 spr_register(env, SPR_BAMR, "BAMR",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_generic, &spr_write_generic,
1352 0x00000000);
1353 /* XXX : not implemented */
1354 spr_register(env, SPR_MSSCR0, "MSSCR0",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
1358 /* Hardware implementation registers */
1359 /* XXX : not implemented */
1360 spr_register(env, SPR_HID0, "HID0",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364 /* XXX : not implemented */
1365 spr_register(env, SPR_HID1, "HID1",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369 /* Altivec */
1370 spr_register(env, SPR_VRSAVE, "VRSAVE",
1371 &spr_read_generic, &spr_write_generic,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 /* XXX : not implemented */
1375 spr_register(env, SPR_L2CR, "L2CR",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379 /* Not strictly an SPR */
1380 vscr_init(env, 0x00010000);
1381 }
1382
1383 static void gen_l3_ctrl (CPUPPCState *env)
1384 {
1385 /* L3CR */
1386 /* XXX : not implemented */
1387 spr_register(env, SPR_L3CR, "L3CR",
1388 SPR_NOACCESS, SPR_NOACCESS,
1389 &spr_read_generic, &spr_write_generic,
1390 0x00000000);
1391 /* L3ITCR0 */
1392 /* XXX : not implemented */
1393 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1394 SPR_NOACCESS, SPR_NOACCESS,
1395 &spr_read_generic, &spr_write_generic,
1396 0x00000000);
1397 /* L3PM */
1398 /* XXX : not implemented */
1399 spr_register(env, SPR_L3PM, "L3PM",
1400 SPR_NOACCESS, SPR_NOACCESS,
1401 &spr_read_generic, &spr_write_generic,
1402 0x00000000);
1403 }
1404
1405 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1406 {
1407 #if !defined(CONFIG_USER_ONLY)
1408 env->nb_tlb = nb_tlbs;
1409 env->nb_ways = nb_ways;
1410 env->id_tlbs = 1;
1411 env->tlb_type = TLB_6XX;
1412 /* XXX : not implemented */
1413 spr_register(env, SPR_PTEHI, "PTEHI",
1414 SPR_NOACCESS, SPR_NOACCESS,
1415 &spr_read_generic, &spr_write_generic,
1416 0x00000000);
1417 /* XXX : not implemented */
1418 spr_register(env, SPR_PTELO, "PTELO",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 &spr_read_generic, &spr_write_generic,
1421 0x00000000);
1422 /* XXX : not implemented */
1423 spr_register(env, SPR_TLBMISS, "TLBMISS",
1424 SPR_NOACCESS, SPR_NOACCESS,
1425 &spr_read_generic, &spr_write_generic,
1426 0x00000000);
1427 #endif
1428 }
1429
1430 #if !defined(CONFIG_USER_ONLY)
1431 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1432 {
1433 TCGv t0 = tcg_temp_new();
1434
1435 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1436 gen_store_spr(sprn, t0);
1437 tcg_temp_free(t0);
1438 }
1439
1440 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1441 {
1442 TCGv_i32 t0 = tcg_const_i32(sprn);
1443 gen_helper_booke206_tlbflush(cpu_env, t0);
1444 tcg_temp_free_i32(t0);
1445 }
1446
1447 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1448 {
1449 TCGv_i32 t0 = tcg_const_i32(sprn);
1450 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1451 tcg_temp_free_i32(t0);
1452 }
1453 #endif
1454
1455 static void gen_spr_usprgh (CPUPPCState *env)
1456 {
1457 spr_register(env, SPR_USPRG4, "USPRG4",
1458 &spr_read_ureg, SPR_NOACCESS,
1459 &spr_read_ureg, SPR_NOACCESS,
1460 0x00000000);
1461 spr_register(env, SPR_USPRG5, "USPRG5",
1462 &spr_read_ureg, SPR_NOACCESS,
1463 &spr_read_ureg, SPR_NOACCESS,
1464 0x00000000);
1465 spr_register(env, SPR_USPRG6, "USPRG6",
1466 &spr_read_ureg, SPR_NOACCESS,
1467 &spr_read_ureg, SPR_NOACCESS,
1468 0x00000000);
1469 spr_register(env, SPR_USPRG7, "USPRG7",
1470 &spr_read_ureg, SPR_NOACCESS,
1471 &spr_read_ureg, SPR_NOACCESS,
1472 0x00000000);
1473 }
1474
1475 /* PowerPC BookE SPR */
1476 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1477 {
1478 const char *ivor_names[64] = {
1479 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1480 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1481 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1482 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1483 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1484 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1485 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1486 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1487 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1488 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1489 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1490 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1491 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1492 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1493 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1494 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1495 };
1496 #define SPR_BOOKE_IVORxx (-1)
1497 int ivor_sprn[64] = {
1498 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1499 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1500 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1501 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1502 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1503 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1504 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1505 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1506 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1507 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1508 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1509 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1510 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1511 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1512 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1513 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1514 };
1515 int i;
1516
1517 /* Interrupt processing */
1518 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_generic, &spr_write_generic,
1521 0x00000000);
1522 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_generic,
1525 0x00000000);
1526 /* Debug */
1527 /* XXX : not implemented */
1528 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
1532 /* XXX : not implemented */
1533 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, &spr_write_generic,
1536 0x00000000);
1537 /* XXX : not implemented */
1538 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
1542 /* XXX : not implemented */
1543 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_generic,
1546 0x00000000);
1547 /* XXX : not implemented */
1548 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_40x_dbcr0,
1551 0x00000000);
1552 /* XXX : not implemented */
1553 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 /* XXX : not implemented */
1558 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
1562 /* XXX : not implemented */
1563 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_clear,
1566 0x00000000);
1567 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, &spr_write_generic,
1570 0x00000000);
1571 spr_register(env, SPR_BOOKE_ESR, "ESR",
1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1576 SPR_NOACCESS, SPR_NOACCESS,
1577 &spr_read_generic, &spr_write_excp_prefix,
1578 0x00000000);
1579 /* Exception vectors */
1580 for (i = 0; i < 64; i++) {
1581 if (ivor_mask & (1ULL << i)) {
1582 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1583 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1584 exit(1);
1585 }
1586 spr_register(env, ivor_sprn[i], ivor_names[i],
1587 SPR_NOACCESS, SPR_NOACCESS,
1588 &spr_read_generic, &spr_write_excp_vector,
1589 0x00000000);
1590 }
1591 }
1592 spr_register(env, SPR_BOOKE_PID, "PID",
1593 SPR_NOACCESS, SPR_NOACCESS,
1594 &spr_read_generic, &spr_write_booke_pid,
1595 0x00000000);
1596 spr_register(env, SPR_BOOKE_TCR, "TCR",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, &spr_write_booke_tcr,
1599 0x00000000);
1600 spr_register(env, SPR_BOOKE_TSR, "TSR",
1601 SPR_NOACCESS, SPR_NOACCESS,
1602 &spr_read_generic, &spr_write_booke_tsr,
1603 0x00000000);
1604 /* Timer */
1605 spr_register(env, SPR_DECR, "DECR",
1606 SPR_NOACCESS, SPR_NOACCESS,
1607 &spr_read_decr, &spr_write_decr,
1608 0x00000000);
1609 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1610 SPR_NOACCESS, SPR_NOACCESS,
1611 SPR_NOACCESS, &spr_write_generic,
1612 0x00000000);
1613 /* SPRGs */
1614 spr_register(env, SPR_USPRG0, "USPRG0",
1615 &spr_read_generic, &spr_write_generic,
1616 &spr_read_generic, &spr_write_generic,
1617 0x00000000);
1618 spr_register(env, SPR_SPRG4, "SPRG4",
1619 SPR_NOACCESS, SPR_NOACCESS,
1620 &spr_read_generic, &spr_write_generic,
1621 0x00000000);
1622 spr_register(env, SPR_SPRG5, "SPRG5",
1623 SPR_NOACCESS, SPR_NOACCESS,
1624 &spr_read_generic, &spr_write_generic,
1625 0x00000000);
1626 spr_register(env, SPR_SPRG6, "SPRG6",
1627 SPR_NOACCESS, SPR_NOACCESS,
1628 &spr_read_generic, &spr_write_generic,
1629 0x00000000);
1630 spr_register(env, SPR_SPRG7, "SPRG7",
1631 SPR_NOACCESS, SPR_NOACCESS,
1632 &spr_read_generic, &spr_write_generic,
1633 0x00000000);
1634 }
1635
1636 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1637 uint32_t maxsize, uint32_t flags,
1638 uint32_t nentries)
1639 {
1640 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1641 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1642 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1643 flags | nentries;
1644 }
1645
1646 /* BookE 2.06 storage control registers */
1647 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1648 uint32_t *tlbncfg)
1649 {
1650 #if !defined(CONFIG_USER_ONLY)
1651 const char *mas_names[8] = {
1652 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1653 };
1654 int mas_sprn[8] = {
1655 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1656 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1657 };
1658 int i;
1659
1660 /* TLB assist registers */
1661 /* XXX : not implemented */
1662 for (i = 0; i < 8; i++) {
1663 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1664 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1665 uea_write = &spr_write_generic;
1666 }
1667 if (mas_mask & (1 << i)) {
1668 spr_register(env, mas_sprn[i], mas_names[i],
1669 SPR_NOACCESS, SPR_NOACCESS,
1670 &spr_read_generic, uea_write,
1671 0x00000000);
1672 }
1673 }
1674 if (env->nb_pids > 1) {
1675 /* XXX : not implemented */
1676 spr_register(env, SPR_BOOKE_PID1, "PID1",
1677 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, &spr_write_booke_pid,
1679 0x00000000);
1680 }
1681 if (env->nb_pids > 2) {
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_BOOKE_PID2, "PID2",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_booke_pid,
1686 0x00000000);
1687 }
1688 /* XXX : not implemented */
1689 spr_register(env, SPR_MMUCFG, "MMUCFG",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, SPR_NOACCESS,
1692 0x00000000); /* TOFIX */
1693 switch (env->nb_ways) {
1694 case 4:
1695 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1696 SPR_NOACCESS, SPR_NOACCESS,
1697 &spr_read_generic, SPR_NOACCESS,
1698 tlbncfg[3]);
1699 /* Fallthru */
1700 case 3:
1701 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, SPR_NOACCESS,
1704 tlbncfg[2]);
1705 /* Fallthru */
1706 case 2:
1707 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1708 SPR_NOACCESS, SPR_NOACCESS,
1709 &spr_read_generic, SPR_NOACCESS,
1710 tlbncfg[1]);
1711 /* Fallthru */
1712 case 1:
1713 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, SPR_NOACCESS,
1716 tlbncfg[0]);
1717 /* Fallthru */
1718 case 0:
1719 default:
1720 break;
1721 }
1722 #endif
1723
1724 gen_spr_usprgh(env);
1725 }
1726
1727 /* SPR specific to PowerPC 440 implementation */
1728 static void gen_spr_440 (CPUPPCState *env)
1729 {
1730 /* Cache control */
1731 /* XXX : not implemented */
1732 spr_register(env, SPR_440_DNV0, "DNV0",
1733 SPR_NOACCESS, SPR_NOACCESS,
1734 &spr_read_generic, &spr_write_generic,
1735 0x00000000);
1736 /* XXX : not implemented */
1737 spr_register(env, SPR_440_DNV1, "DNV1",
1738 SPR_NOACCESS, SPR_NOACCESS,
1739 &spr_read_generic, &spr_write_generic,
1740 0x00000000);
1741 /* XXX : not implemented */
1742 spr_register(env, SPR_440_DNV2, "DNV2",
1743 SPR_NOACCESS, SPR_NOACCESS,
1744 &spr_read_generic, &spr_write_generic,
1745 0x00000000);
1746 /* XXX : not implemented */
1747 spr_register(env, SPR_440_DNV3, "DNV3",
1748 SPR_NOACCESS, SPR_NOACCESS,
1749 &spr_read_generic, &spr_write_generic,
1750 0x00000000);
1751 /* XXX : not implemented */
1752 spr_register(env, SPR_440_DTV0, "DTV0",
1753 SPR_NOACCESS, SPR_NOACCESS,
1754 &spr_read_generic, &spr_write_generic,
1755 0x00000000);
1756 /* XXX : not implemented */
1757 spr_register(env, SPR_440_DTV1, "DTV1",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, &spr_write_generic,
1760 0x00000000);
1761 /* XXX : not implemented */
1762 spr_register(env, SPR_440_DTV2, "DTV2",
1763 SPR_NOACCESS, SPR_NOACCESS,
1764 &spr_read_generic, &spr_write_generic,
1765 0x00000000);
1766 /* XXX : not implemented */
1767 spr_register(env, SPR_440_DTV3, "DTV3",
1768 SPR_NOACCESS, SPR_NOACCESS,
1769 &spr_read_generic, &spr_write_generic,
1770 0x00000000);
1771 /* XXX : not implemented */
1772 spr_register(env, SPR_440_DVLIM, "DVLIM",
1773 SPR_NOACCESS, SPR_NOACCESS,
1774 &spr_read_generic, &spr_write_generic,
1775 0x00000000);
1776 /* XXX : not implemented */
1777 spr_register(env, SPR_440_INV0, "INV0",
1778 SPR_NOACCESS, SPR_NOACCESS,
1779 &spr_read_generic, &spr_write_generic,
1780 0x00000000);
1781 /* XXX : not implemented */
1782 spr_register(env, SPR_440_INV1, "INV1",
1783 SPR_NOACCESS, SPR_NOACCESS,
1784 &spr_read_generic, &spr_write_generic,
1785 0x00000000);
1786 /* XXX : not implemented */
1787 spr_register(env, SPR_440_INV2, "INV2",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 /* XXX : not implemented */
1792 spr_register(env, SPR_440_INV3, "INV3",
1793 SPR_NOACCESS, SPR_NOACCESS,
1794 &spr_read_generic, &spr_write_generic,
1795 0x00000000);
1796 /* XXX : not implemented */
1797 spr_register(env, SPR_440_ITV0, "ITV0",
1798 SPR_NOACCESS, SPR_NOACCESS,
1799 &spr_read_generic, &spr_write_generic,
1800 0x00000000);
1801 /* XXX : not implemented */
1802 spr_register(env, SPR_440_ITV1, "ITV1",
1803 SPR_NOACCESS, SPR_NOACCESS,
1804 &spr_read_generic, &spr_write_generic,
1805 0x00000000);
1806 /* XXX : not implemented */
1807 spr_register(env, SPR_440_ITV2, "ITV2",
1808 SPR_NOACCESS, SPR_NOACCESS,
1809 &spr_read_generic, &spr_write_generic,
1810 0x00000000);
1811 /* XXX : not implemented */
1812 spr_register(env, SPR_440_ITV3, "ITV3",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_generic,
1815 0x00000000);
1816 /* XXX : not implemented */
1817 spr_register(env, SPR_440_IVLIM, "IVLIM",
1818 SPR_NOACCESS, SPR_NOACCESS,
1819 &spr_read_generic, &spr_write_generic,
1820 0x00000000);
1821 /* Cache debug */
1822 /* XXX : not implemented */
1823 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, SPR_NOACCESS,
1826 0x00000000);
1827 /* XXX : not implemented */
1828 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1829 SPR_NOACCESS, SPR_NOACCESS,
1830 &spr_read_generic, SPR_NOACCESS,
1831 0x00000000);
1832 /* XXX : not implemented */
1833 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_generic, SPR_NOACCESS,
1836 0x00000000);
1837 /* XXX : not implemented */
1838 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1839 SPR_NOACCESS, SPR_NOACCESS,
1840 &spr_read_generic, SPR_NOACCESS,
1841 0x00000000);
1842 /* XXX : not implemented */
1843 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1844 SPR_NOACCESS, SPR_NOACCESS,
1845 &spr_read_generic, SPR_NOACCESS,
1846 0x00000000);
1847 /* XXX : not implemented */
1848 spr_register(env, SPR_440_DBDR, "DBDR",
1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_generic, &spr_write_generic,
1851 0x00000000);
1852 /* Processor control */
1853 spr_register(env, SPR_4xx_CCR0, "CCR0",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, &spr_write_generic,
1856 0x00000000);
1857 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, SPR_NOACCESS,
1860 0x00000000);
1861 /* Storage control */
1862 spr_register(env, SPR_440_MMUCR, "MMUCR",
1863 SPR_NOACCESS, SPR_NOACCESS,
1864 &spr_read_generic, &spr_write_generic,
1865 0x00000000);
1866 }
1867
1868 /* SPR shared between PowerPC 40x implementations */
1869 static void gen_spr_40x (CPUPPCState *env)
1870 {
1871 /* Cache */
1872 /* not emulated, as QEMU do not emulate caches */
1873 spr_register(env, SPR_40x_DCCR, "DCCR",
1874 SPR_NOACCESS, SPR_NOACCESS,
1875 &spr_read_generic, &spr_write_generic,
1876 0x00000000);
1877 /* not emulated, as QEMU do not emulate caches */
1878 spr_register(env, SPR_40x_ICCR, "ICCR",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
1882 /* not emulated, as QEMU do not emulate caches */
1883 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, SPR_NOACCESS,
1886 0x00000000);
1887 /* Exception */
1888 spr_register(env, SPR_40x_DEAR, "DEAR",
1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_generic,
1891 0x00000000);
1892 spr_register(env, SPR_40x_ESR, "ESR",
1893 SPR_NOACCESS, SPR_NOACCESS,
1894 &spr_read_generic, &spr_write_generic,
1895 0x00000000);
1896 spr_register(env, SPR_40x_EVPR, "EVPR",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_excp_prefix,
1899 0x00000000);
1900 spr_register(env, SPR_40x_SRR2, "SRR2",
1901 &spr_read_generic, &spr_write_generic,
1902 &spr_read_generic, &spr_write_generic,
1903 0x00000000);
1904 spr_register(env, SPR_40x_SRR3, "SRR3",
1905 &spr_read_generic, &spr_write_generic,
1906 &spr_read_generic, &spr_write_generic,
1907 0x00000000);
1908 /* Timers */
1909 spr_register(env, SPR_40x_PIT, "PIT",
1910 SPR_NOACCESS, SPR_NOACCESS,
1911 &spr_read_40x_pit, &spr_write_40x_pit,
1912 0x00000000);
1913 spr_register(env, SPR_40x_TCR, "TCR",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_booke_tcr,
1916 0x00000000);
1917 spr_register(env, SPR_40x_TSR, "TSR",
1918 SPR_NOACCESS, SPR_NOACCESS,
1919 &spr_read_generic, &spr_write_booke_tsr,
1920 0x00000000);
1921 }
1922
1923 /* SPR specific to PowerPC 405 implementation */
1924 static void gen_spr_405 (CPUPPCState *env)
1925 {
1926 /* MMU */
1927 spr_register(env, SPR_40x_PID, "PID",
1928 SPR_NOACCESS, SPR_NOACCESS,
1929 &spr_read_generic, &spr_write_generic,
1930 0x00000000);
1931 spr_register(env, SPR_4xx_CCR0, "CCR0",
1932 SPR_NOACCESS, SPR_NOACCESS,
1933 &spr_read_generic, &spr_write_generic,
1934 0x00700000);
1935 /* Debug interface */
1936 /* XXX : not implemented */
1937 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_40x_dbcr0,
1940 0x00000000);
1941 /* XXX : not implemented */
1942 spr_register(env, SPR_405_DBCR1, "DBCR1",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 &spr_read_generic, &spr_write_generic,
1945 0x00000000);
1946 /* XXX : not implemented */
1947 spr_register(env, SPR_40x_DBSR, "DBSR",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_clear,
1950 /* Last reset was system reset */
1951 0x00000300);
1952 /* XXX : not implemented */
1953 spr_register(env, SPR_40x_DAC1, "DAC1",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_generic, &spr_write_generic,
1956 0x00000000);
1957 spr_register(env, SPR_40x_DAC2, "DAC2",
1958 SPR_NOACCESS, SPR_NOACCESS,
1959 &spr_read_generic, &spr_write_generic,
1960 0x00000000);
1961 /* XXX : not implemented */
1962 spr_register(env, SPR_405_DVC1, "DVC1",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_generic,
1965 0x00000000);
1966 /* XXX : not implemented */
1967 spr_register(env, SPR_405_DVC2, "DVC2",
1968 SPR_NOACCESS, SPR_NOACCESS,
1969 &spr_read_generic, &spr_write_generic,
1970 0x00000000);
1971 /* XXX : not implemented */
1972 spr_register(env, SPR_40x_IAC1, "IAC1",
1973 SPR_NOACCESS, SPR_NOACCESS,
1974 &spr_read_generic, &spr_write_generic,
1975 0x00000000);
1976 spr_register(env, SPR_40x_IAC2, "IAC2",
1977 SPR_NOACCESS, SPR_NOACCESS,
1978 &spr_read_generic, &spr_write_generic,
1979 0x00000000);
1980 /* XXX : not implemented */
1981 spr_register(env, SPR_405_IAC3, "IAC3",
1982 SPR_NOACCESS, SPR_NOACCESS,
1983 &spr_read_generic, &spr_write_generic,
1984 0x00000000);
1985 /* XXX : not implemented */
1986 spr_register(env, SPR_405_IAC4, "IAC4",
1987 SPR_NOACCESS, SPR_NOACCESS,
1988 &spr_read_generic, &spr_write_generic,
1989 0x00000000);
1990 /* Storage control */
1991 /* XXX: TODO: not implemented */
1992 spr_register(env, SPR_405_SLER, "SLER",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_40x_sler,
1995 0x00000000);
1996 spr_register(env, SPR_40x_ZPR, "ZPR",
1997 SPR_NOACCESS, SPR_NOACCESS,
1998 &spr_read_generic, &spr_write_generic,
1999 0x00000000);
2000 /* XXX : not implemented */
2001 spr_register(env, SPR_405_SU0R, "SU0R",
2002 SPR_NOACCESS, SPR_NOACCESS,
2003 &spr_read_generic, &spr_write_generic,
2004 0x00000000);
2005 /* SPRG */
2006 spr_register(env, SPR_USPRG0, "USPRG0",
2007 &spr_read_ureg, SPR_NOACCESS,
2008 &spr_read_ureg, SPR_NOACCESS,
2009 0x00000000);
2010 spr_register(env, SPR_SPRG4, "SPRG4",
2011 SPR_NOACCESS, SPR_NOACCESS,
2012 &spr_read_generic, &spr_write_generic,
2013 0x00000000);
2014 spr_register(env, SPR_SPRG5, "SPRG5",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 spr_read_generic, &spr_write_generic,
2017 0x00000000);
2018 spr_register(env, SPR_SPRG6, "SPRG6",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 spr_read_generic, &spr_write_generic,
2021 0x00000000);
2022 spr_register(env, SPR_SPRG7, "SPRG7",
2023 SPR_NOACCESS, SPR_NOACCESS,
2024 spr_read_generic, &spr_write_generic,
2025 0x00000000);
2026 gen_spr_usprgh(env);
2027 }
2028
2029 /* SPR shared between PowerPC 401 & 403 implementations */
2030 static void gen_spr_401_403 (CPUPPCState *env)
2031 {
2032 /* Time base */
2033 spr_register(env, SPR_403_VTBL, "TBL",
2034 &spr_read_tbl, SPR_NOACCESS,
2035 &spr_read_tbl, SPR_NOACCESS,
2036 0x00000000);
2037 spr_register(env, SPR_403_TBL, "TBL",
2038 SPR_NOACCESS, SPR_NOACCESS,
2039 SPR_NOACCESS, &spr_write_tbl,
2040 0x00000000);
2041 spr_register(env, SPR_403_VTBU, "TBU",
2042 &spr_read_tbu, SPR_NOACCESS,
2043 &spr_read_tbu, SPR_NOACCESS,
2044 0x00000000);
2045 spr_register(env, SPR_403_TBU, "TBU",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 SPR_NOACCESS, &spr_write_tbu,
2048 0x00000000);
2049 /* Debug */
2050 /* not emulated, as QEMU do not emulate caches */
2051 spr_register(env, SPR_403_CDBCR, "CDBCR",
2052 SPR_NOACCESS, SPR_NOACCESS,
2053 &spr_read_generic, &spr_write_generic,
2054 0x00000000);
2055 }
2056
2057 /* SPR specific to PowerPC 401 implementation */
2058 static void gen_spr_401 (CPUPPCState *env)
2059 {
2060 /* Debug interface */
2061 /* XXX : not implemented */
2062 spr_register(env, SPR_40x_DBCR0, "DBCR",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_generic, &spr_write_40x_dbcr0,
2065 0x00000000);
2066 /* XXX : not implemented */
2067 spr_register(env, SPR_40x_DBSR, "DBSR",
2068 SPR_NOACCESS, SPR_NOACCESS,
2069 &spr_read_generic, &spr_write_clear,
2070 /* Last reset was system reset */
2071 0x00000300);
2072 /* XXX : not implemented */
2073 spr_register(env, SPR_40x_DAC1, "DAC",
2074 SPR_NOACCESS, SPR_NOACCESS,
2075 &spr_read_generic, &spr_write_generic,
2076 0x00000000);
2077 /* XXX : not implemented */
2078 spr_register(env, SPR_40x_IAC1, "IAC",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_generic, &spr_write_generic,
2081 0x00000000);
2082 /* Storage control */
2083 /* XXX: TODO: not implemented */
2084 spr_register(env, SPR_405_SLER, "SLER",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, &spr_write_40x_sler,
2087 0x00000000);
2088 /* not emulated, as QEMU never does speculative access */
2089 spr_register(env, SPR_40x_SGR, "SGR",
2090 SPR_NOACCESS, SPR_NOACCESS,
2091 &spr_read_generic, &spr_write_generic,
2092 0xFFFFFFFF);
2093 /* not emulated, as QEMU do not emulate caches */
2094 spr_register(env, SPR_40x_DCWR, "DCWR",
2095 SPR_NOACCESS, SPR_NOACCESS,
2096 &spr_read_generic, &spr_write_generic,
2097 0x00000000);
2098 }
2099
2100 static void gen_spr_401x2 (CPUPPCState *env)
2101 {
2102 gen_spr_401(env);
2103 spr_register(env, SPR_40x_PID, "PID",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, &spr_write_generic,
2106 0x00000000);
2107 spr_register(env, SPR_40x_ZPR, "ZPR",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_generic, &spr_write_generic,
2110 0x00000000);
2111 }
2112
2113 /* SPR specific to PowerPC 403 implementation */
2114 static void gen_spr_403 (CPUPPCState *env)
2115 {
2116 /* Debug interface */
2117 /* XXX : not implemented */
2118 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_40x_dbcr0,
2121 0x00000000);
2122 /* XXX : not implemented */
2123 spr_register(env, SPR_40x_DBSR, "DBSR",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_clear,
2126 /* Last reset was system reset */
2127 0x00000300);
2128 /* XXX : not implemented */
2129 spr_register(env, SPR_40x_DAC1, "DAC1",
2130 SPR_NOACCESS, SPR_NOACCESS,
2131 &spr_read_generic, &spr_write_generic,
2132 0x00000000);
2133 /* XXX : not implemented */
2134 spr_register(env, SPR_40x_DAC2, "DAC2",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
2138 /* XXX : not implemented */
2139 spr_register(env, SPR_40x_IAC1, "IAC1",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_generic,
2142 0x00000000);
2143 /* XXX : not implemented */
2144 spr_register(env, SPR_40x_IAC2, "IAC2",
2145 SPR_NOACCESS, SPR_NOACCESS,
2146 &spr_read_generic, &spr_write_generic,
2147 0x00000000);
2148 }
2149
2150 static void gen_spr_403_real (CPUPPCState *env)
2151 {
2152 spr_register(env, SPR_403_PBL1, "PBL1",
2153 SPR_NOACCESS, SPR_NOACCESS,
2154 &spr_read_403_pbr, &spr_write_403_pbr,
2155 0x00000000);
2156 spr_register(env, SPR_403_PBU1, "PBU1",
2157 SPR_NOACCESS, SPR_NOACCESS,
2158 &spr_read_403_pbr, &spr_write_403_pbr,
2159 0x00000000);
2160 spr_register(env, SPR_403_PBL2, "PBL2",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_403_pbr, &spr_write_403_pbr,
2163 0x00000000);
2164 spr_register(env, SPR_403_PBU2, "PBU2",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_403_pbr, &spr_write_403_pbr,
2167 0x00000000);
2168 }
2169
2170 static void gen_spr_403_mmu (CPUPPCState *env)
2171 {
2172 /* MMU */
2173 spr_register(env, SPR_40x_PID, "PID",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_generic, &spr_write_generic,
2176 0x00000000);
2177 spr_register(env, SPR_40x_ZPR, "ZPR",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 &spr_read_generic, &spr_write_generic,
2180 0x00000000);
2181 }
2182
2183 /* SPR specific to PowerPC compression coprocessor extension */
2184 static void gen_spr_compress (CPUPPCState *env)
2185 {
2186 /* XXX : not implemented */
2187 spr_register(env, SPR_401_SKR, "SKR",
2188 SPR_NOACCESS, SPR_NOACCESS,
2189 &spr_read_generic, &spr_write_generic,
2190 0x00000000);
2191 }
2192
2193 static void gen_spr_5xx_8xx (CPUPPCState *env)
2194 {
2195 /* Exception processing */
2196 spr_register_kvm(env, SPR_DSISR, "DSISR",
2197 SPR_NOACCESS, SPR_NOACCESS,
2198 &spr_read_generic, &spr_write_generic,
2199 KVM_REG_PPC_DSISR, 0x00000000);
2200 spr_register_kvm(env, SPR_DAR, "DAR",
2201 SPR_NOACCESS, SPR_NOACCESS,
2202 &spr_read_generic, &spr_write_generic,
2203 KVM_REG_PPC_DAR, 0x00000000);
2204 /* Timer */
2205 spr_register(env, SPR_DECR, "DECR",
2206 SPR_NOACCESS, SPR_NOACCESS,
2207 &spr_read_decr, &spr_write_decr,
2208 0x00000000);
2209 /* XXX : not implemented */
2210 spr_register(env, SPR_MPC_EIE, "EIE",
2211 SPR_NOACCESS, SPR_NOACCESS,
2212 &spr_read_generic, &spr_write_generic,
2213 0x00000000);
2214 /* XXX : not implemented */
2215 spr_register(env, SPR_MPC_EID, "EID",
2216 SPR_NOACCESS, SPR_NOACCESS,
2217 &spr_read_generic, &spr_write_generic,
2218 0x00000000);
2219 /* XXX : not implemented */
2220 spr_register(env, SPR_MPC_NRI, "NRI",
2221 SPR_NOACCESS, SPR_NOACCESS,
2222 &spr_read_generic, &spr_write_generic,
2223 0x00000000);
2224 /* XXX : not implemented */
2225 spr_register(env, SPR_MPC_CMPA, "CMPA",
2226 SPR_NOACCESS, SPR_NOACCESS,
2227 &spr_read_generic, &spr_write_generic,
2228 0x00000000);
2229 /* XXX : not implemented */
2230 spr_register(env, SPR_MPC_CMPB, "CMPB",
2231 SPR_NOACCESS, SPR_NOACCESS,
2232 &spr_read_generic, &spr_write_generic,
2233 0x00000000);
2234 /* XXX : not implemented */
2235 spr_register(env, SPR_MPC_CMPC, "CMPC",
2236 SPR_NOACCESS, SPR_NOACCESS,
2237 &spr_read_generic, &spr_write_generic,
2238 0x00000000);
2239 /* XXX : not implemented */
2240 spr_register(env, SPR_MPC_CMPD, "CMPD",
2241 SPR_NOACCESS, SPR_NOACCESS,
2242 &spr_read_generic, &spr_write_generic,
2243 0x00000000);
2244 /* XXX : not implemented */
2245 spr_register(env, SPR_MPC_ECR, "ECR",
2246 SPR_NOACCESS, SPR_NOACCESS,
2247 &spr_read_generic, &spr_write_generic,
2248 0x00000000);
2249 /* XXX : not implemented */
2250 spr_register(env, SPR_MPC_DER, "DER",
2251 SPR_NOACCESS, SPR_NOACCESS,
2252 &spr_read_generic, &spr_write_generic,
2253 0x00000000);
2254 /* XXX : not implemented */
2255 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_generic,
2258 0x00000000);
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_generic,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_MPC_CMPE, "CMPE",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_generic,
2268 0x00000000);
2269 /* XXX : not implemented */
2270 spr_register(env, SPR_MPC_CMPF, "CMPF",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
2274 /* XXX : not implemented */
2275 spr_register(env, SPR_MPC_CMPG, "CMPG",
2276 SPR_NOACCESS, SPR_NOACCESS,
2277 &spr_read_generic, &spr_write_generic,
2278 0x00000000);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_MPC_CMPH, "CMPH",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284 /* XXX : not implemented */
2285 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2286 SPR_NOACCESS, SPR_NOACCESS,
2287 &spr_read_generic, &spr_write_generic,
2288 0x00000000);
2289 /* XXX : not implemented */
2290 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_generic, &spr_write_generic,
2293 0x00000000);
2294 /* XXX : not implemented */
2295 spr_register(env, SPR_MPC_BAR, "BAR",
2296 SPR_NOACCESS, SPR_NOACCESS,
2297 &spr_read_generic, &spr_write_generic,
2298 0x00000000);
2299 /* XXX : not implemented */
2300 spr_register(env, SPR_MPC_DPDR, "DPDR",
2301 SPR_NOACCESS, SPR_NOACCESS,
2302 &spr_read_generic, &spr_write_generic,
2303 0x00000000);
2304 /* XXX : not implemented */
2305 spr_register(env, SPR_MPC_IMMR, "IMMR",
2306 SPR_NOACCESS, SPR_NOACCESS,
2307 &spr_read_generic, &spr_write_generic,
2308 0x00000000);
2309 }
2310
2311 static void gen_spr_5xx (CPUPPCState *env)
2312 {
2313 /* XXX : not implemented */
2314 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2315 SPR_NOACCESS, SPR_NOACCESS,
2316 &spr_read_generic, &spr_write_generic,
2317 0x00000000);
2318 /* XXX : not implemented */
2319 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2320 SPR_NOACCESS, SPR_NOACCESS,
2321 &spr_read_generic, &spr_write_generic,
2322 0x00000000);
2323 /* XXX : not implemented */
2324 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 &spr_read_generic, &spr_write_generic,
2327 0x00000000);
2328 /* XXX : not implemented */
2329 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2330 SPR_NOACCESS, SPR_NOACCESS,
2331 &spr_read_generic, &spr_write_generic,
2332 0x00000000);
2333 /* XXX : not implemented */
2334 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403 /* XXX : not implemented */
2404 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2405 SPR_NOACCESS, SPR_NOACCESS,
2406 &spr_read_generic, &spr_write_generic,
2407 0x00000000);
2408 /* XXX : not implemented */
2409 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2410 SPR_NOACCESS, SPR_NOACCESS,
2411 &spr_read_generic, &spr_write_generic,
2412 0x00000000);
2413 /* XXX : not implemented */
2414 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2415 SPR_NOACCESS, SPR_NOACCESS,
2416 &spr_read_generic, &spr_write_generic,
2417 0x00000000);
2418 }
2419
2420 static void gen_spr_8xx (CPUPPCState *env)
2421 {
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 /* XXX : not implemented */
2428 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2429 SPR_NOACCESS, SPR_NOACCESS,
2430 &spr_read_generic, &spr_write_generic,
2431 0x00000000);
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 /* XXX : not implemented */
2438 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2439 SPR_NOACCESS, SPR_NOACCESS,
2440 &spr_read_generic, &spr_write_generic,
2441 0x00000000);
2442 /* XXX : not implemented */
2443 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_generic, &spr_write_generic,
2446 0x00000000);
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 /* XXX : not implemented */
2508 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2509 SPR_NOACCESS, SPR_NOACCESS,
2510 &spr_read_generic, &spr_write_generic,
2511 0x00000000);
2512 /* XXX : not implemented */
2513 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2514 SPR_NOACCESS, SPR_NOACCESS,
2515 &spr_read_generic, &spr_write_generic,
2516 0x00000000);
2517 /* XXX : not implemented */
2518 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2519 SPR_NOACCESS, SPR_NOACCESS,
2520 &spr_read_generic, &spr_write_generic,
2521 0x00000000);
2522 /* XXX : not implemented */
2523 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2524 SPR_NOACCESS, SPR_NOACCESS,
2525 &spr_read_generic, &spr_write_generic,
2526 0x00000000);
2527 /* XXX : not implemented */
2528 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2529 SPR_NOACCESS, SPR_NOACCESS,
2530 &spr_read_generic, &spr_write_generic,
2531 0x00000000);
2532 /* XXX : not implemented */
2533 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2534 SPR_NOACCESS, SPR_NOACCESS,
2535 &spr_read_generic, &spr_write_generic,
2536 0x00000000);
2537 /* XXX : not implemented */
2538 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2539 SPR_NOACCESS, SPR_NOACCESS,
2540 &spr_read_generic, &spr_write_generic,
2541 0x00000000);
2542 /* XXX : not implemented */
2543 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2544 SPR_NOACCESS, SPR_NOACCESS,
2545 &spr_read_generic, &spr_write_generic,
2546 0x00000000);
2547 }
2548
2549 // XXX: TODO
2550 /*
2551 * AMR => SPR 29 (Power 2.04)
2552 * CTRL => SPR 136 (Power 2.04)
2553 * CTRL => SPR 152 (Power 2.04)
2554 * SCOMC => SPR 276 (64 bits ?)
2555 * SCOMD => SPR 277 (64 bits ?)
2556 * TBU40 => SPR 286 (Power 2.04 hypv)
2557 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2558 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2559 * HDSISR => SPR 306 (Power 2.04 hypv)
2560 * HDAR => SPR 307 (Power 2.04 hypv)
2561 * PURR => SPR 309 (Power 2.04 hypv)
2562 * HDEC => SPR 310 (Power 2.04 hypv)
2563 * HIOR => SPR 311 (hypv)
2564 * RMOR => SPR 312 (970)
2565 * HRMOR => SPR 313 (Power 2.04 hypv)
2566 * HSRR0 => SPR 314 (Power 2.04 hypv)
2567 * HSRR1 => SPR 315 (Power 2.04 hypv)
2568 * LPCR => SPR 316 (970)
2569 * LPIDR => SPR 317 (970)
2570 * EPR => SPR 702 (Power 2.04 emb)
2571 * perf => 768-783 (Power 2.04)
2572 * perf => 784-799 (Power 2.04)
2573 * PPR => SPR 896 (Power 2.04)
2574 * EPLC => SPR 947 (Power 2.04 emb)
2575 * EPSC => SPR 948 (Power 2.04 emb)
2576 * DABRX => 1015 (Power 2.04 hypv)
2577 * FPECR => SPR 1022 (?)
2578 * ... and more (thermal management, performance counters, ...)
2579 */
2580
2581 /*****************************************************************************/
2582 /* Exception vectors models */
2583 static void init_excp_4xx_real (CPUPPCState *env)
2584 {
2585 #if !defined(CONFIG_USER_ONLY)
2586 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2587 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2588 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2589 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2590 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2591 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2592 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2593 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2594 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2595 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2596 env->hreset_excp_prefix = 0x00000000UL;
2597 env->ivor_mask = 0x0000FFF0UL;
2598 env->ivpr_mask = 0xFFFF0000UL;
2599 /* Hardware reset vector */
2600 env->hreset_vector = 0xFFFFFFFCUL;
2601 #endif
2602 }
2603
2604 static void init_excp_4xx_softmmu (CPUPPCState *env)
2605 {
2606 #if !defined(CONFIG_USER_ONLY)
2607 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2608 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2609 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2610 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2611 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2612 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2613 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2614 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2615 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2616 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2617 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2618 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2619 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2620 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2621 env->hreset_excp_prefix = 0x00000000UL;
2622 env->ivor_mask = 0x0000FFF0UL;
2623 env->ivpr_mask = 0xFFFF0000UL;
2624 /* Hardware reset vector */
2625 env->hreset_vector = 0xFFFFFFFCUL;
2626 #endif
2627 }
2628
2629 static void init_excp_MPC5xx (CPUPPCState *env)
2630 {
2631 #if !defined(CONFIG_USER_ONLY)
2632 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2633 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2634 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2635 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2636 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2637 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2638 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2639 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2640 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2641 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2642 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2643 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2644 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2645 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2646 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2647 env->hreset_excp_prefix = 0x00000000UL;
2648 env->ivor_mask = 0x0000FFF0UL;
2649 env->ivpr_mask = 0xFFFF0000UL;
2650 /* Hardware reset vector */
2651 env->hreset_vector = 0xFFFFFFFCUL;
2652 #endif
2653 }
2654
2655 static void init_excp_MPC8xx (CPUPPCState *env)
2656 {
2657 #if !defined(CONFIG_USER_ONLY)
2658 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2659 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2660 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2661 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2662 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2663 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2664 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2665 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2666 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2667 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2668 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2669 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2670 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2671 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2672 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2673 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2674 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2675 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2676 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2677 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2678 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2679 env->hreset_excp_prefix = 0x00000000UL;
2680 env->ivor_mask = 0x0000FFF0UL;
2681 env->ivpr_mask = 0xFFFF0000UL;
2682 /* Hardware reset vector */
2683 env->hreset_vector = 0xFFFFFFFCUL;
2684 #endif
2685 }
2686
2687 static void init_excp_G2 (CPUPPCState *env)
2688 {
2689 #if !defined(CONFIG_USER_ONLY)
2690 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2691 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2692 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2693 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2694 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2695 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2696 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2697 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2698 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2699 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2700 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2701 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2702 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2703 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2704 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2705 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2706 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2707 env->hreset_excp_prefix = 0x00000000UL;
2708 /* Hardware reset vector */
2709 env->hreset_vector = 0xFFFFFFFCUL;
2710 #endif
2711 }
2712
2713 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2714 {
2715 #if !defined(CONFIG_USER_ONLY)
2716 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2717 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2718 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2719 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2720 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2721 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2722 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2723 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2724 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2725 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2726 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2727 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2728 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2729 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2730 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2731 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2732 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2733 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2734 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2735 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2736 env->hreset_excp_prefix = 0x00000000UL;
2737 env->ivor_mask = 0x0000FFF7UL;
2738 env->ivpr_mask = ivpr_mask;
2739 /* Hardware reset vector */
2740 env->hreset_vector = 0xFFFFFFFCUL;
2741 #endif
2742 }
2743
2744 static void init_excp_BookE (CPUPPCState *env)
2745 {
2746 #if !defined(CONFIG_USER_ONLY)
2747 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2748 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2749 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2750 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2751 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2752 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2753 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2754 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2755 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2756 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2757 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2758 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2759 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2760 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2761 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2762 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2763 env->hreset_excp_prefix = 0x00000000UL;
2764 env->ivor_mask = 0x0000FFE0UL;
2765 env->ivpr_mask = 0xFFFF0000UL;
2766 /* Hardware reset vector */
2767 env->hreset_vector = 0xFFFFFFFCUL;
2768 #endif
2769 }
2770
2771 static void init_excp_601 (CPUPPCState *env)
2772 {
2773 #if !defined(CONFIG_USER_ONLY)
2774 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2775 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2776 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2777 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2778 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2779 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2780 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2781 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2782 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2783 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2784 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2785 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2786 env->hreset_excp_prefix = 0xFFF00000UL;
2787 /* Hardware reset vector */
2788 env->hreset_vector = 0x00000100UL;
2789 #endif
2790 }
2791
2792 static void init_excp_602 (CPUPPCState *env)
2793 {
2794 #if !defined(CONFIG_USER_ONLY)
2795 /* XXX: exception prefix has a special behavior on 602 */
2796 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2797 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2798 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2799 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2800 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2801 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2802 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2803 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2804 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2805 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2806 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2807 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2808 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2809 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2810 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2811 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2812 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2813 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2814 env->hreset_excp_prefix = 0xFFF00000UL;
2815 /* Hardware reset vector */
2816 env->hreset_vector = 0xFFFFFFFCUL;
2817 #endif
2818 }
2819
2820 static void init_excp_603 (CPUPPCState *env)
2821 {
2822 #if !defined(CONFIG_USER_ONLY)
2823 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2824 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2825 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2826 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2827 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2828 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2829 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2830 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2831 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2832 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2833 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2834 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2835 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2836 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2837 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2838 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2839 env->hreset_excp_prefix = 0x00000000UL;
2840 /* Hardware reset vector */
2841 env->hreset_vector = 0xFFFFFFFCUL;
2842 #endif
2843 }
2844
2845 static void init_excp_604 (CPUPPCState *env)
2846 {
2847 #if !defined(CONFIG_USER_ONLY)
2848 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2849 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2850 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2851 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2852 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2853 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2854 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2855 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2856 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2857 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2858 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2859 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2860 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2861 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2862 env->hreset_excp_prefix = 0xFFF00000UL;
2863 /* Hardware reset vector */
2864 env->hreset_vector = 0x00000100UL;
2865 #endif
2866 }
2867
2868 static void init_excp_7x0 (CPUPPCState *env)
2869 {
2870 #if !defined(CONFIG_USER_ONLY)
2871 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2872 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2873 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2874 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2875 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2876 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2877 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2878 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2879 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2880 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2881 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2882 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2883 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2884 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2885 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2886 env->hreset_excp_prefix = 0x00000000UL;
2887 /* Hardware reset vector */
2888 env->hreset_vector = 0xFFFFFFFCUL;
2889 #endif
2890 }
2891
2892 static void init_excp_750cl (CPUPPCState *env)
2893 {
2894 #if !defined(CONFIG_USER_ONLY)
2895 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2896 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2897 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2898 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2899 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2900 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2901 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2902 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2903 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2904 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2905 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2906 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2907 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2908 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2909 env->hreset_excp_prefix = 0x00000000UL;
2910 /* Hardware reset vector */
2911 env->hreset_vector = 0xFFFFFFFCUL;
2912 #endif
2913 }
2914
2915 static void init_excp_750cx (CPUPPCState *env)
2916 {
2917 #if !defined(CONFIG_USER_ONLY)
2918 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2919 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2920 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2921 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2922 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2923 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2924 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2925 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2926 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2927 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2928 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2929 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2930 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2931 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2932 env->hreset_excp_prefix = 0x00000000UL;
2933 /* Hardware reset vector */
2934 env->hreset_vector = 0xFFFFFFFCUL;
2935 #endif
2936 }
2937
2938 /* XXX: Check if this is correct */
2939 static void init_excp_7x5 (CPUPPCState *env)
2940 {
2941 #if !defined(CONFIG_USER_ONLY)
2942 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2943 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2944 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2945 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2946 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2947 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2948 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2949 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2950 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2951 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2952 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2953 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2954 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2955 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2956 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2957 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2958 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2959 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2960 env->hreset_excp_prefix = 0x00000000UL;
2961 /* Hardware reset vector */
2962 env->hreset_vector = 0xFFFFFFFCUL;
2963 #endif
2964 }
2965
2966 static void init_excp_7400 (CPUPPCState *env)
2967 {
2968 #if !defined(CONFIG_USER_ONLY)
2969 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2970 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2971 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2972 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2973 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2974 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2975 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2976 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2977 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2978 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2979 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2980 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2981 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2982 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2983 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2984 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2985 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2986 env->hreset_excp_prefix = 0x00000000UL;
2987 /* Hardware reset vector */
2988 env->hreset_vector = 0xFFFFFFFCUL;
2989 #endif
2990 }
2991
2992 static void init_excp_7450 (CPUPPCState *env)
2993 {
2994 #if !defined(CONFIG_USER_ONLY)
2995 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2996 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2997 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2998 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2999 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3000 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3001 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3002 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3003 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3004 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3005 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3006 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3007 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3008 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3009 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3010 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3011 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3012 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3013 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3014 env->hreset_excp_prefix = 0x00000000UL;
3015 /* Hardware reset vector */
3016 env->hreset_vector = 0xFFFFFFFCUL;
3017 #endif
3018 }
3019
3020 #if defined (TARGET_PPC64)
3021 static void init_excp_970 (CPUPPCState *env)
3022 {
3023 #if !defined(CONFIG_USER_ONLY)
3024 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3025 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3026 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3027 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3028 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3029 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3030 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3031 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3032 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3033 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3034 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3035 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3036 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3037 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3038 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3039 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3040 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3041 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3042 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3043 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3044 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3045 /* Hardware reset vector */
3046 env->hreset_vector = 0x0000000000000100ULL;
3047 #endif
3048 }
3049
3050 static void init_excp_POWER7 (CPUPPCState *env)
3051 {
3052 #if !defined(CONFIG_USER_ONLY)
3053 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3054 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3055 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3056 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3057 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3058 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3059 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3060 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3061 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3062 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3063 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3064 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3065 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3066 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3067 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3068 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3069 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3070 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3071 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3072 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3073 env->hreset_excp_prefix = 0;
3074 /* Hardware reset vector */
3075 env->hreset_vector = 0x0000000000000100ULL;
3076 #endif
3077 }
3078 #endif
3079
3080 /*****************************************************************************/
3081 /* Power management enable checks */
3082 static int check_pow_none (CPUPPCState *env)
3083 {
3084 return 0;
3085 }
3086
3087 static int check_pow_nocheck (CPUPPCState *env)
3088 {
3089 return 1;
3090 }
3091
3092 static int check_pow_hid0 (CPUPPCState *env)
3093 {
3094 if (env->spr[SPR_HID0] & 0x00E00000)
3095 return 1;
3096
3097 return 0;
3098 }
3099
3100 static int check_pow_hid0_74xx (CPUPPCState *env)
3101 {
3102 if (env->spr[SPR_HID0] & 0x00600000)
3103 return 1;
3104
3105 return 0;
3106 }
3107
3108 /*****************************************************************************/
3109 /* PowerPC implementations definitions */
3110
3111 #define POWERPC_FAMILY(_name) \
3112 static void \
3113 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3114 \
3115 static const TypeInfo \
3116 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3117 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3118 .parent = TYPE_POWERPC_CPU, \
3119 .abstract = true, \
3120 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3121 }; \
3122 \
3123 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3124 { \
3125 type_register_static( \
3126 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3127 } \
3128 \
3129 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3130 \
3131 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3132
3133 static void init_proc_401 (CPUPPCState *env)
3134 {
3135 gen_spr_40x(env);
3136 gen_spr_401_403(env);
3137 gen_spr_401(env);
3138 init_excp_4xx_real(env);
3139 env->dcache_line_size = 32;
3140 env->icache_line_size = 32;
3141 /* Allocate hardware IRQ controller */
3142 ppc40x_irq_init(env);
3143
3144 SET_FIT_PERIOD(12, 16, 20, 24);
3145 SET_WDT_PERIOD(16, 20, 24, 28);
3146 }
3147
3148 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3149 {
3150 DeviceClass *dc = DEVICE_CLASS(oc);
3151 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3152
3153 dc->desc = "PowerPC 401";
3154 pcc->init_proc = init_proc_401;
3155 pcc->check_pow = check_pow_nocheck;
3156 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3157 PPC_WRTEE | PPC_DCR |
3158 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3159 PPC_CACHE_DCBZ |
3160 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3161 PPC_4xx_COMMON | PPC_40x_EXCP;
3162 pcc->insns_flags2 = PPC_NONE;
3163 pcc->msr_mask = 0x00000000000FD201ULL;
3164 pcc->mmu_model = POWERPC_MMU_REAL;
3165 pcc->excp_model = POWERPC_EXCP_40x;
3166 pcc->bus_model = PPC_FLAGS_INPUT_401;
3167 pcc->bfd_mach = bfd_mach_ppc_403;
3168 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3169 POWERPC_FLAG_BUS_CLK;
3170 }
3171
3172 static void init_proc_401x2 (CPUPPCState *env)
3173 {
3174 gen_spr_40x(env);
3175 gen_spr_401_403(env);
3176 gen_spr_401x2(env);
3177 gen_spr_compress(env);
3178 /* Memory management */
3179 #if !defined(CONFIG_USER_ONLY)
3180 env->nb_tlb = 64;
3181 env->nb_ways = 1;
3182 env->id_tlbs = 0;
3183 env->tlb_type = TLB_EMB;
3184 #endif
3185 init_excp_4xx_softmmu(env);
3186 env->dcache_line_size = 32;
3187 env->icache_line_size = 32;
3188 /* Allocate hardware IRQ controller */
3189 ppc40x_irq_init(env);
3190
3191 SET_FIT_PERIOD(12, 16, 20, 24);
3192 SET_WDT_PERIOD(16, 20, 24, 28);
3193 }
3194
3195 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3196 {
3197 DeviceClass *dc = DEVICE_CLASS(oc);
3198 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3199
3200 dc->desc = "PowerPC 401x2";
3201 pcc->init_proc = init_proc_401x2;
3202 pcc->check_pow = check_pow_nocheck;
3203 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3204 PPC_DCR | PPC_WRTEE |
3205 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3206 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3207 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3208 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3209 PPC_4xx_COMMON | PPC_40x_EXCP;
3210 pcc->insns_flags2 = PPC_NONE;
3211 pcc->msr_mask = 0x00000000001FD231ULL;
3212 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3213 pcc->excp_model = POWERPC_EXCP_40x;
3214 pcc->bus_model = PPC_FLAGS_INPUT_401;
3215 pcc->bfd_mach = bfd_mach_ppc_403;
3216 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3217 POWERPC_FLAG_BUS_CLK;
3218 }
3219
3220 static void init_proc_401x3 (CPUPPCState *env)
3221 {
3222 gen_spr_40x(env);
3223 gen_spr_401_403(env);
3224 gen_spr_401(env);
3225 gen_spr_401x2(env);
3226 gen_spr_compress(env);
3227 init_excp_4xx_softmmu(env);
3228 env->dcache_line_size = 32;
3229 env->icache_line_size = 32;
3230 /* Allocate hardware IRQ controller */
3231 ppc40x_irq_init(env);
3232
3233 SET_FIT_PERIOD(12, 16, 20, 24);
3234 SET_WDT_PERIOD(16, 20, 24, 28);
3235 }
3236
3237 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3238 {
3239 DeviceClass *dc = DEVICE_CLASS(oc);
3240 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3241
3242 dc->desc = "PowerPC 401x3";
3243 pcc->init_proc = init_proc_401x3;
3244 pcc->check_pow = check_pow_nocheck;
3245 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3246 PPC_DCR | PPC_WRTEE |
3247 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3248 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3249 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3250 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3251 PPC_4xx_COMMON | PPC_40x_EXCP;
3252 pcc->insns_flags2 = PPC_NONE;
3253 pcc->msr_mask = 0x00000000001FD631ULL;
3254 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3255 pcc->excp_model = POWERPC_EXCP_40x;
3256 pcc->bus_model = PPC_FLAGS_INPUT_401;
3257 pcc->bfd_mach = bfd_mach_ppc_403;
3258 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3259 POWERPC_FLAG_BUS_CLK;
3260 }
3261
3262 static void init_proc_IOP480 (CPUPPCState *env)
3263 {
3264 gen_spr_40x(env);
3265 gen_spr_401_403(env);
3266 gen_spr_401x2(env);
3267 gen_spr_compress(env);
3268 /* Memory management */
3269 #if !defined(CONFIG_USER_ONLY)
3270 env->nb_tlb = 64;
3271 env->nb_ways = 1;
3272 env->id_tlbs = 0;
3273 env->tlb_type = TLB_EMB;
3274 #endif
3275 init_excp_4xx_softmmu(env);
3276 env->dcache_line_size = 32;
3277 env->icache_line_size = 32;
3278 /* Allocate hardware IRQ controller */
3279 ppc40x_irq_init(env);
3280
3281 SET_FIT_PERIOD(8, 12, 16, 20);
3282 SET_WDT_PERIOD(16, 20, 24, 28);
3283 }
3284
3285 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3286 {
3287 DeviceClass *dc = DEVICE_CLASS(oc);
3288 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3289
3290 dc->desc = "IOP480";
3291 pcc->init_proc = init_proc_IOP480;
3292 pcc->check_pow = check_pow_nocheck;
3293 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3294 PPC_DCR | PPC_WRTEE |
3295 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3296 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3297 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3298 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3299 PPC_4xx_COMMON | PPC_40x_EXCP;
3300 pcc->insns_flags2 = PPC_NONE;
3301 pcc->msr_mask = 0x00000000001FD231ULL;
3302 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3303 pcc->excp_model = POWERPC_EXCP_40x;
3304 pcc->bus_model = PPC_FLAGS_INPUT_401;
3305 pcc->bfd_mach = bfd_mach_ppc_403;
3306 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3307 POWERPC_FLAG_BUS_CLK;
3308 }
3309
3310 static void init_proc_403 (CPUPPCState *env)
3311 {
3312 gen_spr_40x(env);
3313 gen_spr_401_403(env);
3314 gen_spr_403(env);
3315 gen_spr_403_real(env);
3316 init_excp_4xx_real(env);
3317 env->dcache_line_size = 32;
3318 env->icache_line_size = 32;
3319 /* Allocate hardware IRQ controller */
3320 ppc40x_irq_init(env);
3321
3322 SET_FIT_PERIOD(8, 12, 16, 20);
3323 SET_WDT_PERIOD(16, 20, 24, 28);
3324 }
3325
3326 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3327 {
3328 DeviceClass *dc = DEVICE_CLASS(oc);
3329 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3330
3331 dc->desc = "PowerPC 403";
3332 pcc->init_proc = init_proc_403;
3333 pcc->check_pow = check_pow_nocheck;
3334 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3335 PPC_DCR | PPC_WRTEE |
3336 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3337 PPC_CACHE_DCBZ |
3338 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3339 PPC_4xx_COMMON | PPC_40x_EXCP;
3340 pcc->insns_flags2 = PPC_NONE;
3341 pcc->msr_mask = 0x000000000007D00DULL;
3342 pcc->mmu_model = POWERPC_MMU_REAL;
3343 pcc->excp_model = POWERPC_EXCP_40x;
3344 pcc->bus_model = PPC_FLAGS_INPUT_401;
3345 pcc->bfd_mach = bfd_mach_ppc_403;
3346 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3347 POWERPC_FLAG_BUS_CLK;
3348 }
3349
3350 static void init_proc_403GCX (CPUPPCState *env)
3351 {
3352 gen_spr_40x(env);
3353 gen_spr_401_403(env);
3354 gen_spr_403(env);
3355 gen_spr_403_real(env);
3356 gen_spr_403_mmu(env);
3357 /* Bus access control */
3358 /* not emulated, as QEMU never does speculative access */
3359 spr_register(env, SPR_40x_SGR, "SGR",
3360 SPR_NOACCESS, SPR_NOACCESS,
3361 &spr_read_generic, &spr_write_generic,
3362 0xFFFFFFFF);
3363 /* not emulated, as QEMU do not emulate caches */
3364 spr_register(env, SPR_40x_DCWR, "DCWR",
3365 SPR_NOACCESS, SPR_NOACCESS,
3366 &spr_read_generic, &spr_write_generic,
3367 0x00000000);
3368 /* Memory management */
3369 #if !defined(CONFIG_USER_ONLY)
3370 env->nb_tlb = 64;
3371 env->nb_ways = 1;
3372 env->id_tlbs = 0;
3373 env->tlb_type = TLB_EMB;
3374 #endif
3375 init_excp_4xx_softmmu(env);
3376 env->dcache_line_size = 32;
3377 env->icache_line_size = 32;
3378 /* Allocate hardware IRQ controller */
3379 ppc40x_irq_init(env);
3380
3381 SET_FIT_PERIOD(8, 12, 16, 20);
3382 SET_WDT_PERIOD(16, 20, 24, 28);
3383 }
3384
3385 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3386 {
3387 DeviceClass *dc = DEVICE_CLASS(oc);
3388 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3389
3390 dc->desc = "PowerPC 403 GCX";
3391 pcc->init_proc = init_proc_403GCX;
3392 pcc->check_pow = check_pow_nocheck;
3393 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3394 PPC_DCR | PPC_WRTEE |
3395 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3396 PPC_CACHE_DCBZ |
3397 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3398 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3399 PPC_4xx_COMMON | PPC_40x_EXCP;
3400 pcc->insns_flags2 = PPC_NONE;
3401 pcc->msr_mask = 0x000000000007D00DULL;
3402 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3403 pcc->excp_model = POWERPC_EXCP_40x;
3404 pcc->bus_model = PPC_FLAGS_INPUT_401;
3405 pcc->bfd_mach = bfd_mach_ppc_403;
3406 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3407 POWERPC_FLAG_BUS_CLK;
3408 }
3409
3410 static void init_proc_405 (CPUPPCState *env)
3411 {
3412 /* Time base */
3413 gen_tbl(env);
3414 gen_spr_40x(env);
3415 gen_spr_405(env);
3416 /* Bus access control */
3417 /* not emulated, as QEMU never does speculative access */
3418 spr_register(env, SPR_40x_SGR, "SGR",
3419 SPR_NOACCESS, SPR_NOACCESS,
3420 &spr_read_generic, &spr_write_generic,
3421 0xFFFFFFFF);
3422 /* not emulated, as QEMU do not emulate caches */
3423 spr_register(env, SPR_40x_DCWR, "DCWR",
3424 SPR_NOACCESS, SPR_NOACCESS,
3425 &spr_read_generic, &spr_write_generic,
3426 0x00000000);
3427 /* Memory management */
3428 #if !defined(CONFIG_USER_ONLY)
3429 env->nb_tlb = 64;
3430 env->nb_ways = 1;
3431 env->id_tlbs = 0;
3432 env->tlb_type = TLB_EMB;
3433 #endif
3434 init_excp_4xx_softmmu(env);
3435 env->dcache_line_size = 32;
3436 env->icache_line_size = 32;
3437 /* Allocate hardware IRQ controller */
3438 ppc40x_irq_init(env);
3439
3440 SET_FIT_PERIOD(8, 12, 16, 20);
3441 SET_WDT_PERIOD(16, 20, 24, 28);
3442 }
3443
3444 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3445 {
3446 DeviceClass *dc = DEVICE_CLASS(oc);
3447 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3448
3449 dc->desc = "PowerPC 405";
3450 pcc->init_proc = init_proc_405;
3451 pcc->check_pow = check_pow_nocheck;
3452 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3453 PPC_DCR | PPC_WRTEE |
3454 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3455 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3456 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3457 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3458 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3459 pcc->insns_flags2 = PPC_NONE;
3460 pcc->msr_mask = 0x000000000006E630ULL;
3461 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3462 pcc->excp_model = POWERPC_EXCP_40x;
3463 pcc->bus_model = PPC_FLAGS_INPUT_405;
3464 pcc->bfd_mach = bfd_mach_ppc_403;
3465 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3466 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3467 }
3468
3469 static void init_proc_440EP (CPUPPCState *env)
3470 {
3471 /* Time base */
3472 gen_tbl(env);
3473 gen_spr_BookE(env, 0x000000000000FFFFULL);
3474 gen_spr_440(env);
3475 gen_spr_usprgh(env);
3476 /* Processor identification */
3477 spr_register(env, SPR_BOOKE_PIR, "PIR",
3478 SPR_NOACCESS, SPR_NOACCESS,
3479 &spr_read_generic, &spr_write_pir,
3480 0x00000000);
3481 /* XXX : not implemented */
3482 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3483 SPR_NOACCESS, SPR_NOACCESS,
3484 &spr_read_generic, &spr_write_generic,
3485 0x00000000);
3486 /* XXX : not implemented */
3487 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3488 SPR_NOACCESS, SPR_NOACCESS,
3489 &spr_read_generic, &spr_write_generic,
3490 0x00000000);
3491 /* XXX : not implemented */
3492 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3493 SPR_NOACCESS, SPR_NOACCESS,
3494 &spr_read_generic, &spr_write_generic,
3495 0x00000000);
3496 /* XXX : not implemented */
3497 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3498 SPR_NOACCESS, SPR_NOACCESS,
3499 &spr_read_generic, &spr_write_generic,
3500 0x00000000);
3501 /* XXX : not implemented */
3502 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3503 SPR_NOACCESS, SPR_NOACCESS,
3504 &spr_read_generic, &spr_write_generic,
3505 0x00000000);
3506 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3507 SPR_NOACCESS, SPR_NOACCESS,
3508 &spr_read_generic, &spr_write_generic,
3509 0x00000000);
3510 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3511 SPR_NOACCESS, SPR_NOACCESS,
3512 &spr_read_generic, &spr_write_generic,
3513 0x00000000);
3514 /* XXX : not implemented */
3515 spr_register(env, SPR_440_CCR1, "CCR1",
3516 SPR_NOACCESS, SPR_NOACCESS,
3517 &spr_read_generic, &spr_write_generic,
3518 0x00000000);
3519 /* Memory management */
3520 #if !defined(CONFIG_USER_ONLY)
3521 env->nb_tlb = 64;
3522 env->nb_ways = 1;
3523 env->id_tlbs = 0;
3524 env->tlb_type = TLB_EMB;
3525 #endif
3526 init_excp_BookE(env);
3527 env->dcache_line_size = 32;
3528 env->icache_line_size = 32;
3529 ppc40x_irq_init(env);
3530
3531 SET_FIT_PERIOD(12, 16, 20, 24);
3532 SET_WDT_PERIOD(20, 24, 28, 32);
3533 }
3534
3535 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3536 {
3537 DeviceClass *dc = DEVICE_CLASS(oc);
3538 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3539
3540 dc->desc = "PowerPC 440 EP";
3541 pcc->init_proc = init_proc_440EP;
3542 pcc->check_pow = check_pow_nocheck;
3543 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3544 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3545 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3546 PPC_FLOAT_STFIWX |
3547 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3548 PPC_CACHE | PPC_CACHE_ICBI |
3549 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3550 PPC_MEM_TLBSYNC | PPC_MFTB |
3551 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3552 PPC_440_SPEC;
3553 pcc->insns_flags2 = PPC_NONE;
3554 pcc->msr_mask = 0x000000000006FF30ULL;
3555 pcc->mmu_model = POWERPC_MMU_BOOKE;
3556 pcc->excp_model = POWERPC_EXCP_BOOKE;
3557 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3558 pcc->bfd_mach = bfd_mach_ppc_403;
3559 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3560 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3561 }
3562
3563 static void init_proc_440GP (CPUPPCState *env)
3564 {
3565 /* Time base */
3566 gen_tbl(env);
3567 gen_spr_BookE(env, 0x000000000000FFFFULL);
3568 gen_spr_440(env);
3569 gen_spr_usprgh(env);
3570 /* Processor identification */
3571 spr_register(env, SPR_BOOKE_PIR, "PIR",
3572 SPR_NOACCESS, SPR_NOACCESS,
3573 &spr_read_generic, &spr_write_pir,
3574 0x00000000);
3575 /* XXX : not implemented */
3576 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3577 SPR_NOACCESS, SPR_NOACCESS,
3578 &spr_read_generic, &spr_write_generic,
3579 0x00000000);
3580 /* XXX : not implemented */
3581 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3582 SPR_NOACCESS, SPR_NOACCESS,
3583 &spr_read_generic, &spr_write_generic,
3584 0x00000000);
3585 /* XXX : not implemented */
3586 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3587 SPR_NOACCESS, SPR_NOACCESS,
3588 &spr_read_generic, &spr_write_generic,
3589 0x00000000);
3590 /* XXX : not implemented */
3591 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3592 SPR_NOACCESS, SPR_NOACCESS,
3593 &spr_read_generic, &spr_write_generic,
3594 0x00000000);
3595 /* Memory management */
3596 #if !defined(CONFIG_USER_ONLY)
3597 env->nb_tlb = 64;
3598 env->nb_ways = 1;
3599 env->id_tlbs = 0;
3600 env->tlb_type = TLB_EMB;
3601 #endif
3602 init_excp_BookE(env);
3603 env->dcache_line_size = 32;
3604 env->icache_line_size = 32;
3605 /* XXX: TODO: allocate internal IRQ controller */
3606
3607 SET_FIT_PERIOD(12, 16, 20, 24);
3608 SET_WDT_PERIOD(20, 24, 28, 32);
3609 }
3610
3611 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3612 {
3613 DeviceClass *dc = DEVICE_CLASS(oc);
3614 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3615
3616 dc->desc = "PowerPC 440 GP";
3617 pcc->init_proc = init_proc_440GP;
3618 pcc->check_pow = check_pow_nocheck;
3619 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3620 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3621 PPC_CACHE | PPC_CACHE_ICBI |
3622 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3623 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3624 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3625 PPC_440_SPEC;
3626 pcc->insns_flags2 = PPC_NONE;
3627 pcc->msr_mask = 0x000000000006FF30ULL;
3628 pcc->mmu_model = POWERPC_MMU_BOOKE;
3629 pcc->excp_model = POWERPC_EXCP_BOOKE;
3630 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3631 pcc->bfd_mach = bfd_mach_ppc_403;
3632 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3633 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3634 }
3635
3636 static void init_proc_440x4 (CPUPPCState *env)
3637 {
3638 /* Time base */
3639 gen_tbl(env);
3640 gen_spr_BookE(env, 0x000000000000FFFFULL);
3641 gen_spr_440(env);
3642 gen_spr_usprgh(env);
3643 /* Processor identification */
3644 spr_register(env, SPR_BOOKE_PIR, "PIR",
3645 SPR_NOACCESS, SPR_NOACCESS,
3646 &spr_read_generic, &spr_write_pir,
3647 0x00000000);
3648 /* XXX : not implemented */
3649 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3650 SPR_NOACCESS, SPR_NOACCESS,
3651 &spr_read_generic, &spr_write_generic,
3652 0x00000000);
3653 /* XXX : not implemented */
3654 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3655 SPR_NOACCESS, SPR_NOACCESS,
3656 &spr_read_generic, &spr_write_generic,
3657 0x00000000);
3658 /* XXX : not implemented */
3659 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3660 SPR_NOACCESS, SPR_NOACCESS,
3661 &spr_read_generic, &spr_write_generic,
3662 0x00000000);
3663 /* XXX : not implemented */
3664 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3665 SPR_NOACCESS, SPR_NOACCESS,
3666 &spr_read_generic, &spr_write_generic,
3667 0x00000000);
3668 /* Memory management */
3669 #if !defined(CONFIG_USER_ONLY)
3670 env->nb_tlb = 64;
3671 env->nb_ways = 1;
3672 env->id_tlbs = 0;
3673 env->tlb_type = TLB_EMB;
3674 #endif
3675 init_excp_BookE(env);
3676 env->dcache_line_size = 32;
3677 env->icache_line_size = 32;
3678 /* XXX: TODO: allocate internal IRQ controller */
3679
3680 SET_FIT_PERIOD(12, 16, 20, 24);
3681 SET_WDT_PERIOD(20, 24, 28, 32);
3682 }
3683
3684 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3685 {
3686 DeviceClass *dc = DEVICE_CLASS(oc);
3687 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3688
3689 dc->desc = "PowerPC 440x4";
3690 pcc->init_proc = init_proc_440x4;
3691 pcc->check_pow = check_pow_nocheck;
3692 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3693 PPC_DCR | PPC_WRTEE |
3694 PPC_CACHE | PPC_CACHE_ICBI |
3695 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3696 PPC_MEM_TLBSYNC | PPC_MFTB |
3697 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3698 PPC_440_SPEC;
3699 pcc->insns_flags2 = PPC_NONE;
3700 pcc->msr_mask = 0x000000000006FF30ULL;
3701 pcc->mmu_model = POWERPC_MMU_BOOKE;
3702 pcc->excp_model = POWERPC_EXCP_BOOKE;
3703 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3704 pcc->bfd_mach = bfd_mach_ppc_403;
3705 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3706 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3707 }
3708
3709 static void init_proc_440x5 (CPUPPCState *env)
3710 {
3711 /* Time base */
3712 gen_tbl(env);
3713 gen_spr_BookE(env, 0x000000000000FFFFULL);
3714 gen_spr_440(env);
3715 gen_spr_usprgh(env);
3716 /* Processor identification */
3717 spr_register(env, SPR_BOOKE_PIR, "PIR",
3718 SPR_NOACCESS, SPR_NOACCESS,
3719 &spr_read_generic, &spr_write_pir,
3720 0x00000000);
3721 /* XXX : not implemented */
3722 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3723 SPR_NOACCESS, SPR_NOACCESS,
3724 &spr_read_generic, &spr_write_generic,
3725 0x00000000);
3726 /* XXX : not implemented */
3727 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3728 SPR_NOACCESS, SPR_NOACCESS,
3729 &spr_read_generic, &spr_write_generic,
3730 0x00000000);
3731 /* XXX : not implemented */
3732 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3733 SPR_NOACCESS, SPR_NOACCESS,
3734 &spr_read_generic, &spr_write_generic,
3735 0x00000000);
3736 /* XXX : not implemented */
3737 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3738 SPR_NOACCESS, SPR_NOACCESS,
3739 &spr_read_generic, &spr_write_generic,
3740 0x00000000);
3741 /* XXX : not implemented */
3742 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3743 SPR_NOACCESS, SPR_NOACCESS,
3744 &spr_read_generic, &spr_write_generic,
3745 0x00000000);
3746 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3747 SPR_NOACCESS, SPR_NOACCESS,
3748 &spr_read_generic, &spr_write_generic,
3749 0x00000000);
3750 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3751 SPR_NOACCESS, SPR_NOACCESS,
3752 &spr_read_generic, &spr_write_generic,
3753 0x00000000);
3754 /* XXX : not implemented */
3755 spr_register(env, SPR_440_CCR1, "CCR1",
3756 SPR_NOACCESS, SPR_NOACCESS,
3757 &spr_read_generic, &spr_write_generic,
3758 0x00000000);
3759 /* Memory management */
3760 #if !defined(CONFIG_USER_ONLY)
3761 env->nb_tlb = 64;
3762 env->nb_ways = 1;
3763 env->id_tlbs = 0;
3764 env->tlb_type = TLB_EMB;
3765 #endif
3766 init_excp_BookE(env);
3767 env->dcache_line_size = 32;
3768 env->icache_line_size = 32;
3769 ppc40x_irq_init(env);
3770
3771 SET_FIT_PERIOD(12, 16, 20, 24);
3772 SET_WDT_PERIOD(20, 24, 28, 32);
3773 }
3774
3775 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3776 {
3777 DeviceClass *dc = DEVICE_CLASS(oc);
3778 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3779
3780 dc->desc = "PowerPC 440x5";
3781 pcc->init_proc = init_proc_440x5;
3782 pcc->check_pow = check_pow_nocheck;
3783 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3784 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3785 PPC_CACHE | PPC_CACHE_ICBI |
3786 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3787 PPC_MEM_TLBSYNC | PPC_MFTB |
3788 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3789 PPC_440_SPEC;
3790 pcc->insns_flags2 = PPC_NONE;
3791 pcc->msr_mask = 0x000000000006FF30ULL;
3792 pcc->mmu_model = POWERPC_MMU_BOOKE;
3793 pcc->excp_model = POWERPC_EXCP_BOOKE;
3794 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3795 pcc->bfd_mach = bfd_mach_ppc_403;
3796 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3797 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3798 }
3799
3800 static void init_proc_460 (CPUPPCState *env)
3801 {
3802 /* Time base */
3803 gen_tbl(env);
3804 gen_spr_BookE(env, 0x000000000000FFFFULL);
3805 gen_spr_440(env);
3806 gen_spr_usprgh(env);
3807 /* Processor identification */
3808 spr_register(env, SPR_BOOKE_PIR, "PIR",
3809 SPR_NOACCESS, SPR_NOACCESS,
3810 &spr_read_generic, &spr_write_pir,
3811 0x00000000);
3812 /* XXX : not implemented */
3813 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3814 SPR_NOACCESS, SPR_NOACCESS,
3815 &spr_read_generic, &spr_write_generic,
3816 0x00000000);
3817 /* XXX : not implemented */
3818 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3819 SPR_NOACCESS, SPR_NOACCESS,
3820 &spr_read_generic, &spr_write_generic,
3821 0x00000000);
3822 /* XXX : not implemented */
3823 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3824 SPR_NOACCESS, SPR_NOACCESS,
3825 &spr_read_generic, &spr_write_generic,
3826 0x00000000);
3827 /* XXX : not implemented */
3828 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3829 SPR_NOACCESS, SPR_NOACCESS,
3830 &spr_read_generic, &spr_write_generic,
3831 0x00000000);
3832 /* XXX : not implemented */
3833 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3834 SPR_NOACCESS, SPR_NOACCESS,
3835 &spr_read_generic, &spr_write_generic,
3836 0x00000000);
3837 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3838 SPR_NOACCESS, SPR_NOACCESS,
3839 &spr_read_generic, &spr_write_generic,
3840 0x00000000);
3841 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3842 SPR_NOACCESS, SPR_NOACCESS,
3843 &spr_read_generic, &spr_write_generic,
3844 0x00000000);
3845 /* XXX : not implemented */
3846 spr_register(env, SPR_440_CCR1, "CCR1",
3847 SPR_NOACCESS, SPR_NOACCESS,
3848 &spr_read_generic, &spr_write_generic,
3849 0x00000000);
3850 /* XXX : not implemented */
3851 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3852 &spr_read_generic, &spr_write_generic,
3853 &spr_read_generic, &spr_write_generic,
3854 0x00000000);
3855 /* Memory management */
3856 #if !defined(CONFIG_USER_ONLY)
3857 env->nb_tlb = 64;
3858 env->nb_ways = 1;
3859 env->id_tlbs = 0;
3860 env->tlb_type = TLB_EMB;
3861 #endif
3862 init_excp_BookE(env);
3863 env->dcache_line_size = 32;
3864 env->icache_line_size = 32;
3865 /* XXX: TODO: allocate internal IRQ controller */
3866
3867 SET_FIT_PERIOD(12, 16, 20, 24);
3868 SET_WDT_PERIOD(20, 24, 28, 32);
3869 }
3870
3871 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
3872 {
3873 DeviceClass *dc = DEVICE_CLASS(oc);
3874 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3875
3876 dc->desc = "PowerPC 460 (guessed)";
3877 pcc->init_proc = init_proc_460;
3878 pcc->check_pow = check_pow_nocheck;
3879 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3880 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3881 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
3882 PPC_CACHE | PPC_CACHE_ICBI |
3883 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3884 PPC_MEM_TLBSYNC | PPC_TLBIVA |
3885 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3886 PPC_440_SPEC;
3887 pcc->insns_flags2 = PPC_NONE;
3888 pcc->msr_mask = 0x000000000006FF30ULL;
3889 pcc->mmu_model = POWERPC_MMU_BOOKE;
3890 pcc->excp_model = POWERPC_EXCP_BOOKE;
3891 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3892 pcc->bfd_mach = bfd_mach_ppc_403;
3893 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3894 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3895 }
3896
3897 static void init_proc_460F (CPUPPCState *env)
3898 {
3899 /* Time base */
3900 gen_tbl(env);
3901 gen_spr_BookE(env, 0x000000000000FFFFULL);
3902 gen_spr_440(env);
3903 gen_spr_usprgh(env);
3904 /* Processor identification */
3905 spr_register(env, SPR_BOOKE_PIR, "PIR",
3906 SPR_NOACCESS, SPR_NOACCESS,
3907 &spr_read_generic, &spr_write_pir,
3908 0x00000000);
3909 /* XXX : not implemented */
3910 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3911 SPR_NOACCESS, SPR_NOACCESS,
3912 &spr_read_generic, &spr_write_generic,
3913 0x00000000);
3914 /* XXX : not implemented */
3915 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3916 SPR_NOACCESS, SPR_NOACCESS,
3917 &spr_read_generic, &spr_write_generic,
3918 0x00000000);
3919 /* XXX : not implemented */
3920 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3921 SPR_NOACCESS, SPR_NOACCESS,
3922 &spr_read_generic, &spr_write_generic,
3923 0x00000000);
3924 /* XXX : not implemented */
3925 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3926 SPR_NOACCESS, SPR_NOACCESS,
3927 &spr_read_generic, &spr_write_generic,
3928 0x00000000);
3929 /* XXX : not implemented */
3930 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3931 SPR_NOACCESS, SPR_NOACCESS,
3932 &spr_read_generic, &spr_write_generic,
3933 0x00000000);
3934 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3935 SPR_NOACCESS, SPR_NOACCESS,
3936 &spr_read_generic, &spr_write_generic,
3937 0x00000000);
3938 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3939 SPR_NOACCESS, SPR_NOACCESS,
3940 &spr_read_generic, &spr_write_generic,
3941 0x00000000);
3942 /* XXX : not implemented */
3943 spr_register(env, SPR_440_CCR1, "CCR1",
3944 SPR_NOACCESS, SPR_NOACCESS,
3945 &spr_read_generic, &spr_write_generic,
3946 0x00000000);
3947 /* XXX : not implemented */
3948 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3949 &spr_read_generic, &spr_write_generic,
3950 &spr_read_generic, &spr_write_generic,
3951 0x00000000);
3952 /* Memory management */
3953 #if !defined(CONFIG_USER_ONLY)
3954 env->nb_tlb = 64;
3955 env->nb_ways = 1;
3956 env->id_tlbs = 0;
3957 env->tlb_type = TLB_EMB;
3958 #endif
3959 init_excp_BookE(env);
3960 env->dcache_line_size = 32;
3961 env->icache_line_size = 32;
3962 /* XXX: TODO: allocate internal IRQ controller */
3963
3964 SET_FIT_PERIOD(12, 16, 20, 24);
3965 SET_WDT_PERIOD(20, 24, 28, 32);
3966 }
3967
3968 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
3969 {
3970 DeviceClass *dc = DEVICE_CLASS(oc);
3971 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3972
3973 dc->desc = "PowerPC 460F (guessed)";
3974 pcc->init_proc = init_proc_460F;
3975 pcc->check_pow = check_pow_nocheck;
3976 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3977 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3978 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3979 PPC_FLOAT_STFIWX | PPC_MFTB |
3980 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3981 PPC_WRTEE | PPC_MFAPIDI |
3982 PPC_CACHE | PPC_CACHE_ICBI |
3983 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3984 PPC_MEM_TLBSYNC | PPC_TLBIVA |
3985 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3986 PPC_440_SPEC;
3987 pcc->insns_flags2 = PPC_NONE;
3988 pcc->msr_mask = 0x000000000006FF30ULL;
3989 pcc->mmu_model = POWERPC_MMU_BOOKE;
3990 pcc->excp_model = POWERPC_EXCP_BOOKE;
3991 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3992 pcc->bfd_mach = bfd_mach_ppc_403;
3993 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3994 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3995 }
3996
3997 static void init_proc_MPC5xx (CPUPPCState *env)
3998 {
3999 /* Time base */
4000 gen_tbl(env);
4001 gen_spr_5xx_8xx(env);
4002 gen_spr_5xx(env);
4003 init_excp_MPC5xx(env);
4004 env->dcache_line_size = 32;
4005 env->icache_line_size = 32;
4006 /* XXX: TODO: allocate internal IRQ controller */
4007 }
4008
4009 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4010 {
4011 DeviceClass *dc = DEVICE_CLASS(oc);
4012 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4013
4014 dc->desc = "Freescale 5xx cores (aka RCPU)";
4015 pcc->init_proc = init_proc_MPC5xx;
4016 pcc->check_pow = check_pow_none;
4017 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4018 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4019 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4020 PPC_MFTB;
4021 pcc->insns_flags2 = PPC_NONE;
4022 pcc->msr_mask = 0x000000000001FF43ULL;
4023 pcc->mmu_model = POWERPC_MMU_REAL;
4024 pcc->excp_model = POWERPC_EXCP_603;
4025 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4026 pcc->bfd_mach = bfd_mach_ppc_505;
4027 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4028 POWERPC_FLAG_BUS_CLK;
4029 }
4030
4031 static void init_proc_MPC8xx (CPUPPCState *env)
4032 {
4033 /* Time base */
4034 gen_tbl(env);
4035 gen_spr_5xx_8xx(env);
4036 gen_spr_8xx(env);
4037 init_excp_MPC8xx(env);
4038 env->dcache_line_size = 32;
4039 env->icache_line_size = 32;
4040 /* XXX: TODO: allocate internal IRQ controller */
4041 }
4042
4043 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4044 {
4045 DeviceClass *dc = DEVICE_CLASS(oc);
4046 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4047
4048 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4049 pcc->init_proc = init_proc_MPC8xx;
4050 pcc->check_pow = check_pow_none;
4051 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4052 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4053 PPC_CACHE_ICBI | PPC_MFTB;
4054 pcc->insns_flags2 = PPC_NONE;
4055 pcc->msr_mask = 0x000000000001F673ULL;
4056 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4057 pcc->excp_model = POWERPC_EXCP_603;
4058 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4059 pcc->bfd_mach = bfd_mach_ppc_860;
4060 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4061 POWERPC_FLAG_BUS_CLK;
4062 }
4063
4064 /* Freescale 82xx cores (aka PowerQUICC-II) */
4065
4066 static void init_proc_G2 (CPUPPCState *env)
4067 {
4068 gen_spr_ne_601(env);
4069 gen_spr_G2_755(env);
4070 gen_spr_G2(env);
4071 /* Time base */
4072 gen_tbl(env);
4073 /* External access control */
4074 /* XXX : not implemented */
4075 spr_register(env, SPR_EAR, "EAR",
4076 SPR_NOACCESS, SPR_NOACCESS,
4077 &spr_read_generic, &spr_write_generic,
4078 0x00000000);
4079 /* Hardware implementation register */
4080 /* XXX : not implemented */
4081 spr_register(env, SPR_HID0, "HID0",
4082 SPR_NOACCESS, SPR_NOACCESS,
4083 &spr_read_generic, &spr_write_generic,
4084 0x00000000);
4085 /* XXX : not implemented */
4086 spr_register(env, SPR_HID1, "HID1",
4087 SPR_NOACCESS, SPR_NOACCESS,
4088 &spr_read_generic, &spr_write_generic,
4089 0x00000000);
4090 /* XXX : not implemented */
4091 spr_register(env, SPR_HID2, "HID2",
4092 SPR_NOACCESS, SPR_NOACCESS,
4093 &spr_read_generic, &spr_write_generic,
4094 0x00000000);
4095 /* Memory management */
4096 gen_low_BATs(env);
4097 gen_high_BATs(env);
4098 gen_6xx_7xx_soft_tlb(env, 64, 2);
4099 init_excp_G2(env);
4100 env->dcache_line_size = 32;
4101 env->icache_line_size = 32;
4102 /* Allocate hardware IRQ controller */
4103 ppc6xx_irq_init(env);
4104 }
4105
4106 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4107 {
4108 DeviceClass *dc = DEVICE_CLASS(oc);
4109 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4110
4111 dc->desc = "PowerPC G2";
4112 pcc->init_proc = init_proc_G2;
4113 pcc->check_pow = check_pow_hid0;
4114 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4115 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4116 PPC_FLOAT_STFIWX |
4117 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4118 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4119 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4120 PPC_SEGMENT | PPC_EXTERN;
4121 pcc->insns_flags2 = PPC_NONE;
4122 pcc->msr_mask = 0x000000000006FFF2ULL;
4123 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4124 pcc->excp_model = POWERPC_EXCP_G2;
4125 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4126 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4127 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4128 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4129 }
4130
4131 static void init_proc_G2LE (CPUPPCState *env)
4132 {
4133 gen_spr_ne_601(env);
4134 gen_spr_G2_755(env);
4135 gen_spr_G2(env);
4136 /* Time base */
4137 gen_tbl(env);
4138 /* External access control */
4139 /* XXX : not implemented */
4140 spr_register(env, SPR_EAR, "EAR",
4141 SPR_NOACCESS, SPR_NOACCESS,
4142 &spr_read_generic, &spr_write_generic,
4143 0x00000000);
4144 /* Hardware implementation register */
4145 /* XXX : not implemented */
4146 spr_register(env, SPR_HID0, "HID0",
4147 SPR_NOACCESS, SPR_NOACCESS,
4148 &spr_read_generic, &spr_write_generic,
4149 0x00000000);
4150 /* XXX : not implemented */
4151 spr_register(env, SPR_HID1, "HID1",
4152 SPR_NOACCESS, SPR_NOACCESS,
4153 &spr_read_generic, &spr_write_generic,
4154 0x00000000);
4155 /* XXX : not implemented */
4156 spr_register(env, SPR_HID2, "HID2",
4157 SPR_NOACCESS, SPR_NOACCESS,
4158 &spr_read_generic, &spr_write_generic,
4159 0x00000000);
4160 /* Memory management */
4161 gen_low_BATs(env);
4162 gen_high_BATs(env);
4163 gen_6xx_7xx_soft_tlb(env, 64, 2);
4164 init_excp_G2(env);
4165 env->dcache_line_size = 32;
4166 env->icache_line_size = 32;
4167 /* Allocate hardware IRQ controller */
4168 ppc6xx_irq_init(env);
4169 }
4170
4171 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4172 {
4173 DeviceClass *dc = DEVICE_CLASS(oc);
4174 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4175
4176 dc->desc = "PowerPC G2LE";
4177 pcc->init_proc = init_proc_G2LE;
4178 pcc->check_pow = check_pow_hid0;
4179 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4180 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4181 PPC_FLOAT_STFIWX |
4182 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4183 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4184 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4185 PPC_SEGMENT | PPC_EXTERN;
4186 pcc->insns_flags2 = PPC_NONE;
4187 pcc->msr_mask = 0x000000000007FFF3ULL;
4188 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4189 pcc->excp_model = POWERPC_EXCP_G2;
4190 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4191 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4192 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4193 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4194 }
4195
4196 static void init_proc_e200 (CPUPPCState *env)
4197 {
4198 /* Time base */
4199 gen_tbl(env);
4200 gen_spr_BookE(env, 0x000000070000FFFFULL);
4201 /* XXX : not implemented */
4202 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4203 &spr_read_spefscr, &spr_write_spefscr,
4204 &spr_read_spefscr, &spr_write_spefscr,
4205 0x00000000);
4206 /* Memory management */
4207 gen_spr_BookE206(env, 0x0000005D, NULL);
4208 /* XXX : not implemented */
4209 spr_register(env, SPR_HID0, "HID0",
4210 SPR_NOACCESS, SPR_NOACCESS,
4211 &spr_read_generic, &spr_write_generic,
4212 0x00000000);
4213 /* XXX : not implemented */
4214 spr_register(env, SPR_HID1, "HID1",
4215 SPR_NOACCESS, SPR_NOACCESS,
4216 &spr_read_generic, &spr_write_generic,
4217 0x00000000);
4218 /* XXX : not implemented */
4219 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4220 SPR_NOACCESS, SPR_NOACCESS,
4221 &spr_read_generic, &spr_write_generic,
4222 0x00000000);
4223 /* XXX : not implemented */
4224 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4225 SPR_NOACCESS, SPR_NOACCESS,
4226 &spr_read_generic, &spr_write_generic,
4227 0x00000000);
4228 /* XXX : not implemented */
4229 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4230 SPR_NOACCESS, SPR_NOACCESS,
4231 &spr_read_generic, &spr_write_generic,
4232 0x00000000);
4233 /* XXX : not implemented */
4234 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4235 SPR_NOACCESS, SPR_NOACCESS,
4236 &spr_read_generic, &spr_write_generic,
4237 0x00000000);
4238 /* XXX : not implemented */
4239 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4240 SPR_NOACCESS, SPR_NOACCESS,
4241 &spr_read_generic, &spr_write_generic,
4242 0x00000000);
4243 /* XXX : not implemented */
4244 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4245 SPR_NOACCESS, SPR_NOACCESS,
4246 &spr_read_generic, &spr_write_generic,
4247 0x00000000);
4248 /* XXX : not implemented */
4249 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4250 SPR_NOACCESS, SPR_NOACCESS,
4251 &spr_read_generic, &spr_write_generic,
4252 0x00000000);
4253 /* XXX : not implemented */
4254 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4255 SPR_NOACCESS, SPR_NOACCESS,
4256 &spr_read_generic, &spr_write_generic,
4257 0x00000000);
4258 /* XXX : not implemented */
4259 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4260 SPR_NOACCESS, SPR_NOACCESS,
4261 &spr_read_generic, &spr_write_generic,
4262 0x00000000);
4263 /* XXX : not implemented */
4264 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4265 SPR_NOACCESS, SPR_NOACCESS,
4266 &spr_read_generic, &spr_write_generic,
4267 0x00000000);
4268 /* XXX : not implemented */
4269 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4270 SPR_NOACCESS, SPR_NOACCESS,
4271 &spr_read_generic, &spr_write_generic,
4272 0x00000000);
4273 /* XXX : not implemented */
4274 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4275 SPR_NOACCESS, SPR_NOACCESS,
4276 &spr_read_generic, &spr_write_generic,
4277 0x00000000);
4278 /* XXX : not implemented */
4279 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4280 SPR_NOACCESS, SPR_NOACCESS,
4281 &spr_read_generic, &spr_write_generic,
4282 0x00000000); /* TOFIX */
4283 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4284 SPR_NOACCESS, SPR_NOACCESS,
4285 &spr_read_generic, &spr_write_generic,
4286 0x00000000);
4287 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4288 SPR_NOACCESS, SPR_NOACCESS,
4289 &spr_read_generic, &spr_write_generic,
4290 0x00000000);
4291 #if !defined(CONFIG_USER_ONLY)
4292 env->nb_tlb = 64;
4293 env->nb_ways = 1;
4294 env->id_tlbs = 0;
4295 env->tlb_type = TLB_EMB;
4296 #endif
4297 init_excp_e200(env, 0xFFFF0000UL);
4298 env->dcache_line_size = 32;
4299 env->icache_line_size = 32;
4300 /* XXX: TODO: allocate internal IRQ controller */
4301 }
4302
4303 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4304 {
4305 DeviceClass *dc = DEVICE_CLASS(oc);
4306 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4307
4308 dc->desc = "e200 core";
4309 pcc->init_proc = init_proc_e200;
4310 pcc->check_pow = check_pow_hid0;
4311 /* XXX: unimplemented instructions:
4312 * dcblc
4313 * dcbtlst
4314 * dcbtstls
4315 * icblc
4316 * icbtls
4317 * tlbivax
4318 * all SPE multiply-accumulate instructions
4319 */
4320 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4321 PPC_SPE | PPC_SPE_SINGLE |
4322 PPC_WRTEE | PPC_RFDI |
4323 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4324 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4325 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4326 PPC_BOOKE;
4327 pcc->insns_flags2 = PPC_NONE;
4328 pcc->msr_mask = 0x000000000606FF30ULL;
4329 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4330 pcc->excp_model = POWERPC_EXCP_BOOKE;
4331 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4332 pcc->bfd_mach = bfd_mach_ppc_860;
4333 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4334 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4335 POWERPC_FLAG_BUS_CLK;
4336 }
4337
4338 static void init_proc_e300 (CPUPPCState *env)
4339 {
4340 gen_spr_ne_601(env);
4341 gen_spr_603(env);
4342 /* Time base */
4343 gen_tbl(env);
4344 /* hardware implementation registers */
4345 /* XXX : not implemented */
4346 spr_register(env, SPR_HID0, "HID0",
4347 SPR_NOACCESS, SPR_NOACCESS,
4348 &spr_read_generic, &spr_write_generic,
4349 0x00000000);
4350 /* XXX : not implemented */
4351 spr_register(env, SPR_HID1, "HID1",
4352 SPR_NOACCESS, SPR_NOACCESS,
4353 &spr_read_generic, &spr_write_generic,
4354 0x00000000);
4355 /* XXX : not implemented */
4356 spr_register(env, SPR_HID2, "HID2",
4357 SPR_NOACCESS, SPR_NOACCESS,
4358 &spr_read_generic, &spr_write_generic,
4359 0x00000000);
4360 /* Memory management */
4361 gen_low_BATs(env);
4362 gen_high_BATs(env);
4363 gen_6xx_7xx_soft_tlb(env, 64, 2);
4364 init_excp_603(env);
4365 env->dcache_line_size = 32;
4366 env->icache_line_size = 32;
4367 /* Allocate hardware IRQ controller */
4368 ppc6xx_irq_init(env);
4369 }
4370
4371 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4372 {
4373 DeviceClass *dc = DEVICE_CLASS(oc);
4374 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4375
4376 dc->desc = "e300 core";
4377 pcc->init_proc = init_proc_e300;
4378 pcc->check_pow = check_pow_hid0;
4379 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4380 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4381 PPC_FLOAT_STFIWX |
4382 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4383 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4384 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4385 PPC_SEGMENT | PPC_EXTERN;
4386 pcc->insns_flags2 = PPC_NONE;
4387 pcc->msr_mask = 0x000000000007FFF3ULL;
4388 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4389 pcc->excp_model = POWERPC_EXCP_603;
4390 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4391 pcc->bfd_mach = bfd_mach_ppc_603;
4392 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4393 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4394 }
4395
4396 #if !defined(CONFIG_USER_ONLY)
4397 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4398 {
4399 TCGv val = tcg_temp_new();
4400 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4401 gen_store_spr(SPR_BOOKE_MAS3, val);
4402 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4403 gen_store_spr(SPR_BOOKE_MAS7, val);
4404 tcg_temp_free(val);
4405 }
4406
4407 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4408 {
4409 TCGv mas7 = tcg_temp_new();
4410 TCGv mas3 = tcg_temp_new();
4411 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4412 tcg_gen_shli_tl(mas7, mas7, 32);
4413 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4414 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4415 tcg_temp_free(mas3);
4416 tcg_temp_free(mas7);
4417 }
4418
4419 #endif
4420
4421 enum fsl_e500_version {
4422 fsl_e500v1,
4423 fsl_e500v2,
4424 fsl_e500mc,
4425 fsl_e5500,
4426 };
4427
4428 static void init_proc_e500 (CPUPPCState *env, int version)
4429 {
4430 uint32_t tlbncfg[2];
4431 uint64_t ivor_mask;
4432 uint64_t ivpr_mask = 0xFFFF0000ULL;
4433 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4434 | 0x0020; /* 32 kb */
4435 #if !defined(CONFIG_USER_ONLY)
4436 int i;
4437 #endif
4438
4439 /* Time base */
4440 gen_tbl(env);
4441 /*
4442 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4443 * complain when accessing them.
4444 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4445 */
4446 switch (version) {
4447 case fsl_e500v1:
4448 case fsl_e500v2:
4449 default:
4450 ivor_mask = 0x0000000F0000FFFFULL;
4451 break;
4452 case fsl_e500mc:
4453 case fsl_e5500:
4454 ivor_mask = 0x000003FE0000FFFFULL;
4455 break;
4456 }
4457 gen_spr_BookE(env, ivor_mask);
4458 /* Processor identification */
4459 spr_register(env, SPR_BOOKE_PIR, "PIR",
4460 SPR_NOACCESS, SPR_NOACCESS,
4461 &spr_read_generic, &spr_write_pir,
4462 0x00000000);
4463 /* XXX : not implemented */
4464 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4465 &spr_read_spefscr, &spr_write_spefscr,
4466 &spr_read_spefscr, &spr_write_spefscr,
4467 0x00000000);
4468 #if !defined(CONFIG_USER_ONLY)
4469 /* Memory management */
4470 env->nb_pids = 3;
4471 env->nb_ways = 2;
4472 env->id_tlbs = 0;
4473 switch (version) {
4474 case fsl_e500v1:
4475 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4476 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4477 break;
4478 case fsl_e500v2:
4479 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4480 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4481 break;
4482 case fsl_e500mc:
4483 case fsl_e5500:
4484 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4485 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4486 break;
4487 default:
4488 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4489 }
4490 #endif
4491 /* Cache sizes */
4492 switch (version) {
4493 case fsl_e500v1:
4494 case fsl_e500v2:
4495 env->dcache_line_size = 32;
4496 env->icache_line_size = 32;
4497 break;
4498 case fsl_e500mc:
4499 case fsl_e5500:
4500 env->dcache_line_size = 64;
4501 env->icache_line_size = 64;
4502 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4503 break;
4504 default:
4505 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4506 }
4507 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4508 /* XXX : not implemented */
4509 spr_register(env, SPR_HID0, "HID0",
4510 SPR_NOACCESS, SPR_NOACCESS,
4511 &spr_read_generic, &spr_write_generic,
4512 0x00000000);
4513 /* XXX : not implemented */
4514 spr_register(env, SPR_HID1, "HID1",
4515 SPR_NOACCESS, SPR_NOACCESS,
4516 &spr_read_generic, &spr_write_generic,
4517 0x00000000);
4518 /* XXX : not implemented */
4519 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4520 SPR_NOACCESS, SPR_NOACCESS,
4521 &spr_read_generic, &spr_write_generic,
4522 0x00000000);
4523 /* XXX : not implemented */
4524 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4525 SPR_NOACCESS, SPR_NOACCESS,
4526 &spr_read_generic, &spr_write_generic,
4527 0x00000000);
4528 /* XXX : not implemented */
4529 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4530 SPR_NOACCESS, SPR_NOACCESS,
4531 &spr_read_generic, &spr_write_generic,
4532 0x00000000);
4533 /* XXX : not implemented */
4534 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4535 SPR_NOACCESS, SPR_NOACCESS,
4536 &spr_read_generic, &spr_write_generic,
4537 0x00000000);
4538 /* XXX : not implemented */
4539 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4540 SPR_NOACCESS, SPR_NOACCESS,
4541 &spr_read_generic, &spr_write_generic,
4542 0x00000000);
4543 /* XXX : not implemented */
4544 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4545 SPR_NOACCESS, SPR_NOACCESS,
4546 &spr_read_generic, &spr_write_generic,
4547 0x00000000);
4548 /* XXX : not implemented */
4549 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4550 SPR_NOACCESS, SPR_NOACCESS,
4551 &spr_read_generic, &spr_write_generic,
4552 l1cfg0);
4553 /* XXX : not implemented */
4554 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4555 SPR_NOACCESS, SPR_NOACCESS,
4556 &spr_read_generic, &spr_write_e500_l1csr0,
4557 0x00000000);
4558 /* XXX : not implemented */
4559 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4560 SPR_NOACCESS, SPR_NOACCESS,
4561 &spr_read_generic, &spr_write_generic,
4562 0x00000000);
4563 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4564 SPR_NOACCESS, SPR_NOACCESS,
4565 &spr_read_generic, &spr_write_generic,
4566 0x00000000);
4567 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4568 SPR_NOACCESS, SPR_NOACCESS,
4569 &spr_read_generic, &spr_write_generic,
4570 0x00000000);
4571 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4572 SPR_NOACCESS, SPR_NOACCESS,
4573 &spr_read_generic, &spr_write_booke206_mmucsr0,
4574 0x00000000);
4575 spr_register(env, SPR_BOOKE_EPR, "EPR",
4576 SPR_NOACCESS, SPR_NOACCESS,
4577 &spr_read_generic, SPR_NOACCESS,
4578 0x00000000);
4579 /* XXX better abstract into Emb.xxx features */
4580 if (version == fsl_e5500) {
4581 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4582 SPR_NOACCESS, SPR_NOACCESS,
4583 &spr_read_generic, &spr_write_generic,
4584 0x00000000);
4585 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4586 SPR_NOACCESS, SPR_NOACCESS,
4587 &spr_read_mas73, &spr_write_mas73,
4588 0x00000000);
4589 ivpr_mask = (target_ulong)~0xFFFFULL;
4590 }
4591
4592 #if !defined(CONFIG_USER_ONLY)
4593 env->nb_tlb = 0;
4594 env->tlb_type = TLB_MAS;
4595 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4596 env->nb_tlb += booke206_tlb_size(env, i);
4597 }
4598 #endif
4599
4600 init_excp_e200(env, ivpr_mask);
4601 /* Allocate hardware IRQ controller */
4602 ppce500_irq_init(env);
4603 }
4604
4605 static void init_proc_e500v1(CPUPPCState *env)
4606 {
4607 init_proc_e500(env, fsl_e500v1);
4608 }
4609
4610 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4611 {
4612 DeviceClass *dc = DEVICE_CLASS(oc);
4613 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4614
4615 dc->desc = "e500v1 core";
4616 pcc->init_proc = init_proc_e500v1;
4617 pcc->check_pow = check_pow_hid0;
4618 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4619 PPC_SPE | PPC_SPE_SINGLE |
4620 PPC_WRTEE | PPC_RFDI |
4621 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4622 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4623 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4624 pcc->insns_flags2 = PPC2_BOOKE206;
4625 pcc->msr_mask = 0x000000000606FF30ULL;
4626 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4627 pcc->excp_model = POWERPC_EXCP_BOOKE;
4628 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4629 pcc->bfd_mach = bfd_mach_ppc_860;
4630 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4631 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4632 POWERPC_FLAG_BUS_CLK;
4633 }
4634
4635 static void init_proc_e500v2(CPUPPCState *env)
4636 {
4637 init_proc_e500(env, fsl_e500v2);
4638 }
4639
4640 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4641 {
4642 DeviceClass *dc = DEVICE_CLASS(oc);
4643 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4644
4645 dc->desc = "e500v2 core";
4646 pcc->init_proc = init_proc_e500v2;
4647 pcc->check_pow = check_pow_hid0;
4648 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4649 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4650 PPC_WRTEE | PPC_RFDI |
4651 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4652 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4653 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4654 pcc->insns_flags2 = PPC2_BOOKE206;
4655 pcc->msr_mask = 0x000000000606FF30ULL;
4656 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4657 pcc->excp_model = POWERPC_EXCP_BOOKE;
4658 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4659 pcc->bfd_mach = bfd_mach_ppc_860;
4660 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4661 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4662 POWERPC_FLAG_BUS_CLK;
4663 }
4664
4665 static void init_proc_e500mc(CPUPPCState *env)
4666 {
4667 init_proc_e500(env, fsl_e500mc);
4668 }
4669
4670 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4671 {
4672 DeviceClass *dc = DEVICE_CLASS(oc);
4673 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4674
4675 dc->desc = "e500mc core";
4676 pcc->init_proc = init_proc_e500mc;
4677 pcc->check_pow = check_pow_none;
4678 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4679 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4680 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4681 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4682 PPC_FLOAT | PPC_FLOAT_FRES |
4683 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4684 PPC_FLOAT_STFIWX | PPC_WAIT |
4685 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4686 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4687 pcc->msr_mask = 0x000000001402FB36ULL;
4688 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4689 pcc->excp_model = POWERPC_EXCP_BOOKE;
4690 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4691 /* FIXME: figure out the correct flag for e500mc */
4692 pcc->bfd_mach = bfd_mach_ppc_e500;
4693 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4694 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4695 }
4696
4697 #ifdef TARGET_PPC64
4698 static void init_proc_e5500(CPUPPCState *env)
4699 {
4700 init_proc_e500(env, fsl_e5500);
4701 }
4702
4703 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4704 {
4705 DeviceClass *dc = DEVICE_CLASS(oc);
4706 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4707
4708 dc->desc = "e5500 core";
4709 pcc->init_proc = init_proc_e5500;
4710 pcc->check_pow = check_pow_none;
4711 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4712 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4713 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4714 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4715 PPC_FLOAT | PPC_FLOAT_FRES |
4716 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4717 PPC_FLOAT_STFIWX | PPC_WAIT |
4718 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4719 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4720 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4721 pcc->msr_mask = 0x000000009402FB36ULL;
4722 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4723 pcc->excp_model = POWERPC_EXCP_BOOKE;
4724 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4725 /* FIXME: figure out the correct flag for e5500 */
4726 pcc->bfd_mach = bfd_mach_ppc_e500;
4727 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4728 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4729 }
4730 #endif
4731
4732 /* Non-embedded PowerPC */
4733
4734 /* POWER : same as 601, without mfmsr, mfsr */
4735 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
4736 {
4737 DeviceClass *dc = DEVICE_CLASS(oc);
4738 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4739
4740 dc->desc = "POWER";
4741 /* pcc->insns_flags = XXX_TODO; */
4742 /* POWER RSC (from RAD6000) */
4743 pcc->msr_mask = 0x00000000FEF0ULL;
4744 }
4745
4746 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4747
4748 static void init_proc_601 (CPUPPCState *env)
4749 {
4750 gen_spr_ne_601(env);
4751 gen_spr_601(env);
4752 /* Hardware implementation registers */
4753 /* XXX : not implemented */
4754 spr_register(env, SPR_HID0, "HID0",
4755 SPR_NOACCESS, SPR_NOACCESS,
4756 &spr_read_generic, &spr_write_hid0_601,
4757 0x80010080);
4758 /* XXX : not implemented */
4759 spr_register(env, SPR_HID1, "HID1",
4760 SPR_NOACCESS, SPR_NOACCESS,
4761 &spr_read_generic, &spr_write_generic,
4762 0x00000000);
4763 /* XXX : not implemented */
4764 spr_register(env, SPR_601_HID2, "HID2",
4765 SPR_NOACCESS, SPR_NOACCESS,
4766 &spr_read_generic, &spr_write_generic,
4767 0x00000000);
4768 /* XXX : not implemented */
4769 spr_register(env, SPR_601_HID5, "HID5",
4770 SPR_NOACCESS, SPR_NOACCESS,
4771 &spr_read_generic, &spr_write_generic,
4772 0x00000000);
4773 /* Memory management */
4774 init_excp_601(env);
4775 /* XXX: beware that dcache line size is 64
4776 * but dcbz uses 32 bytes "sectors"
4777 * XXX: this breaks clcs instruction !
4778 */
4779 env->dcache_line_size = 32;
4780 env->icache_line_size = 64;
4781 /* Allocate hardware IRQ controller */
4782 ppc6xx_irq_init(env);
4783 }
4784
4785 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4786 {
4787 DeviceClass *dc = DEVICE_CLASS(oc);
4788 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4789
4790 dc->desc = "PowerPC 601";
4791 pcc->init_proc = init_proc_601;
4792 pcc->check_pow = check_pow_none;
4793 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4794 PPC_FLOAT |
4795 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4796 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4797 PPC_SEGMENT | PPC_EXTERN;
4798 pcc->insns_flags2 = PPC_NONE;
4799 pcc->msr_mask = 0x000000000000FD70ULL;
4800 pcc->mmu_model = POWERPC_MMU_601;
4801 #if defined(CONFIG_SOFTMMU)
4802 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4803 #endif
4804 pcc->excp_model = POWERPC_EXCP_601;
4805 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4806 pcc->bfd_mach = bfd_mach_ppc_601;
4807 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4808 }
4809
4810 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4811
4812 static void init_proc_601v (CPUPPCState *env)
4813 {
4814 init_proc_601(env);
4815 /* XXX : not implemented */
4816 spr_register(env, SPR_601_HID15, "HID15",
4817 SPR_NOACCESS, SPR_NOACCESS,
4818 &spr_read_generic, &spr_write_generic,
4819 0x00000000);
4820 }
4821
4822 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4823 {
4824 DeviceClass *dc = DEVICE_CLASS(oc);
4825 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4826
4827 dc->desc = "PowerPC 601v";
4828 pcc->init_proc = init_proc_601v;
4829 pcc->check_pow = check_pow_none;
4830 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4831 PPC_FLOAT |
4832 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4833 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4834 PPC_SEGMENT | PPC_EXTERN;
4835 pcc->insns_flags2 = PPC_NONE;
4836 pcc->msr_mask = 0x000000000000FD70ULL;
4837 pcc->mmu_model = POWERPC_MMU_601;
4838 #if defined(CONFIG_SOFTMMU)
4839 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4840 #endif
4841 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4842 pcc->bfd_mach = bfd_mach_ppc_601;
4843 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4844 }
4845
4846 static void init_proc_602 (CPUPPCState *env)
4847 {
4848 gen_spr_ne_601(env);
4849 gen_spr_602(env);
4850 /* Time base */
4851 gen_tbl(env);
4852 /* hardware implementation registers */
4853 /* XXX : not implemented */
4854 spr_register(env, SPR_HID0, "HID0",
4855 SPR_NOACCESS, SPR_NOACCESS,
4856 &spr_read_generic, &spr_write_generic,
4857 0x00000000);
4858 /* XXX : not implemented */
4859 spr_register(env, SPR_HID1, "HID1",
4860 SPR_NOACCESS, SPR_NOACCESS,
4861 &spr_read_generic, &spr_write_generic,
4862 0x00000000);
4863 /* Memory management */
4864 gen_low_BATs(env);
4865 gen_6xx_7xx_soft_tlb(env, 64, 2);
4866 init_excp_602(env);
4867 env->dcache_line_size = 32;
4868 env->icache_line_size = 32;
4869 /* Allocate hardware IRQ controller */
4870 ppc6xx_irq_init(env);
4871 }
4872
4873 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
4874 {
4875 DeviceClass *dc = DEVICE_CLASS(oc);
4876 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4877
4878 dc->desc = "PowerPC 602";
4879 pcc->init_proc = init_proc_602;
4880 pcc->check_pow = check_pow_hid0;
4881 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4882 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4883 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4884 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4885 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4886 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
4887 PPC_SEGMENT | PPC_602_SPEC;
4888 pcc->insns_flags2 = PPC_NONE;
4889 pcc->msr_mask = 0x0000000000C7FF73ULL;
4890 /* XXX: 602 MMU is quite specific. Should add a special case */
4891 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4892 pcc->excp_model = POWERPC_EXCP_602;
4893 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4894 pcc->bfd_mach = bfd_mach_ppc_602;
4895 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4896 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4897 }
4898
4899 static void init_proc_603 (CPUPPCState *env)
4900 {
4901 gen_spr_ne_601(env);
4902 gen_spr_603(env);
4903 /* Time base */
4904 gen_tbl(env);
4905 /* hardware implementation registers */
4906 /* XXX : not implemented */
4907 spr_register(env, SPR_HID0, "HID0",
4908 SPR_NOACCESS, SPR_NOACCESS,
4909 &spr_read_generic, &spr_write_generic,
4910 0x00000000);
4911 /* XXX : not implemented */
4912 spr_register(env, SPR_HID1, "HID1",
4913 SPR_NOACCESS, SPR_NOACCESS,
4914 &spr_read_generic, &spr_write_generic,
4915 0x00000000);
4916 /* Memory management */
4917 gen_low_BATs(env);
4918 gen_6xx_7xx_soft_tlb(env, 64, 2);
4919 init_excp_603(env);
4920 env->dcache_line_size = 32;
4921 env->icache_line_size = 32;
4922 /* Allocate hardware IRQ controller */
4923 ppc6xx_irq_init(env);
4924 }
4925
4926 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
4927 {
4928 DeviceClass *dc = DEVICE_CLASS(oc);
4929 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4930
4931 dc->desc = "PowerPC 603";
4932 pcc->init_proc = init_proc_603;
4933 pcc->check_pow = check_pow_hid0;
4934 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4935 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4936 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4937 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4938 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4939 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4940 PPC_SEGMENT | PPC_EXTERN;
4941 pcc->insns_flags2 = PPC_NONE;
4942 pcc->msr_mask = 0x000000000007FF73ULL;
4943 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4944 pcc->excp_model = POWERPC_EXCP_603;
4945 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4946 pcc->bfd_mach = bfd_mach_ppc_603;
4947 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4948 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4949 }
4950
4951 static void init_proc_603E (CPUPPCState *env)
4952 {
4953 gen_spr_ne_601(env);
4954 gen_spr_603(env);
4955 /* Time base */
4956 gen_tbl(env);
4957 /* hardware implementation registers */
4958 /* XXX : not implemented */
4959 spr_register(env, SPR_HID0, "HID0",
4960 SPR_NOACCESS, SPR_NOACCESS,
4961 &spr_read_generic, &spr_write_generic,
4962 0x00000000);
4963 /* XXX : not implemented */
4964 spr_register(env, SPR_HID1, "HID1",
4965 SPR_NOACCESS, SPR_NOACCESS,
4966 &spr_read_generic, &spr_write_generic,
4967 0x00000000);
4968 /* XXX : not implemented */
4969 spr_register(env, SPR_IABR, "IABR",
4970 SPR_NOACCESS, SPR_NOACCESS,
4971 &spr_read_generic, &spr_write_generic,
4972 0x00000000);
4973 /* Memory management */
4974 gen_low_BATs(env);
4975 gen_6xx_7xx_soft_tlb(env, 64, 2);
4976 init_excp_603(env);
4977 env->dcache_line_size = 32;
4978 env->icache_line_size = 32;
4979 /* Allocate hardware IRQ controller */
4980 ppc6xx_irq_init(env);
4981 }
4982
4983 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
4984 {
4985 DeviceClass *dc = DEVICE_CLASS(oc);
4986 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4987
4988 dc->desc = "PowerPC 603e";
4989 pcc->init_proc = init_proc_603E;
4990 pcc->check_pow = check_pow_hid0;
4991 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4992 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4993 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4994 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4995 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4996 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4997 PPC_SEGMENT | PPC_EXTERN;
4998 pcc->insns_flags2 = PPC_NONE;
4999 pcc->msr_mask = 0x000000000007FF73ULL;
5000 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5001 pcc->excp_model = POWERPC_EXCP_603E;
5002 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5003 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5004 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5005 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5006 }
5007
5008 static void init_proc_604 (CPUPPCState *env)
5009 {
5010 gen_spr_ne_601(env);
5011 gen_spr_604(env);
5012 /* Time base */
5013 gen_tbl(env);
5014 /* Hardware implementation registers */
5015 /* XXX : not implemented */
5016 spr_register(env, SPR_HID0, "HID0",
5017 SPR_NOACCESS, SPR_NOACCESS,
5018 &spr_read_generic, &spr_write_generic,
5019 0x00000000);
5020 /* Memory management */
5021 gen_low_BATs(env);
5022 init_excp_604(env);
5023 env->dcache_line_size = 32;
5024 env->icache_line_size = 32;
5025 /* Allocate hardware IRQ controller */
5026 ppc6xx_irq_init(env);
5027 }
5028
5029 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5030 {
5031 DeviceClass *dc = DEVICE_CLASS(oc);
5032 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5033
5034 dc->desc = "PowerPC 604";
5035 pcc->init_proc = init_proc_604;
5036 pcc->check_pow = check_pow_nocheck;
5037 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5038 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5039 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5040 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5041 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5042 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5043 PPC_SEGMENT | PPC_EXTERN;
5044 pcc->insns_flags2 = PPC_NONE;
5045 pcc->msr_mask = 0x000000000005FF77ULL;
5046 pcc->mmu_model = POWERPC_MMU_32B;
5047 #if defined(CONFIG_SOFTMMU)
5048 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5049 #endif
5050 pcc->excp_model = POWERPC_EXCP_604;
5051 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5052 pcc->bfd_mach = bfd_mach_ppc_604;
5053 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5054 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5055 }
5056
5057 static void init_proc_604E (CPUPPCState *env)
5058 {
5059 gen_spr_ne_601(env);
5060 gen_spr_604(env);
5061 /* XXX : not implemented */
5062 spr_register(env, SPR_MMCR1, "MMCR1",
5063 SPR_NOACCESS, SPR_NOACCESS,
5064 &spr_read_generic, &spr_write_generic,
5065 0x00000000);
5066 /* XXX : not implemented */
5067 spr_register(env, SPR_PMC3, "PMC3",
5068 SPR_NOACCESS, SPR_NOACCESS,
5069 &spr_read_generic, &spr_write_generic,
5070 0x00000000);
5071 /* XXX : not implemented */
5072 spr_register(env, SPR_PMC4, "PMC4",
5073 SPR_NOACCESS, SPR_NOACCESS,
5074 &spr_read_generic, &spr_write_generic,
5075 0x00000000);
5076 /* Time base */
5077 gen_tbl(env);
5078 /* Hardware implementation registers */
5079 /* XXX : not implemented */
5080 spr_register(env, SPR_HID0, "HID0",
5081 SPR_NOACCESS, SPR_NOACCESS,
5082 &spr_read_generic, &spr_write_generic,
5083 0x00000000);
5084 /* XXX : not implemented */
5085 spr_register(env, SPR_HID1, "HID1",
5086 SPR_NOACCESS, SPR_NOACCESS,
5087 &spr_read_generic, &spr_write_generic,
5088 0x00000000);
5089 /* Memory management */
5090 gen_low_BATs(env);
5091 init_excp_604(env);
5092 env->dcache_line_size = 32;
5093 env->icache_line_size = 32;
5094 /* Allocate hardware IRQ controller */
5095 ppc6xx_irq_init(env);
5096 }
5097
5098 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5099 {
5100 DeviceClass *dc = DEVICE_CLASS(oc);
5101 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5102
5103 dc->desc = "PowerPC 604E";
5104 pcc->init_proc = init_proc_604E;
5105 pcc->check_pow = check_pow_nocheck;
5106 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5107 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5108 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5109 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5110 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5111 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5112 PPC_SEGMENT | PPC_EXTERN;
5113 pcc->insns_flags2 = PPC_NONE;
5114 pcc->msr_mask = 0x000000000005FF77ULL;
5115 pcc->mmu_model = POWERPC_MMU_32B;
5116 #if defined(CONFIG_SOFTMMU)
5117 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5118 #endif
5119 pcc->excp_model = POWERPC_EXCP_604;
5120 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5121 pcc->bfd_mach = bfd_mach_ppc_604;
5122 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5123 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5124 }
5125
5126 static void init_proc_740 (CPUPPCState *env)
5127 {
5128 gen_spr_ne_601(env);
5129 gen_spr_7xx(env);
5130 /* Time base */
5131 gen_tbl(env);
5132 /* Thermal management */
5133 gen_spr_thrm(env);
5134 /* Hardware implementation registers */
5135 /* XXX : not implemented */
5136 spr_register(env, SPR_HID0, "HID0",
5137 SPR_NOACCESS, SPR_NOACCESS,
5138 &spr_read_generic, &spr_write_generic,
5139 0x00000000);
5140 /* XXX : not implemented */
5141 spr_register(env, SPR_HID1, "HID1",
5142 SPR_NOACCESS, SPR_NOACCESS,
5143 &spr_read_generic, &spr_write_generic,
5144 0x00000000);
5145 /* Memory management */
5146 gen_low_BATs(env);
5147 init_excp_7x0(env);
5148 env->dcache_line_size = 32;
5149 env->icache_line_size = 32;
5150 /* Allocate hardware IRQ controller */
5151 ppc6xx_irq_init(env);
5152 }
5153
5154 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5155 {
5156 DeviceClass *dc = DEVICE_CLASS(oc);
5157 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5158
5159 dc->desc = "PowerPC 740";
5160 pcc->init_proc = init_proc_740;
5161 pcc->check_pow = check_pow_hid0;
5162 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5163 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5164 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5165 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5166 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5167 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5168 PPC_SEGMENT | PPC_EXTERN;
5169 pcc->insns_flags2 = PPC_NONE;
5170 pcc->msr_mask = 0x000000000005FF77ULL;
5171 pcc->mmu_model = POWERPC_MMU_32B;
5172 #if defined(CONFIG_SOFTMMU)
5173 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5174 #endif
5175 pcc->excp_model = POWERPC_EXCP_7x0;
5176 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5177 pcc->bfd_mach = bfd_mach_ppc_750;
5178 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5179 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5180 }
5181
5182 static void init_proc_750 (CPUPPCState *env)
5183 {
5184 gen_spr_ne_601(env);
5185 gen_spr_7xx(env);
5186 /* XXX : not implemented */
5187 spr_register(env, SPR_L2CR, "L2CR",
5188 SPR_NOACCESS, SPR_NOACCESS,
5189 &spr_read_generic, &spr_write_generic,
5190 0x00000000);
5191 /* Time base */
5192 gen_tbl(env);
5193 /* Thermal management */
5194 gen_spr_thrm(env);
5195 /* Hardware implementation registers */
5196 /* XXX : not implemented */
5197 spr_register(env, SPR_HID0, "HID0",
5198 SPR_NOACCESS, SPR_NOACCESS,
5199 &spr_read_generic, &spr_write_generic,
5200 0x00000000);
5201 /* XXX : not implemented */
5202 spr_register(env, SPR_HID1, "HID1",
5203 SPR_NOACCESS, SPR_NOACCESS,
5204 &spr_read_generic, &spr_write_generic,
5205 0x00000000);
5206 /* Memory management */
5207 gen_low_BATs(env);
5208 /* XXX: high BATs are also present but are known to be bugged on
5209 * die version 1.x
5210 */
5211 init_excp_7x0(env);
5212 env->dcache_line_size = 32;
5213 env->icache_line_size = 32;
5214 /* Allocate hardware IRQ controller */
5215 ppc6xx_irq_init(env);
5216 }
5217
5218 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5219 {
5220 DeviceClass *dc = DEVICE_CLASS(oc);
5221 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5222
5223 dc->desc = "PowerPC 750";
5224 pcc->init_proc = init_proc_750;
5225 pcc->check_pow = check_pow_hid0;
5226 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5227 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5228 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5229 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5230 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5231 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5232 PPC_SEGMENT | PPC_EXTERN;
5233 pcc->insns_flags2 = PPC_NONE;
5234 pcc->msr_mask = 0x000000000005FF77ULL;
5235 pcc->mmu_model = POWERPC_MMU_32B;
5236 #if defined(CONFIG_SOFTMMU)
5237 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5238 #endif
5239 pcc->excp_model = POWERPC_EXCP_7x0;
5240 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5241 pcc->bfd_mach = bfd_mach_ppc_750;
5242 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5243 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5244 }
5245
5246 static void init_proc_750cl (CPUPPCState *env)
5247 {
5248 gen_spr_ne_601(env);
5249 gen_spr_7xx(env);
5250 /* XXX : not implemented */
5251 spr_register(env, SPR_L2CR, "L2CR",
5252 SPR_NOACCESS, SPR_NOACCESS,
5253 &spr_read_generic, &spr_write_generic,
5254 0x00000000);
5255 /* Time base */
5256 gen_tbl(env);
5257 /* Thermal management */
5258 /* Those registers are fake on 750CL */
5259 spr_register(env, SPR_THRM1, "THRM1",
5260 SPR_NOACCESS, SPR_NOACCESS,
5261 &spr_read_generic, &spr_write_generic,
5262 0x00000000);
5263 spr_register(env, SPR_THRM2, "THRM2",
5264 SPR_NOACCESS, SPR_NOACCESS,
5265 &spr_read_generic, &spr_write_generic,
5266 0x00000000);
5267 spr_register(env, SPR_THRM3, "THRM3",
5268 SPR_NOACCESS, SPR_NOACCESS,
5269 &spr_read_generic, &spr_write_generic,
5270 0x00000000);
5271 /* XXX: not implemented */
5272 spr_register(env, SPR_750_TDCL, "TDCL",
5273 SPR_NOACCESS, SPR_NOACCESS,
5274 &spr_read_generic, &spr_write_generic,
5275 0x00000000);
5276 spr_register(env, SPR_750_TDCH, "TDCH",
5277 SPR_NOACCESS, SPR_NOACCESS,
5278 &spr_read_generic, &spr_write_generic,
5279 0x00000000);
5280 /* DMA */
5281 /* XXX : not implemented */
5282 spr_register(env, SPR_750_WPAR, "WPAR",
5283 SPR_NOACCESS, SPR_NOACCESS,
5284 &spr_read_generic, &spr_write_generic,
5285 0x00000000);
5286 spr_register(env, SPR_750_DMAL, "DMAL",
5287 SPR_NOACCESS, SPR_NOACCESS,
5288 &spr_read_generic, &spr_write_generic,
5289 0x00000000);
5290 spr_register(env, SPR_750_DMAU, "DMAU",
5291 SPR_NOACCESS, SPR_NOACCESS,
5292 &spr_read_generic, &spr_write_generic,
5293 0x00000000);
5294 /* Hardware implementation registers */
5295 /* XXX : not implemented */
5296 spr_register(env, SPR_HID0, "HID0",
5297 SPR_NOACCESS, SPR_NOACCESS,
5298 &spr_read_generic, &spr_write_generic,
5299 0x00000000);
5300 /* XXX : not implemented */
5301 spr_register(env, SPR_HID1, "HID1",
5302 SPR_NOACCESS, SPR_NOACCESS,
5303 &spr_read_generic, &spr_write_generic,
5304 0x00000000);
5305 /* XXX : not implemented */
5306 spr_register(env, SPR_750CL_HID2, "HID2",
5307 SPR_NOACCESS, SPR_NOACCESS,
5308 &spr_read_generic, &spr_write_generic,
5309 0x00000000);
5310 /* XXX : not implemented */
5311 spr_register(env, SPR_750CL_HID4, "HID4",
5312 SPR_NOACCESS, SPR_NOACCESS,
5313 &spr_read_generic, &spr_write_generic,
5314 0x00000000);
5315 /* Quantization registers */
5316 /* XXX : not implemented */
5317 spr_register(env, SPR_750_GQR0, "GQR0",
5318 SPR_NOACCESS, SPR_NOACCESS,
5319 &spr_read_generic, &spr_write_generic,
5320 0x00000000);
5321 /* XXX : not implemented */
5322 spr_register(env, SPR_750_GQR1, "GQR1",
5323 SPR_NOACCESS, SPR_NOACCESS,
5324 &spr_read_generic, &spr_write_generic,
5325 0x00000000);
5326 /* XXX : not implemented */
5327 spr_register(env, SPR_750_GQR2, "GQR2",
5328 SPR_NOACCESS, SPR_NOACCESS,
5329 &spr_read_generic, &spr_write_generic,
5330 0x00000000);
5331 /* XXX : not implemented */
5332 spr_register(env, SPR_750_GQR3, "GQR3",
5333 SPR_NOACCESS, SPR_NOACCESS,
5334 &spr_read_generic, &spr_write_generic,
5335 0x00000000);
5336 /* XXX : not implemented */
5337 spr_register(env, SPR_750_GQR4, "GQR4",
5338 SPR_NOACCESS, SPR_NOACCESS,
5339 &spr_read_generic, &spr_write_generic,
5340 0x00000000);
5341 /* XXX : not implemented */
5342 spr_register(env, SPR_750_GQR5, "GQR5",
5343 SPR_NOACCESS, SPR_NOACCESS,
5344 &spr_read_generic, &spr_write_generic,
5345 0x00000000);
5346 /* XXX : not implemented */
5347 spr_register(env, SPR_750_GQR6, "GQR6",
5348 SPR_NOACCESS, SPR_NOACCESS,
5349 &spr_read_generic, &spr_write_generic,
5350 0x00000000);
5351 /* XXX : not implemented */
5352 spr_register(env, SPR_750_GQR7, "GQR7",
5353 SPR_NOACCESS, SPR_NOACCESS,
5354 &spr_read_generic, &spr_write_generic,
5355 0x00000000);
5356 /* Memory management */
5357 gen_low_BATs(env);
5358 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5359 gen_high_BATs(env);
5360 init_excp_750cl(env);
5361 env->dcache_line_size = 32;
5362 env->icache_line_size = 32;
5363 /* Allocate hardware IRQ controller */
5364 ppc6xx_irq_init(env);
5365 }
5366
5367 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5368 {
5369 DeviceClass *dc = DEVICE_CLASS(oc);
5370 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5371
5372 dc->desc = "PowerPC 750 CL";
5373 pcc->init_proc = init_proc_750cl;
5374 pcc->check_pow = check_pow_hid0;
5375 /* XXX: not implemented:
5376 * cache lock instructions:
5377 * dcbz_l
5378 * floating point paired instructions
5379 * psq_lux
5380 * psq_lx
5381 * psq_stux
5382 * psq_stx
5383 * ps_abs
5384 * ps_add
5385 * ps_cmpo0
5386 * ps_cmpo1
5387 * ps_cmpu0
5388 * ps_cmpu1
5389 * ps_div
5390 * ps_madd
5391 * ps_madds0
5392 * ps_madds1
5393 * ps_merge00
5394 * ps_merge01
5395 * ps_merge10
5396 * ps_merge11
5397 * ps_mr
5398 * ps_msub
5399 * ps_mul
5400 * ps_muls0
5401 * ps_muls1
5402 * ps_nabs
5403 * ps_neg
5404 * ps_nmadd
5405 * ps_nmsub
5406 * ps_res
5407 * ps_rsqrte
5408 * ps_sel
5409 * ps_sub
5410 * ps_sum0
5411 * ps_sum1
5412 */
5413 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5414 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5415 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5416 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5417 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5418 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5419 PPC_SEGMENT | PPC_EXTERN;
5420 pcc->insns_flags2 = PPC_NONE;
5421 pcc->msr_mask = 0x000000000005FF77ULL;
5422 pcc->mmu_model = POWERPC_MMU_32B;
5423 #if defined(CONFIG_SOFTMMU)
5424 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5425 #endif
5426 pcc->excp_model = POWERPC_EXCP_7x0;
5427 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5428 pcc->bfd_mach = bfd_mach_ppc_750;
5429 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5430 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5431 }
5432
5433 static void init_proc_750cx (CPUPPCState *env)
5434 {
5435 gen_spr_ne_601(env);
5436 gen_spr_7xx(env);
5437 /* XXX : not implemented */
5438 spr_register(env, SPR_L2CR, "L2CR",
5439 SPR_NOACCESS, SPR_NOACCESS,
5440 &spr_read_generic, &spr_write_generic,
5441 0x00000000);
5442 /* Time base */
5443 gen_tbl(env);
5444 /* Thermal management */
5445 gen_spr_thrm(env);
5446 /* This register is not implemented but is present for compatibility */
5447 spr_register(env, SPR_SDA, "SDA",
5448 SPR_NOACCESS, SPR_NOACCESS,
5449 &spr_read_generic, &spr_write_generic,
5450 0x00000000);
5451 /* Hardware implementation registers */
5452 /* XXX : not implemented */
5453 spr_register(env, SPR_HID0, "HID0",
5454 SPR_NOACCESS, SPR_NOACCESS,
5455 &spr_read_generic, &spr_write_generic,
5456 0x00000000);
5457 /* XXX : not implemented */
5458 spr_register(env, SPR_HID1, "HID1",
5459 SPR_NOACCESS, SPR_NOACCESS,
5460 &spr_read_generic, &spr_write_generic,
5461 0x00000000);
5462 /* Memory management */
5463 gen_low_BATs(env);
5464 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5465 gen_high_BATs(env);
5466 init_excp_750cx(env);
5467 env->dcache_line_size = 32;
5468 env->icache_line_size = 32;
5469 /* Allocate hardware IRQ controller */
5470 ppc6xx_irq_init(env);
5471 }
5472
5473 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5474 {
5475 DeviceClass *dc = DEVICE_CLASS(oc);
5476 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5477
5478 dc->desc = "PowerPC 750CX";
5479 pcc->init_proc = init_proc_750cx;
5480 pcc->check_pow = check_pow_hid0;
5481 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5482 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5483 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5484 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5485 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5486 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5487 PPC_SEGMENT | PPC_EXTERN;
5488 pcc->insns_flags2 = PPC_NONE;
5489 pcc->msr_mask = 0x000000000005FF77ULL;
5490 pcc->mmu_model = POWERPC_MMU_32B;
5491 #if defined(CONFIG_SOFTMMU)
5492 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5493 #endif
5494 pcc->excp_model = POWERPC_EXCP_7x0;
5495 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5496 pcc->bfd_mach = bfd_mach_ppc_750;
5497 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5498 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5499 }
5500
5501 static void init_proc_750fx (CPUPPCState *env)
5502 {
5503 gen_spr_ne_601(env);
5504 gen_spr_7xx(env);
5505 /* XXX : not implemented */
5506 spr_register(env, SPR_L2CR, "L2CR",
5507 SPR_NOACCESS, SPR_NOACCESS,
5508 &spr_read_generic, &spr_write_generic,
5509 0x00000000);
5510 /* Time base */
5511 gen_tbl(env);
5512 /* Thermal management */
5513 gen_spr_thrm(env);
5514 /* XXX : not implemented */
5515 spr_register(env, SPR_750_THRM4, "THRM4",
5516 SPR_NOACCESS, SPR_NOACCESS,
5517 &spr_read_generic, &spr_write_generic,
5518 0x00000000);
5519 /* Hardware implementation registers */
5520 /* XXX : not implemented */
5521 spr_register(env, SPR_HID0, "HID0",
5522 SPR_NOACCESS, SPR_NOACCESS,
5523 &spr_read_generic, &spr_write_generic,
5524 0x00000000);
5525 /* XXX : not implemented */
5526 spr_register(env, SPR_HID1, "HID1",
5527 SPR_NOACCESS, SPR_NOACCESS,
5528 &spr_read_generic, &spr_write_generic,
5529 0x00000000);
5530 /* XXX : not implemented */
5531 spr_register(env, SPR_750FX_HID2, "HID2",
5532 SPR_NOACCESS, SPR_NOACCESS,
5533 &spr_read_generic, &spr_write_generic,
5534 0x00000000);
5535 /* Memory management */
5536 gen_low_BATs(env);
5537 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5538 gen_high_BATs(env);
5539 init_excp_7x0(env);
5540 env->dcache_line_size = 32;
5541 env->icache_line_size = 32;
5542 /* Allocate hardware IRQ controller */
5543 ppc6xx_irq_init(env);
5544 }
5545
5546 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5547 {
5548 DeviceClass *dc = DEVICE_CLASS(oc);
5549 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5550
5551 dc->desc = "PowerPC 750FX";
5552 pcc->init_proc = init_proc_750fx;
5553 pcc->check_pow = check_pow_hid0;
5554 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5555 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5556 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5557 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5558 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5559 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5560 PPC_SEGMENT | PPC_EXTERN;
5561 pcc->insns_flags2 = PPC_NONE;
5562 pcc->msr_mask = 0x000000000005FF77ULL;
5563 pcc->mmu_model = POWERPC_MMU_32B;
5564 #if defined(CONFIG_SOFTMMU)
5565 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5566 #endif
5567 pcc->excp_model = POWERPC_EXCP_7x0;
5568 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5569 pcc->bfd_mach = bfd_mach_ppc_750;
5570 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5571 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5572 }
5573
5574 static void init_proc_750gx (CPUPPCState *env)
5575 {
5576 gen_spr_ne_601(env);
5577 gen_spr_7xx(env);
5578 /* XXX : not implemented (XXX: different from 750fx) */
5579 spr_register(env, SPR_L2CR, "L2CR",
5580 SPR_NOACCESS, SPR_NOACCESS,
5581 &spr_read_generic, &spr_write_generic,
5582 0x00000000);
5583 /* Time base */
5584 gen_tbl(env);
5585 /* Thermal management */
5586 gen_spr_thrm(env);
5587 /* XXX : not implemented */
5588 spr_register(env, SPR_750_THRM4, "THRM4",
5589 SPR_NOACCESS, SPR_NOACCESS,
5590 &spr_read_generic, &spr_write_generic,
5591 0x00000000);
5592 /* Hardware implementation registers */
5593 /* XXX : not implemented (XXX: different from 750fx) */
5594 spr_register(env, SPR_HID0, "HID0",
5595 SPR_NOACCESS, SPR_NOACCESS,
5596 &spr_read_generic, &spr_write_generic,
5597 0x00000000);
5598 /* XXX : not implemented */
5599 spr_register(env, SPR_HID1, "HID1",
5600 SPR_NOACCESS, SPR_NOACCESS,
5601 &spr_read_generic, &spr_write_generic,
5602 0x00000000);
5603 /* XXX : not implemented (XXX: different from 750fx) */
5604 spr_register(env, SPR_750FX_HID2, "HID2",
5605 SPR_NOACCESS, SPR_NOACCESS,
5606 &spr_read_generic, &spr_write_generic,
5607 0x00000000);
5608 /* Memory management */
5609 gen_low_BATs(env);
5610 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5611 gen_high_BATs(env);
5612 init_excp_7x0(env);
5613 env->dcache_line_size = 32;
5614 env->icache_line_size = 32;
5615 /* Allocate hardware IRQ controller */
5616 ppc6xx_irq_init(env);
5617 }
5618
5619 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5620 {
5621 DeviceClass *dc = DEVICE_CLASS(oc);
5622 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5623
5624 dc->desc = "PowerPC 750GX";
5625 pcc->init_proc = init_proc_750gx;
5626 pcc->check_pow = check_pow_hid0;
5627 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5628 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5629 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5630 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5631 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5632 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5633 PPC_SEGMENT | PPC_EXTERN;
5634 pcc->insns_flags2 = PPC_NONE;
5635 pcc->msr_mask = 0x000000000005FF77ULL;
5636 pcc->mmu_model = POWERPC_MMU_32B;
5637 #if defined(CONFIG_SOFTMMU)
5638 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5639 #endif
5640 pcc->excp_model = POWERPC_EXCP_7x0;
5641 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5642 pcc->bfd_mach = bfd_mach_ppc_750;
5643 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5644 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5645 }
5646
5647 static void init_proc_745 (CPUPPCState *env)
5648 {
5649 gen_spr_ne_601(env);
5650 gen_spr_7xx(env);
5651 gen_spr_G2_755(env);
5652 /* Time base */
5653 gen_tbl(env);
5654 /* Thermal management */
5655 gen_spr_thrm(env);
5656 /* Hardware implementation registers */
5657 /* XXX : not implemented */
5658 spr_register(env, SPR_HID0, "HID0",
5659 SPR_NOACCESS, SPR_NOACCESS,
5660 &spr_read_generic, &spr_write_generic,
5661 0x00000000);
5662 /* XXX : not implemented */
5663 spr_register(env, SPR_HID1, "HID1",
5664 SPR_NOACCESS, SPR_NOACCESS,
5665 &spr_read_generic, &spr_write_generic,
5666 0x00000000);
5667 /* XXX : not implemented */
5668 spr_register(env, SPR_HID2, "HID2",
5669 SPR_NOACCESS, SPR_NOACCESS,
5670 &spr_read_generic, &spr_write_generic,
5671 0x00000000);
5672 /* Memory management */
5673 gen_low_BATs(env);
5674 gen_high_BATs(env);
5675 gen_6xx_7xx_soft_tlb(env, 64, 2);
5676 init_excp_7x5(env);
5677 env->dcache_line_size = 32;
5678 env->icache_line_size = 32;
5679 /* Allocate hardware IRQ controller */
5680 ppc6xx_irq_init(env);
5681 }
5682
5683 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5684 {
5685 DeviceClass *dc = DEVICE_CLASS(oc);
5686 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5687
5688 dc->desc = "PowerPC 745";
5689 pcc->init_proc = init_proc_745;
5690 pcc->check_pow = check_pow_hid0;
5691 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5692 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5693 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5694 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5695 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5696 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5697 PPC_SEGMENT | PPC_EXTERN;
5698 pcc->insns_flags2 = PPC_NONE;
5699 pcc->msr_mask = 0x000000000005FF77ULL;
5700 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5701 pcc->excp_model = POWERPC_EXCP_7x5;
5702 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5703 pcc->bfd_mach = bfd_mach_ppc_750;
5704 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5705 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5706 }
5707
5708 static void init_proc_755 (CPUPPCState *env)
5709 {
5710 gen_spr_ne_601(env);
5711 gen_spr_7xx(env);
5712 gen_spr_G2_755(env);
5713 /* Time base */
5714 gen_tbl(env);
5715 /* L2 cache control */
5716 /* XXX : not implemented */
5717 spr_register(env, SPR_L2CR, "L2CR",
5718 SPR_NOACCESS, SPR_NOACCESS,
5719 &spr_read_generic, &spr_write_generic,
5720 0x00000000);
5721 /* XXX : not implemented */
5722 spr_register(env, SPR_L2PMCR, "L2PMCR",
5723 SPR_NOACCESS, SPR_NOACCESS,
5724 &spr_read_generic, &spr_write_generic,
5725 0x00000000);
5726 /* Thermal management */
5727 gen_spr_thrm(env);
5728 /* Hardware implementation registers */
5729 /* XXX : not implemented */
5730 spr_register(env, SPR_HID0, "HID0",
5731 SPR_NOACCESS, SPR_NOACCESS,
5732 &spr_read_generic, &spr_write_generic,
5733 0x00000000);
5734 /* XXX : not implemented */
5735 spr_register(env, SPR_HID1, "HID1",
5736 SPR_NOACCESS, SPR_NOACCESS,
5737 &spr_read_generic, &spr_write_generic,
5738 0x00000000);
5739 /* XXX : not implemented */
5740 spr_register(env, SPR_HID2, "HID2",
5741 SPR_NOACCESS, SPR_NOACCESS,
5742 &spr_read_generic, &spr_write_generic,
5743 0x00000000);
5744 /* Memory management */
5745 gen_low_BATs(env);
5746 gen_high_BATs(env);
5747 gen_6xx_7xx_soft_tlb(env, 64, 2);
5748 init_excp_7x5(env);
5749 env->dcache_line_size = 32;
5750 env->icache_line_size = 32;
5751 /* Allocate hardware IRQ controller */
5752 ppc6xx_irq_init(env);
5753 }
5754
5755 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5756 {
5757 DeviceClass *dc = DEVICE_CLASS(oc);
5758 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5759
5760 dc->desc = "PowerPC 755";
5761 pcc->init_proc = init_proc_755;
5762 pcc->check_pow = check_pow_hid0;
5763 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5764 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5765 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5766 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5767 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5768 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5769 PPC_SEGMENT | PPC_EXTERN;
5770 pcc->insns_flags2 = PPC_NONE;
5771 pcc->msr_mask = 0x000000000005FF77ULL;
5772 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5773 pcc->excp_model = POWERPC_EXCP_7x5;
5774 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5775 pcc->bfd_mach = bfd_mach_ppc_750;
5776 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5777 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5778 }
5779
5780 static void init_proc_7400 (CPUPPCState *env)
5781 {
5782 gen_spr_ne_601(env);
5783 gen_spr_7xx(env);
5784 /* Time base */
5785 gen_tbl(env);
5786 /* 74xx specific SPR */
5787 gen_spr_74xx(env);
5788 /* XXX : not implemented */
5789 spr_register(env, SPR_UBAMR, "UBAMR",
5790 &spr_read_ureg, SPR_NOACCESS,
5791 &spr_read_ureg, SPR_NOACCESS,
5792 0x00000000);
5793 /* XXX: this seems not implemented on all revisions. */
5794 /* XXX : not implemented */
5795 spr_register(env, SPR_MSSCR1, "MSSCR1",
5796 SPR_NOACCESS, SPR_NOACCESS,
5797 &spr_read_generic, &spr_write_generic,
5798 0x00000000);
5799 /* Thermal management */
5800 gen_spr_thrm(env);
5801 /* Memory management */
5802 gen_low_BATs(env);
5803 init_excp_7400(env);
5804 env->dcache_line_size = 32;
5805 env->icache_line_size = 32;
5806 /* Allocate hardware IRQ controller */
5807 ppc6xx_irq_init(env);
5808 }
5809
5810 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5811 {
5812 DeviceClass *dc = DEVICE_CLASS(oc);
5813 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5814
5815 dc->desc = "PowerPC 7400 (aka G4)";
5816 pcc->init_proc = init_proc_7400;
5817 pcc->check_pow = check_pow_hid0;
5818 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5819 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5820 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5821 PPC_FLOAT_STFIWX |
5822 PPC_CACHE | PPC_CACHE_ICBI |
5823 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5824 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5825 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5826 PPC_MEM_TLBIA |
5827 PPC_SEGMENT | PPC_EXTERN |
5828 PPC_ALTIVEC;
5829 pcc->insns_flags2 = PPC_NONE;
5830 pcc->msr_mask = 0x000000000205FF77ULL;
5831 pcc->mmu_model = POWERPC_MMU_32B;
5832 #if defined(CONFIG_SOFTMMU)
5833 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5834 #endif
5835 pcc->excp_model = POWERPC_EXCP_74xx;
5836 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5837 pcc->bfd_mach = bfd_mach_ppc_7400;
5838 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5839 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5840 POWERPC_FLAG_BUS_CLK;
5841 }
5842
5843 static void init_proc_7410 (CPUPPCState *env)
5844 {
5845 gen_spr_ne_601(env);
5846 gen_spr_7xx(env);
5847 /* Time base */
5848 gen_tbl(env);
5849 /* 74xx specific SPR */
5850 gen_spr_74xx(env);
5851 /* XXX : not implemented */
5852 spr_register(env, SPR_UBAMR, "UBAMR",
5853 &spr_read_ureg, SPR_NOACCESS,
5854 &spr_read_ureg, SPR_NOACCESS,
5855 0x00000000);
5856 /* Thermal management */
5857 gen_spr_thrm(env);
5858 /* L2PMCR */
5859 /* XXX : not implemented */
5860 spr_register(env, SPR_L2PMCR, "L2PMCR",
5861 SPR_NOACCESS, SPR_NOACCESS,
5862 &spr_read_generic, &spr_write_generic,
5863 0x00000000);
5864 /* LDSTDB */
5865 /* XXX : not implemented */
5866 spr_register(env, SPR_LDSTDB, "LDSTDB",
5867 SPR_NOACCESS, SPR_NOACCESS,
5868 &spr_read_generic, &spr_write_generic,
5869 0x00000000);
5870 /* Memory management */
5871 gen_low_BATs(env);
5872 init_excp_7400(env);
5873 env->dcache_line_size = 32;
5874 env->icache_line_size = 32;
5875 /* Allocate hardware IRQ controller */
5876 ppc6xx_irq_init(env);
5877 }
5878
5879 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
5880 {
5881 DeviceClass *dc = DEVICE_CLASS(oc);
5882 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5883
5884 dc->desc = "PowerPC 7410 (aka G4)";
5885 pcc->init_proc = init_proc_7410;
5886 pcc->check_pow = check_pow_hid0;
5887 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5888 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5889 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5890 PPC_FLOAT_STFIWX |
5891 PPC_CACHE | PPC_CACHE_ICBI |
5892 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5893 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5894 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5895 PPC_MEM_TLBIA |
5896 PPC_SEGMENT | PPC_EXTERN |
5897 PPC_ALTIVEC;
5898 pcc->insns_flags2 = PPC_NONE;
5899 pcc->msr_mask = 0x000000000205FF77ULL;
5900 pcc->mmu_model = POWERPC_MMU_32B;
5901 #if defined(CONFIG_SOFTMMU)
5902 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5903 #endif
5904 pcc->excp_model = POWERPC_EXCP_74xx;
5905 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5906 pcc->bfd_mach = bfd_mach_ppc_7400;
5907 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5908 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5909 POWERPC_FLAG_BUS_CLK;
5910 }
5911
5912 static void init_proc_7440 (CPUPPCState *env)
5913 {
5914 gen_spr_ne_601(env);
5915 gen_spr_7xx(env);
5916 /* Time base */
5917 gen_tbl(env);
5918 /* 74xx specific SPR */
5919 gen_spr_74xx(env);
5920 /* XXX : not implemented */
5921 spr_register(env, SPR_UBAMR, "UBAMR",
5922 &spr_read_ureg, SPR_NOACCESS,
5923 &spr_read_ureg, SPR_NOACCESS,
5924 0x00000000);
5925 /* LDSTCR */
5926 /* XXX : not implemented */
5927 spr_register(env, SPR_LDSTCR, "LDSTCR",
5928 SPR_NOACCESS, SPR_NOACCESS,
5929 &spr_read_generic, &spr_write_generic,
5930 0x00000000);
5931 /* ICTRL */
5932 /* XXX : not implemented */
5933 spr_register(env, SPR_ICTRL, "ICTRL",
5934 SPR_NOACCESS, SPR_NOACCESS,
5935 &spr_read_generic, &spr_write_generic,
5936 0x00000000);
5937 /* MSSSR0 */
5938 /* XXX : not implemented */
5939 spr_register(env, SPR_MSSSR0, "MSSSR0",
5940 SPR_NOACCESS, SPR_NOACCESS,
5941 &spr_read_generic, &spr_write_generic,
5942 0x00000000);
5943 /* PMC */
5944 /* XXX : not implemented */
5945 spr_register(env, SPR_PMC5, "PMC5",
5946 SPR_NOACCESS, SPR_NOACCESS,
5947 &spr_read_generic, &spr_write_generic,
5948 0x00000000);
5949 /* XXX : not implemented */
5950 spr_register(env, SPR_UPMC5, "UPMC5",
5951 &spr_read_ureg, SPR_NOACCESS,
5952 &spr_read_ureg, SPR_NOACCESS,
5953 0x00000000);
5954 /* XXX : not implemented */
5955 spr_register(env, SPR_PMC6, "PMC6",
5956 SPR_NOACCESS, SPR_NOACCESS,
5957 &spr_read_generic, &spr_write_generic,
5958 0x00000000);
5959 /* XXX : not implemented */
5960 spr_register(env, SPR_UPMC6, "UPMC6",
5961 &spr_read_ureg, SPR_NOACCESS,
5962 &spr_read_ureg, SPR_NOACCESS,
5963 0x00000000);
5964 /* Memory management */
5965 gen_low_BATs(env);
5966 gen_74xx_soft_tlb(env, 128, 2);
5967 init_excp_7450(env);
5968 env->dcache_line_size = 32;
5969 env->icache_line_size = 32;
5970 /* Allocate hardware IRQ controller */
5971 ppc6xx_irq_init(env);
5972 }
5973
5974 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
5975 {
5976 DeviceClass *dc = DEVICE_CLASS(oc);
5977 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5978
5979 dc->desc = "PowerPC 7440 (aka G4)";
5980 pcc->init_proc = init_proc_7440;
5981 pcc->check_pow = check_pow_hid0_74xx;
5982 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5983 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5984 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5985 PPC_FLOAT_STFIWX |
5986 PPC_CACHE | PPC_CACHE_ICBI |
5987 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5988 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5989 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5990 PPC_MEM_TLBIA | PPC_74xx_TLB |
5991 PPC_SEGMENT | PPC_EXTERN |
5992 PPC_ALTIVEC;
5993 pcc->insns_flags2 = PPC_NONE;
5994 pcc->msr_mask = 0x000000000205FF77ULL;
5995 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
5996 pcc->excp_model = POWERPC_EXCP_74xx;
5997 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5998 pcc->bfd_mach = bfd_mach_ppc_7400;
5999 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6000 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6001 POWERPC_FLAG_BUS_CLK;
6002 }
6003
6004 static void init_proc_7450 (CPUPPCState *env)
6005 {
6006 gen_spr_ne_601(env);
6007 gen_spr_7xx(env);
6008 /* Time base */
6009 gen_tbl(env);
6010 /* 74xx specific SPR */
6011 gen_spr_74xx(env);
6012 /* Level 3 cache control */
6013 gen_l3_ctrl(env);
6014 /* L3ITCR1 */
6015 /* XXX : not implemented */
6016 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6017 SPR_NOACCESS, SPR_NOACCESS,
6018 &spr_read_generic, &spr_write_generic,
6019 0x00000000);
6020 /* L3ITCR2 */
6021 /* XXX : not implemented */
6022 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6023 SPR_NOACCESS, SPR_NOACCESS,
6024 &spr_read_generic, &spr_write_generic,
6025 0x00000000);
6026 /* L3ITCR3 */
6027 /* XXX : not implemented */
6028 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6029 SPR_NOACCESS, SPR_NOACCESS,
6030 &spr_read_generic, &spr_write_generic,
6031 0x00000000);
6032 /* L3OHCR */
6033 /* XXX : not implemented */
6034 spr_register(env, SPR_L3OHCR, "L3OHCR",
6035 SPR_NOACCESS, SPR_NOACCESS,
6036 &spr_read_generic, &spr_write_generic,
6037 0x00000000);
6038 /* XXX : not implemented */
6039 spr_register(env, SPR_UBAMR, "UBAMR",
6040 &spr_read_ureg, SPR_NOACCESS,
6041 &spr_read_ureg, SPR_NOACCESS,
6042 0x00000000);
6043 /* LDSTCR */
6044 /* XXX : not implemented */
6045 spr_register(env, SPR_LDSTCR, "LDSTCR",
6046 SPR_NOACCESS, SPR_NOACCESS,
6047 &spr_read_generic, &spr_write_generic,
6048 0x00000000);
6049 /* ICTRL */
6050 /* XXX : not implemented */
6051 spr_register(env, SPR_ICTRL, "ICTRL",
6052 SPR_NOACCESS, SPR_NOACCESS,
6053 &spr_read_generic, &spr_write_generic,
6054 0x00000000);
6055 /* MSSSR0 */
6056 /* XXX : not implemented */
6057 spr_register(env, SPR_MSSSR0, "MSSSR0",
6058 SPR_NOACCESS, SPR_NOACCESS,
6059 &spr_read_generic, &spr_write_generic,
6060 0x00000000);
6061 /* PMC */
6062 /* XXX : not implemented */
6063 spr_register(env, SPR_PMC5, "PMC5",
6064 SPR_NOACCESS, SPR_NOACCESS,
6065 &spr_read_generic, &spr_write_generic,
6066 0x00000000);
6067 /* XXX : not implemented */
6068 spr_register(env, SPR_UPMC5, "UPMC5",
6069 &spr_read_ureg, SPR_NOACCESS,
6070 &spr_read_ureg, SPR_NOACCESS,
6071 0x00000000);
6072 /* XXX : not implemented */
6073 spr_register(env, SPR_PMC6, "PMC6",
6074 SPR_NOACCESS, SPR_NOACCESS,
6075 &spr_read_generic, &spr_write_generic,
6076 0x00000000);
6077 /* XXX : not implemented */
6078 spr_register(env, SPR_UPMC6, "UPMC6",
6079 &spr_read_ureg, SPR_NOACCESS,
6080 &spr_read_ureg, SPR_NOACCESS,
6081 0x00000000);
6082 /* Memory management */
6083 gen_low_BATs(env);
6084 gen_74xx_soft_tlb(env, 128, 2);
6085 init_excp_7450(env);
6086 env->dcache_line_size = 32;
6087 env->icache_line_size = 32;
6088 /* Allocate hardware IRQ controller */
6089 ppc6xx_irq_init(env);
6090 }
6091
6092 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6093 {
6094 DeviceClass *dc = DEVICE_CLASS(oc);
6095 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6096
6097 dc->desc = "PowerPC 7450 (aka G4)";
6098 pcc->init_proc = init_proc_7450;
6099 pcc->check_pow = check_pow_hid0_74xx;
6100 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6101 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6102 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6103 PPC_FLOAT_STFIWX |
6104 PPC_CACHE | PPC_CACHE_ICBI |
6105 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6106 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6107 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6108 PPC_MEM_TLBIA | PPC_74xx_TLB |
6109 PPC_SEGMENT | PPC_EXTERN |
6110 PPC_ALTIVEC;
6111 pcc->insns_flags2 = PPC_NONE;
6112 pcc->msr_mask = 0x000000000205FF77ULL;
6113 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6114 pcc->excp_model = POWERPC_EXCP_74xx;
6115 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6116 pcc->bfd_mach = bfd_mach_ppc_7400;
6117 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6118 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6119 POWERPC_FLAG_BUS_CLK;
6120 }
6121
6122 static void init_proc_7445 (CPUPPCState *env)
6123 {
6124 gen_spr_ne_601(env);
6125 gen_spr_7xx(env);
6126 /* Time base */
6127 gen_tbl(env);
6128 /* 74xx specific SPR */
6129 gen_spr_74xx(env);
6130 /* LDSTCR */
6131 /* XXX : not implemented */
6132 spr_register(env, SPR_LDSTCR, "LDSTCR",
6133 SPR_NOACCESS, SPR_NOACCESS,
6134 &spr_read_generic, &spr_write_generic,
6135 0x00000000);
6136 /* ICTRL */
6137 /* XXX : not implemented */
6138 spr_register(env, SPR_ICTRL, "ICTRL",
6139 SPR_NOACCESS, SPR_NOACCESS,
6140 &spr_read_generic, &spr_write_generic,
6141 0x00000000);
6142 /* MSSSR0 */
6143 /* XXX : not implemented */
6144 spr_register(env, SPR_MSSSR0, "MSSSR0",
6145 SPR_NOACCESS, SPR_NOACCESS,
6146 &spr_read_generic, &spr_write_generic,
6147 0x00000000);
6148 /* PMC */
6149 /* XXX : not implemented */
6150 spr_register(env, SPR_PMC5, "PMC5",
6151 SPR_NOACCESS, SPR_NOACCESS,
6152 &spr_read_generic, &spr_write_generic,
6153 0x00000000);
6154 /* XXX : not implemented */
6155 spr_register(env, SPR_UPMC5, "UPMC5",
6156 &spr_read_ureg, SPR_NOACCESS,
6157 &spr_read_ureg, SPR_NOACCESS,
6158 0x00000000);
6159 /* XXX : not implemented */
6160 spr_register(env, SPR_PMC6, "PMC6",
6161 SPR_NOACCESS, SPR_NOACCESS,
6162 &spr_read_generic, &spr_write_generic,
6163 0x00000000);
6164 /* XXX : not implemented */
6165 spr_register(env, SPR_UPMC6, "UPMC6",
6166 &spr_read_ureg, SPR_NOACCESS,
6167 &spr_read_ureg, SPR_NOACCESS,
6168 0x00000000);
6169 /* SPRGs */
6170 spr_register(env, SPR_SPRG4, "SPRG4",
6171 SPR_NOACCESS, SPR_NOACCESS,
6172 &spr_read_generic, &spr_write_generic,
6173 0x00000000);
6174 spr_register(env, SPR_USPRG4, "USPRG4",
6175 &spr_read_ureg, SPR_NOACCESS,
6176 &spr_read_ureg, SPR_NOACCESS,
6177 0x00000000);
6178 spr_register(env, SPR_SPRG5, "SPRG5",
6179 SPR_NOACCESS, SPR_NOACCESS,
6180 &spr_read_generic, &spr_write_generic,
6181 0x00000000);
6182 spr_register(env, SPR_USPRG5, "USPRG5",
6183 &spr_read_ureg, SPR_NOACCESS,
6184 &spr_read_ureg, SPR_NOACCESS,
6185 0x00000000);
6186 spr_register(env, SPR_SPRG6, "SPRG6",
6187 SPR_NOACCESS, SPR_NOACCESS,
6188 &spr_read_generic, &spr_write_generic,
6189 0x00000000);
6190 spr_register(env, SPR_USPRG6, "USPRG6",
6191 &spr_read_ureg, SPR_NOACCESS,
6192 &spr_read_ureg, SPR_NOACCESS,
6193 0x00000000);
6194 spr_register(env, SPR_SPRG7, "SPRG7",
6195 SPR_NOACCESS, SPR_NOACCESS,
6196 &spr_read_generic, &spr_write_generic,
6197 0x00000000);
6198 spr_register(env, SPR_USPRG7, "USPRG7",
6199 &spr_read_ureg, SPR_NOACCESS,
6200 &spr_read_ureg, SPR_NOACCESS,
6201 0x00000000);
6202 /* Memory management */
6203 gen_low_BATs(env);
6204 gen_high_BATs(env);
6205 gen_74xx_soft_tlb(env, 128, 2);
6206 init_excp_7450(env);
6207 env->dcache_line_size = 32;
6208 env->icache_line_size = 32;
6209 /* Allocate hardware IRQ controller */
6210 ppc6xx_irq_init(env);
6211 }
6212
6213 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6214 {
6215 DeviceClass *dc = DEVICE_CLASS(oc);
6216 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6217
6218 dc->desc = "PowerPC 7445 (aka G4)";
6219 pcc->init_proc = init_proc_7445;
6220 pcc->check_pow = check_pow_hid0_74xx;
6221 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6222 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6223 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6224 PPC_FLOAT_STFIWX |
6225 PPC_CACHE | PPC_CACHE_ICBI |
6226 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6227 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6228 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6229 PPC_MEM_TLBIA | PPC_74xx_TLB |
6230 PPC_SEGMENT | PPC_EXTERN |
6231 PPC_ALTIVEC;
6232 pcc->insns_flags2 = PPC_NONE;
6233 pcc->msr_mask = 0x000000000205FF77ULL;
6234 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6235 pcc->excp_model = POWERPC_EXCP_74xx;
6236 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6237 pcc->bfd_mach = bfd_mach_ppc_7400;
6238 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6239 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6240 POWERPC_FLAG_BUS_CLK;
6241 }
6242
6243 static void init_proc_7455 (CPUPPCState *env)
6244 {
6245 gen_spr_ne_601(env);
6246 gen_spr_7xx(env);
6247 /* Time base */
6248 gen_tbl(env);
6249 /* 74xx specific SPR */
6250 gen_spr_74xx(env);
6251 /* Level 3 cache control */
6252 gen_l3_ctrl(env);
6253 /* LDSTCR */
6254 /* XXX : not implemented */
6255 spr_register(env, SPR_LDSTCR, "LDSTCR",
6256 SPR_NOACCESS, SPR_NOACCESS,
6257 &spr_read_generic, &spr_write_generic,
6258 0x00000000);
6259 /* ICTRL */
6260 /* XXX : not implemented */
6261 spr_register(env, SPR_ICTRL, "ICTRL",
6262 SPR_NOACCESS, SPR_NOACCESS,
6263 &spr_read_generic, &spr_write_generic,
6264 0x00000000);
6265 /* MSSSR0 */
6266 /* XXX : not implemented */
6267 spr_register(env, SPR_MSSSR0, "MSSSR0",
6268 SPR_NOACCESS, SPR_NOACCESS,
6269 &spr_read_generic, &spr_write_generic,
6270 0x00000000);
6271 /* PMC */
6272 /* XXX : not implemented */
6273 spr_register(env, SPR_PMC5, "PMC5",
6274 SPR_NOACCESS, SPR_NOACCESS,
6275 &spr_read_generic, &spr_write_generic,
6276 0x00000000);
6277 /* XXX : not implemented */
6278 spr_register(env, SPR_UPMC5, "UPMC5",
6279 &spr_read_ureg, SPR_NOACCESS,
6280 &spr_read_ureg, SPR_NOACCESS,
6281 0x00000000);
6282 /* XXX : not implemented */
6283 spr_register(env, SPR_PMC6, "PMC6",
6284 SPR_NOACCESS, SPR_NOACCESS,
6285 &spr_read_generic, &spr_write_generic,
6286 0x00000000);
6287 /* XXX : not implemented */
6288 spr_register(env, SPR_UPMC6, "UPMC6",
6289 &spr_read_ureg, SPR_NOACCESS,
6290 &spr_read_ureg, SPR_NOACCESS,
6291 0x00000000);
6292 /* SPRGs */
6293 spr_register(env, SPR_SPRG4, "SPRG4",
6294 SPR_NOACCESS, SPR_NOACCESS,
6295 &spr_read_generic, &spr_write_generic,
6296 0x00000000);
6297 spr_register(env, SPR_USPRG4, "USPRG4",
6298 &spr_read_ureg, SPR_NOACCESS,
6299 &spr_read_ureg, SPR_NOACCESS,
6300 0x00000000);
6301 spr_register(env, SPR_SPRG5, "SPRG5",
6302 SPR_NOACCESS, SPR_NOACCESS,
6303 &spr_read_generic, &spr_write_generic,
6304 0x00000000);
6305 spr_register(env, SPR_USPRG5, "USPRG5",
6306 &spr_read_ureg, SPR_NOACCESS,
6307 &spr_read_ureg, SPR_NOACCESS,
6308 0x00000000);
6309 spr_register(env, SPR_SPRG6, "SPRG6",
6310 SPR_NOACCESS, SPR_NOACCESS,
6311 &spr_read_generic, &spr_write_generic,
6312 0x00000000);
6313 spr_register(env, SPR_USPRG6, "USPRG6",
6314 &spr_read_ureg, SPR_NOACCESS,
6315 &spr_read_ureg, SPR_NOACCESS,
6316 0x00000000);
6317 spr_register(env, SPR_SPRG7, "SPRG7",
6318 SPR_NOACCESS, SPR_NOACCESS,
6319 &spr_read_generic, &spr_write_generic,
6320 0x00000000);
6321 spr_register(env, SPR_USPRG7, "USPRG7",
6322 &spr_read_ureg, SPR_NOACCESS,
6323 &spr_read_ureg, SPR_NOACCESS,
6324 0x00000000);
6325 /* Memory management */
6326 gen_low_BATs(env);
6327 gen_high_BATs(env);
6328 gen_74xx_soft_tlb(env, 128, 2);
6329 init_excp_7450(env);
6330 env->dcache_line_size = 32;
6331 env->icache_line_size = 32;
6332 /* Allocate hardware IRQ controller */
6333 ppc6xx_irq_init(env);
6334 }
6335
6336 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6337 {
6338 DeviceClass *dc = DEVICE_CLASS(oc);
6339 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6340
6341 dc->desc = "PowerPC 7455 (aka G4)";
6342 pcc->init_proc = init_proc_7455;
6343 pcc->check_pow = check_pow_hid0_74xx;
6344 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6345 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6346 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6347 PPC_FLOAT_STFIWX |
6348 PPC_CACHE | PPC_CACHE_ICBI |
6349 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6350 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6351 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6352 PPC_MEM_TLBIA | PPC_74xx_TLB |
6353 PPC_SEGMENT | PPC_EXTERN |
6354 PPC_ALTIVEC;
6355 pcc->insns_flags2 = PPC_NONE;
6356 pcc->msr_mask = 0x000000000205FF77ULL;
6357 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6358 pcc->excp_model = POWERPC_EXCP_74xx;
6359 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6360 pcc->bfd_mach = bfd_mach_ppc_7400;
6361 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6362 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6363 POWERPC_FLAG_BUS_CLK;
6364 }
6365
6366 static void init_proc_7457 (CPUPPCState *env)
6367 {
6368 gen_spr_ne_601(env);
6369 gen_spr_7xx(env);
6370 /* Time base */
6371 gen_tbl(env);
6372 /* 74xx specific SPR */
6373 gen_spr_74xx(env);
6374 /* Level 3 cache control */
6375 gen_l3_ctrl(env);
6376 /* L3ITCR1 */
6377 /* XXX : not implemented */
6378 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6379 SPR_NOACCESS, SPR_NOACCESS,
6380 &spr_read_generic, &spr_write_generic,
6381 0x00000000);
6382 /* L3ITCR2 */
6383 /* XXX : not implemented */
6384 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6385 SPR_NOACCESS, SPR_NOACCESS,
6386 &spr_read_generic, &spr_write_generic,
6387 0x00000000);
6388 /* L3ITCR3 */
6389 /* XXX : not implemented */
6390 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6391 SPR_NOACCESS, SPR_NOACCESS,
6392 &spr_read_generic, &spr_write_generic,
6393 0x00000000);
6394 /* L3OHCR */
6395 /* XXX : not implemented */
6396 spr_register(env, SPR_L3OHCR, "L3OHCR",
6397 SPR_NOACCESS, SPR_NOACCESS,
6398 &spr_read_generic, &spr_write_generic,
6399 0x00000000);
6400 /* LDSTCR */
6401 /* XXX : not implemented */
6402 spr_register(env, SPR_LDSTCR, "LDSTCR",
6403 SPR_NOACCESS, SPR_NOACCESS,
6404 &spr_read_generic, &spr_write_generic,
6405 0x00000000);
6406 /* ICTRL */
6407 /* XXX : not implemented */
6408 spr_register(env, SPR_ICTRL, "ICTRL",
6409 SPR_NOACCESS, SPR_NOACCESS,
6410 &spr_read_generic, &spr_write_generic,
6411 0x00000000);
6412 /* MSSSR0 */
6413 /* XXX : not implemented */
6414 spr_register(env, SPR_MSSSR0, "MSSSR0",
6415 SPR_NOACCESS, SPR_NOACCESS,
6416 &spr_read_generic, &spr_write_generic,
6417 0x00000000);
6418 /* PMC */
6419 /* XXX : not implemented */
6420 spr_register(env, SPR_PMC5, "PMC5",
6421 SPR_NOACCESS, SPR_NOACCESS,
6422 &spr_read_generic, &spr_write_generic,
6423 0x00000000);
6424 /* XXX : not implemented */
6425 spr_register(env, SPR_UPMC5, "UPMC5",
6426 &spr_read_ureg, SPR_NOACCESS,
6427 &spr_read_ureg, SPR_NOACCESS,
6428 0x00000000);
6429 /* XXX : not implemented */
6430 spr_register(env, SPR_PMC6, "PMC6",
6431 SPR_NOACCESS, SPR_NOACCESS,
6432 &spr_read_generic, &spr_write_generic,
6433 0x00000000);
6434 /* XXX : not implemented */
6435 spr_register(env, SPR_UPMC6, "UPMC6",
6436 &spr_read_ureg, SPR_NOACCESS,
6437 &spr_read_ureg, SPR_NOACCESS,
6438 0x00000000);
6439 /* SPRGs */
6440 spr_register(env, SPR_SPRG4, "SPRG4",
6441 SPR_NOACCESS, SPR_NOACCESS,
6442 &spr_read_generic, &spr_write_generic,
6443 0x00000000);
6444 spr_register(env, SPR_USPRG4, "USPRG4",
6445 &spr_read_ureg, SPR_NOACCESS,
6446 &spr_read_ureg, SPR_NOACCESS,
6447 0x00000000);
6448 spr_register(env, SPR_SPRG5, "SPRG5",
6449 SPR_NOACCESS, SPR_NOACCESS,
6450 &spr_read_generic, &spr_write_generic,
6451 0x00000000);
6452 spr_register(env, SPR_USPRG5, "USPRG5",
6453 &spr_read_ureg, SPR_NOACCESS,
6454 &spr_read_ureg, SPR_NOACCESS,
6455 0x00000000);
6456 spr_register(env, SPR_SPRG6, "SPRG6",
6457 SPR_NOACCESS, SPR_NOACCESS,
6458 &spr_read_generic, &spr_write_generic,
6459 0x00000000);
6460 spr_register(env, SPR_USPRG6, "USPRG6",
6461 &spr_read_ureg, SPR_NOACCESS,
6462 &spr_read_ureg, SPR_NOACCESS,
6463 0x00000000);
6464 spr_register(env, SPR_SPRG7, "SPRG7",
6465 SPR_NOACCESS, SPR_NOACCESS,
6466 &spr_read_generic, &spr_write_generic,
6467 0x00000000);
6468 spr_register(env, SPR_USPRG7, "USPRG7",
6469 &spr_read_ureg, SPR_NOACCESS,
6470 &spr_read_ureg, SPR_NOACCESS,
6471 0x00000000);
6472 /* Memory management */
6473 gen_low_BATs(env);
6474 gen_high_BATs(env);
6475 gen_74xx_soft_tlb(env, 128, 2);
6476 init_excp_7450(env);
6477 env->dcache_line_size = 32;
6478 env->icache_line_size = 32;
6479 /* Allocate hardware IRQ controller */
6480 ppc6xx_irq_init(env);
6481 }
6482
6483 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6484 {
6485 DeviceClass *dc = DEVICE_CLASS(oc);
6486 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6487
6488 dc->desc = "PowerPC 7457 (aka G4)";
6489 pcc->init_proc = init_proc_7457;
6490 pcc->check_pow = check_pow_hid0_74xx;
6491 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6492 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6493 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6494 PPC_FLOAT_STFIWX |
6495 PPC_CACHE | PPC_CACHE_ICBI |
6496 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6497 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6498 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6499 PPC_MEM_TLBIA | PPC_74xx_TLB |
6500 PPC_SEGMENT | PPC_EXTERN |
6501 PPC_ALTIVEC;
6502 pcc->insns_flags2 = PPC_NONE;
6503 pcc->msr_mask = 0x000000000205FF77ULL;
6504 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6505 pcc->excp_model = POWERPC_EXCP_74xx;
6506 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6507 pcc->bfd_mach = bfd_mach_ppc_7400;
6508 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6509 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6510 POWERPC_FLAG_BUS_CLK;
6511 }
6512
6513 #if defined (TARGET_PPC64)
6514 #if defined(CONFIG_USER_ONLY)
6515 #define POWERPC970_HID5_INIT 0x00000080
6516 #else
6517 #define POWERPC970_HID5_INIT 0x00000000
6518 #endif
6519
6520 static int check_pow_970 (CPUPPCState *env)
6521 {
6522 if (env->spr[SPR_HID0] & 0x00600000)
6523 return 1;
6524
6525 return 0;
6526 }
6527
6528 static void init_proc_970 (CPUPPCState *env)
6529 {
6530 gen_spr_ne_601(env);
6531 gen_spr_7xx(env);
6532 /* Time base */
6533 gen_tbl(env);
6534 /* Hardware implementation registers */
6535 /* XXX : not implemented */
6536 spr_register(env, SPR_HID0, "HID0",
6537 SPR_NOACCESS, SPR_NOACCESS,
6538 &spr_read_generic, &spr_write_clear,
6539 0x60000000);
6540 /* XXX : not implemented */
6541 spr_register(env, SPR_HID1, "HID1",
6542 SPR_NOACCESS, SPR_NOACCESS,
6543 &spr_read_generic, &spr_write_generic,
6544 0x00000000);
6545 /* XXX : not implemented */
6546 spr_register(env, SPR_750FX_HID2, "HID2",
6547 SPR_NOACCESS, SPR_NOACCESS,
6548 &spr_read_generic, &spr_write_generic,
6549 0x00000000);
6550 /* XXX : not implemented */
6551 spr_register(env, SPR_970_HID5, "HID5",
6552 SPR_NOACCESS, SPR_NOACCESS,
6553 &spr_read_generic, &spr_write_generic,
6554 POWERPC970_HID5_INIT);
6555 /* XXX : not implemented */
6556 spr_register(env, SPR_L2CR, "L2CR",
6557 SPR_NOACCESS, SPR_NOACCESS,
6558 &spr_read_generic, &spr_write_generic,
6559 0x00000000);
6560 /* Memory management */
6561 /* XXX: not correct */
6562 gen_low_BATs(env);
6563 /* XXX : not implemented */
6564 spr_register(env, SPR_MMUCFG, "MMUCFG",
6565 SPR_NOACCESS, SPR_NOACCESS,
6566 &spr_read_generic, SPR_NOACCESS,
6567 0x00000000); /* TOFIX */
6568 /* XXX : not implemented */
6569 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6570 SPR_NOACCESS, SPR_NOACCESS,
6571 &spr_read_generic, &spr_write_generic,
6572 0x00000000); /* TOFIX */
6573 spr_register(env, SPR_HIOR, "SPR_HIOR",
6574 SPR_NOACCESS, SPR_NOACCESS,
6575 &spr_read_hior, &spr_write_hior,
6576 0x00000000);
6577 #if !defined(CONFIG_USER_ONLY)
6578 env->slb_nr = 32;
6579 #endif
6580 init_excp_970(env);
6581 env->dcache_line_size = 128;
6582 env->icache_line_size = 128;
6583 /* Allocate hardware IRQ controller */
6584 ppc970_irq_init(env);
6585 /* Can't find information on what this should be on reset. This
6586 * value is the one used by 74xx processors. */
6587 vscr_init(env, 0x00010000);
6588 }
6589
6590 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6591 {
6592 DeviceClass *dc = DEVICE_CLASS(oc);
6593 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6594
6595 dc->desc = "PowerPC 970";
6596 pcc->init_proc = init_proc_970;
6597 pcc->check_pow = check_pow_970;
6598 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6599 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6600 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6601 PPC_FLOAT_STFIWX |
6602 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6603 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6604 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6605 PPC_64B | PPC_ALTIVEC |
6606 PPC_SEGMENT_64B | PPC_SLBI;
6607 pcc->insns_flags2 = PPC_NONE;
6608 pcc->msr_mask = 0x900000000204FF36ULL;
6609 pcc->mmu_model = POWERPC_MMU_64B;
6610 #if defined(CONFIG_SOFTMMU)
6611 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6612 #endif
6613 pcc->excp_model = POWERPC_EXCP_970;
6614 pcc->bus_model = PPC_FLAGS_INPUT_970;
6615 pcc->bfd_mach = bfd_mach_ppc64;
6616 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6617 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6618 POWERPC_FLAG_BUS_CLK;
6619 }
6620
6621 static int check_pow_970FX (CPUPPCState *env)
6622 {
6623 if (env->spr[SPR_HID0] & 0x00600000)
6624 return 1;
6625
6626 return 0;
6627 }
6628
6629 static void init_proc_970FX (CPUPPCState *env)
6630 {
6631 gen_spr_ne_601(env);
6632 gen_spr_7xx(env);
6633 /* Time base */
6634 gen_tbl(env);
6635 /* Hardware implementation registers */
6636 /* XXX : not implemented */
6637 spr_register(env, SPR_HID0, "HID0",
6638 SPR_NOACCESS, SPR_NOACCESS,
6639 &spr_read_generic, &spr_write_clear,
6640 0x60000000);
6641 /* XXX : not implemented */
6642 spr_register(env, SPR_HID1, "HID1",
6643 SPR_NOACCESS, SPR_NOACCESS,
6644 &spr_read_generic, &spr_write_generic,
6645 0x00000000);
6646 /* XXX : not implemented */
6647 spr_register(env, SPR_750FX_HID2, "HID2",
6648 SPR_NOACCESS, SPR_NOACCESS,
6649 &spr_read_generic, &spr_write_generic,
6650 0x00000000);
6651 /* XXX : not implemented */
6652 spr_register(env, SPR_970_HID5, "HID5",
6653 SPR_NOACCESS, SPR_NOACCESS,
6654 &spr_read_generic, &spr_write_generic,
6655 POWERPC970_HID5_INIT);
6656 /* XXX : not implemented */
6657 spr_register(env, SPR_L2CR, "L2CR",
6658 SPR_NOACCESS, SPR_NOACCESS,
6659 &spr_read_generic, &spr_write_generic,
6660 0x00000000);
6661 /* Memory management */
6662 /* XXX: not correct */
6663 gen_low_BATs(env);
6664 /* XXX : not implemented */
6665 spr_register(env, SPR_MMUCFG, "MMUCFG",
6666 SPR_NOACCESS, SPR_NOACCESS,
6667 &spr_read_generic, SPR_NOACCESS,
6668 0x00000000); /* TOFIX */
6669 /* XXX : not implemented */
6670 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6671 SPR_NOACCESS, SPR_NOACCESS,
6672 &spr_read_generic, &spr_write_generic,
6673 0x00000000); /* TOFIX */
6674 spr_register(env, SPR_HIOR, "SPR_HIOR",
6675 SPR_NOACCESS, SPR_NOACCESS,
6676 &spr_read_hior, &spr_write_hior,
6677 0x00000000);
6678 spr_register(env, SPR_CTRL, "SPR_CTRL",
6679 SPR_NOACCESS, SPR_NOACCESS,
6680 &spr_read_generic, &spr_write_generic,
6681 0x00000000);
6682 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6683 SPR_NOACCESS, SPR_NOACCESS,
6684 &spr_read_generic, &spr_write_generic,
6685 0x00000000);
6686 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6687 &spr_read_generic, &spr_write_generic,
6688 &spr_read_generic, &spr_write_generic,
6689 0x00000000);
6690 #if !defined(CONFIG_USER_ONLY)
6691 env->slb_nr = 64;
6692 #endif
6693 init_excp_970(env);
6694 env->dcache_line_size = 128;
6695 env->icache_line_size = 128;
6696 /* Allocate hardware IRQ controller */
6697 ppc970_irq_init(env);
6698 /* Can't find information on what this should be on reset. This
6699 * value is the one used by 74xx processors. */
6700 vscr_init(env, 0x00010000);
6701 }
6702
6703 POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
6704 {
6705 DeviceClass *dc = DEVICE_CLASS(oc);
6706 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6707
6708 dc->desc = "PowerPC 970FX (aka G5)";
6709 pcc->init_proc = init_proc_970FX;
6710 pcc->check_pow = check_pow_970FX;
6711 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6712 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6713 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6714 PPC_FLOAT_STFIWX |
6715 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6716 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6717 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6718 PPC_64B | PPC_ALTIVEC |
6719 PPC_SEGMENT_64B | PPC_SLBI;
6720 pcc->insns_flags2 = PPC_NONE;
6721 pcc->msr_mask = 0x800000000204FF36ULL;
6722 pcc->mmu_model = POWERPC_MMU_64B;
6723 #if defined(CONFIG_SOFTMMU)
6724 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6725 #endif
6726 pcc->excp_model = POWERPC_EXCP_970;
6727 pcc->bus_model = PPC_FLAGS_INPUT_970;
6728 pcc->bfd_mach = bfd_mach_ppc64;
6729 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6730 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6731 POWERPC_FLAG_BUS_CLK;
6732 }
6733
6734 static int check_pow_970GX (CPUPPCState *env)
6735 {
6736 if (env->spr[SPR_HID0] & 0x00600000)
6737 return 1;
6738
6739 return 0;
6740 }
6741
6742 static void init_proc_970GX (CPUPPCState *env)
6743 {
6744 gen_spr_ne_601(env);
6745 gen_spr_7xx(env);
6746 /* Time base */
6747 gen_tbl(env);
6748 /* Hardware implementation registers */
6749 /* XXX : not implemented */
6750 spr_register(env, SPR_HID0, "HID0",
6751 SPR_NOACCESS, SPR_NOACCESS,
6752 &spr_read_generic, &spr_write_clear,
6753 0x60000000);
6754 /* XXX : not implemented */
6755 spr_register(env, SPR_HID1, "HID1",
6756 SPR_NOACCESS, SPR_NOACCESS,
6757 &spr_read_generic, &spr_write_generic,
6758 0x00000000);
6759 /* XXX : not implemented */
6760 spr_register(env, SPR_750FX_HID2, "HID2",
6761 SPR_NOACCESS, SPR_NOACCESS,
6762 &spr_read_generic, &spr_write_generic,
6763 0x00000000);
6764 /* XXX : not implemented */
6765 spr_register(env, SPR_970_HID5, "HID5",
6766 SPR_NOACCESS, SPR_NOACCESS,
6767 &spr_read_generic, &spr_write_generic,
6768 POWERPC970_HID5_INIT);
6769 /* XXX : not implemented */
6770 spr_register(env, SPR_L2CR, "L2CR",
6771 SPR_NOACCESS, SPR_NOACCESS,
6772 &spr_read_generic, &spr_write_generic,
6773 0x00000000);
6774 /* Memory management */
6775 /* XXX: not correct */
6776 gen_low_BATs(env);
6777 /* XXX : not implemented */
6778 spr_register(env, SPR_MMUCFG, "MMUCFG",
6779 SPR_NOACCESS, SPR_NOACCESS,
6780 &spr_read_generic, SPR_NOACCESS,
6781 0x00000000); /* TOFIX */
6782 /* XXX : not implemented */
6783 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6784 SPR_NOACCESS, SPR_NOACCESS,
6785 &spr_read_generic, &spr_write_generic,
6786 0x00000000); /* TOFIX */
6787 spr_register(env, SPR_HIOR, "SPR_HIOR",
6788 SPR_NOACCESS, SPR_NOACCESS,
6789 &spr_read_hior, &spr_write_hior,
6790 0x00000000);
6791 #if !defined(CONFIG_USER_ONLY)
6792 env->slb_nr = 32;
6793 #endif
6794 init_excp_970(env);
6795 env->dcache_line_size = 128;
6796 env->icache_line_size = 128;
6797 /* Allocate hardware IRQ controller */
6798 ppc970_irq_init(env);
6799 /* Can't find information on what this should be on reset. This
6800 * value is the one used by 74xx processors. */
6801 vscr_init(env, 0x00010000);
6802 }
6803
6804 POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data)
6805 {
6806 DeviceClass *dc = DEVICE_CLASS(oc);
6807 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6808
6809 dc->desc = "PowerPC 970 GX";
6810 pcc->init_proc = init_proc_970GX;
6811 pcc->check_pow = check_pow_970GX;
6812 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6813 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6814 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6815 PPC_FLOAT_STFIWX |
6816 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6817 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6818 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6819 PPC_64B | PPC_ALTIVEC |
6820 PPC_SEGMENT_64B | PPC_SLBI;
6821 pcc->insns_flags2 = PPC_NONE;
6822 pcc->msr_mask = 0x800000000204FF36ULL;
6823 pcc->mmu_model = POWERPC_MMU_64B;
6824 #if defined(CONFIG_SOFTMMU)
6825 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6826 #endif
6827 pcc->excp_model = POWERPC_EXCP_970;
6828 pcc->bus_model = PPC_FLAGS_INPUT_970;
6829 pcc->bfd_mach = bfd_mach_ppc64;
6830 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6831 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6832 POWERPC_FLAG_BUS_CLK;
6833 }
6834
6835 static int check_pow_970MP (CPUPPCState *env)
6836 {
6837 if (env->spr[SPR_HID0] & 0x01C00000)
6838 return 1;
6839
6840 return 0;
6841 }
6842
6843 static void init_proc_970MP (CPUPPCState *env)
6844 {
6845 gen_spr_ne_601(env);
6846 gen_spr_7xx(env);
6847 /* Time base */
6848 gen_tbl(env);
6849 /* Hardware implementation registers */
6850 /* XXX : not implemented */
6851 spr_register(env, SPR_HID0, "HID0",
6852 SPR_NOACCESS, SPR_NOACCESS,
6853 &spr_read_generic, &spr_write_clear,
6854 0x60000000);
6855 /* XXX : not implemented */
6856 spr_register(env, SPR_HID1, "HID1",
6857 SPR_NOACCESS, SPR_NOACCESS,
6858 &spr_read_generic, &spr_write_generic,
6859 0x00000000);
6860 /* XXX : not implemented */
6861 spr_register(env, SPR_750FX_HID2, "HID2",
6862 SPR_NOACCESS, SPR_NOACCESS,
6863 &spr_read_generic, &spr_write_generic,
6864 0x00000000);
6865 /* XXX : not implemented */
6866 spr_register(env, SPR_970_HID5, "HID5",
6867 SPR_NOACCESS, SPR_NOACCESS,
6868 &spr_read_generic, &spr_write_generic,
6869 POWERPC970_HID5_INIT);
6870 /* XXX : not implemented */
6871 spr_register(env, SPR_L2CR, "L2CR",
6872 SPR_NOACCESS, SPR_NOACCESS,
6873 &spr_read_generic, &spr_write_generic,
6874 0x00000000);
6875 /* Memory management */
6876 /* XXX: not correct */
6877 gen_low_BATs(env);
6878 /* XXX : not implemented */
6879 spr_register(env, SPR_MMUCFG, "MMUCFG",
6880 SPR_NOACCESS, SPR_NOACCESS,
6881 &spr_read_generic, SPR_NOACCESS,
6882 0x00000000); /* TOFIX */
6883 /* XXX : not implemented */
6884 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6885 SPR_NOACCESS, SPR_NOACCESS,
6886 &spr_read_generic, &spr_write_generic,
6887 0x00000000); /* TOFIX */
6888 spr_register(env, SPR_HIOR, "SPR_HIOR",
6889 SPR_NOACCESS, SPR_NOACCESS,
6890 &spr_read_hior, &spr_write_hior,
6891 0x00000000);
6892 #if !defined(CONFIG_USER_ONLY)
6893 env->slb_nr = 32;
6894 #endif
6895 init_excp_970(env);
6896 env->dcache_line_size = 128;
6897 env->icache_line_size = 128;
6898 /* Allocate hardware IRQ controller */
6899 ppc970_irq_init(env);
6900 /* Can't find information on what this should be on reset. This
6901 * value is the one used by 74xx processors. */
6902 vscr_init(env, 0x00010000);
6903 }
6904
6905 POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
6906 {
6907 DeviceClass *dc = DEVICE_CLASS(oc);
6908 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6909
6910 dc->desc = "PowerPC 970 MP";
6911 pcc->init_proc = init_proc_970MP;
6912 pcc->check_pow = check_pow_970MP;
6913 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6914 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6915 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6916 PPC_FLOAT_STFIWX |
6917 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6918 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6919 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6920 PPC_64B | PPC_ALTIVEC |
6921 PPC_SEGMENT_64B | PPC_SLBI;
6922 pcc->insns_flags2 = PPC_NONE;
6923 pcc->msr_mask = 0x900000000204FF36ULL;
6924 pcc->mmu_model = POWERPC_MMU_64B;
6925 #if defined(CONFIG_SOFTMMU)
6926 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6927 #endif
6928 pcc->excp_model = POWERPC_EXCP_970;
6929 pcc->bus_model = PPC_FLAGS_INPUT_970;
6930 pcc->bfd_mach = bfd_mach_ppc64;
6931 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6932 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6933 POWERPC_FLAG_BUS_CLK;
6934 }
6935
6936 static void init_proc_POWER7 (CPUPPCState *env)
6937 {
6938 gen_spr_ne_601(env);
6939 gen_spr_7xx(env);
6940 /* Time base */
6941 gen_tbl(env);
6942 /* Processor identification */
6943 spr_register(env, SPR_PIR, "PIR",
6944 SPR_NOACCESS, SPR_NOACCESS,
6945 &spr_read_generic, &spr_write_pir,
6946 0x00000000);
6947 #if !defined(CONFIG_USER_ONLY)
6948 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6949 spr_register_kvm(env, SPR_PURR, "PURR",
6950 &spr_read_purr, SPR_NOACCESS,
6951 &spr_read_purr, SPR_NOACCESS,
6952 KVM_REG_PPC_PURR, 0x00000000);
6953 spr_register_kvm(env, SPR_SPURR, "SPURR",
6954 &spr_read_purr, SPR_NOACCESS,
6955 &spr_read_purr, SPR_NOACCESS,
6956 KVM_REG_PPC_SPURR, 0x00000000);
6957 spr_register(env, SPR_CFAR, "SPR_CFAR",
6958 SPR_NOACCESS, SPR_NOACCESS,
6959 &spr_read_cfar, &spr_write_cfar,
6960 0x00000000);
6961 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
6962 SPR_NOACCESS, SPR_NOACCESS,
6963 &spr_read_generic, &spr_write_generic,
6964 KVM_REG_PPC_DSCR, 0x00000000);
6965 #endif /* !CONFIG_USER_ONLY */
6966 /* Memory management */
6967 /* XXX : not implemented */
6968 spr_register(env, SPR_MMUCFG, "MMUCFG",
6969 SPR_NOACCESS, SPR_NOACCESS,
6970 &spr_read_generic, SPR_NOACCESS,
6971 0x00000000); /* TOFIX */
6972 gen_spr_amr(env);
6973 /* XXX : not implemented */
6974 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6975 SPR_NOACCESS, SPR_NOACCESS,
6976 &spr_read_generic, &spr_write_generic,
6977 0x80800000);
6978 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6979 SPR_NOACCESS, SPR_NOACCESS,
6980 &spr_read_generic, &spr_write_generic,
6981 0x80800000);
6982 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6983 &spr_read_generic, &spr_write_generic,
6984 &spr_read_generic, &spr_write_generic,
6985 0x00000000);
6986 #if !defined(CONFIG_USER_ONLY)
6987 env->slb_nr = 32;
6988 #endif
6989 init_excp_POWER7(env);
6990 env->dcache_line_size = 128;
6991 env->icache_line_size = 128;
6992 /* Allocate hardware IRQ controller */
6993 ppcPOWER7_irq_init(env);
6994 /* Can't find information on what this should be on reset. This
6995 * value is the one used by 74xx processors. */
6996 vscr_init(env, 0x00010000);
6997 }
6998
6999 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7000 {
7001 DeviceClass *dc = DEVICE_CLASS(oc);
7002 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7003
7004 dc->desc = "POWER7";
7005 pcc->init_proc = init_proc_POWER7;
7006 pcc->check_pow = check_pow_nocheck;
7007 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7008 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7009 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7010 PPC_FLOAT_STFIWX |
7011 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7012 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7013 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7014 PPC_64B | PPC_ALTIVEC |
7015 PPC_SEGMENT_64B | PPC_SLBI |
7016 PPC_POPCNTB | PPC_POPCNTWD;
7017 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
7018 pcc->msr_mask = 0x800000000204FF36ULL;
7019 pcc->mmu_model = POWERPC_MMU_2_06;
7020 #if defined(CONFIG_SOFTMMU)
7021 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7022 #endif
7023 pcc->excp_model = POWERPC_EXCP_POWER7;
7024 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7025 pcc->bfd_mach = bfd_mach_ppc64;
7026 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7027 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7028 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR;
7029 }
7030 #endif /* defined (TARGET_PPC64) */
7031
7032
7033 /*****************************************************************************/
7034 /* Generic CPU instantiation routine */
7035 static void init_ppc_proc(PowerPCCPU *cpu)
7036 {
7037 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7038 CPUPPCState *env = &cpu->env;
7039 #if !defined(CONFIG_USER_ONLY)
7040 int i;
7041
7042 env->irq_inputs = NULL;
7043 /* Set all exception vectors to an invalid address */
7044 for (i = 0; i < POWERPC_EXCP_NB; i++)
7045 env->excp_vectors[i] = (target_ulong)(-1ULL);
7046 env->hreset_excp_prefix = 0x00000000;
7047 env->ivor_mask = 0x00000000;
7048 env->ivpr_mask = 0x00000000;
7049 /* Default MMU definitions */
7050 env->nb_BATs = 0;
7051 env->nb_tlb = 0;
7052 env->nb_ways = 0;
7053 env->tlb_type = TLB_NONE;
7054 #endif
7055 /* Register SPR common to all PowerPC implementations */
7056 gen_spr_generic(env);
7057 spr_register(env, SPR_PVR, "PVR",
7058 /* Linux permits userspace to read PVR */
7059 #if defined(CONFIG_LINUX_USER)
7060 &spr_read_generic,
7061 #else
7062 SPR_NOACCESS,
7063 #endif
7064 SPR_NOACCESS,
7065 &spr_read_generic, SPR_NOACCESS,
7066 pcc->pvr);
7067 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
7068 if (pcc->svr != POWERPC_SVR_NONE) {
7069 if (pcc->svr & POWERPC_SVR_E500) {
7070 spr_register(env, SPR_E500_SVR, "SVR",
7071 SPR_NOACCESS, SPR_NOACCESS,
7072 &spr_read_generic, SPR_NOACCESS,
7073 pcc->svr & ~POWERPC_SVR_E500);
7074 } else {
7075 spr_register(env, SPR_SVR, "SVR",
7076 SPR_NOACCESS, SPR_NOACCESS,
7077 &spr_read_generic, SPR_NOACCESS,
7078 pcc->svr);
7079 }
7080 }
7081 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7082 (*pcc->init_proc)(env);
7083 #if !defined(CONFIG_USER_ONLY)
7084 env->excp_prefix = env->hreset_excp_prefix;
7085 #endif
7086 /* MSR bits & flags consistency checks */
7087 if (env->msr_mask & (1 << 25)) {
7088 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7089 case POWERPC_FLAG_SPE:
7090 case POWERPC_FLAG_VRE:
7091 break;
7092 default:
7093 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7094 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7095 exit(1);
7096 }
7097 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7098 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7099 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7100 exit(1);
7101 }
7102 if (env->msr_mask & (1 << 17)) {
7103 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7104 case POWERPC_FLAG_TGPR:
7105 case POWERPC_FLAG_CE:
7106 break;
7107 default:
7108 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7109 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7110 exit(1);
7111 }
7112 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7113 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7114 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7115 exit(1);
7116 }
7117 if (env->msr_mask & (1 << 10)) {
7118 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7119 POWERPC_FLAG_UBLE)) {
7120 case POWERPC_FLAG_SE:
7121 case POWERPC_FLAG_DWE:
7122 case POWERPC_FLAG_UBLE:
7123 break;
7124 default:
7125 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7126 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7127 "POWERPC_FLAG_UBLE\n");
7128 exit(1);
7129 }
7130 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7131 POWERPC_FLAG_UBLE)) {
7132 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7133 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7134 "POWERPC_FLAG_UBLE\n");
7135 exit(1);
7136 }
7137 if (env->msr_mask & (1 << 9)) {
7138 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7139 case POWERPC_FLAG_BE:
7140 case POWERPC_FLAG_DE:
7141 break;
7142 default:
7143 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7144 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7145 exit(1);
7146 }
7147 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7148 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7149 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7150 exit(1);
7151 }
7152 if (env->msr_mask & (1 << 2)) {
7153 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7154 case POWERPC_FLAG_PX:
7155 case POWERPC_FLAG_PMM:
7156 break;
7157 default:
7158 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7159 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7160 exit(1);
7161 }
7162 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7163 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7164 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7165 exit(1);
7166 }
7167 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
7168 fprintf(stderr, "PowerPC flags inconsistency\n"
7169 "Should define the time-base and decrementer clock source\n");
7170 exit(1);
7171 }
7172 /* Allocate TLBs buffer when needed */
7173 #if !defined(CONFIG_USER_ONLY)
7174 if (env->nb_tlb != 0) {
7175 int nb_tlb = env->nb_tlb;
7176 if (env->id_tlbs != 0)
7177 nb_tlb *= 2;
7178 switch (env->tlb_type) {
7179 case TLB_6XX:
7180 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
7181 break;
7182 case TLB_EMB:
7183 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
7184 break;
7185 case TLB_MAS:
7186 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
7187 break;
7188 }
7189 /* Pre-compute some useful values */
7190 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7191 }
7192 if (env->irq_inputs == NULL) {
7193 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
7194 " Attempt QEMU to crash very soon !\n");
7195 }
7196 #endif
7197 if (env->check_pow == NULL) {
7198 fprintf(stderr, "WARNING: no power management check handler "
7199 "registered.\n"
7200 " Attempt QEMU to crash very soon !\n");
7201 }
7202 }
7203
7204 #if defined(PPC_DUMP_CPU)
7205 static void dump_ppc_sprs (CPUPPCState *env)
7206 {
7207 ppc_spr_t *spr;
7208 #if !defined(CONFIG_USER_ONLY)
7209 uint32_t sr, sw;
7210 #endif
7211 uint32_t ur, uw;
7212 int i, j, n;
7213
7214 printf("Special purpose registers:\n");
7215 for (i = 0; i < 32; i++) {
7216 for (j = 0; j < 32; j++) {
7217 n = (i << 5) | j;
7218 spr = &env->spr_cb[n];
7219 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
7220 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
7221 #if !defined(CONFIG_USER_ONLY)
7222 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
7223 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
7224 if (sw || sr || uw || ur) {
7225 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
7226 (i << 5) | j, (i << 5) | j, spr->name,
7227 sw ? 'w' : '-', sr ? 'r' : '-',
7228 uw ? 'w' : '-', ur ? 'r' : '-');
7229 }
7230 #else
7231 if (uw || ur) {
7232 printf("SPR: %4d (%03x) %-8s u%c%c\n",
7233 (i << 5) | j, (i << 5) | j, spr->name,
7234 uw ? 'w' : '-', ur ? 'r' : '-');
7235 }
7236 #endif
7237 }
7238 }
7239 fflush(stdout);
7240 fflush(stderr);
7241 }
7242 #endif
7243
7244 /*****************************************************************************/
7245 #include <stdlib.h>
7246 #include <string.h>
7247
7248 /* Opcode types */
7249 enum {
7250 PPC_DIRECT = 0, /* Opcode routine */
7251 PPC_INDIRECT = 1, /* Indirect opcode table */
7252 };
7253
7254 static inline int is_indirect_opcode (void *handler)
7255 {
7256 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
7257 }
7258
7259 static inline opc_handler_t **ind_table(void *handler)
7260 {
7261 return (opc_handler_t **)((uintptr_t)handler & ~3);
7262 }
7263
7264 /* Instruction table creation */
7265 /* Opcodes tables creation */
7266 static void fill_new_table (opc_handler_t **table, int len)
7267 {
7268 int i;
7269
7270 for (i = 0; i < len; i++)
7271 table[i] = &invalid_handler;
7272 }
7273
7274 static int create_new_table (opc_handler_t **table, unsigned char idx)
7275 {
7276 opc_handler_t **tmp;
7277
7278 tmp = malloc(0x20 * sizeof(opc_handler_t));
7279 fill_new_table(tmp, 0x20);
7280 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
7281
7282 return 0;
7283 }
7284
7285 static int insert_in_table (opc_handler_t **table, unsigned char idx,
7286 opc_handler_t *handler)
7287 {
7288 if (table[idx] != &invalid_handler)
7289 return -1;
7290 table[idx] = handler;
7291
7292 return 0;
7293 }
7294
7295 static int register_direct_insn (opc_handler_t **ppc_opcodes,
7296 unsigned char idx, opc_handler_t *handler)
7297 {
7298 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
7299 printf("*** ERROR: opcode %02x already assigned in main "
7300 "opcode table\n", idx);
7301 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7302 printf(" Registered handler '%s' - new handler '%s'\n",
7303 ppc_opcodes[idx]->oname, handler->oname);
7304 #endif
7305 return -1;
7306 }
7307
7308 return 0;
7309 }
7310
7311 static int register_ind_in_table (opc_handler_t **table,
7312 unsigned char idx1, unsigned char idx2,
7313 opc_handler_t *handler)
7314 {
7315 if (table[idx1] == &invalid_handler) {
7316 if (create_new_table(table, idx1) < 0) {
7317 printf("*** ERROR: unable to create indirect table "
7318 "idx=%02x\n", idx1);
7319 return -1;
7320 }
7321 } else {
7322 if (!is_indirect_opcode(table[idx1])) {
7323 printf("*** ERROR: idx %02x already assigned to a direct "
7324 "opcode\n", idx1);
7325 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7326 printf(" Registered handler '%s' - new handler '%s'\n",
7327 ind_table(table[idx1])[idx2]->oname, handler->oname);
7328 #endif
7329 return -1;
7330 }
7331 }
7332 if (handler != NULL &&
7333 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
7334 printf("*** ERROR: opcode %02x already assigned in "
7335 "opcode table %02x\n", idx2, idx1);
7336 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7337 printf(" Registered handler '%s' - new handler '%s'\n",
7338 ind_table(table[idx1])[idx2]->oname, handler->oname);
7339 #endif
7340 return -1;
7341 }
7342
7343 return 0;
7344 }
7345
7346 static int register_ind_insn (opc_handler_t **ppc_opcodes,
7347 unsigned char idx1, unsigned char idx2,
7348 opc_handler_t *handler)
7349 {
7350 int ret;
7351
7352 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
7353
7354 return ret;
7355 }
7356
7357 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
7358 unsigned char idx1, unsigned char idx2,
7359 unsigned char idx3, opc_handler_t *handler)
7360 {
7361 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
7362 printf("*** ERROR: unable to join indirect table idx "
7363 "[%02x-%02x]\n", idx1, idx2);
7364 return -1;
7365 }
7366 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
7367 handler) < 0) {
7368 printf("*** ERROR: unable to insert opcode "
7369 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7370 return -1;
7371 }
7372
7373 return 0;
7374 }
7375
7376 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
7377 {
7378 if (insn->opc2 != 0xFF) {
7379 if (insn->opc3 != 0xFF) {
7380 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7381 insn->opc3, &insn->handler) < 0)
7382 return -1;
7383 } else {
7384 if (register_ind_insn(ppc_opcodes, insn->opc1,
7385 insn->opc2, &insn->handler) < 0)
7386 return -1;
7387 }
7388 } else {
7389 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
7390 return -1;
7391 }
7392
7393 return 0;
7394 }
7395
7396 static int test_opcode_table (opc_handler_t **table, int len)
7397 {
7398 int i, count, tmp;
7399
7400 for (i = 0, count = 0; i < len; i++) {
7401 /* Consistency fixup */
7402 if (table[i] == NULL)
7403 table[i] = &invalid_handler;
7404 if (table[i] != &invalid_handler) {
7405 if (is_indirect_opcode(table[i])) {
7406 tmp = test_opcode_table(ind_table(table[i]), 0x20);
7407 if (tmp == 0) {
7408 free(table[i]);
7409 table[i] = &invalid_handler;
7410 } else {
7411 count++;
7412 }
7413 } else {
7414 count++;
7415 }
7416 }
7417 }
7418
7419 return count;
7420 }
7421
7422 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
7423 {
7424 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
7425 printf("*** WARNING: no opcode defined !\n");
7426 }
7427
7428 /*****************************************************************************/
7429 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
7430 {
7431 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7432 CPUPPCState *env = &cpu->env;
7433 opcode_t *opc;
7434
7435 fill_new_table(env->opcodes, 0x40);
7436 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
7437 if (((opc->handler.type & pcc->insns_flags) != 0) ||
7438 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
7439 if (register_insn(env->opcodes, opc) < 0) {
7440 error_setg(errp, "ERROR initializing PowerPC instruction "
7441 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
7442 opc->opc3);
7443 return;
7444 }
7445 }
7446 }
7447 fix_opcode_tables(env->opcodes);
7448 fflush(stdout);
7449 fflush(stderr);
7450 }
7451
7452 #if defined(PPC_DUMP_CPU)
7453 static void dump_ppc_insns (CPUPPCState *env)
7454 {
7455 opc_handler_t **table, *handler;
7456 const char *p, *q;
7457 uint8_t opc1, opc2, opc3;
7458
7459 printf("Instructions set:\n");
7460 /* opc1 is 6 bits long */
7461 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
7462 table = env->opcodes;
7463 handler = table[opc1];
7464 if (is_indirect_opcode(handler)) {
7465 /* opc2 is 5 bits long */
7466 for (opc2 = 0; opc2 < 0x20; opc2++) {
7467 table = env->opcodes;
7468 handler = env->opcodes[opc1];
7469 table = ind_table(handler);
7470 handler = table[opc2];
7471 if (is_indirect_opcode(handler)) {
7472 table = ind_table(handler);
7473 /* opc3 is 5 bits long */
7474 for (opc3 = 0; opc3 < 0x20; opc3++) {
7475 handler = table[opc3];
7476 if (handler->handler != &gen_invalid) {
7477 /* Special hack to properly dump SPE insns */
7478 p = strchr(handler->oname, '_');
7479 if (p == NULL) {
7480 printf("INSN: %02x %02x %02x (%02d %04d) : "
7481 "%s\n",
7482 opc1, opc2, opc3, opc1,
7483 (opc3 << 5) | opc2,
7484 handler->oname);
7485 } else {
7486 q = "speundef";
7487 if ((p - handler->oname) != strlen(q) ||
7488 memcmp(handler->oname, q, strlen(q)) != 0) {
7489 /* First instruction */
7490 printf("INSN: %02x %02x %02x (%02d %04d) : "
7491 "%.*s\n",
7492 opc1, opc2 << 1, opc3, opc1,
7493 (opc3 << 6) | (opc2 << 1),
7494 (int)(p - handler->oname),
7495 handler->oname);
7496 }
7497 if (strcmp(p + 1, q) != 0) {
7498 /* Second instruction */
7499 printf("INSN: %02x %02x %02x (%02d %04d) : "
7500 "%s\n",
7501 opc1, (opc2 << 1) | 1, opc3, opc1,
7502 (opc3 << 6) | (opc2 << 1) | 1,
7503 p + 1);
7504 }
7505 }
7506 }
7507 }
7508 } else {
7509 if (handler->handler != &gen_invalid) {
7510 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
7511 opc1, opc2, opc1, opc2, handler->oname);
7512 }
7513 }
7514 }
7515 } else {
7516 if (handler->handler != &gen_invalid) {
7517 printf("INSN: %02x -- -- (%02d ----) : %s\n",
7518 opc1, opc1, handler->oname);
7519 }
7520 }
7521 }
7522 }
7523 #endif
7524
7525 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7526 {
7527 if (n < 32) {
7528 stfq_p(mem_buf, env->fpr[n]);
7529 return 8;
7530 }
7531 if (n == 32) {
7532 stl_p(mem_buf, env->fpscr);
7533 return 4;
7534 }
7535 return 0;
7536 }
7537
7538 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7539 {
7540 if (n < 32) {
7541 env->fpr[n] = ldfq_p(mem_buf);
7542 return 8;
7543 }
7544 if (n == 32) {
7545 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
7546 return 4;
7547 }
7548 return 0;
7549 }
7550
7551 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7552 {
7553 if (n < 32) {
7554 #ifdef HOST_WORDS_BIGENDIAN
7555 stq_p(mem_buf, env->avr[n].u64[0]);
7556 stq_p(mem_buf+8, env->avr[n].u64[1]);
7557 #else
7558 stq_p(mem_buf, env->avr[n].u64[1]);
7559 stq_p(mem_buf+8, env->avr[n].u64[0]);
7560 #endif
7561 return 16;
7562 }
7563 if (n == 32) {
7564 stl_p(mem_buf, env->vscr);
7565 return 4;
7566 }
7567 if (n == 33) {
7568 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
7569 return 4;
7570 }
7571 return 0;
7572 }
7573
7574 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7575 {
7576 if (n < 32) {
7577 #ifdef HOST_WORDS_BIGENDIAN
7578 env->avr[n].u64[0] = ldq_p(mem_buf);
7579 env->avr[n].u64[1] = ldq_p(mem_buf+8);
7580 #else
7581 env->avr[n].u64[1] = ldq_p(mem_buf);
7582 env->avr[n].u64[0] = ldq_p(mem_buf+8);
7583 #endif
7584 return 16;
7585 }
7586 if (n == 32) {
7587 env->vscr = ldl_p(mem_buf);
7588 return 4;
7589 }
7590 if (n == 33) {
7591 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
7592 return 4;
7593 }
7594 return 0;
7595 }
7596
7597 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7598 {
7599 if (n < 32) {
7600 #if defined(TARGET_PPC64)
7601 stl_p(mem_buf, env->gpr[n] >> 32);
7602 #else
7603 stl_p(mem_buf, env->gprh[n]);
7604 #endif
7605 return 4;
7606 }
7607 if (n == 32) {
7608 stq_p(mem_buf, env->spe_acc);
7609 return 8;
7610 }
7611 if (n == 33) {
7612 stl_p(mem_buf, env->spe_fscr);
7613 return 4;
7614 }
7615 return 0;
7616 }
7617
7618 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7619 {
7620 if (n < 32) {
7621 #if defined(TARGET_PPC64)
7622 target_ulong lo = (uint32_t)env->gpr[n];
7623 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
7624 env->gpr[n] = lo | hi;
7625 #else
7626 env->gprh[n] = ldl_p(mem_buf);
7627 #endif
7628 return 4;
7629 }
7630 if (n == 32) {
7631 env->spe_acc = ldq_p(mem_buf);
7632 return 8;
7633 }
7634 if (n == 33) {
7635 env->spe_fscr = ldl_p(mem_buf);
7636 return 4;
7637 }
7638 return 0;
7639 }
7640
7641 static int ppc_fixup_cpu(PowerPCCPU *cpu)
7642 {
7643 CPUPPCState *env = &cpu->env;
7644
7645 /* TCG doesn't (yet) emulate some groups of instructions that
7646 * are implemented on some otherwise supported CPUs (e.g. VSX
7647 * and decimal floating point instructions on POWER7). We
7648 * remove unsupported instruction groups from the cpu state's
7649 * instruction masks and hope the guest can cope. For at
7650 * least the pseries machine, the unavailability of these
7651 * instructions can be advertised to the guest via the device
7652 * tree. */
7653 if ((env->insns_flags & ~PPC_TCG_INSNS)
7654 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
7655 fprintf(stderr, "Warning: Disabling some instructions which are not "
7656 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
7657 env->insns_flags & ~PPC_TCG_INSNS,
7658 env->insns_flags2 & ~PPC_TCG_INSNS2);
7659 }
7660 env->insns_flags &= PPC_TCG_INSNS;
7661 env->insns_flags2 &= PPC_TCG_INSNS2;
7662 return 0;
7663 }
7664
7665 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
7666 {
7667 PowerPCCPU *cpu = POWERPC_CPU(dev);
7668 CPUPPCState *env = &cpu->env;
7669 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7670 Error *local_err = NULL;
7671 #if !defined(CONFIG_USER_ONLY)
7672 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
7673 #endif
7674
7675 #if !defined(CONFIG_USER_ONLY)
7676 if (smp_threads > max_smt) {
7677 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
7678 max_smt, kvm_enabled() ? "KVM" : "TCG");
7679 return;
7680 }
7681 #endif
7682
7683 if (kvm_enabled()) {
7684 if (kvmppc_fixup_cpu(cpu) != 0) {
7685 error_setg(errp, "Unable to virtualize selected CPU with KVM");
7686 return;
7687 }
7688 } else {
7689 if (ppc_fixup_cpu(cpu) != 0) {
7690 error_setg(errp, "Unable to emulate selected CPU with TCG");
7691 return;
7692 }
7693 }
7694
7695 #if defined(TARGET_PPCEMB)
7696 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
7697 error_setg(errp, "CPU does not possess a BookE MMU. "
7698 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
7699 "or choose another CPU model.");
7700 return;
7701 }
7702 #endif
7703
7704 create_ppc_opcodes(cpu, &local_err);
7705 if (local_err != NULL) {
7706 error_propagate(errp, local_err);
7707 return;
7708 }
7709 init_ppc_proc(cpu);
7710
7711 if (pcc->insns_flags & PPC_FLOAT) {
7712 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
7713 33, "power-fpu.xml", 0);
7714 }
7715 if (pcc->insns_flags & PPC_ALTIVEC) {
7716 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
7717 34, "power-altivec.xml", 0);
7718 }
7719 if (pcc->insns_flags & PPC_SPE) {
7720 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
7721 34, "power-spe.xml", 0);
7722 }
7723
7724 qemu_init_vcpu(env);
7725
7726 pcc->parent_realize(dev, errp);
7727
7728 #if defined(PPC_DUMP_CPU)
7729 {
7730 const char *mmu_model, *excp_model, *bus_model;
7731 switch (env->mmu_model) {
7732 case POWERPC_MMU_32B:
7733 mmu_model = "PowerPC 32";
7734 break;
7735 case POWERPC_MMU_SOFT_6xx:
7736 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
7737 break;
7738 case POWERPC_MMU_SOFT_74xx:
7739 mmu_model = "PowerPC 74xx with software driven TLBs";
7740 break;
7741 case POWERPC_MMU_SOFT_4xx:
7742 mmu_model = "PowerPC 4xx with software driven TLBs";
7743 break;
7744 case POWERPC_MMU_SOFT_4xx_Z:
7745 mmu_model = "PowerPC 4xx with software driven TLBs "
7746 "and zones protections";
7747 break;
7748 case POWERPC_MMU_REAL:
7749 mmu_model = "PowerPC real mode only";
7750 break;
7751 case POWERPC_MMU_MPC8xx:
7752 mmu_model = "PowerPC MPC8xx";
7753 break;
7754 case POWERPC_MMU_BOOKE:
7755 mmu_model = "PowerPC BookE";
7756 break;
7757 case POWERPC_MMU_BOOKE206:
7758 mmu_model = "PowerPC BookE 2.06";
7759 break;
7760 case POWERPC_MMU_601:
7761 mmu_model = "PowerPC 601";
7762 break;
7763 #if defined (TARGET_PPC64)
7764 case POWERPC_MMU_64B:
7765 mmu_model = "PowerPC 64";
7766 break;
7767 #endif
7768 default:
7769 mmu_model = "Unknown or invalid";
7770 break;
7771 }
7772 switch (env->excp_model) {
7773 case POWERPC_EXCP_STD:
7774 excp_model = "PowerPC";
7775 break;
7776 case POWERPC_EXCP_40x:
7777 excp_model = "PowerPC 40x";
7778 break;
7779 case POWERPC_EXCP_601:
7780 excp_model = "PowerPC 601";
7781 break;
7782 case POWERPC_EXCP_602:
7783 excp_model = "PowerPC 602";
7784 break;
7785 case POWERPC_EXCP_603:
7786 excp_model = "PowerPC 603";
7787 break;
7788 case POWERPC_EXCP_603E:
7789 excp_model = "PowerPC 603e";
7790 break;
7791 case POWERPC_EXCP_604:
7792 excp_model = "PowerPC 604";
7793 break;
7794 case POWERPC_EXCP_7x0:
7795 excp_model = "PowerPC 740/750";
7796 break;
7797 case POWERPC_EXCP_7x5:
7798 excp_model = "PowerPC 745/755";
7799 break;
7800 case POWERPC_EXCP_74xx:
7801 excp_model = "PowerPC 74xx";
7802 break;
7803 case POWERPC_EXCP_BOOKE:
7804 excp_model = "PowerPC BookE";
7805 break;
7806 #if defined (TARGET_PPC64)
7807 case POWERPC_EXCP_970:
7808 excp_model = "PowerPC 970";
7809 break;
7810 #endif
7811 default:
7812 excp_model = "Unknown or invalid";
7813 break;
7814 }
7815 switch (env->bus_model) {
7816 case PPC_FLAGS_INPUT_6xx:
7817 bus_model = "PowerPC 6xx";
7818 break;
7819 case PPC_FLAGS_INPUT_BookE:
7820 bus_model = "PowerPC BookE";
7821 break;
7822 case PPC_FLAGS_INPUT_405:
7823 bus_model = "PowerPC 405";
7824 break;
7825 case PPC_FLAGS_INPUT_401:
7826 bus_model = "PowerPC 401/403";
7827 break;
7828 case PPC_FLAGS_INPUT_RCPU:
7829 bus_model = "RCPU / MPC8xx";
7830 break;
7831 #if defined (TARGET_PPC64)
7832 case PPC_FLAGS_INPUT_970:
7833 bus_model = "PowerPC 970";
7834 break;
7835 #endif
7836 default:
7837 bus_model = "Unknown or invalid";
7838 break;
7839 }
7840 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
7841 " MMU model : %s\n",
7842 pcc->name, pcc->pvr, pcc->msr_mask, mmu_model);
7843 #if !defined(CONFIG_USER_ONLY)
7844 if (env->tlb != NULL) {
7845 printf(" %d %s TLB in %d ways\n",
7846 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
7847 env->nb_ways);
7848 }
7849 #endif
7850 printf(" Exceptions model : %s\n"
7851 " Bus model : %s\n",
7852 excp_model, bus_model);
7853 printf(" MSR features :\n");
7854 if (env->flags & POWERPC_FLAG_SPE)
7855 printf(" signal processing engine enable"
7856 "\n");
7857 else if (env->flags & POWERPC_FLAG_VRE)
7858 printf(" vector processor enable\n");
7859 if (env->flags & POWERPC_FLAG_TGPR)
7860 printf(" temporary GPRs\n");
7861 else if (env->flags & POWERPC_FLAG_CE)
7862 printf(" critical input enable\n");
7863 if (env->flags & POWERPC_FLAG_SE)
7864 printf(" single-step trace mode\n");
7865 else if (env->flags & POWERPC_FLAG_DWE)
7866 printf(" debug wait enable\n");
7867 else if (env->flags & POWERPC_FLAG_UBLE)
7868 printf(" user BTB lock enable\n");
7869 if (env->flags & POWERPC_FLAG_BE)
7870 printf(" branch-step trace mode\n");
7871 else if (env->flags & POWERPC_FLAG_DE)
7872 printf(" debug interrupt enable\n");
7873 if (env->flags & POWERPC_FLAG_PX)
7874 printf(" inclusive protection\n");
7875 else if (env->flags & POWERPC_FLAG_PMM)
7876 printf(" performance monitor mark\n");
7877 if (env->flags == POWERPC_FLAG_NONE)
7878 printf(" none\n");
7879 printf(" Time-base/decrementer clock source: %s\n",
7880 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
7881 }
7882 dump_ppc_insns(env);
7883 dump_ppc_sprs(env);
7884 fflush(stdout);
7885 #endif
7886 }
7887
7888 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
7889 {
7890 ObjectClass *oc = (ObjectClass *)a;
7891 uint32_t pvr = *(uint32_t *)b;
7892 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7893
7894 /* -cpu host does a PVR lookup during construction */
7895 if (unlikely(strcmp(object_class_get_name(oc),
7896 TYPE_HOST_POWERPC_CPU) == 0)) {
7897 return -1;
7898 }
7899
7900 #if defined(TARGET_PPCEMB)
7901 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
7902 return -1;
7903 }
7904 #endif
7905
7906 return pcc->pvr == pvr ? 0 : -1;
7907 }
7908
7909 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
7910 {
7911 GSList *list, *item;
7912 PowerPCCPUClass *pcc = NULL;
7913
7914 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7915 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
7916 if (item != NULL) {
7917 pcc = POWERPC_CPU_CLASS(item->data);
7918 }
7919 g_slist_free(list);
7920
7921 return pcc;
7922 }
7923
7924 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
7925 {
7926 ObjectClass *oc = (ObjectClass *)a;
7927 const char *name = b;
7928 #if defined(TARGET_PPCEMB)
7929 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7930 #endif
7931
7932 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
7933 #if defined(TARGET_PPCEMB)
7934 pcc->mmu_model == POWERPC_MMU_BOOKE &&
7935 #endif
7936 strcmp(object_class_get_name(oc) + strlen(name),
7937 "-" TYPE_POWERPC_CPU) == 0) {
7938 return 0;
7939 }
7940 return -1;
7941 }
7942
7943 #include <ctype.h>
7944
7945 static ObjectClass *ppc_cpu_class_by_name(const char *name)
7946 {
7947 GSList *list, *item;
7948 ObjectClass *ret = NULL;
7949 const char *p;
7950 int i, len;
7951
7952 /* Check if the given name is a PVR */
7953 len = strlen(name);
7954 if (len == 10 && name[0] == '0' && name[1] == 'x') {
7955 p = name + 2;
7956 goto check_pvr;
7957 } else if (len == 8) {
7958 p = name;
7959 check_pvr:
7960 for (i = 0; i < 8; i++) {
7961 if (!qemu_isxdigit(*p++))
7962 break;
7963 }
7964 if (i == 8) {
7965 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
7966 return ret;
7967 }
7968 }
7969
7970 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7971 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
7972 return ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
7973 }
7974 }
7975
7976 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7977 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
7978 if (item != NULL) {
7979 ret = OBJECT_CLASS(item->data);
7980 }
7981 g_slist_free(list);
7982
7983 return ret;
7984 }
7985
7986 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
7987 {
7988 PowerPCCPU *cpu;
7989 CPUPPCState *env;
7990 ObjectClass *oc;
7991 Error *err = NULL;
7992
7993 oc = ppc_cpu_class_by_name(cpu_model);
7994 if (oc == NULL) {
7995 return NULL;
7996 }
7997
7998 cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
7999 env = &cpu->env;
8000 env->cpu_model_str = cpu_model;
8001
8002 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
8003 if (err != NULL) {
8004 fprintf(stderr, "%s\n", error_get_pretty(err));
8005 error_free(err);
8006 object_unref(OBJECT(cpu));
8007 return NULL;
8008 }
8009
8010 return cpu;
8011 }
8012
8013 /* Sort by PVR, ordering special case "host" last. */
8014 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
8015 {
8016 ObjectClass *oc_a = (ObjectClass *)a;
8017 ObjectClass *oc_b = (ObjectClass *)b;
8018 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
8019 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
8020 const char *name_a = object_class_get_name(oc_a);
8021 const char *name_b = object_class_get_name(oc_b);
8022
8023 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8024 return 1;
8025 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8026 return -1;
8027 } else {
8028 /* Avoid an integer overflow during subtraction */
8029 if (pcc_a->pvr < pcc_b->pvr) {
8030 return -1;
8031 } else if (pcc_a->pvr > pcc_b->pvr) {
8032 return 1;
8033 } else {
8034 return 0;
8035 }
8036 }
8037 }
8038
8039 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
8040 {
8041 ObjectClass *oc = data;
8042 CPUListState *s = user_data;
8043 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8044 const char *typename = object_class_get_name(oc);
8045 char *name;
8046 int i;
8047
8048 #if defined(TARGET_PPCEMB)
8049 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8050 return;
8051 }
8052 #endif
8053 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
8054 return;
8055 }
8056
8057 name = g_strndup(typename,
8058 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
8059 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
8060 name, pcc->pvr);
8061 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8062 const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8063 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
8064
8065 if (alias_oc != oc) {
8066 continue;
8067 }
8068 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
8069 alias->alias, name);
8070 }
8071 g_free(name);
8072 }
8073
8074 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
8075 {
8076 CPUListState s = {
8077 .file = f,
8078 .cpu_fprintf = cpu_fprintf,
8079 };
8080 GSList *list;
8081
8082 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8083 list = g_slist_sort(list, ppc_cpu_list_compare);
8084 g_slist_foreach(list, ppc_cpu_list_entry, &s);
8085 g_slist_free(list);
8086
8087 #ifdef CONFIG_KVM
8088 cpu_fprintf(f, "\n");
8089 cpu_fprintf(f, "PowerPC %-16s\n", "host");
8090 #endif
8091 }
8092
8093 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
8094 {
8095 ObjectClass *oc = data;
8096 CpuDefinitionInfoList **first = user_data;
8097 const char *typename;
8098 CpuDefinitionInfoList *entry;
8099 CpuDefinitionInfo *info;
8100 #if defined(TARGET_PPCEMB)
8101 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8102
8103 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8104 return;
8105 }
8106 #endif
8107
8108 typename = object_class_get_name(oc);
8109 info = g_malloc0(sizeof(*info));
8110 info->name = g_strndup(typename,
8111 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
8112
8113 entry = g_malloc0(sizeof(*entry));
8114 entry->value = info;
8115 entry->next = *first;
8116 *first = entry;
8117 }
8118
8119 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
8120 {
8121 CpuDefinitionInfoList *cpu_list = NULL;
8122 GSList *list;
8123 int i;
8124
8125 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8126 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
8127 g_slist_free(list);
8128
8129 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8130 const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8131 ObjectClass *oc;
8132 CpuDefinitionInfoList *entry;
8133 CpuDefinitionInfo *info;
8134
8135 oc = ppc_cpu_class_by_name(alias->model);
8136 if (oc == NULL) {
8137 continue;
8138 }
8139
8140 info = g_malloc0(sizeof(*info));
8141 info->name = g_strdup(alias->alias);
8142
8143 entry = g_malloc0(sizeof(*entry));
8144 entry->value = info;
8145 entry->next = cpu_list;
8146 cpu_list = entry;
8147 }
8148
8149 return cpu_list;
8150 }
8151
8152 /* CPUClass::reset() */
8153 static void ppc_cpu_reset(CPUState *s)
8154 {
8155 PowerPCCPU *cpu = POWERPC_CPU(s);
8156 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8157 CPUPPCState *env = &cpu->env;
8158 target_ulong msr;
8159
8160 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
8161 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
8162 log_cpu_state(env, 0);
8163 }
8164
8165 pcc->parent_reset(s);
8166
8167 msr = (target_ulong)0;
8168 if (0) {
8169 /* XXX: find a suitable condition to enable the hypervisor mode */
8170 msr |= (target_ulong)MSR_HVB;
8171 }
8172 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
8173 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
8174 msr |= (target_ulong)1 << MSR_EP;
8175 #if defined(DO_SINGLE_STEP) && 0
8176 /* Single step trace mode */
8177 msr |= (target_ulong)1 << MSR_SE;
8178 msr |= (target_ulong)1 << MSR_BE;
8179 #endif
8180 #if defined(CONFIG_USER_ONLY)
8181 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
8182 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
8183 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
8184 msr |= (target_ulong)1 << MSR_PR;
8185 #else
8186 env->excp_prefix = env->hreset_excp_prefix;
8187 env->nip = env->hreset_vector | env->excp_prefix;
8188 if (env->mmu_model != POWERPC_MMU_REAL) {
8189 ppc_tlb_invalidate_all(env);
8190 }
8191 #endif
8192 env->msr = msr & env->msr_mask;
8193 #if defined(TARGET_PPC64)
8194 if (env->mmu_model & POWERPC_MMU_64) {
8195 env->msr |= (1ULL << MSR_SF);
8196 }
8197 #endif
8198 hreg_compute_hflags(env);
8199 env->reserve_addr = (target_ulong)-1ULL;
8200 /* Be sure no exception or interrupt is pending */
8201 env->pending_interrupts = 0;
8202 env->exception_index = POWERPC_EXCP_NONE;
8203 env->error_code = 0;
8204
8205 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
8206 env->vpa_addr = 0;
8207 env->slb_shadow_addr = 0;
8208 env->slb_shadow_size = 0;
8209 env->dtl_addr = 0;
8210 env->dtl_size = 0;
8211 #endif /* TARGET_PPC64 */
8212
8213 /* Flush all TLBs */
8214 tlb_flush(env, 1);
8215 }
8216
8217 static void ppc_cpu_initfn(Object *obj)
8218 {
8219 CPUState *cs = CPU(obj);
8220 PowerPCCPU *cpu = POWERPC_CPU(obj);
8221 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8222 CPUPPCState *env = &cpu->env;
8223
8224 cs->env_ptr = env;
8225 cpu_exec_init(env);
8226
8227 env->msr_mask = pcc->msr_mask;
8228 env->mmu_model = pcc->mmu_model;
8229 env->excp_model = pcc->excp_model;
8230 env->bus_model = pcc->bus_model;
8231 env->insns_flags = pcc->insns_flags;
8232 env->insns_flags2 = pcc->insns_flags2;
8233 env->flags = pcc->flags;
8234 env->bfd_mach = pcc->bfd_mach;
8235 env->check_pow = pcc->check_pow;
8236
8237 #if defined(TARGET_PPC64)
8238 if (pcc->sps) {
8239 env->sps = *pcc->sps;
8240 } else if (env->mmu_model & POWERPC_MMU_64) {
8241 /* Use default sets of page sizes */
8242 static const struct ppc_segment_page_sizes defsps = {
8243 .sps = {
8244 { .page_shift = 12, /* 4K */
8245 .slb_enc = 0,
8246 .enc = { { .page_shift = 12, .pte_enc = 0 } }
8247 },
8248 { .page_shift = 24, /* 16M */
8249 .slb_enc = 0x100,
8250 .enc = { { .page_shift = 24, .pte_enc = 0 } }
8251 },
8252 },
8253 };
8254 env->sps = defsps;
8255 }
8256 #endif /* defined(TARGET_PPC64) */
8257
8258 if (tcg_enabled()) {
8259 ppc_translate_init();
8260 }
8261 }
8262
8263 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
8264 {
8265 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8266 CPUClass *cc = CPU_CLASS(oc);
8267 DeviceClass *dc = DEVICE_CLASS(oc);
8268
8269 pcc->parent_realize = dc->realize;
8270 dc->realize = ppc_cpu_realizefn;
8271
8272 pcc->parent_reset = cc->reset;
8273 cc->reset = ppc_cpu_reset;
8274
8275 cc->class_by_name = ppc_cpu_class_by_name;
8276 cc->do_interrupt = ppc_cpu_do_interrupt;
8277 }
8278
8279 static const TypeInfo ppc_cpu_type_info = {
8280 .name = TYPE_POWERPC_CPU,
8281 .parent = TYPE_CPU,
8282 .instance_size = sizeof(PowerPCCPU),
8283 .instance_init = ppc_cpu_initfn,
8284 .abstract = true,
8285 .class_size = sizeof(PowerPCCPUClass),
8286 .class_init = ppc_cpu_class_init,
8287 };
8288
8289 static void ppc_cpu_register_types(void)
8290 {
8291 type_register_static(&ppc_cpu_type_info);
8292 }
8293
8294 type_init(ppc_cpu_register_types)
Random patches