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nbd: Fix order of bdrv_set_perm and bdrv_invalidate_cache
[qemu/kevin.git] / hw / pci / pci.c
blob258fbe51e2ee3af0b8d6b893c2436f8f564ddac2
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "hw/pci/pci.h"
27 #include "hw/pci/pci_bridge.h"
28 #include "hw/pci/pci_bus.h"
29 #include "hw/pci/pci_host.h"
30 #include "monitor/monitor.h"
31 #include "net/net.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/loader.h"
34 #include "qemu/error-report.h"
35 #include "qemu/range.h"
36 #include "qmp-commands.h"
37 #include "trace.h"
38 #include "hw/pci/msi.h"
39 #include "hw/pci/msix.h"
40 #include "exec/address-spaces.h"
41 #include "hw/hotplug.h"
42 #include "hw/boards.h"
43 #include "qemu/cutils.h"
44
45 //#define DEBUG_PCI
46 #ifdef DEBUG_PCI
47 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
48 #else
49 # define PCI_DPRINTF(format, ...) do { } while (0)
50 #endif
51
52 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
53 static char *pcibus_get_dev_path(DeviceState *dev);
54 static char *pcibus_get_fw_dev_path(DeviceState *dev);
55 static void pcibus_reset(BusState *qbus);
56
57 static Property pci_props[] = {
58 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
59 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
60 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
61 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
62 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
63 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
64 QEMU_PCI_CAP_SERR_BITNR, true),
65 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
66 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
67 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
68 QEMU_PCIE_EXTCAP_INIT_BITNR, true),
69 DEFINE_PROP_END_OF_LIST()
70 };
71
72 static const VMStateDescription vmstate_pcibus = {
73 .name = "PCIBUS",
74 .version_id = 1,
75 .minimum_version_id = 1,
76 .fields = (VMStateField[]) {
77 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL),
78 VMSTATE_VARRAY_INT32(irq_count, PCIBus,
79 nirq, 0, vmstate_info_int32,
80 int32_t),
81 VMSTATE_END_OF_LIST()
82 }
83 };
84
85 static void pci_init_bus_master(PCIDevice *pci_dev)
86 {
87 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev);
88
89 memory_region_init_alias(&pci_dev->bus_master_enable_region,
90 OBJECT(pci_dev), "bus master",
91 dma_as->root, 0, memory_region_size(dma_as->root));
92 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
93 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0,
94 &pci_dev->bus_master_enable_region);
95 }
96
97 static void pcibus_machine_done(Notifier *notifier, void *data)
98 {
99 PCIBus *bus = container_of(notifier, PCIBus, machine_done);
100 int i;
101
102 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
103 if (bus->devices[i]) {
104 pci_init_bus_master(bus->devices[i]);
105 }
106 }
107 }
108
109 static void pci_bus_realize(BusState *qbus, Error **errp)
110 {
111 PCIBus *bus = PCI_BUS(qbus);
112
113 bus->machine_done.notify = pcibus_machine_done;
114 qemu_add_machine_init_done_notifier(&bus->machine_done);
115
116 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
117 }
118
119 static void pci_bus_unrealize(BusState *qbus, Error **errp)
120 {
121 PCIBus *bus = PCI_BUS(qbus);
122
123 qemu_remove_machine_init_done_notifier(&bus->machine_done);
124
125 vmstate_unregister(NULL, &vmstate_pcibus, bus);
126 }
127
128 static bool pcibus_is_root(PCIBus *bus)
129 {
130 return !bus->parent_dev;
131 }
132
133 static int pcibus_num(PCIBus *bus)
134 {
135 if (pcibus_is_root(bus)) {
136 return 0; /* pci host bridge */
137 }
138 return bus->parent_dev->config[PCI_SECONDARY_BUS];
139 }
140
141 static uint16_t pcibus_numa_node(PCIBus *bus)
142 {
143 return NUMA_NODE_UNASSIGNED;
144 }
145
146 static void pci_bus_class_init(ObjectClass *klass, void *data)
147 {
148 BusClass *k = BUS_CLASS(klass);
149 PCIBusClass *pbc = PCI_BUS_CLASS(klass);
150
151 k->print_dev = pcibus_dev_print;
152 k->get_dev_path = pcibus_get_dev_path;
153 k->get_fw_dev_path = pcibus_get_fw_dev_path;
154 k->realize = pci_bus_realize;
155 k->unrealize = pci_bus_unrealize;
156 k->reset = pcibus_reset;
157
158 pbc->is_root = pcibus_is_root;
159 pbc->bus_num = pcibus_num;
160 pbc->numa_node = pcibus_numa_node;
161 }
162
163 static const TypeInfo pci_bus_info = {
164 .name = TYPE_PCI_BUS,
165 .parent = TYPE_BUS,
166 .instance_size = sizeof(PCIBus),
167 .class_size = sizeof(PCIBusClass),
168 .class_init = pci_bus_class_init,
169 };
170
171 static const TypeInfo pcie_bus_info = {
172 .name = TYPE_PCIE_BUS,
173 .parent = TYPE_PCI_BUS,
174 };
175
176 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
177 static void pci_update_mappings(PCIDevice *d);
178 static void pci_irq_handler(void *opaque, int irq_num, int level);
179 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
180 static void pci_del_option_rom(PCIDevice *pdev);
181
182 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
183 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
184
185 static QLIST_HEAD(, PCIHostState) pci_host_bridges;
186
187 int pci_bar(PCIDevice *d, int reg)
188 {
189 uint8_t type;
190
191 if (reg != PCI_ROM_SLOT)
192 return PCI_BASE_ADDRESS_0 + reg * 4;
193
194 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
195 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
196 }
197
198 static inline int pci_irq_state(PCIDevice *d, int irq_num)
199 {
200 return (d->irq_state >> irq_num) & 0x1;
201 }
202
203 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
204 {
205 d->irq_state &= ~(0x1 << irq_num);
206 d->irq_state |= level << irq_num;
207 }
208
209 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
210 {
211 PCIBus *bus;
212 for (;;) {
213 bus = pci_dev->bus;
214 irq_num = bus->map_irq(pci_dev, irq_num);
215 if (bus->set_irq)
216 break;
217 pci_dev = bus->parent_dev;
218 }
219 bus->irq_count[irq_num] += change;
220 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
221 }
222
223 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
224 {
225 assert(irq_num >= 0);
226 assert(irq_num < bus->nirq);
227 return !!bus->irq_count[irq_num];
228 }
229
230 /* Update interrupt status bit in config space on interrupt
231 * state change. */
232 static void pci_update_irq_status(PCIDevice *dev)
233 {
234 if (dev->irq_state) {
235 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
236 } else {
237 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
238 }
239 }
240
241 void pci_device_deassert_intx(PCIDevice *dev)
242 {
243 int i;
244 for (i = 0; i < PCI_NUM_PINS; ++i) {
245 pci_irq_handler(dev, i, 0);
246 }
247 }
248
249 static void pci_do_device_reset(PCIDevice *dev)
250 {
251 int r;
252
253 pci_device_deassert_intx(dev);
254 assert(dev->irq_state == 0);
255
256 /* Clear all writable bits */
257 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
258 pci_get_word(dev->wmask + PCI_COMMAND) |
259 pci_get_word(dev->w1cmask + PCI_COMMAND));
260 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
261 pci_get_word(dev->wmask + PCI_STATUS) |
262 pci_get_word(dev->w1cmask + PCI_STATUS));
263 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
264 dev->config[PCI_INTERRUPT_LINE] = 0x0;
265 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
266 PCIIORegion *region = &dev->io_regions[r];
267 if (!region->size) {
268 continue;
269 }
270
271 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
272 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
273 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
274 } else {
275 pci_set_long(dev->config + pci_bar(dev, r), region->type);
276 }
277 }
278 pci_update_mappings(dev);
279
280 msi_reset(dev);
281 msix_reset(dev);
282 }
283
284 /*
285 * This function is called on #RST and FLR.
286 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
287 */
288 void pci_device_reset(PCIDevice *dev)
289 {
290 qdev_reset_all(&dev->qdev);
291 pci_do_device_reset(dev);
292 }
293
294 /*
295 * Trigger pci bus reset under a given bus.
296 * Called via qbus_reset_all on RST# assert, after the devices
297 * have been reset qdev_reset_all-ed already.
298 */
299 static void pcibus_reset(BusState *qbus)
300 {
301 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
302 int i;
303
304 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
305 if (bus->devices[i]) {
306 pci_do_device_reset(bus->devices[i]);
307 }
308 }
309
310 for (i = 0; i < bus->nirq; i++) {
311 assert(bus->irq_count[i] == 0);
312 }
313 }
314
315 static void pci_host_bus_register(DeviceState *host)
316 {
317 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
318
319 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
320 }
321
322 PCIBus *pci_find_primary_bus(void)
323 {
324 PCIBus *primary_bus = NULL;
325 PCIHostState *host;
326
327 QLIST_FOREACH(host, &pci_host_bridges, next) {
328 if (primary_bus) {
329 /* We have multiple root buses, refuse to select a primary */
330 return NULL;
331 }
332 primary_bus = host->bus;
333 }
334
335 return primary_bus;
336 }
337
338 PCIBus *pci_device_root_bus(const PCIDevice *d)
339 {
340 PCIBus *bus = d->bus;
341
342 while (!pci_bus_is_root(bus)) {
343 d = bus->parent_dev;
344 assert(d != NULL);
345
346 bus = d->bus;
347 }
348
349 return bus;
350 }
351
352 const char *pci_root_bus_path(PCIDevice *dev)
353 {
354 PCIBus *rootbus = pci_device_root_bus(dev);
355 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
356 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
357
358 assert(host_bridge->bus == rootbus);
359
360 if (hc->root_bus_path) {
361 return (*hc->root_bus_path)(host_bridge, rootbus);
362 }
363
364 return rootbus->qbus.name;
365 }
366
367 static void pci_bus_init(PCIBus *bus, DeviceState *parent,
368 MemoryRegion *address_space_mem,
369 MemoryRegion *address_space_io,
370 uint8_t devfn_min)
371 {
372 assert(PCI_FUNC(devfn_min) == 0);
373 bus->devfn_min = devfn_min;
374 bus->address_space_mem = address_space_mem;
375 bus->address_space_io = address_space_io;
376
377 /* host bridge */
378 QLIST_INIT(&bus->child);
379
380 pci_host_bus_register(parent);
381 }
382
383 bool pci_bus_is_express(PCIBus *bus)
384 {
385 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
386 }
387
388 bool pci_bus_is_root(PCIBus *bus)
389 {
390 return PCI_BUS_GET_CLASS(bus)->is_root(bus);
391 }
392
393 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
394 const char *name,
395 MemoryRegion *address_space_mem,
396 MemoryRegion *address_space_io,
397 uint8_t devfn_min, const char *typename)
398 {
399 qbus_create_inplace(bus, bus_size, typename, parent, name);
400 pci_bus_init(bus, parent, address_space_mem, address_space_io, devfn_min);
401 }
402
403 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
404 MemoryRegion *address_space_mem,
405 MemoryRegion *address_space_io,
406 uint8_t devfn_min, const char *typename)
407 {
408 PCIBus *bus;
409
410 bus = PCI_BUS(qbus_create(typename, parent, name));
411 pci_bus_init(bus, parent, address_space_mem, address_space_io, devfn_min);
412 return bus;
413 }
414
415 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
416 void *irq_opaque, int nirq)
417 {
418 bus->set_irq = set_irq;
419 bus->map_irq = map_irq;
420 bus->irq_opaque = irq_opaque;
421 bus->nirq = nirq;
422 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
423 }
424
425 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
426 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
427 void *irq_opaque,
428 MemoryRegion *address_space_mem,
429 MemoryRegion *address_space_io,
430 uint8_t devfn_min, int nirq, const char *typename)
431 {
432 PCIBus *bus;
433
434 bus = pci_bus_new(parent, name, address_space_mem,
435 address_space_io, devfn_min, typename);
436 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
437 return bus;
438 }
439
440 int pci_bus_num(PCIBus *s)
441 {
442 return PCI_BUS_GET_CLASS(s)->bus_num(s);
443 }
444
445 int pci_bus_numa_node(PCIBus *bus)
446 {
447 return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
448 }
449
450 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size,
451 VMStateField *field)
452 {
453 PCIDevice *s = container_of(pv, PCIDevice, config);
454 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
455 uint8_t *config;
456 int i;
457
458 assert(size == pci_config_size(s));
459 config = g_malloc(size);
460
461 qemu_get_buffer(f, config, size);
462 for (i = 0; i < size; ++i) {
463 if ((config[i] ^ s->config[i]) &
464 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
465 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
466 "cmask: %x wmask: %x w1cmask:%x", __func__,
467 i, config[i], s->config[i],
468 s->cmask[i], s->wmask[i], s->w1cmask[i]);
469 g_free(config);
470 return -EINVAL;
471 }
472 }
473 memcpy(s->config, config, size);
474
475 pci_update_mappings(s);
476 if (pc->is_bridge) {
477 PCIBridge *b = PCI_BRIDGE(s);
478 pci_bridge_update_mappings(b);
479 }
480
481 memory_region_set_enabled(&s->bus_master_enable_region,
482 pci_get_word(s->config + PCI_COMMAND)
483 & PCI_COMMAND_MASTER);
484
485 g_free(config);
486 return 0;
487 }
488
489 /* just put buffer */
490 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size,
491 VMStateField *field, QJSON *vmdesc)
492 {
493 const uint8_t **v = pv;
494 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
495 qemu_put_buffer(f, *v, size);
496
497 return 0;
498 }
499
500 static VMStateInfo vmstate_info_pci_config = {
501 .name = "pci config",
502 .get = get_pci_config_device,
503 .put = put_pci_config_device,
504 };
505
506 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size,
507 VMStateField *field)
508 {
509 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
510 uint32_t irq_state[PCI_NUM_PINS];
511 int i;
512 for (i = 0; i < PCI_NUM_PINS; ++i) {
513 irq_state[i] = qemu_get_be32(f);
514 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
515 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
516 irq_state[i]);
517 return -EINVAL;
518 }
519 }
520
521 for (i = 0; i < PCI_NUM_PINS; ++i) {
522 pci_set_irq_state(s, i, irq_state[i]);
523 }
524
525 return 0;
526 }
527
528 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size,
529 VMStateField *field, QJSON *vmdesc)
530 {
531 int i;
532 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
533
534 for (i = 0; i < PCI_NUM_PINS; ++i) {
535 qemu_put_be32(f, pci_irq_state(s, i));
536 }
537
538 return 0;
539 }
540
541 static VMStateInfo vmstate_info_pci_irq_state = {
542 .name = "pci irq state",
543 .get = get_pci_irq_state,
544 .put = put_pci_irq_state,
545 };
546
547 static bool migrate_is_pcie(void *opaque, int version_id)
548 {
549 return pci_is_express((PCIDevice *)opaque);
550 }
551
552 static bool migrate_is_not_pcie(void *opaque, int version_id)
553 {
554 return !pci_is_express((PCIDevice *)opaque);
555 }
556
557 const VMStateDescription vmstate_pci_device = {
558 .name = "PCIDevice",
559 .version_id = 2,
560 .minimum_version_id = 1,
561 .fields = (VMStateField[]) {
562 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
563 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
564 migrate_is_not_pcie,
565 0, vmstate_info_pci_config,
566 PCI_CONFIG_SPACE_SIZE),
567 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
568 migrate_is_pcie,
569 0, vmstate_info_pci_config,
570 PCIE_CONFIG_SPACE_SIZE),
571 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
572 vmstate_info_pci_irq_state,
573 PCI_NUM_PINS * sizeof(int32_t)),
574 VMSTATE_END_OF_LIST()
575 }
576 };
577
578
579 void pci_device_save(PCIDevice *s, QEMUFile *f)
580 {
581 /* Clear interrupt status bit: it is implicit
582 * in irq_state which we are saving.
583 * This makes us compatible with old devices
584 * which never set or clear this bit. */
585 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
586 vmstate_save_state(f, &vmstate_pci_device, s, NULL);
587 /* Restore the interrupt status bit. */
588 pci_update_irq_status(s);
589 }
590
591 int pci_device_load(PCIDevice *s, QEMUFile *f)
592 {
593 int ret;
594 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
595 /* Restore the interrupt status bit. */
596 pci_update_irq_status(s);
597 return ret;
598 }
599
600 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
601 {
602 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
603 pci_default_sub_vendor_id);
604 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
605 pci_default_sub_device_id);
606 }
607
608 /*
609 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
610 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
611 */
612 static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
613 unsigned int *slotp, unsigned int *funcp)
614 {
615 const char *p;
616 char *e;
617 unsigned long val;
618 unsigned long dom = 0, bus = 0;
619 unsigned int slot = 0;
620 unsigned int func = 0;
621
622 p = addr;
623 val = strtoul(p, &e, 16);
624 if (e == p)
625 return -1;
626 if (*e == ':') {
627 bus = val;
628 p = e + 1;
629 val = strtoul(p, &e, 16);
630 if (e == p)
631 return -1;
632 if (*e == ':') {
633 dom = bus;
634 bus = val;
635 p = e + 1;
636 val = strtoul(p, &e, 16);
637 if (e == p)
638 return -1;
639 }
640 }
641
642 slot = val;
643
644 if (funcp != NULL) {
645 if (*e != '.')
646 return -1;
647
648 p = e + 1;
649 val = strtoul(p, &e, 16);
650 if (e == p)
651 return -1;
652
653 func = val;
654 }
655
656 /* if funcp == NULL func is 0 */
657 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
658 return -1;
659
660 if (*e)
661 return -1;
662
663 *domp = dom;
664 *busp = bus;
665 *slotp = slot;
666 if (funcp != NULL)
667 *funcp = func;
668 return 0;
669 }
670
671 static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root,
672 const char *devaddr)
673 {
674 int dom, bus;
675 unsigned slot;
676
677 if (!root) {
678 fprintf(stderr, "No primary PCI bus\n");
679 return NULL;
680 }
681
682 assert(!root->parent_dev);
683
684 if (!devaddr) {
685 *devfnp = -1;
686 return pci_find_bus_nr(root, 0);
687 }
688
689 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
690 return NULL;
691 }
692
693 if (dom != 0) {
694 fprintf(stderr, "No support for non-zero PCI domains\n");
695 return NULL;
696 }
697
698 *devfnp = PCI_DEVFN(slot, 0);
699 return pci_find_bus_nr(root, bus);
700 }
701
702 static void pci_init_cmask(PCIDevice *dev)
703 {
704 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
705 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
706 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
707 dev->cmask[PCI_REVISION_ID] = 0xff;
708 dev->cmask[PCI_CLASS_PROG] = 0xff;
709 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
710 dev->cmask[PCI_HEADER_TYPE] = 0xff;
711 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
712 }
713
714 static void pci_init_wmask(PCIDevice *dev)
715 {
716 int config_size = pci_config_size(dev);
717
718 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
719 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
720 pci_set_word(dev->wmask + PCI_COMMAND,
721 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
722 PCI_COMMAND_INTX_DISABLE);
723 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
724 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
725 }
726
727 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
728 config_size - PCI_CONFIG_HEADER_SIZE);
729 }
730
731 static void pci_init_w1cmask(PCIDevice *dev)
732 {
733 /*
734 * Note: It's okay to set w1cmask even for readonly bits as
735 * long as their value is hardwired to 0.
736 */
737 pci_set_word(dev->w1cmask + PCI_STATUS,
738 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
739 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
740 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
741 }
742
743 static void pci_init_mask_bridge(PCIDevice *d)
744 {
745 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
746 PCI_SEC_LETENCY_TIMER */
747 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
748
749 /* base and limit */
750 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
751 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
752 pci_set_word(d->wmask + PCI_MEMORY_BASE,
753 PCI_MEMORY_RANGE_MASK & 0xffff);
754 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
755 PCI_MEMORY_RANGE_MASK & 0xffff);
756 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
757 PCI_PREF_RANGE_MASK & 0xffff);
758 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
759 PCI_PREF_RANGE_MASK & 0xffff);
760
761 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
762 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
763
764 /* Supported memory and i/o types */
765 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
766 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
767 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
768 PCI_PREF_RANGE_TYPE_64);
769 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
770 PCI_PREF_RANGE_TYPE_64);
771
772 /*
773 * TODO: Bridges default to 10-bit VGA decoding but we currently only
774 * implement 16-bit decoding (no alias support).
775 */
776 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
777 PCI_BRIDGE_CTL_PARITY |
778 PCI_BRIDGE_CTL_SERR |
779 PCI_BRIDGE_CTL_ISA |
780 PCI_BRIDGE_CTL_VGA |
781 PCI_BRIDGE_CTL_VGA_16BIT |
782 PCI_BRIDGE_CTL_MASTER_ABORT |
783 PCI_BRIDGE_CTL_BUS_RESET |
784 PCI_BRIDGE_CTL_FAST_BACK |
785 PCI_BRIDGE_CTL_DISCARD |
786 PCI_BRIDGE_CTL_SEC_DISCARD |
787 PCI_BRIDGE_CTL_DISCARD_SERR);
788 /* Below does not do anything as we never set this bit, put here for
789 * completeness. */
790 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
791 PCI_BRIDGE_CTL_DISCARD_STATUS);
792 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
793 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
794 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
795 PCI_PREF_RANGE_TYPE_MASK);
796 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
797 PCI_PREF_RANGE_TYPE_MASK);
798 }
799
800 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
801 {
802 uint8_t slot = PCI_SLOT(dev->devfn);
803 uint8_t func;
804
805 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
806 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
807 }
808
809 /*
810 * multifunction bit is interpreted in two ways as follows.
811 * - all functions must set the bit to 1.
812 * Example: Intel X53
813 * - function 0 must set the bit, but the rest function (> 0)
814 * is allowed to leave the bit to 0.
815 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
816 *
817 * So OS (at least Linux) checks the bit of only function 0,
818 * and doesn't see the bit of function > 0.
819 *
820 * The below check allows both interpretation.
821 */
822 if (PCI_FUNC(dev->devfn)) {
823 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
824 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
825 /* function 0 should set multifunction bit */
826 error_setg(errp, "PCI: single function device can't be populated "
827 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
828 return;
829 }
830 return;
831 }
832
833 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
834 return;
835 }
836 /* function 0 indicates single function, so function > 0 must be NULL */
837 for (func = 1; func < PCI_FUNC_MAX; ++func) {
838 if (bus->devices[PCI_DEVFN(slot, func)]) {
839 error_setg(errp, "PCI: %x.0 indicates single function, "
840 "but %x.%x is already populated.",
841 slot, slot, func);
842 return;
843 }
844 }
845 }
846
847 static void pci_config_alloc(PCIDevice *pci_dev)
848 {
849 int config_size = pci_config_size(pci_dev);
850
851 pci_dev->config = g_malloc0(config_size);
852 pci_dev->cmask = g_malloc0(config_size);
853 pci_dev->wmask = g_malloc0(config_size);
854 pci_dev->w1cmask = g_malloc0(config_size);
855 pci_dev->used = g_malloc0(config_size);
856 }
857
858 static void pci_config_free(PCIDevice *pci_dev)
859 {
860 g_free(pci_dev->config);
861 g_free(pci_dev->cmask);
862 g_free(pci_dev->wmask);
863 g_free(pci_dev->w1cmask);
864 g_free(pci_dev->used);
865 }
866
867 static void do_pci_unregister_device(PCIDevice *pci_dev)
868 {
869 pci_dev->bus->devices[pci_dev->devfn] = NULL;
870 pci_config_free(pci_dev);
871
872 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) {
873 memory_region_del_subregion(&pci_dev->bus_master_container_region,
874 &pci_dev->bus_master_enable_region);
875 }
876 address_space_destroy(&pci_dev->bus_master_as);
877 }
878
879 /* Extract PCIReqIDCache into BDF format */
880 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache)
881 {
882 uint8_t bus_n;
883 uint16_t result;
884
885 switch (cache->type) {
886 case PCI_REQ_ID_BDF:
887 result = pci_get_bdf(cache->dev);
888 break;
889 case PCI_REQ_ID_SECONDARY_BUS:
890 bus_n = pci_bus_num(cache->dev->bus);
891 result = PCI_BUILD_BDF(bus_n, 0);
892 break;
893 default:
894 error_printf("Invalid PCI requester ID cache type: %d\n",
895 cache->type);
896 exit(1);
897 break;
898 }
899
900 return result;
901 }
902
903 /* Parse bridges up to the root complex and return requester ID
904 * cache for specific device. For full PCIe topology, the cache
905 * result would be exactly the same as getting BDF of the device.
906 * However, several tricks are required when system mixed up with
907 * legacy PCI devices and PCIe-to-PCI bridges.
908 *
909 * Here we cache the proxy device (and type) not requester ID since
910 * bus number might change from time to time.
911 */
912 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev)
913 {
914 PCIDevice *parent;
915 PCIReqIDCache cache = {
916 .dev = dev,
917 .type = PCI_REQ_ID_BDF,
918 };
919
920 while (!pci_bus_is_root(dev->bus)) {
921 /* We are under PCI/PCIe bridges */
922 parent = dev->bus->parent_dev;
923 if (pci_is_express(parent)) {
924 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
925 /* When we pass through PCIe-to-PCI/PCIX bridges, we
926 * override the requester ID using secondary bus
927 * number of parent bridge with zeroed devfn
928 * (pcie-to-pci bridge spec chap 2.3). */
929 cache.type = PCI_REQ_ID_SECONDARY_BUS;
930 cache.dev = dev;
931 }
932 } else {
933 /* Legacy PCI, override requester ID with the bridge's
934 * BDF upstream. When the root complex connects to
935 * legacy PCI devices (including buses), it can only
936 * obtain requester ID info from directly attached
937 * devices. If devices are attached under bridges, only
938 * the requester ID of the bridge that is directly
939 * attached to the root complex can be recognized. */
940 cache.type = PCI_REQ_ID_BDF;
941 cache.dev = parent;
942 }
943 dev = parent;
944 }
945
946 return cache;
947 }
948
949 uint16_t pci_requester_id(PCIDevice *dev)
950 {
951 return pci_req_id_cache_extract(&dev->requester_id_cache);
952 }
953
954 /* -1 for devfn means auto assign */
955 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
956 const char *name, int devfn,
957 Error **errp)
958 {
959 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
960 PCIConfigReadFunc *config_read = pc->config_read;
961 PCIConfigWriteFunc *config_write = pc->config_write;
962 Error *local_err = NULL;
963 DeviceState *dev = DEVICE(pci_dev);
964
965 pci_dev->bus = bus;
966 /* Only pci bridges can be attached to extra PCI root buses */
967 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) {
968 error_setg(errp,
969 "PCI: Only PCI/PCIe bridges can be plugged into %s",
970 bus->parent_dev->name);
971 return NULL;
972 }
973
974 if (devfn < 0) {
975 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
976 devfn += PCI_FUNC_MAX) {
977 if (!bus->devices[devfn])
978 goto found;
979 }
980 error_setg(errp, "PCI: no slot/function available for %s, all in use",
981 name);
982 return NULL;
983 found: ;
984 } else if (bus->devices[devfn]) {
985 error_setg(errp, "PCI: slot %d function %d not available for %s,"
986 " in use by %s",
987 PCI_SLOT(devfn), PCI_FUNC(devfn), name,
988 bus->devices[devfn]->name);
989 return NULL;
990 } else if (dev->hotplugged &&
991 pci_get_function_0(pci_dev)) {
992 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s,"
993 " new func %s cannot be exposed to guest.",
994 PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
995 pci_get_function_0(pci_dev)->name,
996 name);
997
998 return NULL;
999 }
1000
1001 pci_dev->devfn = devfn;
1002 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev);
1003
1004 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
1005 "bus master container", UINT64_MAX);
1006 address_space_init(&pci_dev->bus_master_as,
1007 &pci_dev->bus_master_container_region, pci_dev->name);
1008
1009 if (qdev_hotplug) {
1010 pci_init_bus_master(pci_dev);
1011 }
1012 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
1013 pci_dev->irq_state = 0;
1014 pci_config_alloc(pci_dev);
1015
1016 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
1017 pci_config_set_device_id(pci_dev->config, pc->device_id);
1018 pci_config_set_revision(pci_dev->config, pc->revision);
1019 pci_config_set_class(pci_dev->config, pc->class_id);
1020
1021 if (!pc->is_bridge) {
1022 if (pc->subsystem_vendor_id || pc->subsystem_id) {
1023 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1024 pc->subsystem_vendor_id);
1025 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1026 pc->subsystem_id);
1027 } else {
1028 pci_set_default_subsystem_id(pci_dev);
1029 }
1030 } else {
1031 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
1032 assert(!pc->subsystem_vendor_id);
1033 assert(!pc->subsystem_id);
1034 }
1035 pci_init_cmask(pci_dev);
1036 pci_init_wmask(pci_dev);
1037 pci_init_w1cmask(pci_dev);
1038 if (pc->is_bridge) {
1039 pci_init_mask_bridge(pci_dev);
1040 }
1041 pci_init_multifunction(bus, pci_dev, &local_err);
1042 if (local_err) {
1043 error_propagate(errp, local_err);
1044 do_pci_unregister_device(pci_dev);
1045 return NULL;
1046 }
1047
1048 if (!config_read)
1049 config_read = pci_default_read_config;
1050 if (!config_write)
1051 config_write = pci_default_write_config;
1052 pci_dev->config_read = config_read;
1053 pci_dev->config_write = config_write;
1054 bus->devices[devfn] = pci_dev;
1055 pci_dev->version_id = 2; /* Current pci device vmstate version */
1056 return pci_dev;
1057 }
1058
1059 static void pci_unregister_io_regions(PCIDevice *pci_dev)
1060 {
1061 PCIIORegion *r;
1062 int i;
1063
1064 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1065 r = &pci_dev->io_regions[i];
1066 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
1067 continue;
1068 memory_region_del_subregion(r->address_space, r->memory);
1069 }
1070
1071 pci_unregister_vga(pci_dev);
1072 }
1073
1074 static void pci_qdev_unrealize(DeviceState *dev, Error **errp)
1075 {
1076 PCIDevice *pci_dev = PCI_DEVICE(dev);
1077 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1078
1079 pci_unregister_io_regions(pci_dev);
1080 pci_del_option_rom(pci_dev);
1081
1082 if (pc->exit) {
1083 pc->exit(pci_dev);
1084 }
1085
1086 pci_device_deassert_intx(pci_dev);
1087 do_pci_unregister_device(pci_dev);
1088 }
1089
1090 void pci_register_bar(PCIDevice *pci_dev, int region_num,
1091 uint8_t type, MemoryRegion *memory)
1092 {
1093 PCIIORegion *r;
1094 uint32_t addr; /* offset in pci config space */
1095 uint64_t wmask;
1096 pcibus_t size = memory_region_size(memory);
1097
1098 assert(region_num >= 0);
1099 assert(region_num < PCI_NUM_REGIONS);
1100 if (size & (size-1)) {
1101 fprintf(stderr, "ERROR: PCI region size must be pow2 "
1102 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
1103 exit(1);
1104 }
1105
1106 r = &pci_dev->io_regions[region_num];
1107 r->addr = PCI_BAR_UNMAPPED;
1108 r->size = size;
1109 r->type = type;
1110 r->memory = memory;
1111 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO
1112 ? pci_dev->bus->address_space_io
1113 : pci_dev->bus->address_space_mem;
1114
1115 wmask = ~(size - 1);
1116 if (region_num == PCI_ROM_SLOT) {
1117 /* ROM enable bit is writable */
1118 wmask |= PCI_ROM_ADDRESS_ENABLE;
1119 }
1120
1121 addr = pci_bar(pci_dev, region_num);
1122 pci_set_long(pci_dev->config + addr, type);
1123
1124 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
1125 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1126 pci_set_quad(pci_dev->wmask + addr, wmask);
1127 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
1128 } else {
1129 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
1130 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
1131 }
1132 }
1133
1134 static void pci_update_vga(PCIDevice *pci_dev)
1135 {
1136 uint16_t cmd;
1137
1138 if (!pci_dev->has_vga) {
1139 return;
1140 }
1141
1142 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1143
1144 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
1145 cmd & PCI_COMMAND_MEMORY);
1146 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
1147 cmd & PCI_COMMAND_IO);
1148 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
1149 cmd & PCI_COMMAND_IO);
1150 }
1151
1152 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
1153 MemoryRegion *io_lo, MemoryRegion *io_hi)
1154 {
1155 assert(!pci_dev->has_vga);
1156
1157 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
1158 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
1159 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem,
1160 QEMU_PCI_VGA_MEM_BASE, mem, 1);
1161
1162 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
1163 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
1164 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
1165 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
1166
1167 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
1168 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
1169 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
1170 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
1171 pci_dev->has_vga = true;
1172
1173 pci_update_vga(pci_dev);
1174 }
1175
1176 void pci_unregister_vga(PCIDevice *pci_dev)
1177 {
1178 if (!pci_dev->has_vga) {
1179 return;
1180 }
1181
1182 memory_region_del_subregion(pci_dev->bus->address_space_mem,
1183 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1184 memory_region_del_subregion(pci_dev->bus->address_space_io,
1185 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1186 memory_region_del_subregion(pci_dev->bus->address_space_io,
1187 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1188 pci_dev->has_vga = false;
1189 }
1190
1191 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1192 {
1193 return pci_dev->io_regions[region_num].addr;
1194 }
1195
1196 static pcibus_t pci_bar_address(PCIDevice *d,
1197 int reg, uint8_t type, pcibus_t size)
1198 {
1199 pcibus_t new_addr, last_addr;
1200 int bar = pci_bar(d, reg);
1201 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1202 Object *machine = qdev_get_machine();
1203 ObjectClass *oc = object_get_class(machine);
1204 MachineClass *mc = MACHINE_CLASS(oc);
1205 bool allow_0_address = mc->pci_allow_0_address;
1206
1207 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1208 if (!(cmd & PCI_COMMAND_IO)) {
1209 return PCI_BAR_UNMAPPED;
1210 }
1211 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1212 last_addr = new_addr + size - 1;
1213 /* Check if 32 bit BAR wraps around explicitly.
1214 * TODO: make priorities correct and remove this work around.
1215 */
1216 if (last_addr <= new_addr || last_addr >= UINT32_MAX ||
1217 (!allow_0_address && new_addr == 0)) {
1218 return PCI_BAR_UNMAPPED;
1219 }
1220 return new_addr;
1221 }
1222
1223 if (!(cmd & PCI_COMMAND_MEMORY)) {
1224 return PCI_BAR_UNMAPPED;
1225 }
1226 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1227 new_addr = pci_get_quad(d->config + bar);
1228 } else {
1229 new_addr = pci_get_long(d->config + bar);
1230 }
1231 /* the ROM slot has a specific enable bit */
1232 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1233 return PCI_BAR_UNMAPPED;
1234 }
1235 new_addr &= ~(size - 1);
1236 last_addr = new_addr + size - 1;
1237 /* NOTE: we do not support wrapping */
1238 /* XXX: as we cannot support really dynamic
1239 mappings, we handle specific values as invalid
1240 mappings. */
1241 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED ||
1242 (!allow_0_address && new_addr == 0)) {
1243 return PCI_BAR_UNMAPPED;
1244 }
1245
1246 /* Now pcibus_t is 64bit.
1247 * Check if 32 bit BAR wraps around explicitly.
1248 * Without this, PC ide doesn't work well.
1249 * TODO: remove this work around.
1250 */
1251 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1252 return PCI_BAR_UNMAPPED;
1253 }
1254
1255 /*
1256 * OS is allowed to set BAR beyond its addressable
1257 * bits. For example, 32 bit OS can set 64bit bar
1258 * to >4G. Check it. TODO: we might need to support
1259 * it in the future for e.g. PAE.
1260 */
1261 if (last_addr >= HWADDR_MAX) {
1262 return PCI_BAR_UNMAPPED;
1263 }
1264
1265 return new_addr;
1266 }
1267
1268 static void pci_update_mappings(PCIDevice *d)
1269 {
1270 PCIIORegion *r;
1271 int i;
1272 pcibus_t new_addr;
1273
1274 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1275 r = &d->io_regions[i];
1276
1277 /* this region isn't registered */
1278 if (!r->size)
1279 continue;
1280
1281 new_addr = pci_bar_address(d, i, r->type, r->size);
1282
1283 /* This bar isn't changed */
1284 if (new_addr == r->addr)
1285 continue;
1286
1287 /* now do the real mapping */
1288 if (r->addr != PCI_BAR_UNMAPPED) {
1289 trace_pci_update_mappings_del(d, pci_bus_num(d->bus),
1290 PCI_SLOT(d->devfn),
1291 PCI_FUNC(d->devfn),
1292 i, r->addr, r->size);
1293 memory_region_del_subregion(r->address_space, r->memory);
1294 }
1295 r->addr = new_addr;
1296 if (r->addr != PCI_BAR_UNMAPPED) {
1297 trace_pci_update_mappings_add(d, pci_bus_num(d->bus),
1298 PCI_SLOT(d->devfn),
1299 PCI_FUNC(d->devfn),
1300 i, r->addr, r->size);
1301 memory_region_add_subregion_overlap(r->address_space,
1302 r->addr, r->memory, 1);
1303 }
1304 }
1305
1306 pci_update_vga(d);
1307 }
1308
1309 static inline int pci_irq_disabled(PCIDevice *d)
1310 {
1311 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1312 }
1313
1314 /* Called after interrupt disabled field update in config space,
1315 * assert/deassert interrupts if necessary.
1316 * Gets original interrupt disable bit value (before update). */
1317 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1318 {
1319 int i, disabled = pci_irq_disabled(d);
1320 if (disabled == was_irq_disabled)
1321 return;
1322 for (i = 0; i < PCI_NUM_PINS; ++i) {
1323 int state = pci_irq_state(d, i);
1324 pci_change_irq_level(d, i, disabled ? -state : state);
1325 }
1326 }
1327
1328 uint32_t pci_default_read_config(PCIDevice *d,
1329 uint32_t address, int len)
1330 {
1331 uint32_t val = 0;
1332
1333 memcpy(&val, d->config + address, len);
1334 return le32_to_cpu(val);
1335 }
1336
1337 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
1338 {
1339 int i, was_irq_disabled = pci_irq_disabled(d);
1340 uint32_t val = val_in;
1341
1342 for (i = 0; i < l; val >>= 8, ++i) {
1343 uint8_t wmask = d->wmask[addr + i];
1344 uint8_t w1cmask = d->w1cmask[addr + i];
1345 assert(!(wmask & w1cmask));
1346 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1347 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1348 }
1349 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1350 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1351 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1352 range_covers_byte(addr, l, PCI_COMMAND))
1353 pci_update_mappings(d);
1354
1355 if (range_covers_byte(addr, l, PCI_COMMAND)) {
1356 pci_update_irq_disabled(d, was_irq_disabled);
1357 memory_region_set_enabled(&d->bus_master_enable_region,
1358 pci_get_word(d->config + PCI_COMMAND)
1359 & PCI_COMMAND_MASTER);
1360 }
1361
1362 msi_write_config(d, addr, val_in, l);
1363 msix_write_config(d, addr, val_in, l);
1364 }
1365
1366 /***********************************************************/
1367 /* generic PCI irq support */
1368
1369 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1370 static void pci_irq_handler(void *opaque, int irq_num, int level)
1371 {
1372 PCIDevice *pci_dev = opaque;
1373 int change;
1374
1375 change = level - pci_irq_state(pci_dev, irq_num);
1376 if (!change)
1377 return;
1378
1379 pci_set_irq_state(pci_dev, irq_num, level);
1380 pci_update_irq_status(pci_dev);
1381 if (pci_irq_disabled(pci_dev))
1382 return;
1383 pci_change_irq_level(pci_dev, irq_num, change);
1384 }
1385
1386 static inline int pci_intx(PCIDevice *pci_dev)
1387 {
1388 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1389 }
1390
1391 qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1392 {
1393 int intx = pci_intx(pci_dev);
1394
1395 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1396 }
1397
1398 void pci_set_irq(PCIDevice *pci_dev, int level)
1399 {
1400 int intx = pci_intx(pci_dev);
1401 pci_irq_handler(pci_dev, intx, level);
1402 }
1403
1404 /* Special hooks used by device assignment */
1405 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1406 {
1407 assert(pci_bus_is_root(bus));
1408 bus->route_intx_to_irq = route_intx_to_irq;
1409 }
1410
1411 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1412 {
1413 PCIBus *bus;
1414
1415 do {
1416 bus = dev->bus;
1417 pin = bus->map_irq(dev, pin);
1418 dev = bus->parent_dev;
1419 } while (dev);
1420
1421 if (!bus->route_intx_to_irq) {
1422 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1423 object_get_typename(OBJECT(bus->qbus.parent)));
1424 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1425 }
1426
1427 return bus->route_intx_to_irq(bus->irq_opaque, pin);
1428 }
1429
1430 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1431 {
1432 return old->mode != new->mode || old->irq != new->irq;
1433 }
1434
1435 void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1436 {
1437 PCIDevice *dev;
1438 PCIBus *sec;
1439 int i;
1440
1441 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1442 dev = bus->devices[i];
1443 if (dev && dev->intx_routing_notifier) {
1444 dev->intx_routing_notifier(dev);
1445 }
1446 }
1447
1448 QLIST_FOREACH(sec, &bus->child, sibling) {
1449 pci_bus_fire_intx_routing_notifier(sec);
1450 }
1451 }
1452
1453 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1454 PCIINTxRoutingNotifier notifier)
1455 {
1456 dev->intx_routing_notifier = notifier;
1457 }
1458
1459 /*
1460 * PCI-to-PCI bridge specification
1461 * 9.1: Interrupt routing. Table 9-1
1462 *
1463 * the PCI Express Base Specification, Revision 2.1
1464 * 2.2.8.1: INTx interrutp signaling - Rules
1465 * the Implementation Note
1466 * Table 2-20
1467 */
1468 /*
1469 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1470 * 0-origin unlike PCI interrupt pin register.
1471 */
1472 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1473 {
1474 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1475 }
1476
1477 /***********************************************************/
1478 /* monitor info on PCI */
1479
1480 typedef struct {
1481 uint16_t class;
1482 const char *desc;
1483 const char *fw_name;
1484 uint16_t fw_ign_bits;
1485 } pci_class_desc;
1486
1487 static const pci_class_desc pci_class_descriptions[] =
1488 {
1489 { 0x0001, "VGA controller", "display"},
1490 { 0x0100, "SCSI controller", "scsi"},
1491 { 0x0101, "IDE controller", "ide"},
1492 { 0x0102, "Floppy controller", "fdc"},
1493 { 0x0103, "IPI controller", "ipi"},
1494 { 0x0104, "RAID controller", "raid"},
1495 { 0x0106, "SATA controller"},
1496 { 0x0107, "SAS controller"},
1497 { 0x0180, "Storage controller"},
1498 { 0x0200, "Ethernet controller", "ethernet"},
1499 { 0x0201, "Token Ring controller", "token-ring"},
1500 { 0x0202, "FDDI controller", "fddi"},
1501 { 0x0203, "ATM controller", "atm"},
1502 { 0x0280, "Network controller"},
1503 { 0x0300, "VGA controller", "display", 0x00ff},
1504 { 0x0301, "XGA controller"},
1505 { 0x0302, "3D controller"},
1506 { 0x0380, "Display controller"},
1507 { 0x0400, "Video controller", "video"},
1508 { 0x0401, "Audio controller", "sound"},
1509 { 0x0402, "Phone"},
1510 { 0x0403, "Audio controller", "sound"},
1511 { 0x0480, "Multimedia controller"},
1512 { 0x0500, "RAM controller", "memory"},
1513 { 0x0501, "Flash controller", "flash"},
1514 { 0x0580, "Memory controller"},
1515 { 0x0600, "Host bridge", "host"},
1516 { 0x0601, "ISA bridge", "isa"},
1517 { 0x0602, "EISA bridge", "eisa"},
1518 { 0x0603, "MC bridge", "mca"},
1519 { 0x0604, "PCI bridge", "pci-bridge"},
1520 { 0x0605, "PCMCIA bridge", "pcmcia"},
1521 { 0x0606, "NUBUS bridge", "nubus"},
1522 { 0x0607, "CARDBUS bridge", "cardbus"},
1523 { 0x0608, "RACEWAY bridge"},
1524 { 0x0680, "Bridge"},
1525 { 0x0700, "Serial port", "serial"},
1526 { 0x0701, "Parallel port", "parallel"},
1527 { 0x0800, "Interrupt controller", "interrupt-controller"},
1528 { 0x0801, "DMA controller", "dma-controller"},
1529 { 0x0802, "Timer", "timer"},
1530 { 0x0803, "RTC", "rtc"},
1531 { 0x0900, "Keyboard", "keyboard"},
1532 { 0x0901, "Pen", "pen"},
1533 { 0x0902, "Mouse", "mouse"},
1534 { 0x0A00, "Dock station", "dock", 0x00ff},
1535 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1536 { 0x0c00, "Fireware contorller", "fireware"},
1537 { 0x0c01, "Access bus controller", "access-bus"},
1538 { 0x0c02, "SSA controller", "ssa"},
1539 { 0x0c03, "USB controller", "usb"},
1540 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1541 { 0x0c05, "SMBus"},
1542 { 0, NULL}
1543 };
1544
1545 static void pci_for_each_device_under_bus_reverse(PCIBus *bus,
1546 void (*fn)(PCIBus *b,
1547 PCIDevice *d,
1548 void *opaque),
1549 void *opaque)
1550 {
1551 PCIDevice *d;
1552 int devfn;
1553
1554 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1555 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn];
1556 if (d) {
1557 fn(bus, d, opaque);
1558 }
1559 }
1560 }
1561
1562 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
1563 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1564 void *opaque)
1565 {
1566 bus = pci_find_bus_nr(bus, bus_num);
1567
1568 if (bus) {
1569 pci_for_each_device_under_bus_reverse(bus, fn, opaque);
1570 }
1571 }
1572
1573 static void pci_for_each_device_under_bus(PCIBus *bus,
1574 void (*fn)(PCIBus *b, PCIDevice *d,
1575 void *opaque),
1576 void *opaque)
1577 {
1578 PCIDevice *d;
1579 int devfn;
1580
1581 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1582 d = bus->devices[devfn];
1583 if (d) {
1584 fn(bus, d, opaque);
1585 }
1586 }
1587 }
1588
1589 void pci_for_each_device(PCIBus *bus, int bus_num,
1590 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1591 void *opaque)
1592 {
1593 bus = pci_find_bus_nr(bus, bus_num);
1594
1595 if (bus) {
1596 pci_for_each_device_under_bus(bus, fn, opaque);
1597 }
1598 }
1599
1600 static const pci_class_desc *get_class_desc(int class)
1601 {
1602 const pci_class_desc *desc;
1603
1604 desc = pci_class_descriptions;
1605 while (desc->desc && class != desc->class) {
1606 desc++;
1607 }
1608
1609 return desc;
1610 }
1611
1612 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1613
1614 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1615 {
1616 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1617 int i;
1618
1619 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1620 const PCIIORegion *r = &dev->io_regions[i];
1621 PciMemoryRegionList *region;
1622
1623 if (!r->size) {
1624 continue;
1625 }
1626
1627 region = g_malloc0(sizeof(*region));
1628 region->value = g_malloc0(sizeof(*region->value));
1629
1630 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1631 region->value->type = g_strdup("io");
1632 } else {
1633 region->value->type = g_strdup("memory");
1634 region->value->has_prefetch = true;
1635 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1636 region->value->has_mem_type_64 = true;
1637 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1638 }
1639
1640 region->value->bar = i;
1641 region->value->address = r->addr;
1642 region->value->size = r->size;
1643
1644 /* XXX: waiting for the qapi to support GSList */
1645 if (!cur_item) {
1646 head = cur_item = region;
1647 } else {
1648 cur_item->next = region;
1649 cur_item = region;
1650 }
1651 }
1652
1653 return head;
1654 }
1655
1656 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1657 int bus_num)
1658 {
1659 PciBridgeInfo *info;
1660 PciMemoryRange *range;
1661
1662 info = g_new0(PciBridgeInfo, 1);
1663
1664 info->bus = g_new0(PciBusInfo, 1);
1665 info->bus->number = dev->config[PCI_PRIMARY_BUS];
1666 info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
1667 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
1668
1669 range = info->bus->io_range = g_new0(PciMemoryRange, 1);
1670 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1671 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1672
1673 range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
1674 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1675 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1676
1677 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
1678 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1679 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1680
1681 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1682 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1683 if (child_bus) {
1684 info->has_devices = true;
1685 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1686 }
1687 }
1688
1689 return info;
1690 }
1691
1692 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1693 int bus_num)
1694 {
1695 const pci_class_desc *desc;
1696 PciDeviceInfo *info;
1697 uint8_t type;
1698 int class;
1699
1700 info = g_new0(PciDeviceInfo, 1);
1701 info->bus = bus_num;
1702 info->slot = PCI_SLOT(dev->devfn);
1703 info->function = PCI_FUNC(dev->devfn);
1704
1705 info->class_info = g_new0(PciDeviceClass, 1);
1706 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1707 info->class_info->q_class = class;
1708 desc = get_class_desc(class);
1709 if (desc->desc) {
1710 info->class_info->has_desc = true;
1711 info->class_info->desc = g_strdup(desc->desc);
1712 }
1713
1714 info->id = g_new0(PciDeviceId, 1);
1715 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1716 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
1717 info->regions = qmp_query_pci_regions(dev);
1718 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1719
1720 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1721 info->has_irq = true;
1722 info->irq = dev->config[PCI_INTERRUPT_LINE];
1723 }
1724
1725 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1726 if (type == PCI_HEADER_TYPE_BRIDGE) {
1727 info->has_pci_bridge = true;
1728 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1729 }
1730
1731 return info;
1732 }
1733
1734 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1735 {
1736 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1737 PCIDevice *dev;
1738 int devfn;
1739
1740 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1741 dev = bus->devices[devfn];
1742 if (dev) {
1743 info = g_malloc0(sizeof(*info));
1744 info->value = qmp_query_pci_device(dev, bus, bus_num);
1745
1746 /* XXX: waiting for the qapi to support GSList */
1747 if (!cur_item) {
1748 head = cur_item = info;
1749 } else {
1750 cur_item->next = info;
1751 cur_item = info;
1752 }
1753 }
1754 }
1755
1756 return head;
1757 }
1758
1759 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1760 {
1761 PciInfo *info = NULL;
1762
1763 bus = pci_find_bus_nr(bus, bus_num);
1764 if (bus) {
1765 info = g_malloc0(sizeof(*info));
1766 info->bus = bus_num;
1767 info->devices = qmp_query_pci_devices(bus, bus_num);
1768 }
1769
1770 return info;
1771 }
1772
1773 PciInfoList *qmp_query_pci(Error **errp)
1774 {
1775 PciInfoList *info, *head = NULL, *cur_item = NULL;
1776 PCIHostState *host_bridge;
1777
1778 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
1779 info = g_malloc0(sizeof(*info));
1780 info->value = qmp_query_pci_bus(host_bridge->bus,
1781 pci_bus_num(host_bridge->bus));
1782
1783 /* XXX: waiting for the qapi to support GSList */
1784 if (!cur_item) {
1785 head = cur_item = info;
1786 } else {
1787 cur_item->next = info;
1788 cur_item = info;
1789 }
1790 }
1791
1792 return head;
1793 }
1794
1795 static const char * const pci_nic_models[] = {
1796 "ne2k_pci",
1797 "i82551",
1798 "i82557b",
1799 "i82559er",
1800 "rtl8139",
1801 "e1000",
1802 "pcnet",
1803 "virtio",
1804 NULL
1805 };
1806
1807 static const char * const pci_nic_names[] = {
1808 "ne2k_pci",
1809 "i82551",
1810 "i82557b",
1811 "i82559er",
1812 "rtl8139",
1813 "e1000",
1814 "pcnet",
1815 "virtio-net-pci",
1816 NULL
1817 };
1818
1819 /* Initialize a PCI NIC. */
1820 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
1821 const char *default_model,
1822 const char *default_devaddr)
1823 {
1824 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1825 PCIBus *bus;
1826 PCIDevice *pci_dev;
1827 DeviceState *dev;
1828 int devfn;
1829 int i;
1830
1831 if (qemu_show_nic_models(nd->model, pci_nic_models)) {
1832 exit(0);
1833 }
1834
1835 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1836 if (i < 0) {
1837 exit(1);
1838 }
1839
1840 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
1841 if (!bus) {
1842 error_report("Invalid PCI device address %s for device %s",
1843 devaddr, pci_nic_names[i]);
1844 exit(1);
1845 }
1846
1847 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1848 dev = &pci_dev->qdev;
1849 qdev_set_nic_properties(dev, nd);
1850 qdev_init_nofail(dev);
1851
1852 return pci_dev;
1853 }
1854
1855 PCIDevice *pci_vga_init(PCIBus *bus)
1856 {
1857 switch (vga_interface_type) {
1858 case VGA_CIRRUS:
1859 return pci_create_simple(bus, -1, "cirrus-vga");
1860 case VGA_QXL:
1861 return pci_create_simple(bus, -1, "qxl-vga");
1862 case VGA_STD:
1863 return pci_create_simple(bus, -1, "VGA");
1864 case VGA_VMWARE:
1865 return pci_create_simple(bus, -1, "vmware-svga");
1866 case VGA_VIRTIO:
1867 return pci_create_simple(bus, -1, "virtio-vga");
1868 case VGA_NONE:
1869 default: /* Other non-PCI types. Checking for unsupported types is already
1870 done in vl.c. */
1871 return NULL;
1872 }
1873 }
1874
1875 /* Whether a given bus number is in range of the secondary
1876 * bus of the given bridge device. */
1877 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1878 {
1879 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1880 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1881 dev->config[PCI_SECONDARY_BUS] <= bus_num &&
1882 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1883 }
1884
1885 /* Whether a given bus number is in a range of a root bus */
1886 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
1887 {
1888 int i;
1889
1890 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1891 PCIDevice *dev = bus->devices[i];
1892
1893 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) {
1894 if (pci_secondary_bus_in_range(dev, bus_num)) {
1895 return true;
1896 }
1897 }
1898 }
1899
1900 return false;
1901 }
1902
1903 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1904 {
1905 PCIBus *sec;
1906
1907 if (!bus) {
1908 return NULL;
1909 }
1910
1911 if (pci_bus_num(bus) == bus_num) {
1912 return bus;
1913 }
1914
1915 /* Consider all bus numbers in range for the host pci bridge. */
1916 if (!pci_bus_is_root(bus) &&
1917 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1918 return NULL;
1919 }
1920
1921 /* try child bus */
1922 for (; bus; bus = sec) {
1923 QLIST_FOREACH(sec, &bus->child, sibling) {
1924 if (pci_bus_num(sec) == bus_num) {
1925 return sec;
1926 }
1927 /* PXB buses assumed to be children of bus 0 */
1928 if (pci_bus_is_root(sec)) {
1929 if (pci_root_bus_in_range(sec, bus_num)) {
1930 break;
1931 }
1932 } else {
1933 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1934 break;
1935 }
1936 }
1937 }
1938 }
1939
1940 return NULL;
1941 }
1942
1943 void pci_for_each_bus_depth_first(PCIBus *bus,
1944 void *(*begin)(PCIBus *bus, void *parent_state),
1945 void (*end)(PCIBus *bus, void *state),
1946 void *parent_state)
1947 {
1948 PCIBus *sec;
1949 void *state;
1950
1951 if (!bus) {
1952 return;
1953 }
1954
1955 if (begin) {
1956 state = begin(bus, parent_state);
1957 } else {
1958 state = parent_state;
1959 }
1960
1961 QLIST_FOREACH(sec, &bus->child, sibling) {
1962 pci_for_each_bus_depth_first(sec, begin, end, state);
1963 }
1964
1965 if (end) {
1966 end(bus, state);
1967 }
1968 }
1969
1970
1971 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1972 {
1973 bus = pci_find_bus_nr(bus, bus_num);
1974
1975 if (!bus)
1976 return NULL;
1977
1978 return bus->devices[devfn];
1979 }
1980
1981 static void pci_qdev_realize(DeviceState *qdev, Error **errp)
1982 {
1983 PCIDevice *pci_dev = (PCIDevice *)qdev;
1984 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1985 Error *local_err = NULL;
1986 PCIBus *bus;
1987 bool is_default_rom;
1988
1989 /* initialize cap_present for pci_is_express() and pci_config_size() */
1990 if (pc->is_express) {
1991 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1992 }
1993
1994 bus = PCI_BUS(qdev_get_parent_bus(qdev));
1995 pci_dev = do_pci_register_device(pci_dev, bus,
1996 object_get_typename(OBJECT(qdev)),
1997 pci_dev->devfn, errp);
1998 if (pci_dev == NULL)
1999 return;
2000
2001 if (pc->realize) {
2002 pc->realize(pci_dev, &local_err);
2003 if (local_err) {
2004 error_propagate(errp, local_err);
2005 do_pci_unregister_device(pci_dev);
2006 return;
2007 }
2008 }
2009
2010 /* rom loading */
2011 is_default_rom = false;
2012 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
2013 pci_dev->romfile = g_strdup(pc->romfile);
2014 is_default_rom = true;
2015 }
2016
2017 pci_add_option_rom(pci_dev, is_default_rom, &local_err);
2018 if (local_err) {
2019 error_propagate(errp, local_err);
2020 pci_qdev_unrealize(DEVICE(pci_dev), NULL);
2021 return;
2022 }
2023 }
2024
2025 static void pci_default_realize(PCIDevice *dev, Error **errp)
2026 {
2027 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2028
2029 if (pc->init) {
2030 if (pc->init(dev) < 0) {
2031 error_setg(errp, "Device initialization failed");
2032 return;
2033 }
2034 }
2035 }
2036
2037 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
2038 const char *name)
2039 {
2040 DeviceState *dev;
2041
2042 dev = qdev_create(&bus->qbus, name);
2043 qdev_prop_set_int32(dev, "addr", devfn);
2044 qdev_prop_set_bit(dev, "multifunction", multifunction);
2045 return PCI_DEVICE(dev);
2046 }
2047
2048 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
2049 bool multifunction,
2050 const char *name)
2051 {
2052 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
2053 qdev_init_nofail(&dev->qdev);
2054 return dev;
2055 }
2056
2057 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
2058 {
2059 return pci_create_multifunction(bus, devfn, false, name);
2060 }
2061
2062 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
2063 {
2064 return pci_create_simple_multifunction(bus, devfn, false, name);
2065 }
2066
2067 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
2068 {
2069 int offset = PCI_CONFIG_HEADER_SIZE;
2070 int i;
2071 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
2072 if (pdev->used[i])
2073 offset = i + 1;
2074 else if (i - offset + 1 == size)
2075 return offset;
2076 }
2077 return 0;
2078 }
2079
2080 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
2081 uint8_t *prev_p)
2082 {
2083 uint8_t next, prev;
2084
2085 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
2086 return 0;
2087
2088 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2089 prev = next + PCI_CAP_LIST_NEXT)
2090 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
2091 break;
2092
2093 if (prev_p)
2094 *prev_p = prev;
2095 return next;
2096 }
2097
2098 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
2099 {
2100 uint8_t next, prev, found = 0;
2101
2102 if (!(pdev->used[offset])) {
2103 return 0;
2104 }
2105
2106 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
2107
2108 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2109 prev = next + PCI_CAP_LIST_NEXT) {
2110 if (next <= offset && next > found) {
2111 found = next;
2112 }
2113 }
2114 return found;
2115 }
2116
2117 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2118 This is needed for an option rom which is used for more than one device. */
2119 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
2120 {
2121 uint16_t vendor_id;
2122 uint16_t device_id;
2123 uint16_t rom_vendor_id;
2124 uint16_t rom_device_id;
2125 uint16_t rom_magic;
2126 uint16_t pcir_offset;
2127 uint8_t checksum;
2128
2129 /* Words in rom data are little endian (like in PCI configuration),
2130 so they can be read / written with pci_get_word / pci_set_word. */
2131
2132 /* Only a valid rom will be patched. */
2133 rom_magic = pci_get_word(ptr);
2134 if (rom_magic != 0xaa55) {
2135 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
2136 return;
2137 }
2138 pcir_offset = pci_get_word(ptr + 0x18);
2139 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
2140 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
2141 return;
2142 }
2143
2144 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
2145 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
2146 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
2147 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
2148
2149 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
2150 vendor_id, device_id, rom_vendor_id, rom_device_id);
2151
2152 checksum = ptr[6];
2153
2154 if (vendor_id != rom_vendor_id) {
2155 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2156 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
2157 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
2158 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2159 ptr[6] = checksum;
2160 pci_set_word(ptr + pcir_offset + 4, vendor_id);
2161 }
2162
2163 if (device_id != rom_device_id) {
2164 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2165 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
2166 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
2167 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2168 ptr[6] = checksum;
2169 pci_set_word(ptr + pcir_offset + 6, device_id);
2170 }
2171 }
2172
2173 /* Add an option rom for the device */
2174 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
2175 Error **errp)
2176 {
2177 int size;
2178 char *path;
2179 void *ptr;
2180 char name[32];
2181 const VMStateDescription *vmsd;
2182
2183 if (!pdev->romfile)
2184 return;
2185 if (strlen(pdev->romfile) == 0)
2186 return;
2187
2188 if (!pdev->rom_bar) {
2189 /*
2190 * Load rom via fw_cfg instead of creating a rom bar,
2191 * for 0.11 compatibility.
2192 */
2193 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
2194
2195 /*
2196 * Hot-plugged devices can't use the option ROM
2197 * if the rom bar is disabled.
2198 */
2199 if (DEVICE(pdev)->hotplugged) {
2200 error_setg(errp, "Hot-plugged device without ROM bar"
2201 " can't have an option ROM");
2202 return;
2203 }
2204
2205 if (class == 0x0300) {
2206 rom_add_vga(pdev->romfile);
2207 } else {
2208 rom_add_option(pdev->romfile, -1);
2209 }
2210 return;
2211 }
2212
2213 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
2214 if (path == NULL) {
2215 path = g_strdup(pdev->romfile);
2216 }
2217
2218 size = get_image_size(path);
2219 if (size < 0) {
2220 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
2221 g_free(path);
2222 return;
2223 } else if (size == 0) {
2224 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
2225 g_free(path);
2226 return;
2227 }
2228 size = pow2ceil(size);
2229
2230 vmsd = qdev_get_vmsd(DEVICE(pdev));
2231
2232 if (vmsd) {
2233 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
2234 } else {
2235 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
2236 }
2237 pdev->has_rom = true;
2238 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal);
2239 ptr = memory_region_get_ram_ptr(&pdev->rom);
2240 load_image(path, ptr);
2241 g_free(path);
2242
2243 if (is_default_rom) {
2244 /* Only the default rom images will be patched (if needed). */
2245 pci_patch_ids(pdev, ptr, size);
2246 }
2247
2248 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
2249 }
2250
2251 static void pci_del_option_rom(PCIDevice *pdev)
2252 {
2253 if (!pdev->has_rom)
2254 return;
2255
2256 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
2257 pdev->has_rom = false;
2258 }
2259
2260 /*
2261 * On success, pci_add_capability() returns a positive value
2262 * that the offset of the pci capability.
2263 * On failure, it sets an error and returns a negative error
2264 * code.
2265 */
2266 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2267 uint8_t offset, uint8_t size,
2268 Error **errp)
2269 {
2270 uint8_t *config;
2271 int i, overlapping_cap;
2272
2273 if (!offset) {
2274 offset = pci_find_space(pdev, size);
2275 /* out of PCI config space is programming error */
2276 assert(offset);
2277 } else {
2278 /* Verify that capabilities don't overlap. Note: device assignment
2279 * depends on this check to verify that the device is not broken.
2280 * Should never trigger for emulated devices, but it's helpful
2281 * for debugging these. */
2282 for (i = offset; i < offset + size; i++) {
2283 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2284 if (overlapping_cap) {
2285 error_setg(errp, "%s:%02x:%02x.%x "
2286 "Attempt to add PCI capability %x at offset "
2287 "%x overlaps existing capability %x at offset %x",
2288 pci_root_bus_path(pdev), pci_bus_num(pdev->bus),
2289 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2290 cap_id, offset, overlapping_cap, i);
2291 return -EINVAL;
2292 }
2293 }
2294 }
2295
2296 config = pdev->config + offset;
2297 config[PCI_CAP_LIST_ID] = cap_id;
2298 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2299 pdev->config[PCI_CAPABILITY_LIST] = offset;
2300 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2301 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2302 /* Make capability read-only by default */
2303 memset(pdev->wmask + offset, 0, size);
2304 /* Check capability by default */
2305 memset(pdev->cmask + offset, 0xFF, size);
2306 return offset;
2307 }
2308
2309 /* Unlink capability from the pci config space. */
2310 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2311 {
2312 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2313 if (!offset)
2314 return;
2315 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2316 /* Make capability writable again */
2317 memset(pdev->wmask + offset, 0xff, size);
2318 memset(pdev->w1cmask + offset, 0, size);
2319 /* Clear cmask as device-specific registers can't be checked */
2320 memset(pdev->cmask + offset, 0, size);
2321 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2322
2323 if (!pdev->config[PCI_CAPABILITY_LIST])
2324 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2325 }
2326
2327 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2328 {
2329 return pci_find_capability_list(pdev, cap_id, NULL);
2330 }
2331
2332 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2333 {
2334 PCIDevice *d = (PCIDevice *)dev;
2335 const pci_class_desc *desc;
2336 char ctxt[64];
2337 PCIIORegion *r;
2338 int i, class;
2339
2340 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2341 desc = pci_class_descriptions;
2342 while (desc->desc && class != desc->class)
2343 desc++;
2344 if (desc->desc) {
2345 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2346 } else {
2347 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2348 }
2349
2350 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2351 "pci id %04x:%04x (sub %04x:%04x)\n",
2352 indent, "", ctxt, pci_bus_num(d->bus),
2353 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2354 pci_get_word(d->config + PCI_VENDOR_ID),
2355 pci_get_word(d->config + PCI_DEVICE_ID),
2356 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2357 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2358 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2359 r = &d->io_regions[i];
2360 if (!r->size)
2361 continue;
2362 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2363 " [0x%"FMT_PCIBUS"]\n",
2364 indent, "",
2365 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2366 r->addr, r->addr + r->size - 1);
2367 }
2368 }
2369
2370 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2371 {
2372 PCIDevice *d = (PCIDevice *)dev;
2373 const char *name = NULL;
2374 const pci_class_desc *desc = pci_class_descriptions;
2375 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2376
2377 while (desc->desc &&
2378 (class & ~desc->fw_ign_bits) !=
2379 (desc->class & ~desc->fw_ign_bits)) {
2380 desc++;
2381 }
2382
2383 if (desc->desc) {
2384 name = desc->fw_name;
2385 }
2386
2387 if (name) {
2388 pstrcpy(buf, len, name);
2389 } else {
2390 snprintf(buf, len, "pci%04x,%04x",
2391 pci_get_word(d->config + PCI_VENDOR_ID),
2392 pci_get_word(d->config + PCI_DEVICE_ID));
2393 }
2394
2395 return buf;
2396 }
2397
2398 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2399 {
2400 PCIDevice *d = (PCIDevice *)dev;
2401 char path[50], name[33];
2402 int off;
2403
2404 off = snprintf(path, sizeof(path), "%s@%x",
2405 pci_dev_fw_name(dev, name, sizeof name),
2406 PCI_SLOT(d->devfn));
2407 if (PCI_FUNC(d->devfn))
2408 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2409 return g_strdup(path);
2410 }
2411
2412 static char *pcibus_get_dev_path(DeviceState *dev)
2413 {
2414 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2415 PCIDevice *t;
2416 int slot_depth;
2417 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2418 * 00 is added here to make this format compatible with
2419 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2420 * Slot.Function list specifies the slot and function numbers for all
2421 * devices on the path from root to the specific device. */
2422 const char *root_bus_path;
2423 int root_bus_len;
2424 char slot[] = ":SS.F";
2425 int slot_len = sizeof slot - 1 /* For '\0' */;
2426 int path_len;
2427 char *path, *p;
2428 int s;
2429
2430 root_bus_path = pci_root_bus_path(d);
2431 root_bus_len = strlen(root_bus_path);
2432
2433 /* Calculate # of slots on path between device and root. */;
2434 slot_depth = 0;
2435 for (t = d; t; t = t->bus->parent_dev) {
2436 ++slot_depth;
2437 }
2438
2439 path_len = root_bus_len + slot_len * slot_depth;
2440
2441 /* Allocate memory, fill in the terminating null byte. */
2442 path = g_malloc(path_len + 1 /* For '\0' */);
2443 path[path_len] = '\0';
2444
2445 memcpy(path, root_bus_path, root_bus_len);
2446
2447 /* Fill in slot numbers. We walk up from device to root, so need to print
2448 * them in the reverse order, last to first. */
2449 p = path + path_len;
2450 for (t = d; t; t = t->bus->parent_dev) {
2451 p -= slot_len;
2452 s = snprintf(slot, sizeof slot, ":%02x.%x",
2453 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2454 assert(s == slot_len);
2455 memcpy(p, slot, slot_len);
2456 }
2457
2458 return path;
2459 }
2460
2461 static int pci_qdev_find_recursive(PCIBus *bus,
2462 const char *id, PCIDevice **pdev)
2463 {
2464 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2465 if (!qdev) {
2466 return -ENODEV;
2467 }
2468
2469 /* roughly check if given qdev is pci device */
2470 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2471 *pdev = PCI_DEVICE(qdev);
2472 return 0;
2473 }
2474 return -EINVAL;
2475 }
2476
2477 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2478 {
2479 PCIHostState *host_bridge;
2480 int rc = -ENODEV;
2481
2482 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2483 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
2484 if (!tmp) {
2485 rc = 0;
2486 break;
2487 }
2488 if (tmp != -ENODEV) {
2489 rc = tmp;
2490 }
2491 }
2492
2493 return rc;
2494 }
2495
2496 MemoryRegion *pci_address_space(PCIDevice *dev)
2497 {
2498 return dev->bus->address_space_mem;
2499 }
2500
2501 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2502 {
2503 return dev->bus->address_space_io;
2504 }
2505
2506 static void pci_device_class_init(ObjectClass *klass, void *data)
2507 {
2508 DeviceClass *k = DEVICE_CLASS(klass);
2509 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
2510
2511 k->realize = pci_qdev_realize;
2512 k->unrealize = pci_qdev_unrealize;
2513 k->bus_type = TYPE_PCI_BUS;
2514 k->props = pci_props;
2515 pc->realize = pci_default_realize;
2516 }
2517
2518 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2519 {
2520 PCIBus *bus = PCI_BUS(dev->bus);
2521 PCIBus *iommu_bus = bus;
2522
2523 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) {
2524 iommu_bus = PCI_BUS(iommu_bus->parent_dev->bus);
2525 }
2526 if (iommu_bus && iommu_bus->iommu_fn) {
2527 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn);
2528 }
2529 return &address_space_memory;
2530 }
2531
2532 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
2533 {
2534 bus->iommu_fn = fn;
2535 bus->iommu_opaque = opaque;
2536 }
2537
2538 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2539 {
2540 Range *range = opaque;
2541 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2542 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
2543 int i;
2544
2545 if (!(cmd & PCI_COMMAND_MEMORY)) {
2546 return;
2547 }
2548
2549 if (pc->is_bridge) {
2550 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2551 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2552
2553 base = MAX(base, 0x1ULL << 32);
2554
2555 if (limit >= base) {
2556 Range pref_range;
2557 range_set_bounds(&pref_range, base, limit);
2558 range_extend(range, &pref_range);
2559 }
2560 }
2561 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2562 PCIIORegion *r = &dev->io_regions[i];
2563 pcibus_t lob, upb;
2564 Range region_range;
2565
2566 if (!r->size ||
2567 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2568 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2569 continue;
2570 }
2571
2572 lob = pci_bar_address(dev, i, r->type, r->size);
2573 upb = lob + r->size - 1;
2574 if (lob == PCI_BAR_UNMAPPED) {
2575 continue;
2576 }
2577
2578 lob = MAX(lob, 0x1ULL << 32);
2579
2580 if (upb >= lob) {
2581 range_set_bounds(&region_range, lob, upb);
2582 range_extend(range, &region_range);
2583 }
2584 }
2585 }
2586
2587 void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2588 {
2589 range_make_empty(range);
2590 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2591 }
2592
2593 static bool pcie_has_upstream_port(PCIDevice *dev)
2594 {
2595 PCIDevice *parent_dev = pci_bridge_get_device(dev->bus);
2596
2597 /* Device associated with an upstream port.
2598 * As there are several types of these, it's easier to check the
2599 * parent device: upstream ports are always connected to
2600 * root or downstream ports.
2601 */
2602 return parent_dev &&
2603 pci_is_express(parent_dev) &&
2604 parent_dev->exp.exp_cap &&
2605 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT ||
2606 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM);
2607 }
2608
2609 PCIDevice *pci_get_function_0(PCIDevice *pci_dev)
2610 {
2611 if(pcie_has_upstream_port(pci_dev)) {
2612 /* With an upstream PCIe port, we only support 1 device at slot 0 */
2613 return pci_dev->bus->devices[0];
2614 } else {
2615 /* Other bus types might support multiple devices at slots 0-31 */
2616 return pci_dev->bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)];
2617 }
2618 }
2619
2620 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector)
2621 {
2622 MSIMessage msg;
2623 if (msix_enabled(dev)) {
2624 msg = msix_get_message(dev, vector);
2625 } else if (msi_enabled(dev)) {
2626 msg = msi_get_message(dev, vector);
2627 } else {
2628 /* Should never happen */
2629 error_report("%s: unknown interrupt type", __func__);
2630 abort();
2631 }
2632 return msg;
2633 }
2634
2635 static const TypeInfo pci_device_type_info = {
2636 .name = TYPE_PCI_DEVICE,
2637 .parent = TYPE_DEVICE,
2638 .instance_size = sizeof(PCIDevice),
2639 .abstract = true,
2640 .class_size = sizeof(PCIDeviceClass),
2641 .class_init = pci_device_class_init,
2642 };
2643
2644 static void pci_register_types(void)
2645 {
2646 type_register_static(&pci_bus_info);
2647 type_register_static(&pcie_bus_info);
2648 type_register_static(&pci_device_type_info);
2649 }
2650
2651 type_init(pci_register_types)
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