4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
21 #include "qemu-common.h"
22 #ifdef CONFIG_USER_ONLY
34 #include "qemu-char.h"
39 #define MAX_PACKET_LENGTH 4096
41 #include "qemu_socket.h"
49 GDB_SIGNAL_UNKNOWN
= 143
52 #ifdef CONFIG_USER_ONLY
54 /* Map target signal numbers to GDB protocol signal numbers and vice
55 * versa. For user emulation's currently supported systems, we can
56 * assume most signals are defined.
59 static int gdb_signal_table
[] = {
219 /* In system mode we only need SIGINT and SIGTRAP; other signals
220 are not yet supported. */
227 static int gdb_signal_table
[] = {
237 #ifdef CONFIG_USER_ONLY
238 static int target_signal_to_gdb (int sig
)
241 for (i
= 0; i
< ARRAY_SIZE (gdb_signal_table
); i
++)
242 if (gdb_signal_table
[i
] == sig
)
244 return GDB_SIGNAL_UNKNOWN
;
248 static int gdb_signal_to_target (int sig
)
250 if (sig
< ARRAY_SIZE (gdb_signal_table
))
251 return gdb_signal_table
[sig
];
258 typedef struct GDBRegisterState
{
264 struct GDBRegisterState
*next
;
275 typedef struct GDBState
{
276 CPUState
*c_cpu
; /* current CPU for step/continue ops */
277 CPUState
*g_cpu
; /* current CPU for other ops */
278 CPUState
*query_cpu
; /* for q{f|s}ThreadInfo */
279 enum RSState state
; /* parsing state */
280 char line_buf
[MAX_PACKET_LENGTH
];
283 uint8_t last_packet
[MAX_PACKET_LENGTH
+ 4];
286 #ifdef CONFIG_USER_ONLY
290 CharDriverState
*chr
;
291 CharDriverState
*mon_chr
;
295 /* By default use no IRQs and no timers while single stepping so as to
296 * make single stepping like an ICE HW step.
298 static int sstep_flags
= SSTEP_ENABLE
|SSTEP_NOIRQ
|SSTEP_NOTIMER
;
300 static GDBState
*gdbserver_state
;
302 /* This is an ugly hack to cope with both new and old gdb.
303 If gdb sends qXfer:features:read then assume we're talking to a newish
304 gdb that understands target descriptions. */
305 static int gdb_has_xml
;
307 #ifdef CONFIG_USER_ONLY
308 /* XXX: This is not thread safe. Do we care? */
309 static int gdbserver_fd
= -1;
311 static int get_char(GDBState
*s
)
317 ret
= recv(s
->fd
, &ch
, 1, 0);
319 if (errno
== ECONNRESET
)
321 if (errno
!= EINTR
&& errno
!= EAGAIN
)
323 } else if (ret
== 0) {
335 static gdb_syscall_complete_cb gdb_current_syscall_cb
;
343 /* If gdb is connected when the first semihosting syscall occurs then use
344 remote gdb syscalls. Otherwise use native file IO. */
345 int use_gdb_syscalls(void)
347 if (gdb_syscall_mode
== GDB_SYS_UNKNOWN
) {
348 gdb_syscall_mode
= (gdbserver_state
? GDB_SYS_ENABLED
351 return gdb_syscall_mode
== GDB_SYS_ENABLED
;
354 /* Resume execution. */
355 static inline void gdb_continue(GDBState
*s
)
357 #ifdef CONFIG_USER_ONLY
358 s
->running_state
= 1;
364 static void put_buffer(GDBState
*s
, const uint8_t *buf
, int len
)
366 #ifdef CONFIG_USER_ONLY
370 ret
= send(s
->fd
, buf
, len
, 0);
372 if (errno
!= EINTR
&& errno
!= EAGAIN
)
380 qemu_chr_write(s
->chr
, buf
, len
);
384 static inline int fromhex(int v
)
386 if (v
>= '0' && v
<= '9')
388 else if (v
>= 'A' && v
<= 'F')
390 else if (v
>= 'a' && v
<= 'f')
396 static inline int tohex(int v
)
404 static void memtohex(char *buf
, const uint8_t *mem
, int len
)
409 for(i
= 0; i
< len
; i
++) {
411 *q
++ = tohex(c
>> 4);
412 *q
++ = tohex(c
& 0xf);
417 static void hextomem(uint8_t *mem
, const char *buf
, int len
)
421 for(i
= 0; i
< len
; i
++) {
422 mem
[i
] = (fromhex(buf
[0]) << 4) | fromhex(buf
[1]);
427 /* return -1 if error, 0 if OK */
428 static int put_packet_binary(GDBState
*s
, const char *buf
, int len
)
439 for(i
= 0; i
< len
; i
++) {
443 *(p
++) = tohex((csum
>> 4) & 0xf);
444 *(p
++) = tohex((csum
) & 0xf);
446 s
->last_packet_len
= p
- s
->last_packet
;
447 put_buffer(s
, (uint8_t *)s
->last_packet
, s
->last_packet_len
);
449 #ifdef CONFIG_USER_ONLY
462 /* return -1 if error, 0 if OK */
463 static int put_packet(GDBState
*s
, const char *buf
)
466 printf("reply='%s'\n", buf
);
469 return put_packet_binary(s
, buf
, strlen(buf
));
472 /* The GDB remote protocol transfers values in target byte order. This means
473 we can use the raw memory access routines to access the value buffer.
474 Conveniently, these also handle the case where the buffer is mis-aligned.
476 #define GET_REG8(val) do { \
477 stb_p(mem_buf, val); \
480 #define GET_REG16(val) do { \
481 stw_p(mem_buf, val); \
484 #define GET_REG32(val) do { \
485 stl_p(mem_buf, val); \
488 #define GET_REG64(val) do { \
489 stq_p(mem_buf, val); \
493 #if TARGET_LONG_BITS == 64
494 #define GET_REGL(val) GET_REG64(val)
495 #define ldtul_p(addr) ldq_p(addr)
497 #define GET_REGL(val) GET_REG32(val)
498 #define ldtul_p(addr) ldl_p(addr)
501 #if defined(TARGET_I386)
504 static const int gpr_map
[16] = {
505 R_EAX
, R_EBX
, R_ECX
, R_EDX
, R_ESI
, R_EDI
, R_EBP
, R_ESP
,
506 8, 9, 10, 11, 12, 13, 14, 15
509 static const int gpr_map
[8] = {0, 1, 2, 3, 4, 5, 6, 7};
512 #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
514 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
516 if (n
< CPU_NB_REGS
) {
517 GET_REGL(env
->regs
[gpr_map
[n
]]);
518 } else if (n
>= CPU_NB_REGS
+ 8 && n
< CPU_NB_REGS
+ 16) {
519 /* FIXME: byteswap float values. */
520 #ifdef USE_X86LDOUBLE
521 memcpy(mem_buf
, &env
->fpregs
[n
- (CPU_NB_REGS
+ 8)], 10);
523 memset(mem_buf
, 0, 10);
526 } else if (n
>= CPU_NB_REGS
+ 24) {
527 n
-= CPU_NB_REGS
+ 24;
528 if (n
< CPU_NB_REGS
) {
529 stq_p(mem_buf
, env
->xmm_regs
[n
].XMM_Q(0));
530 stq_p(mem_buf
+ 8, env
->xmm_regs
[n
].XMM_Q(1));
532 } else if (n
== CPU_NB_REGS
) {
533 GET_REG32(env
->mxcsr
);
538 case 0: GET_REGL(env
->eip
);
539 case 1: GET_REG32(env
->eflags
);
540 case 2: GET_REG32(env
->segs
[R_CS
].selector
);
541 case 3: GET_REG32(env
->segs
[R_SS
].selector
);
542 case 4: GET_REG32(env
->segs
[R_DS
].selector
);
543 case 5: GET_REG32(env
->segs
[R_ES
].selector
);
544 case 6: GET_REG32(env
->segs
[R_FS
].selector
);
545 case 7: GET_REG32(env
->segs
[R_GS
].selector
);
546 /* 8...15 x87 regs. */
547 case 16: GET_REG32(env
->fpuc
);
548 case 17: GET_REG32((env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11);
549 case 18: GET_REG32(0); /* ftag */
550 case 19: GET_REG32(0); /* fiseg */
551 case 20: GET_REG32(0); /* fioff */
552 case 21: GET_REG32(0); /* foseg */
553 case 22: GET_REG32(0); /* fooff */
554 case 23: GET_REG32(0); /* fop */
561 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int i
)
565 if (i
< CPU_NB_REGS
) {
566 env
->regs
[gpr_map
[i
]] = ldtul_p(mem_buf
);
567 return sizeof(target_ulong
);
568 } else if (i
>= CPU_NB_REGS
+ 8 && i
< CPU_NB_REGS
+ 16) {
569 i
-= CPU_NB_REGS
+ 8;
570 #ifdef USE_X86LDOUBLE
571 memcpy(&env
->fpregs
[i
], mem_buf
, 10);
574 } else if (i
>= CPU_NB_REGS
+ 24) {
575 i
-= CPU_NB_REGS
+ 24;
576 if (i
< CPU_NB_REGS
) {
577 env
->xmm_regs
[i
].XMM_Q(0) = ldq_p(mem_buf
);
578 env
->xmm_regs
[i
].XMM_Q(1) = ldq_p(mem_buf
+ 8);
580 } else if (i
== CPU_NB_REGS
) {
581 env
->mxcsr
= ldl_p(mem_buf
);
587 case 0: env
->eip
= ldtul_p(mem_buf
); return sizeof(target_ulong
);
588 case 1: env
->eflags
= ldl_p(mem_buf
); return 4;
589 #if defined(CONFIG_USER_ONLY)
590 #define LOAD_SEG(index, sreg)\
591 tmp = ldl_p(mem_buf);\
592 if (tmp != env->segs[sreg].selector)\
593 cpu_x86_load_seg(env, sreg, tmp);
595 /* FIXME: Honor segment registers. Needs to avoid raising an exception
596 when the selector is invalid. */
597 #define LOAD_SEG(index, sreg) do {} while(0)
599 case 2: LOAD_SEG(10, R_CS
); return 4;
600 case 3: LOAD_SEG(11, R_SS
); return 4;
601 case 4: LOAD_SEG(12, R_DS
); return 4;
602 case 5: LOAD_SEG(13, R_ES
); return 4;
603 case 6: LOAD_SEG(14, R_FS
); return 4;
604 case 7: LOAD_SEG(15, R_GS
); return 4;
605 /* 8...15 x87 regs. */
606 case 16: env
->fpuc
= ldl_p(mem_buf
); return 4;
608 tmp
= ldl_p(mem_buf
);
609 env
->fpstt
= (tmp
>> 11) & 7;
610 env
->fpus
= tmp
& ~0x3800;
612 case 18: /* ftag */ return 4;
613 case 19: /* fiseg */ return 4;
614 case 20: /* fioff */ return 4;
615 case 21: /* foseg */ return 4;
616 case 22: /* fooff */ return 4;
617 case 23: /* fop */ return 4;
621 /* Unrecognised register. */
625 #elif defined (TARGET_PPC)
627 /* Old gdb always expects FP registers. Newer (xml-aware) gdb only
628 expects whatever the target description contains. Due to a
629 historical mishap the FP registers appear in between core integer
630 regs and PC, MSR, CR, and so forth. We hack round this by giving the
631 FP regs zero size when talking to a newer gdb. */
632 #define NUM_CORE_REGS 71
633 #if defined (TARGET_PPC64)
634 #define GDB_CORE_XML "power64-core.xml"
636 #define GDB_CORE_XML "power-core.xml"
639 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
643 GET_REGL(env
->gpr
[n
]);
648 stfq_p(mem_buf
, env
->fpr
[n
-32]);
652 case 64: GET_REGL(env
->nip
);
653 case 65: GET_REGL(env
->msr
);
658 for (i
= 0; i
< 8; i
++)
659 cr
|= env
->crf
[i
] << (32 - ((i
+ 1) * 4));
662 case 67: GET_REGL(env
->lr
);
663 case 68: GET_REGL(env
->ctr
);
664 case 69: GET_REGL(env
->xer
);
669 GET_REG32(0); /* fpscr */
676 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
680 env
->gpr
[n
] = ldtul_p(mem_buf
);
681 return sizeof(target_ulong
);
686 env
->fpr
[n
-32] = ldfq_p(mem_buf
);
691 env
->nip
= ldtul_p(mem_buf
);
692 return sizeof(target_ulong
);
694 ppc_store_msr(env
, ldtul_p(mem_buf
));
695 return sizeof(target_ulong
);
698 uint32_t cr
= ldl_p(mem_buf
);
700 for (i
= 0; i
< 8; i
++)
701 env
->crf
[i
] = (cr
>> (32 - ((i
+ 1) * 4))) & 0xF;
705 env
->lr
= ldtul_p(mem_buf
);
706 return sizeof(target_ulong
);
708 env
->ctr
= ldtul_p(mem_buf
);
709 return sizeof(target_ulong
);
711 env
->xer
= ldtul_p(mem_buf
);
712 return sizeof(target_ulong
);
723 #elif defined (TARGET_SPARC)
725 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
726 #define NUM_CORE_REGS 86
728 #define NUM_CORE_REGS 72
732 #define GET_REGA(val) GET_REG32(val)
734 #define GET_REGA(val) GET_REGL(val)
737 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
741 GET_REGA(env
->gregs
[n
]);
744 /* register window */
745 GET_REGA(env
->regwptr
[n
- 8]);
747 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
750 GET_REG32(*((uint32_t *)&env
->fpr
[n
- 32]));
752 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
754 case 64: GET_REGA(env
->y
);
755 case 65: GET_REGA(GET_PSR(env
));
756 case 66: GET_REGA(env
->wim
);
757 case 67: GET_REGA(env
->tbr
);
758 case 68: GET_REGA(env
->pc
);
759 case 69: GET_REGA(env
->npc
);
760 case 70: GET_REGA(env
->fsr
);
761 case 71: GET_REGA(0); /* csr */
762 default: GET_REGA(0);
767 GET_REG32(*((uint32_t *)&env
->fpr
[n
- 32]));
770 /* f32-f62 (double width, even numbers only) */
773 val
= (uint64_t)*((uint32_t *)&env
->fpr
[(n
- 64) * 2 + 32]) << 32;
774 val
|= *((uint32_t *)&env
->fpr
[(n
- 64) * 2 + 33]);
778 case 80: GET_REGL(env
->pc
);
779 case 81: GET_REGL(env
->npc
);
780 case 82: GET_REGL(((uint64_t)GET_CCR(env
) << 32) |
781 ((env
->asi
& 0xff) << 24) |
782 ((env
->pstate
& 0xfff) << 8) |
784 case 83: GET_REGL(env
->fsr
);
785 case 84: GET_REGL(env
->fprs
);
786 case 85: GET_REGL(env
->y
);
792 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
794 #if defined(TARGET_ABI32)
797 tmp
= ldl_p(mem_buf
);
801 tmp
= ldtul_p(mem_buf
);
808 /* register window */
809 env
->regwptr
[n
- 8] = tmp
;
811 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
814 *((uint32_t *)&env
->fpr
[n
- 32]) = tmp
;
816 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
818 case 64: env
->y
= tmp
; break;
819 case 65: PUT_PSR(env
, tmp
); break;
820 case 66: env
->wim
= tmp
; break;
821 case 67: env
->tbr
= tmp
; break;
822 case 68: env
->pc
= tmp
; break;
823 case 69: env
->npc
= tmp
; break;
824 case 70: env
->fsr
= tmp
; break;
832 env
->fpr
[n
] = ldfl_p(mem_buf
);
835 /* f32-f62 (double width, even numbers only) */
836 *((uint32_t *)&env
->fpr
[(n
- 64) * 2 + 32]) = tmp
>> 32;
837 *((uint32_t *)&env
->fpr
[(n
- 64) * 2 + 33]) = tmp
;
840 case 80: env
->pc
= tmp
; break;
841 case 81: env
->npc
= tmp
; break;
843 PUT_CCR(env
, tmp
>> 32);
844 env
->asi
= (tmp
>> 24) & 0xff;
845 env
->pstate
= (tmp
>> 8) & 0xfff;
846 PUT_CWP64(env
, tmp
& 0xff);
848 case 83: env
->fsr
= tmp
; break;
849 case 84: env
->fprs
= tmp
; break;
850 case 85: env
->y
= tmp
; break;
857 #elif defined (TARGET_ARM)
859 /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
860 whatever the target description contains. Due to a historical mishap
861 the FPA registers appear in between core integer regs and the CPSR.
862 We hack round this by giving the FPA regs zero size when talking to a
864 #define NUM_CORE_REGS 26
865 #define GDB_CORE_XML "arm-core.xml"
867 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
870 /* Core integer register. */
871 GET_REG32(env
->regs
[n
]);
877 memset(mem_buf
, 0, 12);
882 /* FPA status register. */
888 GET_REG32(cpsr_read(env
));
890 /* Unknown register. */
894 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
898 tmp
= ldl_p(mem_buf
);
900 /* Mask out low bit of PC to workaround gdb bugs. This will probably
901 cause problems if we ever implement the Jazelle DBX extensions. */
906 /* Core integer register. */
910 if (n
< 24) { /* 16-23 */
911 /* FPA registers (ignored). */
918 /* FPA status register (ignored). */
924 cpsr_write (env
, tmp
, 0xffffffff);
927 /* Unknown register. */
931 #elif defined (TARGET_M68K)
933 #define NUM_CORE_REGS 18
935 #define GDB_CORE_XML "cf-core.xml"
937 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
941 GET_REG32(env
->dregs
[n
]);
944 GET_REG32(env
->aregs
[n
- 8]);
947 case 16: GET_REG32(env
->sr
);
948 case 17: GET_REG32(env
->pc
);
951 /* FP registers not included here because they vary between
952 ColdFire and m68k. Use XML bits for these. */
956 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
960 tmp
= ldl_p(mem_buf
);
967 env
->aregs
[n
- 8] = tmp
;
970 case 16: env
->sr
= tmp
; break;
971 case 17: env
->pc
= tmp
; break;
977 #elif defined (TARGET_MIPS)
979 #define NUM_CORE_REGS 73
981 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
984 GET_REGL(env
->active_tc
.gpr
[n
]);
986 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
987 if (n
>= 38 && n
< 70) {
988 if (env
->CP0_Status
& (1 << CP0St_FR
))
989 GET_REGL(env
->active_fpu
.fpr
[n
- 38].d
);
991 GET_REGL(env
->active_fpu
.fpr
[n
- 38].w
[FP_ENDIAN_IDX
]);
994 case 70: GET_REGL((int32_t)env
->active_fpu
.fcr31
);
995 case 71: GET_REGL((int32_t)env
->active_fpu
.fcr0
);
999 case 32: GET_REGL((int32_t)env
->CP0_Status
);
1000 case 33: GET_REGL(env
->active_tc
.LO
[0]);
1001 case 34: GET_REGL(env
->active_tc
.HI
[0]);
1002 case 35: GET_REGL(env
->CP0_BadVAddr
);
1003 case 36: GET_REGL((int32_t)env
->CP0_Cause
);
1004 case 37: GET_REGL(env
->active_tc
.PC
);
1005 case 72: GET_REGL(0); /* fp */
1006 case 89: GET_REGL((int32_t)env
->CP0_PRid
);
1008 if (n
>= 73 && n
<= 88) {
1009 /* 16 embedded regs. */
1016 /* convert MIPS rounding mode in FCR31 to IEEE library */
1017 static unsigned int ieee_rm
[] =
1019 float_round_nearest_even
,
1020 float_round_to_zero
,
1024 #define RESTORE_ROUNDING_MODE \
1025 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1027 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1031 tmp
= ldtul_p(mem_buf
);
1034 env
->active_tc
.gpr
[n
] = tmp
;
1035 return sizeof(target_ulong
);
1037 if (env
->CP0_Config1
& (1 << CP0C1_FP
)
1038 && n
>= 38 && n
< 73) {
1040 if (env
->CP0_Status
& (1 << CP0St_FR
))
1041 env
->active_fpu
.fpr
[n
- 38].d
= tmp
;
1043 env
->active_fpu
.fpr
[n
- 38].w
[FP_ENDIAN_IDX
] = tmp
;
1047 env
->active_fpu
.fcr31
= tmp
& 0xFF83FFFF;
1048 /* set rounding mode */
1049 RESTORE_ROUNDING_MODE
;
1050 #ifndef CONFIG_SOFTFLOAT
1051 /* no floating point exception for native float */
1052 SET_FP_ENABLE(env
->active_fpu
.fcr31
, 0);
1055 case 71: env
->active_fpu
.fcr0
= tmp
; break;
1057 return sizeof(target_ulong
);
1060 case 32: env
->CP0_Status
= tmp
; break;
1061 case 33: env
->active_tc
.LO
[0] = tmp
; break;
1062 case 34: env
->active_tc
.HI
[0] = tmp
; break;
1063 case 35: env
->CP0_BadVAddr
= tmp
; break;
1064 case 36: env
->CP0_Cause
= tmp
; break;
1065 case 37: env
->active_tc
.PC
= tmp
; break;
1066 case 72: /* fp, ignored */ break;
1070 /* Other registers are readonly. Ignore writes. */
1074 return sizeof(target_ulong
);
1076 #elif defined (TARGET_SH4)
1078 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
1079 /* FIXME: We should use XML for this. */
1081 #define NUM_CORE_REGS 59
1083 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1086 if ((env
->sr
& (SR_MD
| SR_RB
)) == (SR_MD
| SR_RB
)) {
1087 GET_REGL(env
->gregs
[n
+ 16]);
1089 GET_REGL(env
->gregs
[n
]);
1091 } else if (n
< 16) {
1092 GET_REGL(env
->gregs
[n
- 8]);
1093 } else if (n
>= 25 && n
< 41) {
1094 GET_REGL(env
->fregs
[(n
- 25) + ((env
->fpscr
& FPSCR_FR
) ? 16 : 0)]);
1095 } else if (n
>= 43 && n
< 51) {
1096 GET_REGL(env
->gregs
[n
- 43]);
1097 } else if (n
>= 51 && n
< 59) {
1098 GET_REGL(env
->gregs
[n
- (51 - 16)]);
1101 case 16: GET_REGL(env
->pc
);
1102 case 17: GET_REGL(env
->pr
);
1103 case 18: GET_REGL(env
->gbr
);
1104 case 19: GET_REGL(env
->vbr
);
1105 case 20: GET_REGL(env
->mach
);
1106 case 21: GET_REGL(env
->macl
);
1107 case 22: GET_REGL(env
->sr
);
1108 case 23: GET_REGL(env
->fpul
);
1109 case 24: GET_REGL(env
->fpscr
);
1110 case 41: GET_REGL(env
->ssr
);
1111 case 42: GET_REGL(env
->spc
);
1117 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1121 tmp
= ldl_p(mem_buf
);
1124 if ((env
->sr
& (SR_MD
| SR_RB
)) == (SR_MD
| SR_RB
)) {
1125 env
->gregs
[n
+ 16] = tmp
;
1127 env
->gregs
[n
] = tmp
;
1130 } else if (n
< 16) {
1131 env
->gregs
[n
- 8] = tmp
;
1133 } else if (n
>= 25 && n
< 41) {
1134 env
->fregs
[(n
- 25) + ((env
->fpscr
& FPSCR_FR
) ? 16 : 0)] = tmp
;
1135 } else if (n
>= 43 && n
< 51) {
1136 env
->gregs
[n
- 43] = tmp
;
1138 } else if (n
>= 51 && n
< 59) {
1139 env
->gregs
[n
- (51 - 16)] = tmp
;
1143 case 16: env
->pc
= tmp
;
1144 case 17: env
->pr
= tmp
;
1145 case 18: env
->gbr
= tmp
;
1146 case 19: env
->vbr
= tmp
;
1147 case 20: env
->mach
= tmp
;
1148 case 21: env
->macl
= tmp
;
1149 case 22: env
->sr
= tmp
;
1150 case 23: env
->fpul
= tmp
;
1151 case 24: env
->fpscr
= tmp
;
1152 case 41: env
->ssr
= tmp
;
1153 case 42: env
->spc
= tmp
;
1159 #elif defined (TARGET_MICROBLAZE)
1161 #define NUM_CORE_REGS (32 + 5)
1163 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1166 GET_REG32(env
->regs
[n
]);
1168 GET_REG32(env
->sregs
[n
- 32]);
1173 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1177 if (n
> NUM_CORE_REGS
)
1180 tmp
= ldl_p(mem_buf
);
1185 env
->sregs
[n
- 32] = tmp
;
1189 #elif defined (TARGET_CRIS)
1191 #define NUM_CORE_REGS 49
1193 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1197 srs
= env
->pregs
[PR_SRS
];
1199 GET_REG32(env
->regs
[n
]);
1202 if (n
>= 21 && n
< 32) {
1203 GET_REG32(env
->pregs
[n
- 16]);
1205 if (n
>= 33 && n
< 49) {
1206 GET_REG32(env
->sregs
[srs
][n
- 33]);
1209 case 16: GET_REG8(env
->pregs
[0]);
1210 case 17: GET_REG8(env
->pregs
[1]);
1211 case 18: GET_REG32(env
->pregs
[2]);
1212 case 19: GET_REG8(srs
);
1213 case 20: GET_REG16(env
->pregs
[4]);
1214 case 32: GET_REG32(env
->pc
);
1220 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1227 tmp
= ldl_p(mem_buf
);
1233 if (n
>= 21 && n
< 32) {
1234 env
->pregs
[n
- 16] = tmp
;
1237 /* FIXME: Should support function regs be writable? */
1241 case 18: env
->pregs
[PR_PID
] = tmp
; break;
1244 case 32: env
->pc
= tmp
; break;
1249 #elif defined (TARGET_ALPHA)
1251 #define NUM_CORE_REGS 65
1253 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1256 GET_REGL(env
->ir
[n
]);
1264 val
=*((uint64_t *)&env
->fir
[n
-32]);
1268 GET_REGL(env
->fpcr
);
1280 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1283 tmp
= ldtul_p(mem_buf
);
1289 if (n
> 31 && n
< 63) {
1290 env
->fir
[n
- 32] = ldfl_p(mem_buf
);
1301 #define NUM_CORE_REGS 0
1303 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1308 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1315 static int num_g_regs
= NUM_CORE_REGS
;
1318 /* Encode data using the encoding for 'x' packets. */
1319 static int memtox(char *buf
, const char *mem
, int len
)
1327 case '#': case '$': case '*': case '}':
1339 static const char *get_feature_xml(const char *p
, const char **newp
)
1341 extern const char *const xml_builtin
[][2];
1345 static char target_xml
[1024];
1348 while (p
[len
] && p
[len
] != ':')
1353 if (strncmp(p
, "target.xml", len
) == 0) {
1354 /* Generate the XML description for this CPU. */
1355 if (!target_xml
[0]) {
1356 GDBRegisterState
*r
;
1358 snprintf(target_xml
, sizeof(target_xml
),
1359 "<?xml version=\"1.0\"?>"
1360 "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1362 "<xi:include href=\"%s\"/>",
1365 for (r
= first_cpu
->gdb_regs
; r
; r
= r
->next
) {
1366 pstrcat(target_xml
, sizeof(target_xml
), "<xi:include href=\"");
1367 pstrcat(target_xml
, sizeof(target_xml
), r
->xml
);
1368 pstrcat(target_xml
, sizeof(target_xml
), "\"/>");
1370 pstrcat(target_xml
, sizeof(target_xml
), "</target>");
1374 for (i
= 0; ; i
++) {
1375 name
= xml_builtin
[i
][0];
1376 if (!name
|| (strncmp(name
, p
, len
) == 0 && strlen(name
) == len
))
1379 return name
? xml_builtin
[i
][1] : NULL
;
1383 static int gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int reg
)
1385 GDBRegisterState
*r
;
1387 if (reg
< NUM_CORE_REGS
)
1388 return cpu_gdb_read_register(env
, mem_buf
, reg
);
1390 for (r
= env
->gdb_regs
; r
; r
= r
->next
) {
1391 if (r
->base_reg
<= reg
&& reg
< r
->base_reg
+ r
->num_regs
) {
1392 return r
->get_reg(env
, mem_buf
, reg
- r
->base_reg
);
1398 static int gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int reg
)
1400 GDBRegisterState
*r
;
1402 if (reg
< NUM_CORE_REGS
)
1403 return cpu_gdb_write_register(env
, mem_buf
, reg
);
1405 for (r
= env
->gdb_regs
; r
; r
= r
->next
) {
1406 if (r
->base_reg
<= reg
&& reg
< r
->base_reg
+ r
->num_regs
) {
1407 return r
->set_reg(env
, mem_buf
, reg
- r
->base_reg
);
1413 /* Register a supplemental set of CPU registers. If g_pos is nonzero it
1414 specifies the first register number and these registers are included in
1415 a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
1416 gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1419 void gdb_register_coprocessor(CPUState
* env
,
1420 gdb_reg_cb get_reg
, gdb_reg_cb set_reg
,
1421 int num_regs
, const char *xml
, int g_pos
)
1423 GDBRegisterState
*s
;
1424 GDBRegisterState
**p
;
1425 static int last_reg
= NUM_CORE_REGS
;
1427 s
= (GDBRegisterState
*)qemu_mallocz(sizeof(GDBRegisterState
));
1428 s
->base_reg
= last_reg
;
1429 s
->num_regs
= num_regs
;
1430 s
->get_reg
= get_reg
;
1431 s
->set_reg
= set_reg
;
1435 /* Check for duplicates. */
1436 if (strcmp((*p
)->xml
, xml
) == 0)
1440 /* Add to end of list. */
1441 last_reg
+= num_regs
;
1444 if (g_pos
!= s
->base_reg
) {
1445 fprintf(stderr
, "Error: Bad gdb register numbering for '%s'\n"
1446 "Expected %d got %d\n", xml
, g_pos
, s
->base_reg
);
1448 num_g_regs
= last_reg
;
1453 #ifndef CONFIG_USER_ONLY
1454 static const int xlat_gdb_type
[] = {
1455 [GDB_WATCHPOINT_WRITE
] = BP_GDB
| BP_MEM_WRITE
,
1456 [GDB_WATCHPOINT_READ
] = BP_GDB
| BP_MEM_READ
,
1457 [GDB_WATCHPOINT_ACCESS
] = BP_GDB
| BP_MEM_ACCESS
,
1461 static int gdb_breakpoint_insert(target_ulong addr
, target_ulong len
, int type
)
1467 return kvm_insert_breakpoint(gdbserver_state
->c_cpu
, addr
, len
, type
);
1470 case GDB_BREAKPOINT_SW
:
1471 case GDB_BREAKPOINT_HW
:
1472 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1473 err
= cpu_breakpoint_insert(env
, addr
, BP_GDB
, NULL
);
1478 #ifndef CONFIG_USER_ONLY
1479 case GDB_WATCHPOINT_WRITE
:
1480 case GDB_WATCHPOINT_READ
:
1481 case GDB_WATCHPOINT_ACCESS
:
1482 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1483 err
= cpu_watchpoint_insert(env
, addr
, len
, xlat_gdb_type
[type
],
1495 static int gdb_breakpoint_remove(target_ulong addr
, target_ulong len
, int type
)
1501 return kvm_remove_breakpoint(gdbserver_state
->c_cpu
, addr
, len
, type
);
1504 case GDB_BREAKPOINT_SW
:
1505 case GDB_BREAKPOINT_HW
:
1506 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1507 err
= cpu_breakpoint_remove(env
, addr
, BP_GDB
);
1512 #ifndef CONFIG_USER_ONLY
1513 case GDB_WATCHPOINT_WRITE
:
1514 case GDB_WATCHPOINT_READ
:
1515 case GDB_WATCHPOINT_ACCESS
:
1516 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1517 err
= cpu_watchpoint_remove(env
, addr
, len
, xlat_gdb_type
[type
]);
1528 static void gdb_breakpoint_remove_all(void)
1532 if (kvm_enabled()) {
1533 kvm_remove_all_breakpoints(gdbserver_state
->c_cpu
);
1537 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1538 cpu_breakpoint_remove_all(env
, BP_GDB
);
1539 #ifndef CONFIG_USER_ONLY
1540 cpu_watchpoint_remove_all(env
, BP_GDB
);
1545 static void gdb_set_cpu_pc(GDBState
*s
, target_ulong pc
)
1547 #if defined(TARGET_I386)
1549 cpu_synchronize_state(s
->c_cpu
, 1);
1550 #elif defined (TARGET_PPC)
1552 #elif defined (TARGET_SPARC)
1554 s
->c_cpu
->npc
= pc
+ 4;
1555 #elif defined (TARGET_ARM)
1556 s
->c_cpu
->regs
[15] = pc
;
1557 #elif defined (TARGET_SH4)
1559 #elif defined (TARGET_MIPS)
1560 s
->c_cpu
->active_tc
.PC
= pc
;
1561 #elif defined (TARGET_MICROBLAZE)
1562 s
->c_cpu
->sregs
[SR_PC
] = pc
;
1563 #elif defined (TARGET_CRIS)
1565 #elif defined (TARGET_ALPHA)
1570 static inline int gdb_id(CPUState
*env
)
1572 #if defined(CONFIG_USER_ONLY) && defined(USE_NPTL)
1573 return env
->host_tid
;
1575 return env
->cpu_index
+ 1;
1579 static CPUState
*find_cpu(uint32_t thread_id
)
1583 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1584 if (gdb_id(env
) == thread_id
) {
1592 static int gdb_handle_packet(GDBState
*s
, const char *line_buf
)
1597 int ch
, reg_size
, type
, res
;
1598 char buf
[MAX_PACKET_LENGTH
];
1599 uint8_t mem_buf
[MAX_PACKET_LENGTH
];
1601 target_ulong addr
, len
;
1604 printf("command='%s'\n", line_buf
);
1610 /* TODO: Make this return the correct value for user-mode. */
1611 snprintf(buf
, sizeof(buf
), "T%02xthread:%02x;", GDB_SIGNAL_TRAP
,
1614 /* Remove all the breakpoints when this query is issued,
1615 * because gdb is doing and initial connect and the state
1616 * should be cleaned up.
1618 gdb_breakpoint_remove_all();
1622 addr
= strtoull(p
, (char **)&p
, 16);
1623 gdb_set_cpu_pc(s
, addr
);
1629 s
->signal
= gdb_signal_to_target (strtoul(p
, (char **)&p
, 16));
1630 if (s
->signal
== -1)
1635 /* Kill the target */
1636 fprintf(stderr
, "\nQEMU: Terminated via GDBstub\n");
1640 gdb_breakpoint_remove_all();
1642 put_packet(s
, "OK");
1646 addr
= strtoull(p
, (char **)&p
, 16);
1647 gdb_set_cpu_pc(s
, addr
);
1649 cpu_single_step(s
->c_cpu
, sstep_flags
);
1657 ret
= strtoull(p
, (char **)&p
, 16);
1660 err
= strtoull(p
, (char **)&p
, 16);
1667 if (gdb_current_syscall_cb
)
1668 gdb_current_syscall_cb(s
->c_cpu
, ret
, err
);
1670 put_packet(s
, "T02");
1677 cpu_synchronize_state(s
->g_cpu
, 0);
1679 for (addr
= 0; addr
< num_g_regs
; addr
++) {
1680 reg_size
= gdb_read_register(s
->g_cpu
, mem_buf
+ len
, addr
);
1683 memtohex(buf
, mem_buf
, len
);
1687 registers
= mem_buf
;
1688 len
= strlen(p
) / 2;
1689 hextomem((uint8_t *)registers
, p
, len
);
1690 for (addr
= 0; addr
< num_g_regs
&& len
> 0; addr
++) {
1691 reg_size
= gdb_write_register(s
->g_cpu
, registers
, addr
);
1693 registers
+= reg_size
;
1695 cpu_synchronize_state(s
->g_cpu
, 1);
1696 put_packet(s
, "OK");
1699 addr
= strtoull(p
, (char **)&p
, 16);
1702 len
= strtoull(p
, NULL
, 16);
1703 if (cpu_memory_rw_debug(s
->g_cpu
, addr
, mem_buf
, len
, 0) != 0) {
1704 put_packet (s
, "E14");
1706 memtohex(buf
, mem_buf
, len
);
1711 addr
= strtoull(p
, (char **)&p
, 16);
1714 len
= strtoull(p
, (char **)&p
, 16);
1717 hextomem(mem_buf
, p
, len
);
1718 if (cpu_memory_rw_debug(s
->g_cpu
, addr
, mem_buf
, len
, 1) != 0)
1719 put_packet(s
, "E14");
1721 put_packet(s
, "OK");
1724 /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
1725 This works, but can be very slow. Anything new enough to
1726 understand XML also knows how to use this properly. */
1728 goto unknown_command
;
1729 addr
= strtoull(p
, (char **)&p
, 16);
1730 reg_size
= gdb_read_register(s
->g_cpu
, mem_buf
, addr
);
1732 memtohex(buf
, mem_buf
, reg_size
);
1735 put_packet(s
, "E14");
1740 goto unknown_command
;
1741 addr
= strtoull(p
, (char **)&p
, 16);
1744 reg_size
= strlen(p
) / 2;
1745 hextomem(mem_buf
, p
, reg_size
);
1746 gdb_write_register(s
->g_cpu
, mem_buf
, addr
);
1747 put_packet(s
, "OK");
1751 type
= strtoul(p
, (char **)&p
, 16);
1754 addr
= strtoull(p
, (char **)&p
, 16);
1757 len
= strtoull(p
, (char **)&p
, 16);
1759 res
= gdb_breakpoint_insert(addr
, len
, type
);
1761 res
= gdb_breakpoint_remove(addr
, len
, type
);
1763 put_packet(s
, "OK");
1764 else if (res
== -ENOSYS
)
1767 put_packet(s
, "E22");
1771 thread
= strtoull(p
, (char **)&p
, 16);
1772 if (thread
== -1 || thread
== 0) {
1773 put_packet(s
, "OK");
1776 env
= find_cpu(thread
);
1778 put_packet(s
, "E22");
1784 put_packet(s
, "OK");
1788 put_packet(s
, "OK");
1791 put_packet(s
, "E22");
1796 thread
= strtoull(p
, (char **)&p
, 16);
1797 env
= find_cpu(thread
);
1800 put_packet(s
, "OK");
1802 put_packet(s
, "E22");
1807 /* parse any 'q' packets here */
1808 if (!strcmp(p
,"qemu.sstepbits")) {
1809 /* Query Breakpoint bit definitions */
1810 snprintf(buf
, sizeof(buf
), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1816 } else if (strncmp(p
,"qemu.sstep",10) == 0) {
1817 /* Display or change the sstep_flags */
1820 /* Display current setting */
1821 snprintf(buf
, sizeof(buf
), "0x%x", sstep_flags
);
1826 type
= strtoul(p
, (char **)&p
, 16);
1828 put_packet(s
, "OK");
1830 } else if (strcmp(p
,"C") == 0) {
1831 /* "Current thread" remains vague in the spec, so always return
1832 * the first CPU (gdb returns the first thread). */
1833 put_packet(s
, "QC1");
1835 } else if (strcmp(p
,"fThreadInfo") == 0) {
1836 s
->query_cpu
= first_cpu
;
1837 goto report_cpuinfo
;
1838 } else if (strcmp(p
,"sThreadInfo") == 0) {
1841 snprintf(buf
, sizeof(buf
), "m%x", gdb_id(s
->query_cpu
));
1843 s
->query_cpu
= s
->query_cpu
->next_cpu
;
1847 } else if (strncmp(p
,"ThreadExtraInfo,", 16) == 0) {
1848 thread
= strtoull(p
+16, (char **)&p
, 16);
1849 env
= find_cpu(thread
);
1851 cpu_synchronize_state(env
, 0);
1852 len
= snprintf((char *)mem_buf
, sizeof(mem_buf
),
1853 "CPU#%d [%s]", env
->cpu_index
,
1854 env
->halted
? "halted " : "running");
1855 memtohex(buf
, mem_buf
, len
);
1860 #ifdef CONFIG_USER_ONLY
1861 else if (strncmp(p
, "Offsets", 7) == 0) {
1862 TaskState
*ts
= s
->c_cpu
->opaque
;
1864 snprintf(buf
, sizeof(buf
),
1865 "Text=" TARGET_ABI_FMT_lx
";Data=" TARGET_ABI_FMT_lx
1866 ";Bss=" TARGET_ABI_FMT_lx
,
1867 ts
->info
->code_offset
,
1868 ts
->info
->data_offset
,
1869 ts
->info
->data_offset
);
1873 #else /* !CONFIG_USER_ONLY */
1874 else if (strncmp(p
, "Rcmd,", 5) == 0) {
1875 int len
= strlen(p
+ 5);
1877 if ((len
% 2) != 0) {
1878 put_packet(s
, "E01");
1881 hextomem(mem_buf
, p
+ 5, len
);
1884 qemu_chr_read(s
->mon_chr
, mem_buf
, len
);
1885 put_packet(s
, "OK");
1888 #endif /* !CONFIG_USER_ONLY */
1889 if (strncmp(p
, "Supported", 9) == 0) {
1890 snprintf(buf
, sizeof(buf
), "PacketSize=%x", MAX_PACKET_LENGTH
);
1892 pstrcat(buf
, sizeof(buf
), ";qXfer:features:read+");
1898 if (strncmp(p
, "Xfer:features:read:", 19) == 0) {
1900 target_ulong total_len
;
1904 xml
= get_feature_xml(p
, &p
);
1906 snprintf(buf
, sizeof(buf
), "E00");
1913 addr
= strtoul(p
, (char **)&p
, 16);
1916 len
= strtoul(p
, (char **)&p
, 16);
1918 total_len
= strlen(xml
);
1919 if (addr
> total_len
) {
1920 snprintf(buf
, sizeof(buf
), "E00");
1924 if (len
> (MAX_PACKET_LENGTH
- 5) / 2)
1925 len
= (MAX_PACKET_LENGTH
- 5) / 2;
1926 if (len
< total_len
- addr
) {
1928 len
= memtox(buf
+ 1, xml
+ addr
, len
);
1931 len
= memtox(buf
+ 1, xml
+ addr
, total_len
- addr
);
1933 put_packet_binary(s
, buf
, len
+ 1);
1937 /* Unrecognised 'q' command. */
1938 goto unknown_command
;
1942 /* put empty packet */
1950 void gdb_set_stop_cpu(CPUState
*env
)
1952 gdbserver_state
->c_cpu
= env
;
1953 gdbserver_state
->g_cpu
= env
;
1956 #ifndef CONFIG_USER_ONLY
1957 static void gdb_vm_state_change(void *opaque
, int running
, int reason
)
1959 GDBState
*s
= gdbserver_state
;
1960 CPUState
*env
= s
->c_cpu
;
1965 if (running
|| (reason
!= EXCP_DEBUG
&& reason
!= EXCP_INTERRUPT
) ||
1966 s
->state
== RS_INACTIVE
|| s
->state
== RS_SYSCALL
)
1969 /* disable single step if it was enable */
1970 cpu_single_step(env
, 0);
1972 if (reason
== EXCP_DEBUG
) {
1973 if (env
->watchpoint_hit
) {
1974 switch (env
->watchpoint_hit
->flags
& BP_MEM_ACCESS
) {
1985 snprintf(buf
, sizeof(buf
),
1986 "T%02xthread:%02x;%swatch:" TARGET_FMT_lx
";",
1987 GDB_SIGNAL_TRAP
, gdb_id(env
), type
,
1988 env
->watchpoint_hit
->vaddr
);
1990 env
->watchpoint_hit
= NULL
;
1994 ret
= GDB_SIGNAL_TRAP
;
1996 ret
= GDB_SIGNAL_INT
;
1998 snprintf(buf
, sizeof(buf
), "T%02xthread:%02x;", ret
, gdb_id(env
));
2003 /* Send a gdb syscall request.
2004 This accepts limited printf-style format specifiers, specifically:
2005 %x - target_ulong argument printed in hex.
2006 %lx - 64-bit argument printed in hex.
2007 %s - string pointer (target_ulong) and length (int) pair. */
2008 void gdb_do_syscall(gdb_syscall_complete_cb cb
, const char *fmt
, ...)
2017 s
= gdbserver_state
;
2020 gdb_current_syscall_cb
= cb
;
2021 s
->state
= RS_SYSCALL
;
2022 #ifndef CONFIG_USER_ONLY
2023 vm_stop(EXCP_DEBUG
);
2034 addr
= va_arg(va
, target_ulong
);
2035 p
+= snprintf(p
, &buf
[sizeof(buf
)] - p
, TARGET_FMT_lx
, addr
);
2038 if (*(fmt
++) != 'x')
2040 i64
= va_arg(va
, uint64_t);
2041 p
+= snprintf(p
, &buf
[sizeof(buf
)] - p
, "%" PRIx64
, i64
);
2044 addr
= va_arg(va
, target_ulong
);
2045 p
+= snprintf(p
, &buf
[sizeof(buf
)] - p
, TARGET_FMT_lx
"/%x",
2046 addr
, va_arg(va
, int));
2050 fprintf(stderr
, "gdbstub: Bad syscall format string '%s'\n",
2061 #ifdef CONFIG_USER_ONLY
2062 gdb_handlesig(s
->c_cpu
, 0);
2068 static void gdb_read_byte(GDBState
*s
, int ch
)
2073 #ifndef CONFIG_USER_ONLY
2074 if (s
->last_packet_len
) {
2075 /* Waiting for a response to the last packet. If we see the start
2076 of a new command then abandon the previous response. */
2079 printf("Got NACK, retransmitting\n");
2081 put_buffer(s
, (uint8_t *)s
->last_packet
, s
->last_packet_len
);
2085 printf("Got ACK\n");
2087 printf("Got '%c' when expecting ACK/NACK\n", ch
);
2089 if (ch
== '+' || ch
== '$')
2090 s
->last_packet_len
= 0;
2095 /* when the CPU is running, we cannot do anything except stop
2096 it when receiving a char */
2097 vm_stop(EXCP_INTERRUPT
);
2104 s
->line_buf_index
= 0;
2105 s
->state
= RS_GETLINE
;
2110 s
->state
= RS_CHKSUM1
;
2111 } else if (s
->line_buf_index
>= sizeof(s
->line_buf
) - 1) {
2114 s
->line_buf
[s
->line_buf_index
++] = ch
;
2118 s
->line_buf
[s
->line_buf_index
] = '\0';
2119 s
->line_csum
= fromhex(ch
) << 4;
2120 s
->state
= RS_CHKSUM2
;
2123 s
->line_csum
|= fromhex(ch
);
2125 for(i
= 0; i
< s
->line_buf_index
; i
++) {
2126 csum
+= s
->line_buf
[i
];
2128 if (s
->line_csum
!= (csum
& 0xff)) {
2130 put_buffer(s
, &reply
, 1);
2134 put_buffer(s
, &reply
, 1);
2135 s
->state
= gdb_handle_packet(s
, s
->line_buf
);
2144 #ifdef CONFIG_USER_ONLY
2150 s
= gdbserver_state
;
2152 if (gdbserver_fd
< 0 || s
->fd
< 0)
2159 gdb_handlesig (CPUState
*env
, int sig
)
2165 s
= gdbserver_state
;
2166 if (gdbserver_fd
< 0 || s
->fd
< 0)
2169 /* disable single step if it was enabled */
2170 cpu_single_step(env
, 0);
2175 snprintf(buf
, sizeof(buf
), "S%02x", target_signal_to_gdb (sig
));
2178 /* put_packet() might have detected that the peer terminated the
2185 s
->running_state
= 0;
2186 while (s
->running_state
== 0) {
2187 n
= read (s
->fd
, buf
, 256);
2192 for (i
= 0; i
< n
; i
++)
2193 gdb_read_byte (s
, buf
[i
]);
2195 else if (n
== 0 || errno
!= EAGAIN
)
2197 /* XXX: Connection closed. Should probably wait for annother
2198 connection before continuing. */
2207 /* Tell the remote gdb that the process has exited. */
2208 void gdb_exit(CPUState
*env
, int code
)
2213 s
= gdbserver_state
;
2214 if (gdbserver_fd
< 0 || s
->fd
< 0)
2217 snprintf(buf
, sizeof(buf
), "W%02x", code
);
2221 /* Tell the remote gdb that the process has exited due to SIG. */
2222 void gdb_signalled(CPUState
*env
, int sig
)
2227 s
= gdbserver_state
;
2228 if (gdbserver_fd
< 0 || s
->fd
< 0)
2231 snprintf(buf
, sizeof(buf
), "X%02x", target_signal_to_gdb (sig
));
2235 static void gdb_accept(void)
2238 struct sockaddr_in sockaddr
;
2243 len
= sizeof(sockaddr
);
2244 fd
= accept(gdbserver_fd
, (struct sockaddr
*)&sockaddr
, &len
);
2245 if (fd
< 0 && errno
!= EINTR
) {
2248 } else if (fd
>= 0) {
2253 /* set short latency */
2255 setsockopt(fd
, IPPROTO_TCP
, TCP_NODELAY
, (char *)&val
, sizeof(val
));
2257 s
= qemu_mallocz(sizeof(GDBState
));
2258 s
->c_cpu
= first_cpu
;
2259 s
->g_cpu
= first_cpu
;
2263 gdbserver_state
= s
;
2265 fcntl(fd
, F_SETFL
, O_NONBLOCK
);
2268 static int gdbserver_open(int port
)
2270 struct sockaddr_in sockaddr
;
2273 fd
= socket(PF_INET
, SOCK_STREAM
, 0);
2279 /* allow fast reuse */
2281 setsockopt(fd
, SOL_SOCKET
, SO_REUSEADDR
, (char *)&val
, sizeof(val
));
2283 sockaddr
.sin_family
= AF_INET
;
2284 sockaddr
.sin_port
= htons(port
);
2285 sockaddr
.sin_addr
.s_addr
= 0;
2286 ret
= bind(fd
, (struct sockaddr
*)&sockaddr
, sizeof(sockaddr
));
2291 ret
= listen(fd
, 0);
2299 int gdbserver_start(int port
)
2301 gdbserver_fd
= gdbserver_open(port
);
2302 if (gdbserver_fd
< 0)
2304 /* accept connections */
2309 /* Disable gdb stub for child processes. */
2310 void gdbserver_fork(CPUState
*env
)
2312 GDBState
*s
= gdbserver_state
;
2313 if (gdbserver_fd
< 0 || s
->fd
< 0)
2317 cpu_breakpoint_remove_all(env
, BP_GDB
);
2318 cpu_watchpoint_remove_all(env
, BP_GDB
);
2321 static int gdb_chr_can_receive(void *opaque
)
2323 /* We can handle an arbitrarily large amount of data.
2324 Pick the maximum packet size, which is as good as anything. */
2325 return MAX_PACKET_LENGTH
;
2328 static void gdb_chr_receive(void *opaque
, const uint8_t *buf
, int size
)
2332 for (i
= 0; i
< size
; i
++) {
2333 gdb_read_byte(gdbserver_state
, buf
[i
]);
2337 static void gdb_chr_event(void *opaque
, int event
)
2340 case CHR_EVENT_RESET
:
2341 vm_stop(EXCP_INTERRUPT
);
2349 static void gdb_monitor_output(GDBState
*s
, const char *msg
, int len
)
2351 char buf
[MAX_PACKET_LENGTH
];
2354 if (len
> (MAX_PACKET_LENGTH
/2) - 1)
2355 len
= (MAX_PACKET_LENGTH
/2) - 1;
2356 memtohex(buf
+ 1, (uint8_t *)msg
, len
);
2360 static int gdb_monitor_write(CharDriverState
*chr
, const uint8_t *buf
, int len
)
2362 const char *p
= (const char *)buf
;
2365 max_sz
= (sizeof(gdbserver_state
->last_packet
) - 2) / 2;
2367 if (len
<= max_sz
) {
2368 gdb_monitor_output(gdbserver_state
, p
, len
);
2371 gdb_monitor_output(gdbserver_state
, p
, max_sz
);
2379 static void gdb_sigterm_handler(int signal
)
2382 vm_stop(EXCP_INTERRUPT
);
2386 int gdbserver_start(const char *device
)
2389 char gdbstub_device_name
[128];
2390 CharDriverState
*chr
= NULL
;
2391 CharDriverState
*mon_chr
;
2395 if (strcmp(device
, "none") != 0) {
2396 if (strstart(device
, "tcp:", NULL
)) {
2397 /* enforce required TCP attributes */
2398 snprintf(gdbstub_device_name
, sizeof(gdbstub_device_name
),
2399 "%s,nowait,nodelay,server", device
);
2400 device
= gdbstub_device_name
;
2403 else if (strcmp(device
, "stdio") == 0) {
2404 struct sigaction act
;
2406 memset(&act
, 0, sizeof(act
));
2407 act
.sa_handler
= gdb_sigterm_handler
;
2408 sigaction(SIGINT
, &act
, NULL
);
2411 chr
= qemu_chr_open("gdb", device
, NULL
);
2415 qemu_chr_add_handlers(chr
, gdb_chr_can_receive
, gdb_chr_receive
,
2416 gdb_chr_event
, NULL
);
2419 s
= gdbserver_state
;
2421 s
= qemu_mallocz(sizeof(GDBState
));
2422 gdbserver_state
= s
;
2424 qemu_add_vm_change_state_handler(gdb_vm_state_change
, NULL
);
2426 /* Initialize a monitor terminal for gdb */
2427 mon_chr
= qemu_mallocz(sizeof(*mon_chr
));
2428 mon_chr
->chr_write
= gdb_monitor_write
;
2429 monitor_init(mon_chr
, 0);
2432 qemu_chr_close(s
->chr
);
2433 mon_chr
= s
->mon_chr
;
2434 memset(s
, 0, sizeof(GDBState
));
2436 s
->c_cpu
= first_cpu
;
2437 s
->g_cpu
= first_cpu
;
2439 s
->state
= chr
? RS_IDLE
: RS_INACTIVE
;
2440 s
->mon_chr
= mon_chr
;