2 * internal execution defines for qemu
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
24 #include "qemu-common.h"
26 /* allow to see translation results - the slowdown should be negligible, so we leave it */
29 /* is_jmp field values */
30 #define DISAS_NEXT 0 /* next instruction can be analyzed */
31 #define DISAS_JUMP 1 /* only pc was modified dynamically */
32 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
33 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
35 typedef struct TranslationBlock TranslationBlock
;
37 /* XXX: make safe guess about sizes */
38 #define MAX_OP_PER_INSTR 64
39 /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
40 #define MAX_OPC_PARAM 10
41 #define OPC_BUF_SIZE 512
42 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
44 /* Maximum size a TCG op can expand to. This is complicated because a
45 single op may require several host instructions and regirster reloads.
46 For now take a wild guess at 128 bytes, which should allow at least
47 a couple of fixup instructions per argument. */
48 #define TCG_MAX_OP_SIZE 128
50 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
52 extern target_ulong gen_opc_pc
[OPC_BUF_SIZE
];
53 extern target_ulong gen_opc_npc
[OPC_BUF_SIZE
];
54 extern uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
55 extern uint8_t gen_opc_instr_start
[OPC_BUF_SIZE
];
56 extern uint16_t gen_opc_icount
[OPC_BUF_SIZE
];
57 extern target_ulong gen_opc_jump_pc
[2];
58 extern uint32_t gen_opc_hflags
[OPC_BUF_SIZE
];
62 void gen_intermediate_code(CPUState
*env
, struct TranslationBlock
*tb
);
63 void gen_intermediate_code_pc(CPUState
*env
, struct TranslationBlock
*tb
);
64 void gen_pc_load(CPUState
*env
, struct TranslationBlock
*tb
,
65 unsigned long searched_pc
, int pc_pos
, void *puc
);
67 unsigned long code_gen_max_block_size(void);
68 void cpu_gen_init(void);
69 int cpu_gen_code(CPUState
*env
, struct TranslationBlock
*tb
,
70 int *gen_code_size_ptr
);
71 int cpu_restore_state(struct TranslationBlock
*tb
,
72 CPUState
*env
, unsigned long searched_pc
,
74 int cpu_restore_state_copy(struct TranslationBlock
*tb
,
75 CPUState
*env
, unsigned long searched_pc
,
77 void cpu_resume_from_signal(CPUState
*env1
, void *puc
);
78 void cpu_io_recompile(CPUState
*env
, void *retaddr
);
79 TranslationBlock
*tb_gen_code(CPUState
*env
,
80 target_ulong pc
, target_ulong cs_base
, int flags
,
82 void cpu_exec_init(CPUState
*env
);
83 void QEMU_NORETURN
cpu_loop_exit(void);
84 int page_unprotect(target_ulong address
, unsigned long pc
, void *puc
);
85 void tb_invalidate_phys_page_range(target_phys_addr_t start
, target_phys_addr_t end
,
86 int is_cpu_write_access
);
87 void tb_invalidate_page_range(target_ulong start
, target_ulong end
);
88 void tlb_flush_page(CPUState
*env
, target_ulong addr
);
89 void tlb_flush(CPUState
*env
, int flush_global
);
90 int tlb_set_page_exec(CPUState
*env
, target_ulong vaddr
,
91 target_phys_addr_t paddr
, int prot
,
92 int mmu_idx
, int is_softmmu
);
93 static inline int tlb_set_page(CPUState
*env1
, target_ulong vaddr
,
94 target_phys_addr_t paddr
, int prot
,
95 int mmu_idx
, int is_softmmu
)
99 return tlb_set_page_exec(env1
, vaddr
, paddr
, prot
, mmu_idx
, is_softmmu
);
102 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
104 #define CODE_GEN_PHYS_HASH_BITS 15
105 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
107 #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
109 /* estimated block size for TB allocation */
110 /* XXX: use a per code average code fragment size and modulate it
111 according to the host CPU */
112 #if defined(CONFIG_SOFTMMU)
113 #define CODE_GEN_AVG_BLOCK_SIZE 128
115 #define CODE_GEN_AVG_BLOCK_SIZE 64
118 #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__)
119 #define USE_DIRECT_JUMP
121 #if defined(__i386__) && !defined(_WIN32)
122 #define USE_DIRECT_JUMP
125 struct TranslationBlock
{
126 target_ulong pc
; /* simulated PC corresponding to this block (EIP + CS base) */
127 target_ulong cs_base
; /* CS base for this block */
128 uint64_t flags
; /* flags defining in which context the code was generated */
129 uint16_t size
; /* size of target code for this block (1 <=
130 size <= TARGET_PAGE_SIZE) */
131 uint16_t cflags
; /* compile flags */
132 #define CF_COUNT_MASK 0x7fff
133 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
135 uint8_t *tc_ptr
; /* pointer to the translated code */
136 /* next matching tb for physical address. */
137 struct TranslationBlock
*phys_hash_next
;
138 /* first and second physical page containing code. The lower bit
139 of the pointer tells the index in page_next[] */
140 struct TranslationBlock
*page_next
[2];
141 target_ulong page_addr
[2];
143 /* the following data are used to directly call another TB from
144 the code of this one. */
145 uint16_t tb_next_offset
[2]; /* offset of original jump target */
146 #ifdef USE_DIRECT_JUMP
147 uint16_t tb_jmp_offset
[4]; /* offset of jump instruction */
149 unsigned long tb_next
[2]; /* address of jump generated code */
151 /* list of TBs jumping to this one. This is a circular list using
152 the two least significant bits of the pointers to tell what is
153 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
155 struct TranslationBlock
*jmp_next
[2];
156 struct TranslationBlock
*jmp_first
;
160 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc
)
163 tmp
= pc
^ (pc
>> (TARGET_PAGE_BITS
- TB_JMP_PAGE_BITS
));
164 return (tmp
>> (TARGET_PAGE_BITS
- TB_JMP_PAGE_BITS
)) & TB_JMP_PAGE_MASK
;
167 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc
)
170 tmp
= pc
^ (pc
>> (TARGET_PAGE_BITS
- TB_JMP_PAGE_BITS
));
171 return (((tmp
>> (TARGET_PAGE_BITS
- TB_JMP_PAGE_BITS
)) & TB_JMP_PAGE_MASK
)
172 | (tmp
& TB_JMP_ADDR_MASK
));
175 static inline unsigned int tb_phys_hash_func(unsigned long pc
)
177 return pc
& (CODE_GEN_PHYS_HASH_SIZE
- 1);
180 TranslationBlock
*tb_alloc(target_ulong pc
);
181 void tb_free(TranslationBlock
*tb
);
182 void tb_flush(CPUState
*env
);
183 void tb_link_phys(TranslationBlock
*tb
,
184 target_ulong phys_pc
, target_ulong phys_page2
);
185 void tb_phys_invalidate(TranslationBlock
*tb
, target_ulong page_addr
);
187 extern TranslationBlock
*tb_phys_hash
[CODE_GEN_PHYS_HASH_SIZE
];
188 extern uint8_t *code_gen_ptr
;
189 extern int code_gen_max_blocks
;
191 #if defined(USE_DIRECT_JUMP)
193 #if defined(_ARCH_PPC)
194 extern void ppc_tb_set_jmp_target(unsigned long jmp_addr
, unsigned long addr
);
195 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
196 #elif defined(__i386__) || defined(__x86_64__)
197 static inline void tb_set_jmp_target1(unsigned long jmp_addr
, unsigned long addr
)
199 /* patch the branch destination */
200 *(uint32_t *)jmp_addr
= addr
- (jmp_addr
+ 4);
201 /* no need to flush icache explicitly */
203 #elif defined(__arm__)
204 static inline void tb_set_jmp_target1(unsigned long jmp_addr
, unsigned long addr
)
206 #if QEMU_GNUC_PREREQ(4, 1)
207 void __clear_cache(char *beg
, char *end
);
209 register unsigned long _beg
__asm ("a1");
210 register unsigned long _end
__asm ("a2");
211 register unsigned long _flg
__asm ("a3");
214 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
215 *(uint32_t *)jmp_addr
|= ((addr
- (jmp_addr
+ 8)) >> 2) & 0xffffff;
217 #if QEMU_GNUC_PREREQ(4, 1)
218 __clear_cache((char *) jmp_addr
, (char *) jmp_addr
+ 4);
224 __asm
__volatile__ ("swi 0x9f0002" : : "r" (_beg
), "r" (_end
), "r" (_flg
));
229 static inline void tb_set_jmp_target(TranslationBlock
*tb
,
230 int n
, unsigned long addr
)
232 unsigned long offset
;
234 offset
= tb
->tb_jmp_offset
[n
];
235 tb_set_jmp_target1((unsigned long)(tb
->tc_ptr
+ offset
), addr
);
236 offset
= tb
->tb_jmp_offset
[n
+ 2];
237 if (offset
!= 0xffff)
238 tb_set_jmp_target1((unsigned long)(tb
->tc_ptr
+ offset
), addr
);
243 /* set the jump target */
244 static inline void tb_set_jmp_target(TranslationBlock
*tb
,
245 int n
, unsigned long addr
)
247 tb
->tb_next
[n
] = addr
;
252 static inline void tb_add_jump(TranslationBlock
*tb
, int n
,
253 TranslationBlock
*tb_next
)
255 /* NOTE: this test is only needed for thread safety */
256 if (!tb
->jmp_next
[n
]) {
257 /* patch the native jump address */
258 tb_set_jmp_target(tb
, n
, (unsigned long)tb_next
->tc_ptr
);
260 /* add in TB jmp circular list */
261 tb
->jmp_next
[n
] = tb_next
->jmp_first
;
262 tb_next
->jmp_first
= (TranslationBlock
*)((long)(tb
) | (n
));
266 TranslationBlock
*tb_find_pc(unsigned long pc_ptr
);
268 extern CPUWriteMemoryFunc
*io_mem_write
[IO_MEM_NB_ENTRIES
][4];
269 extern CPUReadMemoryFunc
*io_mem_read
[IO_MEM_NB_ENTRIES
][4];
270 extern void *io_mem_opaque
[IO_MEM_NB_ENTRIES
];
272 #include "qemu-lock.h"
274 extern spinlock_t tb_lock
;
276 extern int tb_invalidated_flag
;
278 #if !defined(CONFIG_USER_ONLY)
280 void tlb_fill(target_ulong addr
, int is_write
, int mmu_idx
,
283 #include "softmmu_defs.h"
285 #define ACCESS_TYPE (NB_MMU_MODES + 1)
286 #define MEMSUFFIX _code
287 #define env cpu_single_env
290 #include "softmmu_header.h"
293 #include "softmmu_header.h"
296 #include "softmmu_header.h"
299 #include "softmmu_header.h"
307 #if defined(CONFIG_USER_ONLY)
308 static inline target_ulong
get_phys_addr_code(CPUState
*env1
, target_ulong addr
)
313 /* NOTE: this function can trigger an exception */
314 /* NOTE2: the returned address is not exactly the physical address: it
315 is the offset relative to phys_ram_base */
316 static inline target_ulong
get_phys_addr_code(CPUState
*env1
, target_ulong addr
)
318 int mmu_idx
, page_index
, pd
;
321 page_index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
322 mmu_idx
= cpu_mmu_index(env1
);
323 if (unlikely(env1
->tlb_table
[mmu_idx
][page_index
].addr_code
!=
324 (addr
& TARGET_PAGE_MASK
))) {
327 pd
= env1
->tlb_table
[mmu_idx
][page_index
].addr_code
& ~TARGET_PAGE_MASK
;
328 if (pd
> IO_MEM_ROM
&& !(pd
& IO_MEM_ROMD
)) {
329 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
330 do_unassigned_access(addr
, 0, 1, 0, 4);
332 cpu_abort(env1
, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx
"\n", addr
);
335 p
= (void *)(unsigned long)addr
336 + env1
->tlb_table
[mmu_idx
][page_index
].addend
;
337 return qemu_ram_addr_from_host(p
);
340 /* Deterministic execution requires that IO only be performed on the last
341 instruction of a TB so that interrupts take effect immediately. */
342 static inline int can_do_io(CPUState
*env
)
347 /* If not executing code then assume we are ok. */
348 if (!env
->current_tb
)
351 return env
->can_do_io
!= 0;
356 #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
358 #define MSR_QPI_COMMBASE 0xfabe0010
360 int kqemu_init(CPUState
*env
);
361 int kqemu_cpu_exec(CPUState
*env
);
362 void kqemu_flush_page(CPUState
*env
, target_ulong addr
);
363 void kqemu_flush(CPUState
*env
, int global
);
364 void kqemu_set_notdirty(CPUState
*env
, ram_addr_t ram_addr
);
365 void kqemu_modify_page(CPUState
*env
, ram_addr_t ram_addr
);
366 void kqemu_set_phys_mem(uint64_t start_addr
, ram_addr_t size
,
367 ram_addr_t phys_offset
);
368 void kqemu_cpu_interrupt(CPUState
*env
);
369 void kqemu_record_dump(void);
371 extern uint32_t kqemu_comm_base
;
373 extern ram_addr_t kqemu_phys_ram_size
;
374 extern uint8_t *kqemu_phys_ram_base
;
376 static inline int kqemu_is_ok(CPUState
*env
)
378 return(env
->kqemu_enabled
&&
379 (env
->cr
[0] & CR0_PE_MASK
) &&
380 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
) &&
381 (env
->eflags
& IF_MASK
) &&
382 !(env
->eflags
& VM_MASK
) &&
383 (env
->kqemu_enabled
== 2 ||
384 ((env
->hflags
& HF_CPL_MASK
) == 3 &&
385 (env
->eflags
& IOPL_MASK
) != IOPL_MASK
)));
390 typedef void (CPUDebugExcpHandler
)(CPUState
*env
);
392 CPUDebugExcpHandler
*cpu_set_debug_excp_handler(CPUDebugExcpHandler
*handler
);
395 extern int singlestep
;