4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "exec/helper-proto.h"
21 #include "internals.h"
22 #include "exec/cpu_ldst.h"
24 #define SIGNBIT (uint32_t)0x80000000
25 #define SIGNBIT64 ((uint64_t)1 << 63)
27 static void raise_exception(CPUARMState
*env
, int tt
)
29 ARMCPU
*cpu
= arm_env_get_cpu(env
);
30 CPUState
*cs
= CPU(cpu
);
32 cs
->exception_index
= tt
;
36 uint32_t HELPER(neon_tbl
)(CPUARMState
*env
, uint32_t ireg
, uint32_t def
,
37 uint32_t rn
, uint32_t maxindex
)
44 table
= (uint64_t *)&env
->vfp
.regs
[rn
];
46 for (shift
= 0; shift
< 32; shift
+= 8) {
47 index
= (ireg
>> shift
) & 0xff;
48 if (index
< maxindex
) {
49 tmp
= (table
[index
>> 3] >> ((index
& 7) << 3)) & 0xff;
52 val
|= def
& (0xff << shift
);
58 #if !defined(CONFIG_USER_ONLY)
60 /* try to fill the TLB and return an exception if error. If retaddr is
61 * NULL, it means that the function was called in C code (i.e. not
62 * from generated code or from helper.c)
64 void tlb_fill(CPUState
*cs
, target_ulong addr
, int is_write
, int mmu_idx
,
69 ret
= arm_cpu_handle_mmu_fault(cs
, addr
, is_write
, mmu_idx
);
71 ARMCPU
*cpu
= ARM_CPU(cs
);
72 CPUARMState
*env
= &cpu
->env
;
75 /* now we have a real cpu fault */
76 cpu_restore_state(cs
, retaddr
);
78 raise_exception(env
, cs
->exception_index
);
83 uint32_t HELPER(add_setq
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
86 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
))
91 uint32_t HELPER(add_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
94 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
)) {
96 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
101 uint32_t HELPER(sub_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
103 uint32_t res
= a
- b
;
104 if (((res
^ a
) & SIGNBIT
) && ((a
^ b
) & SIGNBIT
)) {
106 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
111 uint32_t HELPER(double_saturate
)(CPUARMState
*env
, int32_t val
)
114 if (val
>= 0x40000000) {
117 } else if (val
<= (int32_t)0xc0000000) {
126 uint32_t HELPER(add_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
128 uint32_t res
= a
+ b
;
136 uint32_t HELPER(sub_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
138 uint32_t res
= a
- b
;
146 /* Signed saturation. */
147 static inline uint32_t do_ssat(CPUARMState
*env
, int32_t val
, int shift
)
153 mask
= (1u << shift
) - 1;
157 } else if (top
< -1) {
164 /* Unsigned saturation. */
165 static inline uint32_t do_usat(CPUARMState
*env
, int32_t val
, int shift
)
169 max
= (1u << shift
) - 1;
173 } else if (val
> max
) {
180 /* Signed saturate. */
181 uint32_t HELPER(ssat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
183 return do_ssat(env
, x
, shift
);
186 /* Dual halfword signed saturate. */
187 uint32_t HELPER(ssat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
191 res
= (uint16_t)do_ssat(env
, (int16_t)x
, shift
);
192 res
|= do_ssat(env
, ((int32_t)x
) >> 16, shift
) << 16;
196 /* Unsigned saturate. */
197 uint32_t HELPER(usat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
199 return do_usat(env
, x
, shift
);
202 /* Dual halfword unsigned saturate. */
203 uint32_t HELPER(usat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
207 res
= (uint16_t)do_usat(env
, (int16_t)x
, shift
);
208 res
|= do_usat(env
, ((int32_t)x
) >> 16, shift
) << 16;
212 void HELPER(wfi
)(CPUARMState
*env
)
214 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
216 cs
->exception_index
= EXCP_HLT
;
221 void HELPER(wfe
)(CPUARMState
*env
)
223 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
225 /* Don't actually halt the CPU, just yield back to top
228 cs
->exception_index
= EXCP_YIELD
;
232 /* Raise an internal-to-QEMU exception. This is limited to only
233 * those EXCP values which are special cases for QEMU to interrupt
234 * execution and not to be used for exceptions which are passed to
235 * the guest (those must all have syndrome information and thus should
236 * use exception_with_syndrome).
238 void HELPER(exception_internal
)(CPUARMState
*env
, uint32_t excp
)
240 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
242 assert(excp_is_internal(excp
));
243 cs
->exception_index
= excp
;
247 /* Raise an exception with the specified syndrome register value */
248 void HELPER(exception_with_syndrome
)(CPUARMState
*env
, uint32_t excp
,
251 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
253 assert(!excp_is_internal(excp
));
254 cs
->exception_index
= excp
;
255 env
->exception
.syndrome
= syndrome
;
259 uint32_t HELPER(cpsr_read
)(CPUARMState
*env
)
261 return cpsr_read(env
) & ~(CPSR_EXEC
| CPSR_RESERVED
);
264 void HELPER(cpsr_write
)(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
266 cpsr_write(env
, val
, mask
);
269 /* Access to user mode registers from privileged modes. */
270 uint32_t HELPER(get_user_reg
)(CPUARMState
*env
, uint32_t regno
)
275 val
= env
->banked_r13
[0];
276 } else if (regno
== 14) {
277 val
= env
->banked_r14
[0];
278 } else if (regno
>= 8
279 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
280 val
= env
->usr_regs
[regno
- 8];
282 val
= env
->regs
[regno
];
287 void HELPER(set_user_reg
)(CPUARMState
*env
, uint32_t regno
, uint32_t val
)
290 env
->banked_r13
[0] = val
;
291 } else if (regno
== 14) {
292 env
->banked_r14
[0] = val
;
293 } else if (regno
>= 8
294 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
295 env
->usr_regs
[regno
- 8] = val
;
297 env
->regs
[regno
] = val
;
301 void HELPER(access_check_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t syndrome
)
303 const ARMCPRegInfo
*ri
= rip
;
304 switch (ri
->accessfn(env
, ri
)) {
308 env
->exception
.syndrome
= syndrome
;
310 case CP_ACCESS_TRAP_UNCATEGORIZED
:
311 env
->exception
.syndrome
= syn_uncategorized();
314 g_assert_not_reached();
316 raise_exception(env
, EXCP_UDEF
);
319 void HELPER(set_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t value
)
321 const ARMCPRegInfo
*ri
= rip
;
323 ri
->writefn(env
, ri
, value
);
326 uint32_t HELPER(get_cp_reg
)(CPUARMState
*env
, void *rip
)
328 const ARMCPRegInfo
*ri
= rip
;
330 return ri
->readfn(env
, ri
);
333 void HELPER(set_cp_reg64
)(CPUARMState
*env
, void *rip
, uint64_t value
)
335 const ARMCPRegInfo
*ri
= rip
;
337 ri
->writefn(env
, ri
, value
);
340 uint64_t HELPER(get_cp_reg64
)(CPUARMState
*env
, void *rip
)
342 const ARMCPRegInfo
*ri
= rip
;
344 return ri
->readfn(env
, ri
);
347 void HELPER(msr_i_pstate
)(CPUARMState
*env
, uint32_t op
, uint32_t imm
)
349 /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
350 * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
351 * to catch that case at translate time.
353 if (arm_current_pl(env
) == 0 && !(env
->cp15
.c1_sys
& SCTLR_UMA
)) {
354 raise_exception(env
, EXCP_UDEF
);
358 case 0x05: /* SPSel */
359 update_spsel(env
, imm
);
361 case 0x1e: /* DAIFSet */
362 env
->daif
|= (imm
<< 6) & PSTATE_DAIF
;
364 case 0x1f: /* DAIFClear */
365 env
->daif
&= ~((imm
<< 6) & PSTATE_DAIF
);
368 g_assert_not_reached();
372 void HELPER(exception_return
)(CPUARMState
*env
)
374 int cur_el
= arm_current_pl(env
);
375 unsigned int spsr_idx
= aarch64_banked_spsr_index(cur_el
);
376 uint32_t spsr
= env
->banked_spsr
[spsr_idx
];
379 aarch64_save_sp(env
, cur_el
);
381 env
->exclusive_addr
= -1;
383 /* We must squash the PSTATE.SS bit to zero unless both of the
385 * 1. debug exceptions are currently disabled
386 * 2. singlestep will be active in the EL we return to
387 * We check 1 here and 2 after we've done the pstate/cpsr write() to
388 * transition to the EL we're going to.
390 if (arm_generate_debug_exceptions(env
)) {
394 if (spsr
& PSTATE_nRW
) {
395 /* TODO: We currently assume EL1/2/3 are running in AArch64. */
398 env
->uncached_cpsr
= 0x10;
399 cpsr_write(env
, spsr
, ~0);
400 if (!arm_singlestep_active(env
)) {
401 env
->uncached_cpsr
&= ~PSTATE_SS
;
403 for (i
= 0; i
< 15; i
++) {
404 env
->regs
[i
] = env
->xregs
[i
];
407 env
->regs
[15] = env
->elr_el
[1] & ~0x1;
409 new_el
= extract32(spsr
, 2, 2);
411 || (new_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
))) {
412 /* Disallow return to an EL which is unimplemented or higher
413 * than the current one.
417 if (extract32(spsr
, 1, 1)) {
418 /* Return with reserved M[1] bit set */
421 if (new_el
== 0 && (spsr
& PSTATE_SP
)) {
422 /* Return to EL0 with M[0] bit set */
426 pstate_write(env
, spsr
);
427 if (!arm_singlestep_active(env
)) {
428 env
->pstate
&= ~PSTATE_SS
;
430 aarch64_restore_sp(env
, new_el
);
431 env
->pc
= env
->elr_el
[cur_el
];
437 /* Illegal return events of various kinds have architecturally
438 * mandated behaviour:
439 * restore NZCV and DAIF from SPSR_ELx
441 * restore PC from ELR_ELx
442 * no change to exception level, execution state or stack pointer
444 env
->pstate
|= PSTATE_IL
;
445 env
->pc
= env
->elr_el
[cur_el
];
446 spsr
&= PSTATE_NZCV
| PSTATE_DAIF
;
447 spsr
|= pstate_read(env
) & ~(PSTATE_NZCV
| PSTATE_DAIF
);
448 pstate_write(env
, spsr
);
449 if (!arm_singlestep_active(env
)) {
450 env
->pstate
&= ~PSTATE_SS
;
454 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
455 The only way to do that in TCG is a conditional branch, which clobbers
456 all our temporaries. For now implement these as helper functions. */
458 /* Similarly for variable shift instructions. */
460 uint32_t HELPER(shl_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
462 int shift
= i
& 0xff;
469 } else if (shift
!= 0) {
470 env
->CF
= (x
>> (32 - shift
)) & 1;
476 uint32_t HELPER(shr_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
478 int shift
= i
& 0xff;
481 env
->CF
= (x
>> 31) & 1;
485 } else if (shift
!= 0) {
486 env
->CF
= (x
>> (shift
- 1)) & 1;
492 uint32_t HELPER(sar_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
494 int shift
= i
& 0xff;
496 env
->CF
= (x
>> 31) & 1;
497 return (int32_t)x
>> 31;
498 } else if (shift
!= 0) {
499 env
->CF
= (x
>> (shift
- 1)) & 1;
500 return (int32_t)x
>> shift
;
505 uint32_t HELPER(ror_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
509 shift
= shift1
& 0x1f;
512 env
->CF
= (x
>> 31) & 1;
515 env
->CF
= (x
>> (shift
- 1)) & 1;
516 return ((uint32_t)x
>> shift
) | (x
<< (32 - shift
));