target/hexagon/macros.h

   1 /*
   2  *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef HEXAGON_MACROS_H
  19 #define HEXAGON_MACROS_H
  20
  21 #include "cpu.h"
  22 #include "hex_regs.h"
  23 #include "reg_fields.h"
  24
  25 #ifdef QEMU_GENERATE
  26 #define READ_REG(dest, NUM)              gen_read_reg(dest, NUM)
  27 #else
  28 #define READ_REG(NUM)                    (env->gpr[(NUM)])
  29 #define READ_PREG(NUM)                   (env->pred[NUM])
  30
  31 #define WRITE_RREG(NUM, VAL)             log_reg_write(env, NUM, VAL, slot)
  32 #define WRITE_PREG(NUM, VAL)             log_pred_write(env, NUM, VAL)
  33 #endif
  34
  35 #define PCALIGN 4
  36 #define PCALIGN_MASK (PCALIGN - 1)
  37
  38 #define GET_FIELD(FIELD, REGIN) \
  39     fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \
  40                    reg_field_info[FIELD].offset)
  41
  42 #ifdef QEMU_GENERATE
  43 #define GET_USR_FIELD(FIELD, DST) \
  44     tcg_gen_extract_tl(DST, hex_gpr[HEX_REG_USR], \
  45                        reg_field_info[FIELD].offset, \
  46                        reg_field_info[FIELD].width)
  47
  48 #define TYPE_INT(X)          __builtin_types_compatible_p(typeof(X), int)
  49 #define TYPE_TCGV(X)         __builtin_types_compatible_p(typeof(X), TCGv)
  50 #define TYPE_TCGV_I64(X)     __builtin_types_compatible_p(typeof(X), TCGv_i64)
  51
  52 #define SET_USR_FIELD_FUNC(X) \
  53     __builtin_choose_expr(TYPE_INT(X), \
  54         gen_set_usr_fieldi, \
  55         __builtin_choose_expr(TYPE_TCGV(X), \
  56             gen_set_usr_field, (void)0))
  57 #define SET_USR_FIELD(FIELD, VAL) \
  58     SET_USR_FIELD_FUNC(VAL)(FIELD, VAL)
  59 #else
  60 #define GET_USR_FIELD(FIELD) \
  61     fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
  62                    reg_field_info[FIELD].offset)
  63
  64 #define SET_USR_FIELD(FIELD, VAL) \
  65     fINSERT_BITS(env->new_value[HEX_REG_USR], reg_field_info[FIELD].width, \
  66                  reg_field_info[FIELD].offset, (VAL))
  67 #endif
  68
  69 #ifdef QEMU_GENERATE
  70 /*
  71  * Section 5.5 of the Hexagon V67 Programmer's Reference Manual
  72  *
  73  * Slot 1 store with slot 0 load
  74  * A slot 1 store operation with a slot 0 load operation can appear in a packet.
  75  * The packet attribute :mem_noshuf inhibits the instruction reordering that
  76  * would otherwise be done by the assembler. For example:
  77  *     {
  78  *         memw(R5) = R2 // slot 1 store
  79  *         R3 = memh(R6) // slot 0 load
  80  *     }:mem_noshuf
  81  * Unlike most packetized operations, these memory operations are not executed
  82  * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1
  83  * effectively executes first, followed by the load instruction in Slot 0. If
  84  * the addresses of the two operations are overlapping, the load will receive
  85  * the newly stored data. This feature is supported in processor versions
  86  * V65 or greater.
  87  *
  88  *
  89  * For qemu, we look for a load in slot 0 when there is  a store in slot 1
  90  * in the same packet.  When we see this, we call a helper that merges the
  91  * bytes from the store buffer with the value loaded from memory.
  92  */
  93 #define CHECK_NOSHUF \
  94     do { \
  95         if (insn->slot == 0 && pkt->pkt_has_store_s1) { \
  96             process_store(ctx, pkt, 1); \
  97         } \
  98     } while (0)
  99
 100 #define MEM_LOAD1s(DST, VA) \
 101     do { \
 102         CHECK_NOSHUF; \
 103         tcg_gen_qemu_ld8s(DST, VA, ctx->mem_idx); \
 104     } while (0)
 105 #define MEM_LOAD1u(DST, VA) \
 106     do { \
 107         CHECK_NOSHUF; \
 108         tcg_gen_qemu_ld8u(DST, VA, ctx->mem_idx); \
 109     } while (0)
 110 #define MEM_LOAD2s(DST, VA) \
 111     do { \
 112         CHECK_NOSHUF; \
 113         tcg_gen_qemu_ld16s(DST, VA, ctx->mem_idx); \
 114     } while (0)
 115 #define MEM_LOAD2u(DST, VA) \
 116     do { \
 117         CHECK_NOSHUF; \
 118         tcg_gen_qemu_ld16u(DST, VA, ctx->mem_idx); \
 119     } while (0)
 120 #define MEM_LOAD4s(DST, VA) \
 121     do { \
 122         CHECK_NOSHUF; \
 123         tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
 124     } while (0)
 125 #define MEM_LOAD4u(DST, VA) \
 126     do { \
 127         CHECK_NOSHUF; \
 128         tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
 129     } while (0)
 130 #define MEM_LOAD8u(DST, VA) \
 131     do { \
 132         CHECK_NOSHUF; \
 133         tcg_gen_qemu_ld64(DST, VA, ctx->mem_idx); \
 134     } while (0)
 135
 136 #define MEM_STORE1_FUNC(X) \
 137     __builtin_choose_expr(TYPE_INT(X), \
 138         gen_store1i, \
 139         __builtin_choose_expr(TYPE_TCGV(X), \
 140             gen_store1, (void)0))
 141 #define MEM_STORE1(VA, DATA, SLOT) \
 142     MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT)
 143
 144 #define MEM_STORE2_FUNC(X) \
 145     __builtin_choose_expr(TYPE_INT(X), \
 146         gen_store2i, \
 147         __builtin_choose_expr(TYPE_TCGV(X), \
 148             gen_store2, (void)0))
 149 #define MEM_STORE2(VA, DATA, SLOT) \
 150     MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT)
 151
 152 #define MEM_STORE4_FUNC(X) \
 153     __builtin_choose_expr(TYPE_INT(X), \
 154         gen_store4i, \
 155         __builtin_choose_expr(TYPE_TCGV(X), \
 156             gen_store4, (void)0))
 157 #define MEM_STORE4(VA, DATA, SLOT) \
 158     MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT)
 159
 160 #define MEM_STORE8_FUNC(X) \
 161     __builtin_choose_expr(TYPE_INT(X), \
 162         gen_store8i, \
 163         __builtin_choose_expr(TYPE_TCGV_I64(X), \
 164             gen_store8, (void)0))
 165 #define MEM_STORE8(VA, DATA, SLOT) \
 166     MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT)
 167 #else
 168 #define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, slot, VA))
 169 #define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, slot, VA))
 170 #define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, slot, VA))
 171 #define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, slot, VA))
 172 #define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, slot, VA))
 173 #define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, slot, VA))
 174 #define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, slot, VA))
 175 #define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, slot, VA))
 176
 177 #define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)
 178 #define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)
 179 #define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)
 180 #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT)
 181 #endif
 182
 183 #define CANCEL cancel_slot(env, slot)
 184
 185 #define LOAD_CANCEL(EA) do { CANCEL; } while (0)
 186
 187 #ifdef QEMU_GENERATE
 188 static inline void gen_pred_cancel(TCGv pred, int slot_num)
 189  {
 190     TCGv slot_mask = tcg_temp_new();
 191     TCGv tmp = tcg_temp_new();
 192     TCGv zero = tcg_constant_tl(0);
 193     tcg_gen_ori_tl(slot_mask, hex_slot_cancelled, 1 << slot_num);
 194     tcg_gen_andi_tl(tmp, pred, 1);
 195     tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero,
 196                        slot_mask, hex_slot_cancelled);
 197     tcg_temp_free(slot_mask);
 198     tcg_temp_free(tmp);
 199 }
 200 #define PRED_LOAD_CANCEL(PRED, EA) \
 201     gen_pred_cancel(PRED, insn->is_endloop ? 4 : insn->slot)
 202 #endif
 203
 204 #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); }
 205
 206 #define fMAX(A, B) (((A) > (B)) ? (A) : (B))
 207
 208 #define fMIN(A, B) (((A) < (B)) ? (A) : (B))
 209
 210 #define fABS(A) (((A) < 0) ? (-(A)) : (A))
 211 #define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \
 212     REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG)
 213 #define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \
 214     ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL)
 215 #define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \
 216     (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8)))
 217 #define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \
 218     (((HIBIT) - (LOWBIT) + 1) ? \
 219         extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \
 220         0LL)
 221 #define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \
 222     do { \
 223         int width = ((HIBIT) - (LOWBIT) + 1); \
 224         INREG = (width >= 0 ? \
 225             deposit64((INREG), (LOWBIT), width, (INVAL)) : \
 226             INREG); \
 227     } while (0)
 228
 229 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00)
 230
 231 #ifdef QEMU_GENERATE
 232 #define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1)
 233 #else
 234 #define fLSBOLD(VAL)  ((VAL) & 1)
 235 #endif
 236
 237 #ifdef QEMU_GENERATE
 238 #define fLSBNEW(PVAL)   tcg_gen_andi_tl(LSB, (PVAL), 1)
 239 #define fLSBNEW0        tcg_gen_andi_tl(LSB, hex_new_pred_value[0], 1)
 240 #define fLSBNEW1        tcg_gen_andi_tl(LSB, hex_new_pred_value[1], 1)
 241 #else
 242 #define fLSBNEW(PVAL)   ((PVAL) & 1)
 243 #define fLSBNEW0        (env->new_pred_value[0] & 1)
 244 #define fLSBNEW1        (env->new_pred_value[1] & 1)
 245 #endif
 246
 247 #ifdef QEMU_GENERATE
 248 #define fLSBOLDNOT(VAL) \
 249     do { \
 250         tcg_gen_andi_tl(LSB, (VAL), 1); \
 251         tcg_gen_xori_tl(LSB, LSB, 1); \
 252     } while (0)
 253 #define fLSBNEWNOT(PNUM) \
 254     do { \
 255         tcg_gen_andi_tl(LSB, (PNUM), 1); \
 256         tcg_gen_xori_tl(LSB, LSB, 1); \
 257     } while (0)
 258 #else
 259 #define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM))
 260 #define fLSBOLDNOT(VAL) (!fLSBOLD(VAL))
 261 #define fLSBNEW0NOT (!fLSBNEW0)
 262 #define fLSBNEW1NOT (!fLSBNEW1)
 263 #endif
 264
 265 #define fNEWREG(VAL) ((int32_t)(VAL))
 266
 267 #define fNEWREG_ST(VAL) (VAL)
 268
 269 #define fSATUVALN(N, VAL) \
 270     ({ \
 271         fSET_OVERFLOW(); \
 272         ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \
 273     })
 274 #define fSATVALN(N, VAL) \
 275     ({ \
 276         fSET_OVERFLOW(); \
 277         ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
 278     })
 279 #define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL)
 280 #define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL)
 281 #define fSATN(N, VAL) \
 282     ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL))
 283 #define fADDSAT64(DST, A, B) \
 284     do { \
 285         uint64_t __a = fCAST8u(A); \
 286         uint64_t __b = fCAST8u(B); \
 287         uint64_t __sum = __a + __b; \
 288         uint64_t __xor = __a ^ __b; \
 289         const uint64_t __mask = 0x8000000000000000ULL; \
 290         if (__xor & __mask) { \
 291             DST = __sum; \
 292         } \
 293         else if ((__a ^ __sum) & __mask) { \
 294             if (__sum & __mask) { \
 295                 DST = 0x7FFFFFFFFFFFFFFFLL; \
 296                 fSET_OVERFLOW(); \
 297             } else { \
 298                 DST = 0x8000000000000000LL; \
 299                 fSET_OVERFLOW(); \
 300             } \
 301         } else { \
 302             DST = __sum; \
 303         } \
 304     } while (0)
 305 #define fSATUN(N, VAL) \
 306     ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL))
 307 #define fSATH(VAL) (fSATN(16, VAL))
 308 #define fSATUH(VAL) (fSATUN(16, VAL))
 309 #define fSATUB(VAL) (fSATUN(8, VAL))
 310 #define fSATB(VAL) (fSATN(8, VAL))
 311 #define fIMMEXT(IMM) (IMM = IMM)
 312 #define fMUST_IMMEXT(IMM) fIMMEXT(IMM)
 313
 314 #define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK)
 315
 316 #ifdef QEMU_GENERATE
 317 static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
 318 {
 319     /*
 320      * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual
 321      *
 322      *  The "I" value from a modifier register is divided into two pieces
 323      *      LSB         bits 23:17
 324      *      MSB         bits 31:28
 325      * The value is signed
 326      *
 327      * At the end we shift the result according to the shift argument
 328      */
 329     TCGv msb = tcg_temp_new();
 330     TCGv lsb = tcg_temp_new();
 331
 332     tcg_gen_extract_tl(lsb, val, 17, 7);
 333     tcg_gen_sari_tl(msb, val, 21);
 334     tcg_gen_deposit_tl(result, msb, lsb, 0, 7);
 335
 336     tcg_gen_shli_tl(result, result, shift);
 337
 338     tcg_temp_free(msb);
 339     tcg_temp_free(lsb);
 340
 341     return result;
 342 }
 343 #define fREAD_IREG(VAL, SHIFT) gen_read_ireg(ireg, (VAL), (SHIFT))
 344 #else
 345 #define fREAD_IREG(VAL) \
 346     (fSXTN(11, 64, (((VAL) & 0xf0000000) >> 21) | ((VAL >> 17) & 0x7f)))
 347 #endif
 348
 349 #define fREAD_LR() (READ_REG(HEX_REG_LR))
 350
 351 #define fWRITE_LR(A) WRITE_RREG(HEX_REG_LR, A)
 352 #define fWRITE_FP(A) WRITE_RREG(HEX_REG_FP, A)
 353 #define fWRITE_SP(A) WRITE_RREG(HEX_REG_SP, A)
 354
 355 #define fREAD_SP() (READ_REG(HEX_REG_SP))
 356 #define fREAD_LC0 (READ_REG(HEX_REG_LC0))
 357 #define fREAD_LC1 (READ_REG(HEX_REG_LC1))
 358 #define fREAD_SA0 (READ_REG(HEX_REG_SA0))
 359 #define fREAD_SA1 (READ_REG(HEX_REG_SA1))
 360 #define fREAD_FP() (READ_REG(HEX_REG_FP))
 361 #ifdef FIXME
 362 /* Figure out how to get insn->extension_valid to helper */
 363 #define fREAD_GP() \
 364     (insn->extension_valid ? 0 : READ_REG(HEX_REG_GP))
 365 #else
 366 #define fREAD_GP() READ_REG(HEX_REG_GP)
 367 #endif
 368 #define fREAD_PC() (READ_REG(HEX_REG_PC))
 369
 370 #define fREAD_NPC() (env->next_PC & (0xfffffffe))
 371
 372 #define fREAD_P0() (READ_PREG(0))
 373 #define fREAD_P3() (READ_PREG(3))
 374
 375 #define fCHECK_PCALIGN(A)
 376
 377 #define fWRITE_NPC(A) write_new_pc(env, A)
 378
 379 #define fBRANCH(LOC, TYPE)          fWRITE_NPC(LOC)
 380 #define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR)
 381 #define fHINTJR(TARGET) { /* Not modelled in qemu */}
 382 #define fCALL(A) \
 383     do { \
 384         fWRITE_LR(fREAD_NPC()); \
 385         fBRANCH(A, COF_TYPE_CALL); \
 386     } while (0)
 387 #define fCALLR(A) \
 388     do { \
 389         fWRITE_LR(fREAD_NPC()); \
 390         fBRANCH(A, COF_TYPE_CALLR); \
 391     } while (0)
 392 #define fWRITE_LOOP_REGS0(START, COUNT) \
 393     do { \
 394         WRITE_RREG(HEX_REG_LC0, COUNT);  \
 395         WRITE_RREG(HEX_REG_SA0, START); \
 396     } while (0)
 397 #define fWRITE_LOOP_REGS1(START, COUNT) \
 398     do { \
 399         WRITE_RREG(HEX_REG_LC1, COUNT);  \
 400         WRITE_RREG(HEX_REG_SA1, START);\
 401     } while (0)
 402 #define fWRITE_LC0(VAL) WRITE_RREG(HEX_REG_LC0, VAL)
 403 #define fWRITE_LC1(VAL) WRITE_RREG(HEX_REG_LC1, VAL)
 404
 405 #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1)
 406 #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL))
 407 #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG))
 408 #define fWRITE_P0(VAL) WRITE_PREG(0, VAL)
 409 #define fWRITE_P1(VAL) WRITE_PREG(1, VAL)
 410 #define fWRITE_P2(VAL) WRITE_PREG(2, VAL)
 411 #define fWRITE_P3(VAL) WRITE_PREG(3, VAL)
 412 #define fPART1(WORK) if (part1) { WORK; return; }
 413 #define fCAST4u(A) ((uint32_t)(A))
 414 #define fCAST4s(A) ((int32_t)(A))
 415 #define fCAST8u(A) ((uint64_t)(A))
 416 #define fCAST8s(A) ((int64_t)(A))
 417 #define fCAST4_4s(A) ((int32_t)(A))
 418 #define fCAST4_4u(A) ((uint32_t)(A))
 419 #define fCAST4_8s(A) ((int64_t)((int32_t)(A)))
 420 #define fCAST4_8u(A) ((uint64_t)((uint32_t)(A)))
 421 #define fCAST8_8s(A) ((int64_t)(A))
 422 #define fCAST8_8u(A) ((uint64_t)(A))
 423 #define fCAST2_8s(A) ((int64_t)((int16_t)(A)))
 424 #define fCAST2_8u(A) ((uint64_t)((uint16_t)(A)))
 425 #define fZE8_16(A) ((int16_t)((uint8_t)(A)))
 426 #define fSE8_16(A) ((int16_t)((int8_t)(A)))
 427 #define fSE16_32(A) ((int32_t)((int16_t)(A)))
 428 #define fZE16_32(A) ((uint32_t)((uint16_t)(A)))
 429 #define fSE32_64(A) ((int64_t)((int32_t)(A)))
 430 #define fZE32_64(A) ((uint64_t)((uint32_t)(A)))
 431 #define fSE8_32(A) ((int32_t)((int8_t)(A)))
 432 #define fZE8_32(A) ((int32_t)((uint8_t)(A)))
 433 #define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B))
 434 #define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B))
 435 #define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B))
 436 #define fMPY8SS(A, B) (int)((short)(A) * (short)(B))
 437 #define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B))
 438 #define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B))
 439 #define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B))
 440 #define fMPY16US(A, B) fMPY16SU(B, A)
 441 #define fMPY32SS(A, B) (fSE32_64(A) * fSE32_64(B))
 442 #define fMPY32UU(A, B) (fZE32_64(A) * fZE32_64(B))
 443 #define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B))
 444 #define fMPY3216SS(A, B) (fSE32_64(A) * fSXTN(16, 64, B))
 445 #define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B))
 446 #define fROUND(A) (A + 0x8000)
 447 #define fCLIP(DST, SRC, U) \
 448     do { \
 449         int32_t maxv = (1 << U) - 1; \
 450         int32_t minv = -(1 << U); \
 451         DST = fMIN(maxv, fMAX(SRC, minv)); \
 452     } while (0)
 453 #define fCRND(A) ((((A) & 0x3) == 0x3) ? ((A) + 1) : ((A)))
 454 #define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1))))))
 455 #define fCRNDN(A, N) (conv_round(A, N))
 456 #define fADD128(A, B) (int128_add(A, B))
 457 #define fSUB128(A, B) (int128_sub(A, B))
 458 #define fSHIFTR128(A, B) (int128_rshift(A, B))
 459 #define fSHIFTL128(A, B) (int128_lshift(A, B))
 460 #define fAND128(A, B) (int128_and(A, B))
 461 #define fCAST8S_16S(A) (int128_exts64(A))
 462 #define fCAST16S_8S(A) (int128_getlo(A))
 463
 464 #ifdef QEMU_GENERATE
 465 #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM)
 466 #define fEA_RRs(REG, REG2, SCALE) \
 467     do { \
 468         TCGv tmp = tcg_temp_new(); \
 469         tcg_gen_shli_tl(tmp, REG2, SCALE); \
 470         tcg_gen_add_tl(EA, REG, tmp); \
 471         tcg_temp_free(tmp); \
 472     } while (0)
 473 #define fEA_IRs(IMM, REG, SCALE) \
 474     do { \
 475         tcg_gen_shli_tl(EA, REG, SCALE); \
 476         tcg_gen_addi_tl(EA, EA, IMM); \
 477     } while (0)
 478 #else
 479 #define fEA_RI(REG, IMM) \
 480     do { \
 481         EA = REG + IMM; \
 482     } while (0)
 483 #define fEA_RRs(REG, REG2, SCALE) \
 484     do { \
 485         EA = REG + (REG2 << SCALE); \
 486     } while (0)
 487 #define fEA_IRs(IMM, REG, SCALE) \
 488     do { \
 489         EA = IMM + (REG << SCALE); \
 490     } while (0)
 491 #endif
 492
 493 #ifdef QEMU_GENERATE
 494 #define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM)
 495 #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG)
 496 #define fEA_BREVR(REG)      gen_helper_fbrev(EA, REG)
 497 #define fPM_I(REG, IMM)     tcg_gen_addi_tl(REG, REG, IMM)
 498 #define fPM_M(REG, MVAL)    tcg_gen_add_tl(REG, REG, MVAL)
 499 #define fPM_CIRI(REG, IMM, MVAL) \
 500     do { \
 501         TCGv tcgv_siV = tcg_constant_tl(siV); \
 502         gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, \
 503                             hex_gpr[HEX_REG_CS0 + MuN]); \
 504     } while (0)
 505 #else
 506 #define fEA_IMM(IMM)        do { EA = (IMM); } while (0)
 507 #define fEA_REG(REG)        do { EA = (REG); } while (0)
 508 #define fEA_GPI(IMM)        do { EA = (fREAD_GP() + (IMM)); } while (0)
 509 #define fPM_I(REG, IMM)     do { REG = REG + (IMM); } while (0)
 510 #define fPM_M(REG, MVAL)    do { REG = REG + (MVAL); } while (0)
 511 #endif
 512 #define fSCALE(N, A) (((int64_t)(A)) << N)
 513 #define fSATW(A) fSATN(32, ((long long)A))
 514 #define fSAT(A) fSATN(32, (A))
 515 #define fSAT_ORIG_SHL(A, ORIG_REG) \
 516     ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \
 517         ? fSATVALN(32, ((int32_t)(ORIG_REG))) \
 518         : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \
 519                                             : fSAT(A)))
 520 #define fPASS(A) A
 521 #define fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE) \
 522     (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
 523                    : (fCAST##REGSTYPE(SRC) << (SHAMT)))
 524 #define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \
 525     fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##s)
 526 #define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \
 527     fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##u)
 528 #define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \
 529     (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
 530                    : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC)))
 531 #define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \
 532     (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \
 533                    : (fCAST##REGSTYPE(SRC) >> (SHAMT)))
 534 #define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \
 535     fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##s)
 536 #define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \
 537     fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u)
 538 #define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \
 539     (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \
 540                         << ((-(SHAMT)) - 1)) << 1, (SRC)) \
 541                    : (fCAST##REGSTYPE##s(SRC) >> (SHAMT)))
 542 #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT))
 543 #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \
 544     (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT)))
 545 #define fROTL(SRC, SHAMT, REGSTYPE) \
 546     (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \
 547                               ((fCAST##REGSTYPE##u(SRC) >> \
 548                                  ((sizeof(SRC) * 8) - (SHAMT))))))
 549 #define fROTR(SRC, SHAMT, REGSTYPE) \
 550     (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \
 551                               ((fCAST##REGSTYPE##u(SRC) << \
 552                                  ((sizeof(SRC) * 8) - (SHAMT))))))
 553 #define fASHIFTL(SRC, SHAMT, REGSTYPE) \
 554     (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT)))
 555
 556 #ifdef QEMU_GENERATE
 557 #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
 558 #else
 559 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \
 560     DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA)
 561 #endif
 562
 563 #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
 564
 565 #define fGET_FRAMEKEY() READ_REG(HEX_REG_FRAMEKEY)
 566 #define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32))
 567 #define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL)
 568
 569 #ifdef CONFIG_USER_ONLY
 570 #define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-user */
 571 #else
 572 /* System mode not implemented yet */
 573 #define fFRAMECHECK(ADDR, EA)  g_assert_not_reached();
 574 #endif
 575
 576 #ifdef QEMU_GENERATE
 577 #define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \
 578     gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx);
 579 #endif
 580
 581 #ifdef QEMU_GENERATE
 582 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot)
 583 #else
 584 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot)
 585 #endif
 586
 587 #ifdef QEMU_GENERATE
 588 #define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \
 589     gen_store_conditional##SIZE(ctx, PRED, EA, SRC);
 590 #endif
 591
 592 #ifdef QEMU_GENERATE
 593 #define GETBYTE_FUNC(X) \
 594     __builtin_choose_expr(TYPE_TCGV(X), \
 595         gen_get_byte, \
 596         __builtin_choose_expr(TYPE_TCGV_I64(X), \
 597             gen_get_byte_i64, (void)0))
 598 #define fGETBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, true)
 599 #define fGETUBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, false)
 600 #else
 601 #define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff))
 602 #define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff))
 603 #endif
 604
 605 #define fSETBYTE(N, DST, VAL) \
 606     do { \
 607         DST = (DST & ~(0x0ffLL << ((N) * 8))) | \
 608         (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \
 609     } while (0)
 610
 611 #ifdef QEMU_GENERATE
 612 #define fGETHALF(N, SRC)  gen_get_half(HALF, N, SRC, true)
 613 #define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false)
 614 #else
 615 #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff))
 616 #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff))
 617 #endif
 618 #define fSETHALF(N, DST, VAL) \
 619     do { \
 620         DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \
 621         (((uint64_t)((VAL) & 0x0ffff)) << ((N) * 16)); \
 622     } while (0)
 623 #define fSETHALFw fSETHALF
 624 #define fSETHALFd fSETHALF
 625
 626 #define fGETWORD(N, SRC) \
 627     ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
 628 #define fGETUWORD(N, SRC) \
 629     ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
 630
 631 #define fSETWORD(N, DST, VAL) \
 632     do { \
 633         DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \
 634               (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \
 635     } while (0)
 636
 637 #define fSETBIT(N, DST, VAL) \
 638     do { \
 639         DST = (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \
 640     } while (0)
 641
 642 #define fGETBIT(N, SRC) (((SRC) >> N) & 1)
 643 #define fSETBITS(HI, LO, DST, VAL) \
 644     do { \
 645         int j; \
 646         for (j = LO; j <= HI; j++) { \
 647             fSETBIT(j, DST, VAL); \
 648         } \
 649     } while (0)
 650 #define fCOUNTONES_4(VAL) ctpop32(VAL)
 651 #define fCOUNTONES_8(VAL) ctpop64(VAL)
 652 #define fBREV_8(VAL) revbit64(VAL)
 653 #define fBREV_4(VAL) revbit32(VAL)
 654 #define fCL1_8(VAL) clo64(VAL)
 655 #define fCL1_4(VAL) clo32(VAL)
 656 #define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN)
 657 #define fDEINTERLEAVE(MIXED) deinterleave(MIXED)
 658 #define fHIDE(A) A
 659 #define fCONSTLL(A) A##LL
 660 #define fECHO(A) (A)
 661
 662 #define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0)
 663 #define fPAUSE(IMM)
 664
 665 #define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \
 666     ((VAL) << reg_field_info[FIELD].offset)
 667 #define fGET_REG_FIELD_MASK(FIELD) \
 668     (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset)
 669 #define fREAD_REG_FIELD(REG, FIELD) \
 670     fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
 671                    reg_field_info[FIELD].width, \
 672                    reg_field_info[FIELD].offset)
 673 #define fGET_FIELD(VAL, FIELD)
 674 #define fSET_FIELD(VAL, FIELD, NEWVAL)
 675 #define fBARRIER()
 676 #define fSYNCH()
 677 #define fISYNC()
 678 #define fDCFETCH(REG) \
 679     do { (void)REG; } while (0) /* Nothing to do in qemu */
 680 #define fICINVA(REG) \
 681     do { (void)REG; } while (0) /* Nothing to do in qemu */
 682 #define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS)
 683 #define fDCCLEANA(REG) \
 684     do { (void)REG; } while (0) /* Nothing to do in qemu */
 685 #define fDCCLEANINVA(REG) \
 686     do { (void)REG; } while (0) /* Nothing to do in qemu */
 687
 688 #define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0)
 689
 690 #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \
 691                                 STRBITNUM) /* Nothing */
 692
 693
 694 #endif