target-m68k/cpu.h

   1 /*
   2  * m68k virtual CPU header
   3  *
   4  *  Copyright (c) 2005-2007 CodeSourcery
   5  *  Written by Paul Brook
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef M68K_CPU_H
  22 #define M68K_CPU_H
  23
  24 #define TARGET_LONG_BITS 32
  25
  26 #define CPUArchState struct CPUM68KState
  27
  28 #include "qemu-common.h"
  29 #include "exec/cpu-defs.h"
  30 #include "cpu-qom.h"
  31 #include "fpu/softfloat.h"
  32
  33 #define MAX_QREGS 32
  34
  35 #define EXCP_ACCESS         2   /* Access (MMU) error.  */
  36 #define EXCP_ADDRESS        3   /* Address error.  */
  37 #define EXCP_ILLEGAL        4   /* Illegal instruction.  */
  38 #define EXCP_DIV0           5   /* Divide by zero */
  39 #define EXCP_PRIVILEGE      8   /* Privilege violation.  */
  40 #define EXCP_TRACE          9
  41 #define EXCP_LINEA          10  /* Unimplemented line-A (MAC) opcode.  */
  42 #define EXCP_LINEF          11  /* Unimplemented line-F (FPU) opcode.  */
  43 #define EXCP_DEBUGNBP       12  /* Non-breakpoint debug interrupt.  */
  44 #define EXCP_DEBEGBP        13  /* Breakpoint debug interrupt.  */
  45 #define EXCP_FORMAT         14  /* RTE format error.  */
  46 #define EXCP_UNINITIALIZED  15
  47 #define EXCP_TRAP0          32   /* User trap #0.  */
  48 #define EXCP_TRAP15         47   /* User trap #15.  */
  49 #define EXCP_UNSUPPORTED    61
  50 #define EXCP_ICE            13
  51
  52 #define EXCP_RTE            0x100
  53 #define EXCP_HALT_INSN      0x101
  54
  55 #define NB_MMU_MODES 2
  56
  57 typedef struct CPUM68KState {
  58     uint32_t dregs[8];
  59     uint32_t aregs[8];
  60     uint32_t pc;
  61     uint32_t sr;
  62
  63     /* SSP and USP.  The current_sp is stored in aregs[7], the other here.  */
  64     int current_sp;
  65     uint32_t sp[2];
  66
  67     /* Condition flags.  */
  68     uint32_t cc_op;
  69     uint32_t cc_dest;
  70     uint32_t cc_src;
  71     uint32_t cc_x;
  72
  73     float64 fregs[8];
  74     float64 fp_result;
  75     uint32_t fpcr;
  76     uint32_t fpsr;
  77     float_status fp_status;
  78
  79     uint64_t mactmp;
  80     /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
  81        two 8-bit parts.  We store a single 64-bit value and
  82        rearrange/extend this when changing modes.  */
  83     uint64_t macc[4];
  84     uint32_t macsr;
  85     uint32_t mac_mask;
  86
  87     /* Temporary storage for DIV helpers.  */
  88     uint32_t div1;
  89     uint32_t div2;
  90
  91     /* MMU status.  */
  92     struct {
  93         uint32_t ar;
  94     } mmu;
  95
  96     /* Control registers.  */
  97     uint32_t vbr;
  98     uint32_t mbar;
  99     uint32_t rambar0;
 100     uint32_t cacr;
 101
 102     int pending_vector;
 103     int pending_level;
 104
 105     uint32_t qregs[MAX_QREGS];
 106
 107     CPU_COMMON
 108
 109     /* Fields from here on are preserved across CPU reset. */
 110     uint32_t features;
 111 } CPUM68KState;
 112
 113 /**
 114  * M68kCPU:
 115  * @env: #CPUM68KState
 116  *
 117  * A Motorola 68k CPU.
 118  */
 119 struct M68kCPU {
 120     /*< private >*/
 121     CPUState parent_obj;
 122     /*< public >*/
 123
 124     CPUM68KState env;
 125 };
 126
 127 static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
 128 {
 129     return container_of(env, M68kCPU, env);
 130 }
 131
 132 #define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))
 133
 134 #define ENV_OFFSET offsetof(M68kCPU, env)
 135
 136 void m68k_cpu_do_interrupt(CPUState *cpu);
 137 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
 138 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 139                          int flags);
 140 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 141 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 142 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 143
 144 void m68k_cpu_exec_enter(CPUState *cs);
 145 void m68k_cpu_exec_exit(CPUState *cs);
 146
 147 void m68k_tcg_init(void);
 148 void m68k_cpu_init_gdb(M68kCPU *cpu);
 149 M68kCPU *cpu_m68k_init(const char *cpu_model);
 150 /* you can call this signal handler from your SIGBUS and SIGSEGV
 151    signal handlers to inform the virtual CPU of exceptions. non zero
 152    is returned if the signal was handled by the virtual CPU.  */
 153 int cpu_m68k_signal_handler(int host_signum, void *pinfo,
 154                            void *puc);
 155 void cpu_m68k_flush_flags(CPUM68KState *, int);
 156
 157 enum {
 158     CC_OP_DYNAMIC, /* Use env->cc_op  */
 159     CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
 160     CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */
 161     CC_OP_ADD,   /* CC_DEST = result, CC_SRC = source */
 162     CC_OP_SUB,   /* CC_DEST = result, CC_SRC = source */
 163     CC_OP_CMPB,  /* CC_DEST = result, CC_SRC = source */
 164     CC_OP_CMPW,  /* CC_DEST = result, CC_SRC = source */
 165     CC_OP_ADDX,  /* CC_DEST = result, CC_SRC = source */
 166     CC_OP_SUBX,  /* CC_DEST = result, CC_SRC = source */
 167     CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
 168 };
 169
 170 #define CCF_C 0x01
 171 #define CCF_V 0x02
 172 #define CCF_Z 0x04
 173 #define CCF_N 0x08
 174 #define CCF_X 0x10
 175
 176 #define SR_I_SHIFT 8
 177 #define SR_I  0x0700
 178 #define SR_M  0x1000
 179 #define SR_S  0x2000
 180 #define SR_T  0x8000
 181
 182 #define M68K_SSP    0
 183 #define M68K_USP    1
 184
 185 /* CACR fields are implementation defined, but some bits are common.  */
 186 #define M68K_CACR_EUSP  0x10
 187
 188 #define MACSR_PAV0  0x100
 189 #define MACSR_OMC   0x080
 190 #define MACSR_SU    0x040
 191 #define MACSR_FI    0x020
 192 #define MACSR_RT    0x010
 193 #define MACSR_N     0x008
 194 #define MACSR_Z     0x004
 195 #define MACSR_V     0x002
 196 #define MACSR_EV    0x001
 197
 198 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
 199 void m68k_set_macsr(CPUM68KState *env, uint32_t val);
 200 void m68k_switch_sp(CPUM68KState *env);
 201
 202 #define M68K_FPCR_PREC (1 << 6)
 203
 204 void do_m68k_semihosting(CPUM68KState *env, int nr);
 205
 206 /* There are 4 ColdFire core ISA revisions: A, A+, B and C.
 207    Each feature covers the subset of instructions common to the
 208    ISA revisions mentioned.  */
 209
 210 enum m68k_features {
 211     M68K_FEATURE_CF_ISA_A,
 212     M68K_FEATURE_CF_ISA_B, /* (ISA B or C).  */
 213     M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).  */
 214     M68K_FEATURE_BRAL, /* Long unconditional branch.  (ISA A+ or B).  */
 215     M68K_FEATURE_CF_FPU,
 216     M68K_FEATURE_CF_MAC,
 217     M68K_FEATURE_CF_EMAC,
 218     M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate).  */
 219     M68K_FEATURE_USP, /* User Stack Pointer.  (ISA A+, B or C).  */
 220     M68K_FEATURE_EXT_FULL, /* 68020+ full extension word.  */
 221     M68K_FEATURE_WORD_INDEX /* word sized address index registers.  */
 222 };
 223
 224 static inline int m68k_feature(CPUM68KState *env, int feature)
 225 {
 226     return (env->features & (1u << feature)) != 0;
 227 }
 228
 229 void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 230
 231 void register_m68k_insns (CPUM68KState *env);
 232
 233 #ifdef CONFIG_USER_ONLY
 234 /* Linux uses 8k pages.  */
 235 #define TARGET_PAGE_BITS 13
 236 #else
 237 /* Smallest TLB entry size is 1k.  */
 238 #define TARGET_PAGE_BITS 10
 239 #endif
 240
 241 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 242 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 243
 244 #define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model))
 245
 246 #define cpu_signal_handler cpu_m68k_signal_handler
 247 #define cpu_list m68k_cpu_list
 248
 249 /* MMU modes definitions */
 250 #define MMU_MODE0_SUFFIX _kernel
 251 #define MMU_MODE1_SUFFIX _user
 252 #define MMU_USER_IDX 1
 253 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
 254 {
 255     return (env->sr & SR_S) == 0 ? 1 : 0;
 256 }
 257
 258 int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 259                               int mmu_idx);
 260
 261 #include "exec/cpu-all.h"
 262
 263 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
 264                                         target_ulong *cs_base, uint32_t *flags)
 265 {
 266     *pc = env->pc;
 267     *cs_base = 0;
 268     *flags = (env->fpcr & M68K_FPCR_PREC)       /* Bit  6 */
 269             | (env->sr & SR_S)                  /* Bit  13 */
 270             | ((env->macsr >> 4) & 0xf);        /* Bits 0-3 */
 271 }
 272
 273 #endif