2 * USB xHCI controller emulation
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qemu/timer.h"
24 #include "qemu/module.h"
25 #include "qemu/queue.h"
27 #include "migration/vmstate.h"
28 #include "hw/pci/pci.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/pci/msi.h"
31 #include "hw/pci/msix.h"
33 #include "qapi/error.h"
41 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
43 #define DPRINTF(...) do {} while (0)
45 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
46 __func__, __LINE__, _msg); abort(); } while (0)
48 #define TRB_LINK_LIMIT 32
49 #define COMMAND_LIMIT 256
50 #define TRANSFER_LIMIT 256
53 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
54 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
55 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
57 #define OFF_OPER LEN_CAP
58 #define OFF_RUNTIME 0x1000
59 #define OFF_DOORBELL 0x2000
60 #define OFF_MSIX_TABLE 0x3000
61 #define OFF_MSIX_PBA 0x3800
62 /* must be power of 2 */
63 #define LEN_REGS 0x4000
65 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
66 #error Increase OFF_RUNTIME
68 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
69 #error Increase OFF_DOORBELL
71 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
72 # error Increase LEN_REGS
76 #define USBCMD_RS (1<<0)
77 #define USBCMD_HCRST (1<<1)
78 #define USBCMD_INTE (1<<2)
79 #define USBCMD_HSEE (1<<3)
80 #define USBCMD_LHCRST (1<<7)
81 #define USBCMD_CSS (1<<8)
82 #define USBCMD_CRS (1<<9)
83 #define USBCMD_EWE (1<<10)
84 #define USBCMD_EU3S (1<<11)
86 #define USBSTS_HCH (1<<0)
87 #define USBSTS_HSE (1<<2)
88 #define USBSTS_EINT (1<<3)
89 #define USBSTS_PCD (1<<4)
90 #define USBSTS_SSS (1<<8)
91 #define USBSTS_RSS (1<<9)
92 #define USBSTS_SRE (1<<10)
93 #define USBSTS_CNR (1<<11)
94 #define USBSTS_HCE (1<<12)
97 #define PORTSC_CCS (1<<0)
98 #define PORTSC_PED (1<<1)
99 #define PORTSC_OCA (1<<3)
100 #define PORTSC_PR (1<<4)
101 #define PORTSC_PLS_SHIFT 5
102 #define PORTSC_PLS_MASK 0xf
103 #define PORTSC_PP (1<<9)
104 #define PORTSC_SPEED_SHIFT 10
105 #define PORTSC_SPEED_MASK 0xf
106 #define PORTSC_SPEED_FULL (1<<10)
107 #define PORTSC_SPEED_LOW (2<<10)
108 #define PORTSC_SPEED_HIGH (3<<10)
109 #define PORTSC_SPEED_SUPER (4<<10)
110 #define PORTSC_PIC_SHIFT 14
111 #define PORTSC_PIC_MASK 0x3
112 #define PORTSC_LWS (1<<16)
113 #define PORTSC_CSC (1<<17)
114 #define PORTSC_PEC (1<<18)
115 #define PORTSC_WRC (1<<19)
116 #define PORTSC_OCC (1<<20)
117 #define PORTSC_PRC (1<<21)
118 #define PORTSC_PLC (1<<22)
119 #define PORTSC_CEC (1<<23)
120 #define PORTSC_CAS (1<<24)
121 #define PORTSC_WCE (1<<25)
122 #define PORTSC_WDE (1<<26)
123 #define PORTSC_WOE (1<<27)
124 #define PORTSC_DR (1<<30)
125 #define PORTSC_WPR (1<<31)
127 #define CRCR_RCS (1<<0)
128 #define CRCR_CS (1<<1)
129 #define CRCR_CA (1<<2)
130 #define CRCR_CRR (1<<3)
132 #define IMAN_IP (1<<0)
133 #define IMAN_IE (1<<1)
135 #define ERDP_EHB (1<<3)
138 typedef struct XHCITRB
{
157 PLS_COMPILANCE_MODE
= 10,
162 #define CR_LINK TR_LINK
165 #define TRB_TYPE_SHIFT 10
166 #define TRB_TYPE_MASK 0x3f
167 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
169 #define TRB_EV_ED (1<<2)
171 #define TRB_TR_ENT (1<<1)
172 #define TRB_TR_ISP (1<<2)
173 #define TRB_TR_NS (1<<3)
174 #define TRB_TR_CH (1<<4)
175 #define TRB_TR_IOC (1<<5)
176 #define TRB_TR_IDT (1<<6)
177 #define TRB_TR_TBC_SHIFT 7
178 #define TRB_TR_TBC_MASK 0x3
179 #define TRB_TR_BEI (1<<9)
180 #define TRB_TR_TLBPC_SHIFT 16
181 #define TRB_TR_TLBPC_MASK 0xf
182 #define TRB_TR_FRAMEID_SHIFT 20
183 #define TRB_TR_FRAMEID_MASK 0x7ff
184 #define TRB_TR_SIA (1<<31)
186 #define TRB_TR_DIR (1<<16)
188 #define TRB_CR_SLOTID_SHIFT 24
189 #define TRB_CR_SLOTID_MASK 0xff
190 #define TRB_CR_EPID_SHIFT 16
191 #define TRB_CR_EPID_MASK 0x1f
193 #define TRB_CR_BSR (1<<9)
194 #define TRB_CR_DC (1<<9)
196 #define TRB_LK_TC (1<<1)
198 #define TRB_INTR_SHIFT 22
199 #define TRB_INTR_MASK 0x3ff
200 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
202 #define EP_TYPE_MASK 0x7
203 #define EP_TYPE_SHIFT 3
205 #define EP_STATE_MASK 0x7
206 #define EP_DISABLED (0<<0)
207 #define EP_RUNNING (1<<0)
208 #define EP_HALTED (2<<0)
209 #define EP_STOPPED (3<<0)
210 #define EP_ERROR (4<<0)
212 #define SLOT_STATE_MASK 0x1f
213 #define SLOT_STATE_SHIFT 27
214 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
215 #define SLOT_ENABLED 0
216 #define SLOT_DEFAULT 1
217 #define SLOT_ADDRESSED 2
218 #define SLOT_CONFIGURED 3
220 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
221 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
223 #define get_field(data, field) \
224 (((data) >> field##_SHIFT) & field##_MASK)
226 #define set_field(data, newval, field) do { \
227 uint32_t val = *data; \
228 val &= ~(field##_MASK << field##_SHIFT); \
229 val |= ((newval) & field##_MASK) << field##_SHIFT; \
233 typedef enum EPType
{
244 typedef struct XHCITransfer
{
245 XHCIEPContext
*epctx
;
252 unsigned int iso_pkts
;
253 unsigned int streamid
;
258 unsigned int trb_count
;
264 unsigned int pktsize
;
265 unsigned int cur_pkt
;
267 uint64_t mfindex_kick
;
269 QTAILQ_ENTRY(XHCITransfer
) next
;
272 struct XHCIStreamContext
{
278 struct XHCIEPContext
{
285 QTAILQ_HEAD(, XHCITransfer
) transfers
;
289 unsigned int max_psize
;
291 uint32_t kick_active
;
294 unsigned int max_pstreams
;
296 unsigned int nr_pstreams
;
297 XHCIStreamContext
*pstreams
;
299 /* iso xfer scheduling */
300 unsigned int interval
;
301 int64_t mfindex_last
;
302 QEMUTimer
*kick_timer
;
305 typedef struct XHCIEvRingSeg
{
312 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
313 unsigned int epid
, unsigned int streamid
);
314 static void xhci_kick_epctx(XHCIEPContext
*epctx
, unsigned int streamid
);
315 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
317 static void xhci_xfer_report(XHCITransfer
*xfer
);
318 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
319 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
320 static USBEndpoint
*xhci_epid_to_usbep(XHCIEPContext
*epctx
);
322 static const char *TRBType_names
[] = {
323 [TRB_RESERVED
] = "TRB_RESERVED",
324 [TR_NORMAL
] = "TR_NORMAL",
325 [TR_SETUP
] = "TR_SETUP",
326 [TR_DATA
] = "TR_DATA",
327 [TR_STATUS
] = "TR_STATUS",
328 [TR_ISOCH
] = "TR_ISOCH",
329 [TR_LINK
] = "TR_LINK",
330 [TR_EVDATA
] = "TR_EVDATA",
331 [TR_NOOP
] = "TR_NOOP",
332 [CR_ENABLE_SLOT
] = "CR_ENABLE_SLOT",
333 [CR_DISABLE_SLOT
] = "CR_DISABLE_SLOT",
334 [CR_ADDRESS_DEVICE
] = "CR_ADDRESS_DEVICE",
335 [CR_CONFIGURE_ENDPOINT
] = "CR_CONFIGURE_ENDPOINT",
336 [CR_EVALUATE_CONTEXT
] = "CR_EVALUATE_CONTEXT",
337 [CR_RESET_ENDPOINT
] = "CR_RESET_ENDPOINT",
338 [CR_STOP_ENDPOINT
] = "CR_STOP_ENDPOINT",
339 [CR_SET_TR_DEQUEUE
] = "CR_SET_TR_DEQUEUE",
340 [CR_RESET_DEVICE
] = "CR_RESET_DEVICE",
341 [CR_FORCE_EVENT
] = "CR_FORCE_EVENT",
342 [CR_NEGOTIATE_BW
] = "CR_NEGOTIATE_BW",
343 [CR_SET_LATENCY_TOLERANCE
] = "CR_SET_LATENCY_TOLERANCE",
344 [CR_GET_PORT_BANDWIDTH
] = "CR_GET_PORT_BANDWIDTH",
345 [CR_FORCE_HEADER
] = "CR_FORCE_HEADER",
346 [CR_NOOP
] = "CR_NOOP",
347 [ER_TRANSFER
] = "ER_TRANSFER",
348 [ER_COMMAND_COMPLETE
] = "ER_COMMAND_COMPLETE",
349 [ER_PORT_STATUS_CHANGE
] = "ER_PORT_STATUS_CHANGE",
350 [ER_BANDWIDTH_REQUEST
] = "ER_BANDWIDTH_REQUEST",
351 [ER_DOORBELL
] = "ER_DOORBELL",
352 [ER_HOST_CONTROLLER
] = "ER_HOST_CONTROLLER",
353 [ER_DEVICE_NOTIFICATION
] = "ER_DEVICE_NOTIFICATION",
354 [ER_MFINDEX_WRAP
] = "ER_MFINDEX_WRAP",
355 [CR_VENDOR_NEC_FIRMWARE_REVISION
] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
356 [CR_VENDOR_NEC_CHALLENGE_RESPONSE
] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
359 static const char *TRBCCode_names
[] = {
360 [CC_INVALID
] = "CC_INVALID",
361 [CC_SUCCESS
] = "CC_SUCCESS",
362 [CC_DATA_BUFFER_ERROR
] = "CC_DATA_BUFFER_ERROR",
363 [CC_BABBLE_DETECTED
] = "CC_BABBLE_DETECTED",
364 [CC_USB_TRANSACTION_ERROR
] = "CC_USB_TRANSACTION_ERROR",
365 [CC_TRB_ERROR
] = "CC_TRB_ERROR",
366 [CC_STALL_ERROR
] = "CC_STALL_ERROR",
367 [CC_RESOURCE_ERROR
] = "CC_RESOURCE_ERROR",
368 [CC_BANDWIDTH_ERROR
] = "CC_BANDWIDTH_ERROR",
369 [CC_NO_SLOTS_ERROR
] = "CC_NO_SLOTS_ERROR",
370 [CC_INVALID_STREAM_TYPE_ERROR
] = "CC_INVALID_STREAM_TYPE_ERROR",
371 [CC_SLOT_NOT_ENABLED_ERROR
] = "CC_SLOT_NOT_ENABLED_ERROR",
372 [CC_EP_NOT_ENABLED_ERROR
] = "CC_EP_NOT_ENABLED_ERROR",
373 [CC_SHORT_PACKET
] = "CC_SHORT_PACKET",
374 [CC_RING_UNDERRUN
] = "CC_RING_UNDERRUN",
375 [CC_RING_OVERRUN
] = "CC_RING_OVERRUN",
376 [CC_VF_ER_FULL
] = "CC_VF_ER_FULL",
377 [CC_PARAMETER_ERROR
] = "CC_PARAMETER_ERROR",
378 [CC_BANDWIDTH_OVERRUN
] = "CC_BANDWIDTH_OVERRUN",
379 [CC_CONTEXT_STATE_ERROR
] = "CC_CONTEXT_STATE_ERROR",
380 [CC_NO_PING_RESPONSE_ERROR
] = "CC_NO_PING_RESPONSE_ERROR",
381 [CC_EVENT_RING_FULL_ERROR
] = "CC_EVENT_RING_FULL_ERROR",
382 [CC_INCOMPATIBLE_DEVICE_ERROR
] = "CC_INCOMPATIBLE_DEVICE_ERROR",
383 [CC_MISSED_SERVICE_ERROR
] = "CC_MISSED_SERVICE_ERROR",
384 [CC_COMMAND_RING_STOPPED
] = "CC_COMMAND_RING_STOPPED",
385 [CC_COMMAND_ABORTED
] = "CC_COMMAND_ABORTED",
386 [CC_STOPPED
] = "CC_STOPPED",
387 [CC_STOPPED_LENGTH_INVALID
] = "CC_STOPPED_LENGTH_INVALID",
388 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
]
389 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
390 [CC_ISOCH_BUFFER_OVERRUN
] = "CC_ISOCH_BUFFER_OVERRUN",
391 [CC_EVENT_LOST_ERROR
] = "CC_EVENT_LOST_ERROR",
392 [CC_UNDEFINED_ERROR
] = "CC_UNDEFINED_ERROR",
393 [CC_INVALID_STREAM_ID_ERROR
] = "CC_INVALID_STREAM_ID_ERROR",
394 [CC_SECONDARY_BANDWIDTH_ERROR
] = "CC_SECONDARY_BANDWIDTH_ERROR",
395 [CC_SPLIT_TRANSACTION_ERROR
] = "CC_SPLIT_TRANSACTION_ERROR",
398 static const char *ep_state_names
[] = {
399 [EP_DISABLED
] = "disabled",
400 [EP_RUNNING
] = "running",
401 [EP_HALTED
] = "halted",
402 [EP_STOPPED
] = "stopped",
403 [EP_ERROR
] = "error",
406 static const char *lookup_name(uint32_t index
, const char **list
, uint32_t llen
)
408 if (index
>= llen
|| list
[index
] == NULL
) {
414 static const char *trb_name(XHCITRB
*trb
)
416 return lookup_name(TRB_TYPE(*trb
), TRBType_names
,
417 ARRAY_SIZE(TRBType_names
));
420 static const char *event_name(XHCIEvent
*event
)
422 return lookup_name(event
->ccode
, TRBCCode_names
,
423 ARRAY_SIZE(TRBCCode_names
));
426 static const char *ep_state_name(uint32_t state
)
428 return lookup_name(state
, ep_state_names
,
429 ARRAY_SIZE(ep_state_names
));
432 static bool xhci_get_flag(XHCIState
*xhci
, enum xhci_flags bit
)
434 return xhci
->flags
& (1 << bit
);
437 static void xhci_set_flag(XHCIState
*xhci
, enum xhci_flags bit
)
439 xhci
->flags
|= (1 << bit
);
442 static uint64_t xhci_mfindex_get(XHCIState
*xhci
)
444 int64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
445 return (now
- xhci
->mfindex_start
) / 125000;
448 static void xhci_mfwrap_update(XHCIState
*xhci
)
450 const uint32_t bits
= USBCMD_RS
| USBCMD_EWE
;
451 uint32_t mfindex
, left
;
454 if ((xhci
->usbcmd
& bits
) == bits
) {
455 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
456 mfindex
= ((now
- xhci
->mfindex_start
) / 125000) & 0x3fff;
457 left
= 0x4000 - mfindex
;
458 timer_mod(xhci
->mfwrap_timer
, now
+ left
* 125000);
460 timer_del(xhci
->mfwrap_timer
);
464 static void xhci_mfwrap_timer(void *opaque
)
466 XHCIState
*xhci
= opaque
;
467 XHCIEvent wrap
= { ER_MFINDEX_WRAP
, CC_SUCCESS
};
469 xhci_event(xhci
, &wrap
, 0);
470 xhci_mfwrap_update(xhci
);
473 static inline dma_addr_t
xhci_addr64(uint32_t low
, uint32_t high
)
475 if (sizeof(dma_addr_t
) == 4) {
478 return low
| (((dma_addr_t
)high
<< 16) << 16);
482 static inline dma_addr_t
xhci_mask64(uint64_t addr
)
484 if (sizeof(dma_addr_t
) == 4) {
485 return addr
& 0xffffffff;
491 static inline void xhci_dma_read_u32s(XHCIState
*xhci
, dma_addr_t addr
,
492 uint32_t *buf
, size_t len
)
496 assert((len
% sizeof(uint32_t)) == 0);
498 pci_dma_read(PCI_DEVICE(xhci
), addr
, buf
, len
);
500 for (i
= 0; i
< (len
/ sizeof(uint32_t)); i
++) {
501 buf
[i
] = le32_to_cpu(buf
[i
]);
505 static inline void xhci_dma_write_u32s(XHCIState
*xhci
, dma_addr_t addr
,
506 uint32_t *buf
, size_t len
)
510 uint32_t n
= len
/ sizeof(uint32_t);
512 assert((len
% sizeof(uint32_t)) == 0);
513 assert(n
<= ARRAY_SIZE(tmp
));
515 for (i
= 0; i
< n
; i
++) {
516 tmp
[i
] = cpu_to_le32(buf
[i
]);
518 pci_dma_write(PCI_DEVICE(xhci
), addr
, tmp
, len
);
521 static XHCIPort
*xhci_lookup_port(XHCIState
*xhci
, struct USBPort
*uport
)
528 switch (uport
->dev
->speed
) {
532 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
533 index
= uport
->index
+ xhci
->numports_3
;
535 index
= uport
->index
;
538 case USB_SPEED_SUPER
:
539 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
540 index
= uport
->index
;
542 index
= uport
->index
+ xhci
->numports_2
;
548 return &xhci
->ports
[index
];
551 static void xhci_intx_update(XHCIState
*xhci
)
553 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
556 if (msix_enabled(pci_dev
) ||
557 msi_enabled(pci_dev
)) {
561 if (xhci
->intr
[0].iman
& IMAN_IP
&&
562 xhci
->intr
[0].iman
& IMAN_IE
&&
563 xhci
->usbcmd
& USBCMD_INTE
) {
567 trace_usb_xhci_irq_intx(level
);
568 pci_set_irq(pci_dev
, level
);
571 static void xhci_msix_update(XHCIState
*xhci
, int v
)
573 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
576 if (!msix_enabled(pci_dev
)) {
580 enabled
= xhci
->intr
[v
].iman
& IMAN_IE
;
581 if (enabled
== xhci
->intr
[v
].msix_used
) {
586 trace_usb_xhci_irq_msix_use(v
);
587 msix_vector_use(pci_dev
, v
);
588 xhci
->intr
[v
].msix_used
= true;
590 trace_usb_xhci_irq_msix_unuse(v
);
591 msix_vector_unuse(pci_dev
, v
);
592 xhci
->intr
[v
].msix_used
= false;
596 static void xhci_intr_raise(XHCIState
*xhci
, int v
)
598 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
599 bool pending
= (xhci
->intr
[v
].erdp_low
& ERDP_EHB
);
601 xhci
->intr
[v
].erdp_low
|= ERDP_EHB
;
602 xhci
->intr
[v
].iman
|= IMAN_IP
;
603 xhci
->usbsts
|= USBSTS_EINT
;
608 if (!(xhci
->intr
[v
].iman
& IMAN_IE
)) {
612 if (!(xhci
->usbcmd
& USBCMD_INTE
)) {
616 if (msix_enabled(pci_dev
)) {
617 trace_usb_xhci_irq_msix(v
);
618 msix_notify(pci_dev
, v
);
622 if (msi_enabled(pci_dev
)) {
623 trace_usb_xhci_irq_msi(v
);
624 msi_notify(pci_dev
, v
);
629 trace_usb_xhci_irq_intx(1);
630 pci_irq_assert(pci_dev
);
634 static inline int xhci_running(XHCIState
*xhci
)
636 return !(xhci
->usbsts
& USBSTS_HCH
);
639 static void xhci_die(XHCIState
*xhci
)
641 xhci
->usbsts
|= USBSTS_HCE
;
642 DPRINTF("xhci: asserted controller error\n");
645 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
647 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
648 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
652 ev_trb
.parameter
= cpu_to_le64(event
->ptr
);
653 ev_trb
.status
= cpu_to_le32(event
->length
| (event
->ccode
<< 24));
654 ev_trb
.control
= (event
->slotid
<< 24) | (event
->epid
<< 16) |
655 event
->flags
| (event
->type
<< TRB_TYPE_SHIFT
);
657 ev_trb
.control
|= TRB_C
;
659 ev_trb
.control
= cpu_to_le32(ev_trb
.control
);
661 trace_usb_xhci_queue_event(v
, intr
->er_ep_idx
, trb_name(&ev_trb
),
662 event_name(event
), ev_trb
.parameter
,
663 ev_trb
.status
, ev_trb
.control
);
665 addr
= intr
->er_start
+ TRB_SIZE
*intr
->er_ep_idx
;
666 pci_dma_write(pci_dev
, addr
, &ev_trb
, TRB_SIZE
);
669 if (intr
->er_ep_idx
>= intr
->er_size
) {
671 intr
->er_pcs
= !intr
->er_pcs
;
675 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
677 XHCIInterrupter
*intr
;
681 if (v
>= xhci
->numintrs
) {
682 DPRINTF("intr nr out of range (%d >= %d)\n", v
, xhci
->numintrs
);
685 intr
= &xhci
->intr
[v
];
687 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
688 if (erdp
< intr
->er_start
||
689 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
690 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
691 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
692 v
, intr
->er_start
, intr
->er_size
);
697 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
698 assert(dp_idx
< intr
->er_size
);
700 if ((intr
->er_ep_idx
+ 2) % intr
->er_size
== dp_idx
) {
701 DPRINTF("xhci: ER %d full, send ring full error\n", v
);
702 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
703 xhci_write_event(xhci
, &full
, v
);
704 } else if ((intr
->er_ep_idx
+ 1) % intr
->er_size
== dp_idx
) {
705 DPRINTF("xhci: ER %d full, drop event\n", v
);
707 xhci_write_event(xhci
, event
, v
);
710 xhci_intr_raise(xhci
, v
);
713 static void xhci_ring_init(XHCIState
*xhci
, XHCIRing
*ring
,
716 ring
->dequeue
= base
;
720 static TRBType
xhci_ring_fetch(XHCIState
*xhci
, XHCIRing
*ring
, XHCITRB
*trb
,
723 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
724 uint32_t link_cnt
= 0;
728 pci_dma_read(pci_dev
, ring
->dequeue
, trb
, TRB_SIZE
);
729 trb
->addr
= ring
->dequeue
;
730 trb
->ccs
= ring
->ccs
;
731 le64_to_cpus(&trb
->parameter
);
732 le32_to_cpus(&trb
->status
);
733 le32_to_cpus(&trb
->control
);
735 trace_usb_xhci_fetch_trb(ring
->dequeue
, trb_name(trb
),
736 trb
->parameter
, trb
->status
, trb
->control
);
738 if ((trb
->control
& TRB_C
) != ring
->ccs
) {
742 type
= TRB_TYPE(*trb
);
744 if (type
!= TR_LINK
) {
746 *addr
= ring
->dequeue
;
748 ring
->dequeue
+= TRB_SIZE
;
751 if (++link_cnt
> TRB_LINK_LIMIT
) {
752 trace_usb_xhci_enforced_limit("trb-link");
755 ring
->dequeue
= xhci_mask64(trb
->parameter
);
756 if (trb
->control
& TRB_LK_TC
) {
757 ring
->ccs
= !ring
->ccs
;
763 static int xhci_ring_chain_length(XHCIState
*xhci
, const XHCIRing
*ring
)
765 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
768 dma_addr_t dequeue
= ring
->dequeue
;
769 bool ccs
= ring
->ccs
;
770 /* hack to bundle together the two/three TDs that make a setup transfer */
771 bool control_td_set
= 0;
772 uint32_t link_cnt
= 0;
776 pci_dma_read(pci_dev
, dequeue
, &trb
, TRB_SIZE
);
777 le64_to_cpus(&trb
.parameter
);
778 le32_to_cpus(&trb
.status
);
779 le32_to_cpus(&trb
.control
);
781 if ((trb
.control
& TRB_C
) != ccs
) {
785 type
= TRB_TYPE(trb
);
787 if (type
== TR_LINK
) {
788 if (++link_cnt
> TRB_LINK_LIMIT
) {
791 dequeue
= xhci_mask64(trb
.parameter
);
792 if (trb
.control
& TRB_LK_TC
) {
801 if (type
== TR_SETUP
) {
803 } else if (type
== TR_STATUS
) {
807 if (!control_td_set
&& !(trb
.control
& TRB_TR_CH
)) {
813 static void xhci_er_reset(XHCIState
*xhci
, int v
)
815 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
817 dma_addr_t erstba
= xhci_addr64(intr
->erstba_low
, intr
->erstba_high
);
819 if (intr
->erstsz
== 0 || erstba
== 0) {
825 /* cache the (sole) event ring segment location */
826 if (intr
->erstsz
!= 1) {
827 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr
->erstsz
);
831 pci_dma_read(PCI_DEVICE(xhci
), erstba
, &seg
, sizeof(seg
));
832 le32_to_cpus(&seg
.addr_low
);
833 le32_to_cpus(&seg
.addr_high
);
834 le32_to_cpus(&seg
.size
);
835 if (seg
.size
< 16 || seg
.size
> 4096) {
836 DPRINTF("xhci: invalid value for segment size: %d\n", seg
.size
);
840 intr
->er_start
= xhci_addr64(seg
.addr_low
, seg
.addr_high
);
841 intr
->er_size
= seg
.size
;
846 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT
" [%d]\n",
847 v
, intr
->er_start
, intr
->er_size
);
850 static void xhci_run(XHCIState
*xhci
)
852 trace_usb_xhci_run();
853 xhci
->usbsts
&= ~USBSTS_HCH
;
854 xhci
->mfindex_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
857 static void xhci_stop(XHCIState
*xhci
)
859 trace_usb_xhci_stop();
860 xhci
->usbsts
|= USBSTS_HCH
;
861 xhci
->crcr_low
&= ~CRCR_CRR
;
864 static XHCIStreamContext
*xhci_alloc_stream_contexts(unsigned count
,
867 XHCIStreamContext
*stctx
;
870 stctx
= g_new0(XHCIStreamContext
, count
);
871 for (i
= 0; i
< count
; i
++) {
872 stctx
[i
].pctx
= base
+ i
* 16;
878 static void xhci_reset_streams(XHCIEPContext
*epctx
)
882 for (i
= 0; i
< epctx
->nr_pstreams
; i
++) {
883 epctx
->pstreams
[i
].sct
= -1;
887 static void xhci_alloc_streams(XHCIEPContext
*epctx
, dma_addr_t base
)
889 assert(epctx
->pstreams
== NULL
);
890 epctx
->nr_pstreams
= 2 << epctx
->max_pstreams
;
891 epctx
->pstreams
= xhci_alloc_stream_contexts(epctx
->nr_pstreams
, base
);
894 static void xhci_free_streams(XHCIEPContext
*epctx
)
896 assert(epctx
->pstreams
!= NULL
);
898 g_free(epctx
->pstreams
);
899 epctx
->pstreams
= NULL
;
900 epctx
->nr_pstreams
= 0;
903 static int xhci_epmask_to_eps_with_streams(XHCIState
*xhci
,
906 XHCIEPContext
**epctxs
,
910 XHCIEPContext
*epctx
;
914 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
916 slot
= &xhci
->slots
[slotid
- 1];
918 for (i
= 2, j
= 0; i
<= 31; i
++) {
919 if (!(epmask
& (1u << i
))) {
923 epctx
= slot
->eps
[i
- 1];
924 ep
= xhci_epid_to_usbep(epctx
);
925 if (!epctx
|| !epctx
->nr_pstreams
|| !ep
) {
937 static void xhci_free_device_streams(XHCIState
*xhci
, unsigned int slotid
,
940 USBEndpoint
*eps
[30];
943 nr_eps
= xhci_epmask_to_eps_with_streams(xhci
, slotid
, epmask
, NULL
, eps
);
945 usb_device_free_streams(eps
[0]->dev
, eps
, nr_eps
);
949 static TRBCCode
xhci_alloc_device_streams(XHCIState
*xhci
, unsigned int slotid
,
952 XHCIEPContext
*epctxs
[30];
953 USBEndpoint
*eps
[30];
954 int i
, r
, nr_eps
, req_nr_streams
, dev_max_streams
;
956 nr_eps
= xhci_epmask_to_eps_with_streams(xhci
, slotid
, epmask
, epctxs
,
962 req_nr_streams
= epctxs
[0]->nr_pstreams
;
963 dev_max_streams
= eps
[0]->max_streams
;
965 for (i
= 1; i
< nr_eps
; i
++) {
967 * HdG: I don't expect these to ever trigger, but if they do we need
968 * to come up with another solution, ie group identical endpoints
969 * together and make an usb_device_alloc_streams call per group.
971 if (epctxs
[i
]->nr_pstreams
!= req_nr_streams
) {
972 FIXME("guest streams config not identical for all eps");
973 return CC_RESOURCE_ERROR
;
975 if (eps
[i
]->max_streams
!= dev_max_streams
) {
976 FIXME("device streams config not identical for all eps");
977 return CC_RESOURCE_ERROR
;
982 * max-streams in both the device descriptor and in the controller is a
983 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
984 * streams the guest will ask for 5 rounded up to the next power of 2 which
985 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
987 * For redirected devices however this is an issue, as there we must ask
988 * the real xhci controller to alloc streams, and the host driver for the
989 * real xhci controller will likely disallow allocating more streams then
990 * the device can handle.
992 * So we limit the requested nr_streams to the maximum number the device
995 if (req_nr_streams
> dev_max_streams
) {
996 req_nr_streams
= dev_max_streams
;
999 r
= usb_device_alloc_streams(eps
[0]->dev
, eps
, nr_eps
, req_nr_streams
);
1001 DPRINTF("xhci: alloc streams failed\n");
1002 return CC_RESOURCE_ERROR
;
1008 static XHCIStreamContext
*xhci_find_stream(XHCIEPContext
*epctx
,
1009 unsigned int streamid
,
1012 XHCIStreamContext
*sctx
;
1014 uint32_t ctx
[2], sct
;
1016 assert(streamid
!= 0);
1018 if (streamid
>= epctx
->nr_pstreams
) {
1019 *cc_error
= CC_INVALID_STREAM_ID_ERROR
;
1022 sctx
= epctx
->pstreams
+ streamid
;
1024 FIXME("secondary streams not implemented yet");
1027 if (sctx
->sct
== -1) {
1028 xhci_dma_read_u32s(epctx
->xhci
, sctx
->pctx
, ctx
, sizeof(ctx
));
1029 sct
= (ctx
[0] >> 1) & 0x07;
1030 if (epctx
->lsa
&& sct
!= 1) {
1031 *cc_error
= CC_INVALID_STREAM_TYPE_ERROR
;
1035 base
= xhci_addr64(ctx
[0] & ~0xf, ctx
[1]);
1036 xhci_ring_init(epctx
->xhci
, &sctx
->ring
, base
);
1041 static void xhci_set_ep_state(XHCIState
*xhci
, XHCIEPContext
*epctx
,
1042 XHCIStreamContext
*sctx
, uint32_t state
)
1044 XHCIRing
*ring
= NULL
;
1048 xhci_dma_read_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1049 ctx
[0] &= ~EP_STATE_MASK
;
1052 /* update ring dequeue ptr */
1053 if (epctx
->nr_pstreams
) {
1056 xhci_dma_read_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1058 ctx2
[0] |= sctx
->ring
.dequeue
| sctx
->ring
.ccs
;
1059 ctx2
[1] = (sctx
->ring
.dequeue
>> 16) >> 16;
1060 xhci_dma_write_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1063 ring
= &epctx
->ring
;
1066 ctx
[2] = ring
->dequeue
| ring
->ccs
;
1067 ctx
[3] = (ring
->dequeue
>> 16) >> 16;
1069 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT
" state=%d dequeue=%08x%08x\n",
1070 epctx
->pctx
, state
, ctx
[3], ctx
[2]);
1073 xhci_dma_write_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1074 if (epctx
->state
!= state
) {
1075 trace_usb_xhci_ep_state(epctx
->slotid
, epctx
->epid
,
1076 ep_state_name(epctx
->state
),
1077 ep_state_name(state
));
1079 epctx
->state
= state
;
1082 static void xhci_ep_kick_timer(void *opaque
)
1084 XHCIEPContext
*epctx
= opaque
;
1085 xhci_kick_epctx(epctx
, 0);
1088 static XHCIEPContext
*xhci_alloc_epctx(XHCIState
*xhci
,
1089 unsigned int slotid
,
1092 XHCIEPContext
*epctx
;
1094 epctx
= g_new0(XHCIEPContext
, 1);
1096 epctx
->slotid
= slotid
;
1099 QTAILQ_INIT(&epctx
->transfers
);
1100 epctx
->kick_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, xhci_ep_kick_timer
, epctx
);
1105 static void xhci_init_epctx(XHCIEPContext
*epctx
,
1106 dma_addr_t pctx
, uint32_t *ctx
)
1110 dequeue
= xhci_addr64(ctx
[2] & ~0xf, ctx
[3]);
1112 epctx
->type
= (ctx
[1] >> EP_TYPE_SHIFT
) & EP_TYPE_MASK
;
1114 epctx
->max_psize
= ctx
[1]>>16;
1115 epctx
->max_psize
*= 1+((ctx
[1]>>8)&0xff);
1116 epctx
->max_pstreams
= (ctx
[0] >> 10) & epctx
->xhci
->max_pstreams_mask
;
1117 epctx
->lsa
= (ctx
[0] >> 15) & 1;
1118 if (epctx
->max_pstreams
) {
1119 xhci_alloc_streams(epctx
, dequeue
);
1121 xhci_ring_init(epctx
->xhci
, &epctx
->ring
, dequeue
);
1122 epctx
->ring
.ccs
= ctx
[2] & 1;
1125 epctx
->interval
= 1 << ((ctx
[0] >> 16) & 0xff);
1128 static TRBCCode
xhci_enable_ep(XHCIState
*xhci
, unsigned int slotid
,
1129 unsigned int epid
, dma_addr_t pctx
,
1133 XHCIEPContext
*epctx
;
1135 trace_usb_xhci_ep_enable(slotid
, epid
);
1136 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1137 assert(epid
>= 1 && epid
<= 31);
1139 slot
= &xhci
->slots
[slotid
-1];
1140 if (slot
->eps
[epid
-1]) {
1141 xhci_disable_ep(xhci
, slotid
, epid
);
1144 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
1145 slot
->eps
[epid
-1] = epctx
;
1146 xhci_init_epctx(epctx
, pctx
, ctx
);
1148 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1149 "size is %d\n", epid
/2, epid
%2, epctx
->type
, epctx
->max_psize
);
1151 epctx
->mfindex_last
= 0;
1153 epctx
->state
= EP_RUNNING
;
1154 ctx
[0] &= ~EP_STATE_MASK
;
1155 ctx
[0] |= EP_RUNNING
;
1160 static XHCITransfer
*xhci_ep_alloc_xfer(XHCIEPContext
*epctx
,
1163 uint32_t limit
= epctx
->nr_pstreams
+ 16;
1166 if (epctx
->xfer_count
>= limit
) {
1170 xfer
= g_new0(XHCITransfer
, 1);
1171 xfer
->epctx
= epctx
;
1172 xfer
->trbs
= g_new(XHCITRB
, length
);
1173 xfer
->trb_count
= length
;
1174 usb_packet_init(&xfer
->packet
);
1176 QTAILQ_INSERT_TAIL(&epctx
->transfers
, xfer
, next
);
1177 epctx
->xfer_count
++;
1182 static void xhci_ep_free_xfer(XHCITransfer
*xfer
)
1184 QTAILQ_REMOVE(&xfer
->epctx
->transfers
, xfer
, next
);
1185 xfer
->epctx
->xfer_count
--;
1187 usb_packet_cleanup(&xfer
->packet
);
1192 static int xhci_ep_nuke_one_xfer(XHCITransfer
*t
, TRBCCode report
)
1196 if (report
&& (t
->running_async
|| t
->running_retry
)) {
1198 xhci_xfer_report(t
);
1201 if (t
->running_async
) {
1202 usb_cancel_packet(&t
->packet
);
1203 t
->running_async
= 0;
1206 if (t
->running_retry
) {
1208 t
->epctx
->retry
= NULL
;
1209 timer_del(t
->epctx
->kick_timer
);
1211 t
->running_retry
= 0;
1222 static int xhci_ep_nuke_xfers(XHCIState
*xhci
, unsigned int slotid
,
1223 unsigned int epid
, TRBCCode report
)
1226 XHCIEPContext
*epctx
;
1229 USBEndpoint
*ep
= NULL
;
1230 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1231 assert(epid
>= 1 && epid
<= 31);
1233 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid
, epid
);
1235 slot
= &xhci
->slots
[slotid
-1];
1237 if (!slot
->eps
[epid
-1]) {
1241 epctx
= slot
->eps
[epid
-1];
1244 xfer
= QTAILQ_FIRST(&epctx
->transfers
);
1248 killed
+= xhci_ep_nuke_one_xfer(xfer
, report
);
1250 report
= 0; /* Only report once */
1252 xhci_ep_free_xfer(xfer
);
1255 ep
= xhci_epid_to_usbep(epctx
);
1257 usb_device_ep_stopped(ep
->dev
, ep
);
1262 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
1266 XHCIEPContext
*epctx
;
1268 trace_usb_xhci_ep_disable(slotid
, epid
);
1269 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1270 assert(epid
>= 1 && epid
<= 31);
1272 slot
= &xhci
->slots
[slotid
-1];
1274 if (!slot
->eps
[epid
-1]) {
1275 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid
, epid
);
1279 xhci_ep_nuke_xfers(xhci
, slotid
, epid
, 0);
1281 epctx
= slot
->eps
[epid
-1];
1283 if (epctx
->nr_pstreams
) {
1284 xhci_free_streams(epctx
);
1287 /* only touch guest RAM if we're not resetting the HC */
1288 if (xhci
->dcbaap_low
|| xhci
->dcbaap_high
) {
1289 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_DISABLED
);
1292 timer_free(epctx
->kick_timer
);
1294 slot
->eps
[epid
-1] = NULL
;
1299 static TRBCCode
xhci_stop_ep(XHCIState
*xhci
, unsigned int slotid
,
1303 XHCIEPContext
*epctx
;
1305 trace_usb_xhci_ep_stop(slotid
, epid
);
1306 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1308 if (epid
< 1 || epid
> 31) {
1309 DPRINTF("xhci: bad ep %d\n", epid
);
1310 return CC_TRB_ERROR
;
1313 slot
= &xhci
->slots
[slotid
-1];
1315 if (!slot
->eps
[epid
-1]) {
1316 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1317 return CC_EP_NOT_ENABLED_ERROR
;
1320 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
, CC_STOPPED
) > 0) {
1321 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1322 "data might be lost\n");
1325 epctx
= slot
->eps
[epid
-1];
1327 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1329 if (epctx
->nr_pstreams
) {
1330 xhci_reset_streams(epctx
);
1336 static TRBCCode
xhci_reset_ep(XHCIState
*xhci
, unsigned int slotid
,
1340 XHCIEPContext
*epctx
;
1342 trace_usb_xhci_ep_reset(slotid
, epid
);
1343 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1345 if (epid
< 1 || epid
> 31) {
1346 DPRINTF("xhci: bad ep %d\n", epid
);
1347 return CC_TRB_ERROR
;
1350 slot
= &xhci
->slots
[slotid
-1];
1352 if (!slot
->eps
[epid
-1]) {
1353 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1354 return CC_EP_NOT_ENABLED_ERROR
;
1357 epctx
= slot
->eps
[epid
-1];
1359 if (epctx
->state
!= EP_HALTED
) {
1360 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1361 epid
, epctx
->state
);
1362 return CC_CONTEXT_STATE_ERROR
;
1365 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
, 0) > 0) {
1366 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1367 "data might be lost\n");
1370 if (!xhci
->slots
[slotid
-1].uport
||
1371 !xhci
->slots
[slotid
-1].uport
->dev
||
1372 !xhci
->slots
[slotid
-1].uport
->dev
->attached
) {
1373 return CC_USB_TRANSACTION_ERROR
;
1376 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1378 if (epctx
->nr_pstreams
) {
1379 xhci_reset_streams(epctx
);
1385 static TRBCCode
xhci_set_ep_dequeue(XHCIState
*xhci
, unsigned int slotid
,
1386 unsigned int epid
, unsigned int streamid
,
1390 XHCIEPContext
*epctx
;
1391 XHCIStreamContext
*sctx
;
1394 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1396 if (epid
< 1 || epid
> 31) {
1397 DPRINTF("xhci: bad ep %d\n", epid
);
1398 return CC_TRB_ERROR
;
1401 trace_usb_xhci_ep_set_dequeue(slotid
, epid
, streamid
, pdequeue
);
1402 dequeue
= xhci_mask64(pdequeue
);
1404 slot
= &xhci
->slots
[slotid
-1];
1406 if (!slot
->eps
[epid
-1]) {
1407 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1408 return CC_EP_NOT_ENABLED_ERROR
;
1411 epctx
= slot
->eps
[epid
-1];
1413 if (epctx
->state
!= EP_STOPPED
) {
1414 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid
);
1415 return CC_CONTEXT_STATE_ERROR
;
1418 if (epctx
->nr_pstreams
) {
1420 sctx
= xhci_find_stream(epctx
, streamid
, &err
);
1424 xhci_ring_init(xhci
, &sctx
->ring
, dequeue
& ~0xf);
1425 sctx
->ring
.ccs
= dequeue
& 1;
1428 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
& ~0xF);
1429 epctx
->ring
.ccs
= dequeue
& 1;
1432 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_STOPPED
);
1437 static int xhci_xfer_create_sgl(XHCITransfer
*xfer
, int in_xfer
)
1439 XHCIState
*xhci
= xfer
->epctx
->xhci
;
1442 xfer
->int_req
= false;
1443 pci_dma_sglist_init(&xfer
->sgl
, PCI_DEVICE(xhci
), xfer
->trb_count
);
1444 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1445 XHCITRB
*trb
= &xfer
->trbs
[i
];
1447 unsigned int chunk
= 0;
1449 if (trb
->control
& TRB_TR_IOC
) {
1450 xfer
->int_req
= true;
1453 switch (TRB_TYPE(*trb
)) {
1455 if ((!(trb
->control
& TRB_TR_DIR
)) != (!in_xfer
)) {
1456 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
1462 addr
= xhci_mask64(trb
->parameter
);
1463 chunk
= trb
->status
& 0x1ffff;
1464 if (trb
->control
& TRB_TR_IDT
) {
1465 if (chunk
> 8 || in_xfer
) {
1466 DPRINTF("xhci: invalid immediate data TRB\n");
1469 qemu_sglist_add(&xfer
->sgl
, trb
->addr
, chunk
);
1471 qemu_sglist_add(&xfer
->sgl
, addr
, chunk
);
1480 qemu_sglist_destroy(&xfer
->sgl
);
1485 static void xhci_xfer_unmap(XHCITransfer
*xfer
)
1487 usb_packet_unmap(&xfer
->packet
, &xfer
->sgl
);
1488 qemu_sglist_destroy(&xfer
->sgl
);
1491 static void xhci_xfer_report(XHCITransfer
*xfer
)
1497 XHCIEvent event
= {ER_TRANSFER
, CC_SUCCESS
};
1498 XHCIState
*xhci
= xfer
->epctx
->xhci
;
1501 left
= xfer
->packet
.actual_length
;
1503 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1504 XHCITRB
*trb
= &xfer
->trbs
[i
];
1505 unsigned int chunk
= 0;
1507 switch (TRB_TYPE(*trb
)) {
1509 chunk
= trb
->status
& 0x1ffff;
1517 chunk
= trb
->status
& 0x1ffff;
1520 if (xfer
->status
== CC_SUCCESS
) {
1533 if (!reported
&& ((trb
->control
& TRB_TR_IOC
) ||
1534 (shortpkt
&& (trb
->control
& TRB_TR_ISP
)) ||
1535 (xfer
->status
!= CC_SUCCESS
&& left
== 0))) {
1536 event
.slotid
= xfer
->epctx
->slotid
;
1537 event
.epid
= xfer
->epctx
->epid
;
1538 event
.length
= (trb
->status
& 0x1ffff) - chunk
;
1540 event
.ptr
= trb
->addr
;
1541 if (xfer
->status
== CC_SUCCESS
) {
1542 event
.ccode
= shortpkt
? CC_SHORT_PACKET
: CC_SUCCESS
;
1544 event
.ccode
= xfer
->status
;
1546 if (TRB_TYPE(*trb
) == TR_EVDATA
) {
1547 event
.ptr
= trb
->parameter
;
1548 event
.flags
|= TRB_EV_ED
;
1549 event
.length
= edtla
& 0xffffff;
1550 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event
.length
);
1553 xhci_event(xhci
, &event
, TRB_INTR(*trb
));
1555 if (xfer
->status
!= CC_SUCCESS
) {
1560 switch (TRB_TYPE(*trb
)) {
1570 static void xhci_stall_ep(XHCITransfer
*xfer
)
1572 XHCIEPContext
*epctx
= xfer
->epctx
;
1573 XHCIState
*xhci
= epctx
->xhci
;
1575 XHCIStreamContext
*sctx
;
1577 if (epctx
->type
== ET_ISO_IN
|| epctx
->type
== ET_ISO_OUT
) {
1578 /* never halt isoch endpoints, 4.10.2 */
1582 if (epctx
->nr_pstreams
) {
1583 sctx
= xhci_find_stream(epctx
, xfer
->streamid
, &err
);
1587 sctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1588 sctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1589 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_HALTED
);
1591 epctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1592 epctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1593 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_HALTED
);
1597 static int xhci_setup_packet(XHCITransfer
*xfer
)
1602 dir
= xfer
->in_xfer
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1604 if (xfer
->packet
.ep
) {
1605 ep
= xfer
->packet
.ep
;
1607 ep
= xhci_epid_to_usbep(xfer
->epctx
);
1609 DPRINTF("xhci: slot %d has no device\n",
1610 xfer
->epctx
->slotid
);
1615 xhci_xfer_create_sgl(xfer
, dir
== USB_TOKEN_IN
); /* Also sets int_req */
1616 usb_packet_setup(&xfer
->packet
, dir
, ep
, xfer
->streamid
,
1617 xfer
->trbs
[0].addr
, false, xfer
->int_req
);
1618 usb_packet_map(&xfer
->packet
, &xfer
->sgl
);
1619 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1620 xfer
->packet
.pid
, ep
->dev
->addr
, ep
->nr
);
1624 static int xhci_try_complete_packet(XHCITransfer
*xfer
)
1626 if (xfer
->packet
.status
== USB_RET_ASYNC
) {
1627 trace_usb_xhci_xfer_async(xfer
);
1628 xfer
->running_async
= 1;
1629 xfer
->running_retry
= 0;
1632 } else if (xfer
->packet
.status
== USB_RET_NAK
) {
1633 trace_usb_xhci_xfer_nak(xfer
);
1634 xfer
->running_async
= 0;
1635 xfer
->running_retry
= 1;
1639 xfer
->running_async
= 0;
1640 xfer
->running_retry
= 0;
1642 xhci_xfer_unmap(xfer
);
1645 if (xfer
->packet
.status
== USB_RET_SUCCESS
) {
1646 trace_usb_xhci_xfer_success(xfer
, xfer
->packet
.actual_length
);
1647 xfer
->status
= CC_SUCCESS
;
1648 xhci_xfer_report(xfer
);
1653 trace_usb_xhci_xfer_error(xfer
, xfer
->packet
.status
);
1654 switch (xfer
->packet
.status
) {
1656 case USB_RET_IOERROR
:
1657 xfer
->status
= CC_USB_TRANSACTION_ERROR
;
1658 xhci_xfer_report(xfer
);
1659 xhci_stall_ep(xfer
);
1662 xfer
->status
= CC_STALL_ERROR
;
1663 xhci_xfer_report(xfer
);
1664 xhci_stall_ep(xfer
);
1666 case USB_RET_BABBLE
:
1667 xfer
->status
= CC_BABBLE_DETECTED
;
1668 xhci_xfer_report(xfer
);
1669 xhci_stall_ep(xfer
);
1672 DPRINTF("%s: FIXME: status = %d\n", __func__
,
1673 xfer
->packet
.status
);
1674 FIXME("unhandled USB_RET_*");
1679 static int xhci_fire_ctl_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
)
1681 XHCITRB
*trb_setup
, *trb_status
;
1682 uint8_t bmRequestType
;
1684 trb_setup
= &xfer
->trbs
[0];
1685 trb_status
= &xfer
->trbs
[xfer
->trb_count
-1];
1687 trace_usb_xhci_xfer_start(xfer
, xfer
->epctx
->slotid
,
1688 xfer
->epctx
->epid
, xfer
->streamid
);
1690 /* at most one Event Data TRB allowed after STATUS */
1691 if (TRB_TYPE(*trb_status
) == TR_EVDATA
&& xfer
->trb_count
> 2) {
1695 /* do some sanity checks */
1696 if (TRB_TYPE(*trb_setup
) != TR_SETUP
) {
1697 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1698 TRB_TYPE(*trb_setup
));
1701 if (TRB_TYPE(*trb_status
) != TR_STATUS
) {
1702 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1703 TRB_TYPE(*trb_status
));
1706 if (!(trb_setup
->control
& TRB_TR_IDT
)) {
1707 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1710 if ((trb_setup
->status
& 0x1ffff) != 8) {
1711 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1712 (trb_setup
->status
& 0x1ffff));
1716 bmRequestType
= trb_setup
->parameter
;
1718 xfer
->in_xfer
= bmRequestType
& USB_DIR_IN
;
1719 xfer
->iso_xfer
= false;
1720 xfer
->timed_xfer
= false;
1722 if (xhci_setup_packet(xfer
) < 0) {
1725 xfer
->packet
.parameter
= trb_setup
->parameter
;
1727 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1728 xhci_try_complete_packet(xfer
);
1732 static void xhci_calc_intr_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1733 XHCIEPContext
*epctx
, uint64_t mfindex
)
1735 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1736 ~(epctx
->interval
-1));
1737 uint64_t kick
= epctx
->mfindex_last
+ epctx
->interval
;
1739 assert(epctx
->interval
!= 0);
1740 xfer
->mfindex_kick
= MAX(asap
, kick
);
1743 static void xhci_calc_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1744 XHCIEPContext
*epctx
, uint64_t mfindex
)
1746 if (xfer
->trbs
[0].control
& TRB_TR_SIA
) {
1747 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1748 ~(epctx
->interval
-1));
1749 if (asap
>= epctx
->mfindex_last
&&
1750 asap
<= epctx
->mfindex_last
+ epctx
->interval
* 4) {
1751 xfer
->mfindex_kick
= epctx
->mfindex_last
+ epctx
->interval
;
1753 xfer
->mfindex_kick
= asap
;
1756 xfer
->mfindex_kick
= ((xfer
->trbs
[0].control
>> TRB_TR_FRAMEID_SHIFT
)
1757 & TRB_TR_FRAMEID_MASK
) << 3;
1758 xfer
->mfindex_kick
|= mfindex
& ~0x3fff;
1759 if (xfer
->mfindex_kick
+ 0x100 < mfindex
) {
1760 xfer
->mfindex_kick
+= 0x4000;
1765 static void xhci_check_intr_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1766 XHCIEPContext
*epctx
, uint64_t mfindex
)
1768 if (xfer
->mfindex_kick
> mfindex
) {
1769 timer_mod(epctx
->kick_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1770 (xfer
->mfindex_kick
- mfindex
) * 125000);
1771 xfer
->running_retry
= 1;
1773 epctx
->mfindex_last
= xfer
->mfindex_kick
;
1774 timer_del(epctx
->kick_timer
);
1775 xfer
->running_retry
= 0;
1780 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1784 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", epctx
->slotid
, epctx
->epid
);
1786 xfer
->in_xfer
= epctx
->type
>>2;
1788 switch(epctx
->type
) {
1792 xfer
->iso_xfer
= false;
1793 xfer
->timed_xfer
= true;
1794 mfindex
= xhci_mfindex_get(xhci
);
1795 xhci_calc_intr_kick(xhci
, xfer
, epctx
, mfindex
);
1796 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1797 if (xfer
->running_retry
) {
1804 xfer
->iso_xfer
= false;
1805 xfer
->timed_xfer
= false;
1810 xfer
->iso_xfer
= true;
1811 xfer
->timed_xfer
= true;
1812 mfindex
= xhci_mfindex_get(xhci
);
1813 xhci_calc_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1814 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1815 if (xfer
->running_retry
) {
1820 trace_usb_xhci_unimplemented("endpoint type", epctx
->type
);
1824 if (xhci_setup_packet(xfer
) < 0) {
1827 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1828 xhci_try_complete_packet(xfer
);
1832 static int xhci_fire_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1834 trace_usb_xhci_xfer_start(xfer
, xfer
->epctx
->slotid
,
1835 xfer
->epctx
->epid
, xfer
->streamid
);
1836 return xhci_submit(xhci
, xfer
, epctx
);
1839 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
1840 unsigned int epid
, unsigned int streamid
)
1842 XHCIEPContext
*epctx
;
1844 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1845 assert(epid
>= 1 && epid
<= 31);
1847 if (!xhci
->slots
[slotid
-1].enabled
) {
1848 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid
);
1851 epctx
= xhci
->slots
[slotid
-1].eps
[epid
-1];
1853 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1858 if (epctx
->kick_active
) {
1861 xhci_kick_epctx(epctx
, streamid
);
1864 static void xhci_kick_epctx(XHCIEPContext
*epctx
, unsigned int streamid
)
1866 XHCIState
*xhci
= epctx
->xhci
;
1867 XHCIStreamContext
*stctx
= NULL
;
1870 USBEndpoint
*ep
= NULL
;
1872 unsigned int count
= 0;
1876 trace_usb_xhci_ep_kick(epctx
->slotid
, epctx
->epid
, streamid
);
1877 assert(!epctx
->kick_active
);
1879 /* If the device has been detached, but the guest has not noticed this
1880 yet the 2 above checks will succeed, but we must NOT continue */
1881 if (!xhci
->slots
[epctx
->slotid
- 1].uport
||
1882 !xhci
->slots
[epctx
->slotid
- 1].uport
->dev
||
1883 !xhci
->slots
[epctx
->slotid
- 1].uport
->dev
->attached
) {
1888 XHCITransfer
*xfer
= epctx
->retry
;
1890 trace_usb_xhci_xfer_retry(xfer
);
1891 assert(xfer
->running_retry
);
1892 if (xfer
->timed_xfer
) {
1893 /* time to kick the transfer? */
1894 mfindex
= xhci_mfindex_get(xhci
);
1895 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1896 if (xfer
->running_retry
) {
1899 xfer
->timed_xfer
= 0;
1900 xfer
->running_retry
= 1;
1902 if (xfer
->iso_xfer
) {
1903 /* retry iso transfer */
1904 if (xhci_setup_packet(xfer
) < 0) {
1907 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1908 assert(xfer
->packet
.status
!= USB_RET_NAK
);
1909 xhci_try_complete_packet(xfer
);
1911 /* retry nak'ed transfer */
1912 if (xhci_setup_packet(xfer
) < 0) {
1915 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1916 if (xfer
->packet
.status
== USB_RET_NAK
) {
1917 xhci_xfer_unmap(xfer
);
1920 xhci_try_complete_packet(xfer
);
1922 assert(!xfer
->running_retry
);
1923 if (xfer
->complete
) {
1924 /* update ring dequeue ptr */
1925 xhci_set_ep_state(xhci
, epctx
, stctx
, epctx
->state
);
1926 xhci_ep_free_xfer(epctx
->retry
);
1928 epctx
->retry
= NULL
;
1931 if (epctx
->state
== EP_HALTED
) {
1932 DPRINTF("xhci: ep halted, not running schedule\n");
1937 if (epctx
->nr_pstreams
) {
1939 stctx
= xhci_find_stream(epctx
, streamid
, &err
);
1940 if (stctx
== NULL
) {
1943 ring
= &stctx
->ring
;
1944 xhci_set_ep_state(xhci
, epctx
, stctx
, EP_RUNNING
);
1946 ring
= &epctx
->ring
;
1948 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_RUNNING
);
1950 assert(ring
->dequeue
!= 0);
1952 epctx
->kick_active
++;
1954 length
= xhci_ring_chain_length(xhci
, ring
);
1956 if (epctx
->type
== ET_ISO_OUT
|| epctx
->type
== ET_ISO_IN
) {
1958 XHCIEvent ev
= { ER_TRANSFER
};
1959 ev
.ccode
= epctx
->type
== ET_ISO_IN
?
1960 CC_RING_OVERRUN
: CC_RING_UNDERRUN
;
1961 ev
.slotid
= epctx
->slotid
;
1962 ev
.epid
= epctx
->epid
;
1963 ev
.ptr
= epctx
->ring
.dequeue
;
1964 xhci_event(xhci
, &ev
, xhci
->slots
[epctx
->slotid
-1].intr
);
1968 xfer
= xhci_ep_alloc_xfer(epctx
, length
);
1973 for (i
= 0; i
< length
; i
++) {
1975 type
= xhci_ring_fetch(xhci
, ring
, &xfer
->trbs
[i
], NULL
);
1978 xhci_ep_free_xfer(xfer
);
1979 epctx
->kick_active
--;
1983 xfer
->streamid
= streamid
;
1985 if (epctx
->epid
== 1) {
1986 xhci_fire_ctl_transfer(xhci
, xfer
);
1988 xhci_fire_transfer(xhci
, xfer
, epctx
);
1990 if (xfer
->complete
) {
1991 /* update ring dequeue ptr */
1992 xhci_set_ep_state(xhci
, epctx
, stctx
, epctx
->state
);
1993 xhci_ep_free_xfer(xfer
);
1997 if (epctx
->state
== EP_HALTED
) {
2000 if (xfer
!= NULL
&& xfer
->running_retry
) {
2001 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2002 epctx
->retry
= xfer
;
2003 xhci_xfer_unmap(xfer
);
2006 if (count
++ > TRANSFER_LIMIT
) {
2007 trace_usb_xhci_enforced_limit("transfers");
2011 epctx
->kick_active
--;
2013 ep
= xhci_epid_to_usbep(epctx
);
2015 usb_device_flush_ep_queue(ep
->dev
, ep
);
2019 static TRBCCode
xhci_enable_slot(XHCIState
*xhci
, unsigned int slotid
)
2021 trace_usb_xhci_slot_enable(slotid
);
2022 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2023 xhci
->slots
[slotid
-1].enabled
= 1;
2024 xhci
->slots
[slotid
-1].uport
= NULL
;
2025 memset(xhci
->slots
[slotid
-1].eps
, 0, sizeof(XHCIEPContext
*)*31);
2030 static TRBCCode
xhci_disable_slot(XHCIState
*xhci
, unsigned int slotid
)
2034 trace_usb_xhci_slot_disable(slotid
);
2035 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2037 for (i
= 1; i
<= 31; i
++) {
2038 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2039 xhci_disable_ep(xhci
, slotid
, i
);
2043 xhci
->slots
[slotid
-1].enabled
= 0;
2044 xhci
->slots
[slotid
-1].addressed
= 0;
2045 xhci
->slots
[slotid
-1].uport
= NULL
;
2046 xhci
->slots
[slotid
-1].intr
= 0;
2050 static USBPort
*xhci_lookup_uport(XHCIState
*xhci
, uint32_t *slot_ctx
)
2056 port
= (slot_ctx
[1]>>16) & 0xFF;
2057 if (port
< 1 || port
> xhci
->numports
) {
2060 port
= xhci
->ports
[port
-1].uport
->index
+1;
2061 pos
= snprintf(path
, sizeof(path
), "%d", port
);
2062 for (i
= 0; i
< 5; i
++) {
2063 port
= (slot_ctx
[0] >> 4*i
) & 0x0f;
2067 pos
+= snprintf(path
+ pos
, sizeof(path
) - pos
, ".%d", port
);
2070 QTAILQ_FOREACH(uport
, &xhci
->bus
.used
, next
) {
2071 if (strcmp(uport
->path
, path
) == 0) {
2078 static TRBCCode
xhci_address_slot(XHCIState
*xhci
, unsigned int slotid
,
2079 uint64_t pictx
, bool bsr
)
2084 dma_addr_t ictx
, octx
, dcbaap
;
2086 uint32_t ictl_ctx
[2];
2087 uint32_t slot_ctx
[4];
2088 uint32_t ep0_ctx
[5];
2092 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2094 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
2095 poctx
= ldq_le_pci_dma(PCI_DEVICE(xhci
), dcbaap
+ 8 * slotid
);
2096 ictx
= xhci_mask64(pictx
);
2097 octx
= xhci_mask64(poctx
);
2099 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2100 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2102 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2104 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] != 0x3) {
2105 DPRINTF("xhci: invalid input context control %08x %08x\n",
2106 ictl_ctx
[0], ictl_ctx
[1]);
2107 return CC_TRB_ERROR
;
2110 xhci_dma_read_u32s(xhci
, ictx
+32, slot_ctx
, sizeof(slot_ctx
));
2111 xhci_dma_read_u32s(xhci
, ictx
+64, ep0_ctx
, sizeof(ep0_ctx
));
2113 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2114 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2116 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2117 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2119 uport
= xhci_lookup_uport(xhci
, slot_ctx
);
2120 if (uport
== NULL
) {
2121 DPRINTF("xhci: port not found\n");
2122 return CC_TRB_ERROR
;
2124 trace_usb_xhci_slot_address(slotid
, uport
->path
);
2127 if (!dev
|| !dev
->attached
) {
2128 DPRINTF("xhci: port %s not connected\n", uport
->path
);
2129 return CC_USB_TRANSACTION_ERROR
;
2132 for (i
= 0; i
< xhci
->numslots
; i
++) {
2133 if (i
== slotid
-1) {
2136 if (xhci
->slots
[i
].uport
== uport
) {
2137 DPRINTF("xhci: port %s already assigned to slot %d\n",
2139 return CC_TRB_ERROR
;
2143 slot
= &xhci
->slots
[slotid
-1];
2144 slot
->uport
= uport
;
2146 slot
->intr
= get_field(slot_ctx
[2], TRB_INTR
);
2148 /* Make sure device is in USB_STATE_DEFAULT state */
2149 usb_device_reset(dev
);
2151 slot_ctx
[3] = SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2156 slot_ctx
[3] = (SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
) | slotid
;
2157 memset(&p
, 0, sizeof(p
));
2158 usb_packet_addbuf(&p
, buf
, sizeof(buf
));
2159 usb_packet_setup(&p
, USB_TOKEN_OUT
,
2160 usb_ep_get(dev
, USB_TOKEN_OUT
, 0), 0,
2162 usb_device_handle_control(dev
, &p
,
2163 DeviceOutRequest
| USB_REQ_SET_ADDRESS
,
2164 slotid
, 0, 0, NULL
);
2165 assert(p
.status
!= USB_RET_ASYNC
);
2166 usb_packet_cleanup(&p
);
2169 res
= xhci_enable_ep(xhci
, slotid
, 1, octx
+32, ep0_ctx
);
2171 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2172 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2173 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2174 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2176 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2177 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2179 xhci
->slots
[slotid
-1].addressed
= 1;
2184 static TRBCCode
xhci_configure_slot(XHCIState
*xhci
, unsigned int slotid
,
2185 uint64_t pictx
, bool dc
)
2187 dma_addr_t ictx
, octx
;
2188 uint32_t ictl_ctx
[2];
2189 uint32_t slot_ctx
[4];
2190 uint32_t islot_ctx
[4];
2195 trace_usb_xhci_slot_configure(slotid
);
2196 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2198 ictx
= xhci_mask64(pictx
);
2199 octx
= xhci
->slots
[slotid
-1].ctx
;
2201 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2202 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2205 for (i
= 2; i
<= 31; i
++) {
2206 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2207 xhci_disable_ep(xhci
, slotid
, i
);
2211 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2212 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2213 slot_ctx
[3] |= SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
;
2214 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2215 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2216 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2221 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2223 if ((ictl_ctx
[0] & 0x3) != 0x0 || (ictl_ctx
[1] & 0x3) != 0x1) {
2224 DPRINTF("xhci: invalid input context control %08x %08x\n",
2225 ictl_ctx
[0], ictl_ctx
[1]);
2226 return CC_TRB_ERROR
;
2229 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2230 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2232 if (SLOT_STATE(slot_ctx
[3]) < SLOT_ADDRESSED
) {
2233 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx
[3]);
2234 return CC_CONTEXT_STATE_ERROR
;
2237 xhci_free_device_streams(xhci
, slotid
, ictl_ctx
[0] | ictl_ctx
[1]);
2239 for (i
= 2; i
<= 31; i
++) {
2240 if (ictl_ctx
[0] & (1<<i
)) {
2241 xhci_disable_ep(xhci
, slotid
, i
);
2243 if (ictl_ctx
[1] & (1<<i
)) {
2244 xhci_dma_read_u32s(xhci
, ictx
+32+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2245 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2246 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2247 ep_ctx
[3], ep_ctx
[4]);
2248 xhci_disable_ep(xhci
, slotid
, i
);
2249 res
= xhci_enable_ep(xhci
, slotid
, i
, octx
+(32*i
), ep_ctx
);
2250 if (res
!= CC_SUCCESS
) {
2253 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2254 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2255 ep_ctx
[3], ep_ctx
[4]);
2256 xhci_dma_write_u32s(xhci
, octx
+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2260 res
= xhci_alloc_device_streams(xhci
, slotid
, ictl_ctx
[1]);
2261 if (res
!= CC_SUCCESS
) {
2262 for (i
= 2; i
<= 31; i
++) {
2263 if (ictl_ctx
[1] & (1u << i
)) {
2264 xhci_disable_ep(xhci
, slotid
, i
);
2270 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2271 slot_ctx
[3] |= SLOT_CONFIGURED
<< SLOT_STATE_SHIFT
;
2272 slot_ctx
[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK
<< SLOT_CONTEXT_ENTRIES_SHIFT
);
2273 slot_ctx
[0] |= islot_ctx
[0] & (SLOT_CONTEXT_ENTRIES_MASK
<<
2274 SLOT_CONTEXT_ENTRIES_SHIFT
);
2275 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2276 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2278 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2284 static TRBCCode
xhci_evaluate_slot(XHCIState
*xhci
, unsigned int slotid
,
2287 dma_addr_t ictx
, octx
;
2288 uint32_t ictl_ctx
[2];
2289 uint32_t iep0_ctx
[5];
2290 uint32_t ep0_ctx
[5];
2291 uint32_t islot_ctx
[4];
2292 uint32_t slot_ctx
[4];
2294 trace_usb_xhci_slot_evaluate(slotid
);
2295 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2297 ictx
= xhci_mask64(pictx
);
2298 octx
= xhci
->slots
[slotid
-1].ctx
;
2300 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2301 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2303 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2305 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] & ~0x3) {
2306 DPRINTF("xhci: invalid input context control %08x %08x\n",
2307 ictl_ctx
[0], ictl_ctx
[1]);
2308 return CC_TRB_ERROR
;
2311 if (ictl_ctx
[1] & 0x1) {
2312 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2314 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2315 islot_ctx
[0], islot_ctx
[1], islot_ctx
[2], islot_ctx
[3]);
2317 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2319 slot_ctx
[1] &= ~0xFFFF; /* max exit latency */
2320 slot_ctx
[1] |= islot_ctx
[1] & 0xFFFF;
2321 /* update interrupter target field */
2322 xhci
->slots
[slotid
-1].intr
= get_field(islot_ctx
[2], TRB_INTR
);
2323 set_field(&slot_ctx
[2], xhci
->slots
[slotid
-1].intr
, TRB_INTR
);
2325 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2326 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2328 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2331 if (ictl_ctx
[1] & 0x2) {
2332 xhci_dma_read_u32s(xhci
, ictx
+64, iep0_ctx
, sizeof(iep0_ctx
));
2334 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2335 iep0_ctx
[0], iep0_ctx
[1], iep0_ctx
[2],
2336 iep0_ctx
[3], iep0_ctx
[4]);
2338 xhci_dma_read_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2340 ep0_ctx
[1] &= ~0xFFFF0000; /* max packet size*/
2341 ep0_ctx
[1] |= iep0_ctx
[1] & 0xFFFF0000;
2343 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2344 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2346 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2352 static TRBCCode
xhci_reset_slot(XHCIState
*xhci
, unsigned int slotid
)
2354 uint32_t slot_ctx
[4];
2358 trace_usb_xhci_slot_reset(slotid
);
2359 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2361 octx
= xhci
->slots
[slotid
-1].ctx
;
2363 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2365 for (i
= 2; i
<= 31; i
++) {
2366 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2367 xhci_disable_ep(xhci
, slotid
, i
);
2371 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2372 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2373 slot_ctx
[3] |= SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2374 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2375 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2376 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2381 static unsigned int xhci_get_slot(XHCIState
*xhci
, XHCIEvent
*event
, XHCITRB
*trb
)
2383 unsigned int slotid
;
2384 slotid
= (trb
->control
>> TRB_CR_SLOTID_SHIFT
) & TRB_CR_SLOTID_MASK
;
2385 if (slotid
< 1 || slotid
> xhci
->numslots
) {
2386 DPRINTF("xhci: bad slot id %d\n", slotid
);
2387 event
->ccode
= CC_TRB_ERROR
;
2389 } else if (!xhci
->slots
[slotid
-1].enabled
) {
2390 DPRINTF("xhci: slot id %d not enabled\n", slotid
);
2391 event
->ccode
= CC_SLOT_NOT_ENABLED_ERROR
;
2397 /* cleanup slot state on usb device detach */
2398 static void xhci_detach_slot(XHCIState
*xhci
, USBPort
*uport
)
2402 for (slot
= 0; slot
< xhci
->numslots
; slot
++) {
2403 if (xhci
->slots
[slot
].uport
== uport
) {
2407 if (slot
== xhci
->numslots
) {
2411 for (ep
= 0; ep
< 31; ep
++) {
2412 if (xhci
->slots
[slot
].eps
[ep
]) {
2413 xhci_ep_nuke_xfers(xhci
, slot
+ 1, ep
+ 1, 0);
2416 xhci
->slots
[slot
].uport
= NULL
;
2419 static TRBCCode
xhci_get_port_bandwidth(XHCIState
*xhci
, uint64_t pctx
)
2422 uint8_t bw_ctx
[xhci
->numports
+1];
2424 DPRINTF("xhci_get_port_bandwidth()\n");
2426 ctx
= xhci_mask64(pctx
);
2428 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT
"\n", ctx
);
2430 /* TODO: actually implement real values here */
2432 memset(&bw_ctx
[1], 80, xhci
->numports
); /* 80% */
2433 pci_dma_write(PCI_DEVICE(xhci
), ctx
, bw_ctx
, sizeof(bw_ctx
));
2438 static uint32_t rotl(uint32_t v
, unsigned count
)
2441 return (v
<< count
) | (v
>> (32 - count
));
2445 static uint32_t xhci_nec_challenge(uint32_t hi
, uint32_t lo
)
2448 val
= rotl(lo
- 0x49434878, 32 - ((hi
>>8) & 0x1F));
2449 val
+= rotl(lo
+ 0x49434878, hi
& 0x1F);
2450 val
-= rotl(hi
^ 0x49434878, (lo
>> 16) & 0x1F);
2454 static void xhci_process_commands(XHCIState
*xhci
)
2458 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_SUCCESS
};
2460 unsigned int i
, slotid
= 0, count
= 0;
2462 DPRINTF("xhci_process_commands()\n");
2463 if (!xhci_running(xhci
)) {
2464 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2468 xhci
->crcr_low
|= CRCR_CRR
;
2470 while ((type
= xhci_ring_fetch(xhci
, &xhci
->cmd_ring
, &trb
, &addr
))) {
2473 case CR_ENABLE_SLOT
:
2474 for (i
= 0; i
< xhci
->numslots
; i
++) {
2475 if (!xhci
->slots
[i
].enabled
) {
2479 if (i
>= xhci
->numslots
) {
2480 DPRINTF("xhci: no device slots available\n");
2481 event
.ccode
= CC_NO_SLOTS_ERROR
;
2484 event
.ccode
= xhci_enable_slot(xhci
, slotid
);
2487 case CR_DISABLE_SLOT
:
2488 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2490 event
.ccode
= xhci_disable_slot(xhci
, slotid
);
2493 case CR_ADDRESS_DEVICE
:
2494 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2496 event
.ccode
= xhci_address_slot(xhci
, slotid
, trb
.parameter
,
2497 trb
.control
& TRB_CR_BSR
);
2500 case CR_CONFIGURE_ENDPOINT
:
2501 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2503 event
.ccode
= xhci_configure_slot(xhci
, slotid
, trb
.parameter
,
2504 trb
.control
& TRB_CR_DC
);
2507 case CR_EVALUATE_CONTEXT
:
2508 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2510 event
.ccode
= xhci_evaluate_slot(xhci
, slotid
, trb
.parameter
);
2513 case CR_STOP_ENDPOINT
:
2514 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2516 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2518 event
.ccode
= xhci_stop_ep(xhci
, slotid
, epid
);
2521 case CR_RESET_ENDPOINT
:
2522 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2524 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2526 event
.ccode
= xhci_reset_ep(xhci
, slotid
, epid
);
2529 case CR_SET_TR_DEQUEUE
:
2530 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2532 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2534 unsigned int streamid
= (trb
.status
>> 16) & 0xffff;
2535 event
.ccode
= xhci_set_ep_dequeue(xhci
, slotid
,
2540 case CR_RESET_DEVICE
:
2541 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2543 event
.ccode
= xhci_reset_slot(xhci
, slotid
);
2546 case CR_GET_PORT_BANDWIDTH
:
2547 event
.ccode
= xhci_get_port_bandwidth(xhci
, trb
.parameter
);
2550 event
.ccode
= CC_SUCCESS
;
2552 case CR_VENDOR_NEC_FIRMWARE_REVISION
:
2553 if (xhci
->nec_quirks
) {
2554 event
.type
= 48; /* NEC reply */
2555 event
.length
= 0x3025;
2557 event
.ccode
= CC_TRB_ERROR
;
2560 case CR_VENDOR_NEC_CHALLENGE_RESPONSE
:
2561 if (xhci
->nec_quirks
) {
2562 uint32_t chi
= trb
.parameter
>> 32;
2563 uint32_t clo
= trb
.parameter
;
2564 uint32_t val
= xhci_nec_challenge(chi
, clo
);
2565 event
.length
= val
& 0xFFFF;
2566 event
.epid
= val
>> 16;
2568 event
.type
= 48; /* NEC reply */
2570 event
.ccode
= CC_TRB_ERROR
;
2574 trace_usb_xhci_unimplemented("command", type
);
2575 event
.ccode
= CC_TRB_ERROR
;
2578 event
.slotid
= slotid
;
2579 xhci_event(xhci
, &event
, 0);
2581 if (count
++ > COMMAND_LIMIT
) {
2582 trace_usb_xhci_enforced_limit("commands");
2588 static bool xhci_port_have_device(XHCIPort
*port
)
2590 if (!port
->uport
->dev
|| !port
->uport
->dev
->attached
) {
2591 return false; /* no device present */
2593 if (!((1 << port
->uport
->dev
->speed
) & port
->speedmask
)) {
2594 return false; /* speed mismatch */
2599 static void xhci_port_notify(XHCIPort
*port
, uint32_t bits
)
2601 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
,
2602 port
->portnr
<< 24 };
2604 if ((port
->portsc
& bits
) == bits
) {
2607 trace_usb_xhci_port_notify(port
->portnr
, bits
);
2608 port
->portsc
|= bits
;
2609 if (!xhci_running(port
->xhci
)) {
2612 xhci_event(port
->xhci
, &ev
, 0);
2615 static void xhci_port_update(XHCIPort
*port
, int is_detach
)
2617 uint32_t pls
= PLS_RX_DETECT
;
2620 port
->portsc
= PORTSC_PP
;
2621 if (!is_detach
&& xhci_port_have_device(port
)) {
2622 port
->portsc
|= PORTSC_CCS
;
2623 switch (port
->uport
->dev
->speed
) {
2625 port
->portsc
|= PORTSC_SPEED_LOW
;
2628 case USB_SPEED_FULL
:
2629 port
->portsc
|= PORTSC_SPEED_FULL
;
2632 case USB_SPEED_HIGH
:
2633 port
->portsc
|= PORTSC_SPEED_HIGH
;
2636 case USB_SPEED_SUPER
:
2637 port
->portsc
|= PORTSC_SPEED_SUPER
;
2638 port
->portsc
|= PORTSC_PED
;
2643 set_field(&port
->portsc
, pls
, PORTSC_PLS
);
2644 trace_usb_xhci_port_link(port
->portnr
, pls
);
2645 xhci_port_notify(port
, PORTSC_CSC
);
2648 static void xhci_port_reset(XHCIPort
*port
, bool warm_reset
)
2650 trace_usb_xhci_port_reset(port
->portnr
, warm_reset
);
2652 if (!xhci_port_have_device(port
)) {
2656 usb_device_reset(port
->uport
->dev
);
2658 switch (port
->uport
->dev
->speed
) {
2659 case USB_SPEED_SUPER
:
2661 port
->portsc
|= PORTSC_WRC
;
2665 case USB_SPEED_FULL
:
2666 case USB_SPEED_HIGH
:
2667 set_field(&port
->portsc
, PLS_U0
, PORTSC_PLS
);
2668 trace_usb_xhci_port_link(port
->portnr
, PLS_U0
);
2669 port
->portsc
|= PORTSC_PED
;
2673 port
->portsc
&= ~PORTSC_PR
;
2674 xhci_port_notify(port
, PORTSC_PRC
);
2677 static void xhci_reset(DeviceState
*dev
)
2679 XHCIState
*xhci
= XHCI(dev
);
2682 trace_usb_xhci_reset();
2683 if (!(xhci
->usbsts
& USBSTS_HCH
)) {
2684 DPRINTF("xhci: reset while running!\n");
2688 xhci
->usbsts
= USBSTS_HCH
;
2691 xhci
->crcr_high
= 0;
2692 xhci
->dcbaap_low
= 0;
2693 xhci
->dcbaap_high
= 0;
2696 for (i
= 0; i
< xhci
->numslots
; i
++) {
2697 xhci_disable_slot(xhci
, i
+1);
2700 for (i
= 0; i
< xhci
->numports
; i
++) {
2701 xhci_port_update(xhci
->ports
+ i
, 0);
2704 for (i
= 0; i
< xhci
->numintrs
; i
++) {
2705 xhci
->intr
[i
].iman
= 0;
2706 xhci
->intr
[i
].imod
= 0;
2707 xhci
->intr
[i
].erstsz
= 0;
2708 xhci
->intr
[i
].erstba_low
= 0;
2709 xhci
->intr
[i
].erstba_high
= 0;
2710 xhci
->intr
[i
].erdp_low
= 0;
2711 xhci
->intr
[i
].erdp_high
= 0;
2712 xhci
->intr
[i
].msix_used
= 0;
2714 xhci
->intr
[i
].er_ep_idx
= 0;
2715 xhci
->intr
[i
].er_pcs
= 1;
2716 xhci
->intr
[i
].ev_buffer_put
= 0;
2717 xhci
->intr
[i
].ev_buffer_get
= 0;
2720 xhci
->mfindex_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
2721 xhci_mfwrap_update(xhci
);
2724 static uint64_t xhci_cap_read(void *ptr
, hwaddr reg
, unsigned size
)
2726 XHCIState
*xhci
= ptr
;
2730 case 0x00: /* HCIVERSION, CAPLENGTH */
2731 ret
= 0x01000000 | LEN_CAP
;
2733 case 0x04: /* HCSPARAMS 1 */
2734 ret
= ((xhci
->numports_2
+xhci
->numports_3
)<<24)
2735 | (xhci
->numintrs
<<8) | xhci
->numslots
;
2737 case 0x08: /* HCSPARAMS 2 */
2740 case 0x0c: /* HCSPARAMS 3 */
2743 case 0x10: /* HCCPARAMS */
2744 if (sizeof(dma_addr_t
) == 4) {
2745 ret
= 0x00080000 | (xhci
->max_pstreams_mask
<< 12);
2747 ret
= 0x00080001 | (xhci
->max_pstreams_mask
<< 12);
2750 case 0x14: /* DBOFF */
2753 case 0x18: /* RTSOFF */
2757 /* extended capabilities */
2758 case 0x20: /* Supported Protocol:00 */
2759 ret
= 0x02000402; /* USB 2.0 */
2761 case 0x24: /* Supported Protocol:04 */
2762 ret
= 0x20425355; /* "USB " */
2764 case 0x28: /* Supported Protocol:08 */
2765 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
2766 ret
= (xhci
->numports_2
<<8) | (xhci
->numports_3
+1);
2768 ret
= (xhci
->numports_2
<<8) | 1;
2771 case 0x2c: /* Supported Protocol:0c */
2772 ret
= 0x00000000; /* reserved */
2774 case 0x30: /* Supported Protocol:00 */
2775 ret
= 0x03000002; /* USB 3.0 */
2777 case 0x34: /* Supported Protocol:04 */
2778 ret
= 0x20425355; /* "USB " */
2780 case 0x38: /* Supported Protocol:08 */
2781 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
2782 ret
= (xhci
->numports_3
<<8) | 1;
2784 ret
= (xhci
->numports_3
<<8) | (xhci
->numports_2
+1);
2787 case 0x3c: /* Supported Protocol:0c */
2788 ret
= 0x00000000; /* reserved */
2791 trace_usb_xhci_unimplemented("cap read", reg
);
2795 trace_usb_xhci_cap_read(reg
, ret
);
2799 static uint64_t xhci_port_read(void *ptr
, hwaddr reg
, unsigned size
)
2801 XHCIPort
*port
= ptr
;
2805 case 0x00: /* PORTSC */
2808 case 0x04: /* PORTPMSC */
2809 case 0x08: /* PORTLI */
2812 case 0x0c: /* reserved */
2814 trace_usb_xhci_unimplemented("port read", reg
);
2818 trace_usb_xhci_port_read(port
->portnr
, reg
, ret
);
2822 static void xhci_port_write(void *ptr
, hwaddr reg
,
2823 uint64_t val
, unsigned size
)
2825 XHCIPort
*port
= ptr
;
2826 uint32_t portsc
, notify
;
2828 trace_usb_xhci_port_write(port
->portnr
, reg
, val
);
2831 case 0x00: /* PORTSC */
2832 /* write-1-to-start bits */
2833 if (val
& PORTSC_WPR
) {
2834 xhci_port_reset(port
, true);
2837 if (val
& PORTSC_PR
) {
2838 xhci_port_reset(port
, false);
2842 portsc
= port
->portsc
;
2844 /* write-1-to-clear bits*/
2845 portsc
&= ~(val
& (PORTSC_CSC
|PORTSC_PEC
|PORTSC_WRC
|PORTSC_OCC
|
2846 PORTSC_PRC
|PORTSC_PLC
|PORTSC_CEC
));
2847 if (val
& PORTSC_LWS
) {
2848 /* overwrite PLS only when LWS=1 */
2849 uint32_t old_pls
= get_field(port
->portsc
, PORTSC_PLS
);
2850 uint32_t new_pls
= get_field(val
, PORTSC_PLS
);
2853 if (old_pls
!= PLS_U0
) {
2854 set_field(&portsc
, new_pls
, PORTSC_PLS
);
2855 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
2856 notify
= PORTSC_PLC
;
2860 if (old_pls
< PLS_U3
) {
2861 set_field(&portsc
, new_pls
, PORTSC_PLS
);
2862 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
2866 /* windows does this for some reason, don't spam stderr */
2869 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
2870 __func__
, old_pls
, new_pls
);
2874 /* read/write bits */
2875 portsc
&= ~(PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
);
2876 portsc
|= (val
& (PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
));
2877 port
->portsc
= portsc
;
2879 xhci_port_notify(port
, notify
);
2882 case 0x04: /* PORTPMSC */
2883 case 0x08: /* PORTLI */
2885 trace_usb_xhci_unimplemented("port write", reg
);
2889 static uint64_t xhci_oper_read(void *ptr
, hwaddr reg
, unsigned size
)
2891 XHCIState
*xhci
= ptr
;
2895 case 0x00: /* USBCMD */
2898 case 0x04: /* USBSTS */
2901 case 0x08: /* PAGESIZE */
2904 case 0x14: /* DNCTRL */
2907 case 0x18: /* CRCR low */
2908 ret
= xhci
->crcr_low
& ~0xe;
2910 case 0x1c: /* CRCR high */
2911 ret
= xhci
->crcr_high
;
2913 case 0x30: /* DCBAAP low */
2914 ret
= xhci
->dcbaap_low
;
2916 case 0x34: /* DCBAAP high */
2917 ret
= xhci
->dcbaap_high
;
2919 case 0x38: /* CONFIG */
2923 trace_usb_xhci_unimplemented("oper read", reg
);
2927 trace_usb_xhci_oper_read(reg
, ret
);
2931 static void xhci_oper_write(void *ptr
, hwaddr reg
,
2932 uint64_t val
, unsigned size
)
2934 XHCIState
*xhci
= ptr
;
2935 DeviceState
*d
= DEVICE(ptr
);
2937 trace_usb_xhci_oper_write(reg
, val
);
2940 case 0x00: /* USBCMD */
2941 if ((val
& USBCMD_RS
) && !(xhci
->usbcmd
& USBCMD_RS
)) {
2943 } else if (!(val
& USBCMD_RS
) && (xhci
->usbcmd
& USBCMD_RS
)) {
2946 if (val
& USBCMD_CSS
) {
2948 xhci
->usbsts
&= ~USBSTS_SRE
;
2950 if (val
& USBCMD_CRS
) {
2952 xhci
->usbsts
|= USBSTS_SRE
;
2954 xhci
->usbcmd
= val
& 0xc0f;
2955 xhci_mfwrap_update(xhci
);
2956 if (val
& USBCMD_HCRST
) {
2959 xhci_intx_update(xhci
);
2962 case 0x04: /* USBSTS */
2963 /* these bits are write-1-to-clear */
2964 xhci
->usbsts
&= ~(val
& (USBSTS_HSE
|USBSTS_EINT
|USBSTS_PCD
|USBSTS_SRE
));
2965 xhci_intx_update(xhci
);
2968 case 0x14: /* DNCTRL */
2969 xhci
->dnctrl
= val
& 0xffff;
2971 case 0x18: /* CRCR low */
2972 xhci
->crcr_low
= (val
& 0xffffffcf) | (xhci
->crcr_low
& CRCR_CRR
);
2974 case 0x1c: /* CRCR high */
2975 xhci
->crcr_high
= val
;
2976 if (xhci
->crcr_low
& (CRCR_CA
|CRCR_CS
) && (xhci
->crcr_low
& CRCR_CRR
)) {
2977 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_COMMAND_RING_STOPPED
};
2978 xhci
->crcr_low
&= ~CRCR_CRR
;
2979 xhci_event(xhci
, &event
, 0);
2980 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci
->crcr_low
);
2982 dma_addr_t base
= xhci_addr64(xhci
->crcr_low
& ~0x3f, val
);
2983 xhci_ring_init(xhci
, &xhci
->cmd_ring
, base
);
2985 xhci
->crcr_low
&= ~(CRCR_CA
| CRCR_CS
);
2987 case 0x30: /* DCBAAP low */
2988 xhci
->dcbaap_low
= val
& 0xffffffc0;
2990 case 0x34: /* DCBAAP high */
2991 xhci
->dcbaap_high
= val
;
2993 case 0x38: /* CONFIG */
2994 xhci
->config
= val
& 0xff;
2997 trace_usb_xhci_unimplemented("oper write", reg
);
3001 static uint64_t xhci_runtime_read(void *ptr
, hwaddr reg
,
3004 XHCIState
*xhci
= ptr
;
3009 case 0x00: /* MFINDEX */
3010 ret
= xhci_mfindex_get(xhci
) & 0x3fff;
3013 trace_usb_xhci_unimplemented("runtime read", reg
);
3017 int v
= (reg
- 0x20) / 0x20;
3018 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
3019 switch (reg
& 0x1f) {
3020 case 0x00: /* IMAN */
3023 case 0x04: /* IMOD */
3026 case 0x08: /* ERSTSZ */
3029 case 0x10: /* ERSTBA low */
3030 ret
= intr
->erstba_low
;
3032 case 0x14: /* ERSTBA high */
3033 ret
= intr
->erstba_high
;
3035 case 0x18: /* ERDP low */
3036 ret
= intr
->erdp_low
;
3038 case 0x1c: /* ERDP high */
3039 ret
= intr
->erdp_high
;
3044 trace_usb_xhci_runtime_read(reg
, ret
);
3048 static void xhci_runtime_write(void *ptr
, hwaddr reg
,
3049 uint64_t val
, unsigned size
)
3051 XHCIState
*xhci
= ptr
;
3052 int v
= (reg
- 0x20) / 0x20;
3053 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
3054 trace_usb_xhci_runtime_write(reg
, val
);
3057 trace_usb_xhci_unimplemented("runtime write", reg
);
3061 switch (reg
& 0x1f) {
3062 case 0x00: /* IMAN */
3063 if (val
& IMAN_IP
) {
3064 intr
->iman
&= ~IMAN_IP
;
3066 intr
->iman
&= ~IMAN_IE
;
3067 intr
->iman
|= val
& IMAN_IE
;
3069 xhci_intx_update(xhci
);
3071 xhci_msix_update(xhci
, v
);
3073 case 0x04: /* IMOD */
3076 case 0x08: /* ERSTSZ */
3077 intr
->erstsz
= val
& 0xffff;
3079 case 0x10: /* ERSTBA low */
3080 if (xhci
->nec_quirks
) {
3081 /* NEC driver bug: it doesn't align this to 64 bytes */
3082 intr
->erstba_low
= val
& 0xfffffff0;
3084 intr
->erstba_low
= val
& 0xffffffc0;
3087 case 0x14: /* ERSTBA high */
3088 intr
->erstba_high
= val
;
3089 xhci_er_reset(xhci
, v
);
3091 case 0x18: /* ERDP low */
3092 if (val
& ERDP_EHB
) {
3093 intr
->erdp_low
&= ~ERDP_EHB
;
3095 intr
->erdp_low
= (val
& ~ERDP_EHB
) | (intr
->erdp_low
& ERDP_EHB
);
3096 if (val
& ERDP_EHB
) {
3097 dma_addr_t erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
3098 unsigned int dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
3099 if (erdp
>= intr
->er_start
&&
3100 erdp
< (intr
->er_start
+ TRB_SIZE
* intr
->er_size
) &&
3101 dp_idx
!= intr
->er_ep_idx
) {
3102 xhci_intr_raise(xhci
, v
);
3106 case 0x1c: /* ERDP high */
3107 intr
->erdp_high
= val
;
3110 trace_usb_xhci_unimplemented("oper write", reg
);
3114 static uint64_t xhci_doorbell_read(void *ptr
, hwaddr reg
,
3117 /* doorbells always read as 0 */
3118 trace_usb_xhci_doorbell_read(reg
, 0);
3122 static void xhci_doorbell_write(void *ptr
, hwaddr reg
,
3123 uint64_t val
, unsigned size
)
3125 XHCIState
*xhci
= ptr
;
3126 unsigned int epid
, streamid
;
3128 trace_usb_xhci_doorbell_write(reg
, val
);
3130 if (!xhci_running(xhci
)) {
3131 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
3139 xhci_process_commands(xhci
);
3141 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
3146 streamid
= (val
>> 16) & 0xffff;
3147 if (reg
> xhci
->numslots
) {
3148 DPRINTF("xhci: bad doorbell %d\n", (int)reg
);
3149 } else if (epid
== 0 || epid
> 31) {
3150 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
3151 (int)reg
, (uint32_t)val
);
3153 xhci_kick_ep(xhci
, reg
, epid
, streamid
);
3158 static void xhci_cap_write(void *opaque
, hwaddr addr
, uint64_t val
,
3164 static const MemoryRegionOps xhci_cap_ops
= {
3165 .read
= xhci_cap_read
,
3166 .write
= xhci_cap_write
,
3167 .valid
.min_access_size
= 1,
3168 .valid
.max_access_size
= 4,
3169 .impl
.min_access_size
= 4,
3170 .impl
.max_access_size
= 4,
3171 .endianness
= DEVICE_LITTLE_ENDIAN
,
3174 static const MemoryRegionOps xhci_oper_ops
= {
3175 .read
= xhci_oper_read
,
3176 .write
= xhci_oper_write
,
3177 .valid
.min_access_size
= 4,
3178 .valid
.max_access_size
= 4,
3179 .endianness
= DEVICE_LITTLE_ENDIAN
,
3182 static const MemoryRegionOps xhci_port_ops
= {
3183 .read
= xhci_port_read
,
3184 .write
= xhci_port_write
,
3185 .valid
.min_access_size
= 4,
3186 .valid
.max_access_size
= 4,
3187 .endianness
= DEVICE_LITTLE_ENDIAN
,
3190 static const MemoryRegionOps xhci_runtime_ops
= {
3191 .read
= xhci_runtime_read
,
3192 .write
= xhci_runtime_write
,
3193 .valid
.min_access_size
= 4,
3194 .valid
.max_access_size
= 4,
3195 .endianness
= DEVICE_LITTLE_ENDIAN
,
3198 static const MemoryRegionOps xhci_doorbell_ops
= {
3199 .read
= xhci_doorbell_read
,
3200 .write
= xhci_doorbell_write
,
3201 .valid
.min_access_size
= 4,
3202 .valid
.max_access_size
= 4,
3203 .endianness
= DEVICE_LITTLE_ENDIAN
,
3206 static void xhci_attach(USBPort
*usbport
)
3208 XHCIState
*xhci
= usbport
->opaque
;
3209 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3211 xhci_port_update(port
, 0);
3214 static void xhci_detach(USBPort
*usbport
)
3216 XHCIState
*xhci
= usbport
->opaque
;
3217 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3219 xhci_detach_slot(xhci
, usbport
);
3220 xhci_port_update(port
, 1);
3223 static void xhci_wakeup(USBPort
*usbport
)
3225 XHCIState
*xhci
= usbport
->opaque
;
3226 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3229 if (get_field(port
->portsc
, PORTSC_PLS
) != PLS_U3
) {
3232 set_field(&port
->portsc
, PLS_RESUME
, PORTSC_PLS
);
3233 xhci_port_notify(port
, PORTSC_PLC
);
3236 static void xhci_complete(USBPort
*port
, USBPacket
*packet
)
3238 XHCITransfer
*xfer
= container_of(packet
, XHCITransfer
, packet
);
3240 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
3241 xhci_ep_nuke_one_xfer(xfer
, 0);
3244 xhci_try_complete_packet(xfer
);
3245 xhci_kick_epctx(xfer
->epctx
, xfer
->streamid
);
3246 if (xfer
->complete
) {
3247 xhci_ep_free_xfer(xfer
);
3251 static void xhci_child_detach(USBPort
*uport
, USBDevice
*child
)
3253 USBBus
*bus
= usb_bus_from_device(child
);
3254 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3256 xhci_detach_slot(xhci
, child
->port
);
3259 static USBPortOps xhci_uport_ops
= {
3260 .attach
= xhci_attach
,
3261 .detach
= xhci_detach
,
3262 .wakeup
= xhci_wakeup
,
3263 .complete
= xhci_complete
,
3264 .child_detach
= xhci_child_detach
,
3267 static int xhci_find_epid(USBEndpoint
*ep
)
3272 if (ep
->pid
== USB_TOKEN_IN
) {
3273 return ep
->nr
* 2 + 1;
3279 static USBEndpoint
*xhci_epid_to_usbep(XHCIEPContext
*epctx
)
3287 uport
= epctx
->xhci
->slots
[epctx
->slotid
- 1].uport
;
3288 if (!uport
|| !uport
->dev
) {
3291 token
= (epctx
->epid
& 1) ? USB_TOKEN_IN
: USB_TOKEN_OUT
;
3292 return usb_ep_get(uport
->dev
, token
, epctx
->epid
>> 1);
3295 static void xhci_wakeup_endpoint(USBBus
*bus
, USBEndpoint
*ep
,
3296 unsigned int stream
)
3298 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3301 DPRINTF("%s\n", __func__
);
3302 slotid
= ep
->dev
->addr
;
3303 if (slotid
== 0 || !xhci
->slots
[slotid
-1].enabled
) {
3304 DPRINTF("%s: oops, no slot for dev %d\n", __func__
, ep
->dev
->addr
);
3307 xhci_kick_ep(xhci
, slotid
, xhci_find_epid(ep
), stream
);
3310 static USBBusOps xhci_bus_ops
= {
3311 .wakeup_endpoint
= xhci_wakeup_endpoint
,
3314 static void usb_xhci_init(XHCIState
*xhci
)
3316 DeviceState
*dev
= DEVICE(xhci
);
3318 unsigned int i
, usbports
, speedmask
;
3320 xhci
->usbsts
= USBSTS_HCH
;
3322 if (xhci
->numports_2
> MAXPORTS_2
) {
3323 xhci
->numports_2
= MAXPORTS_2
;
3325 if (xhci
->numports_3
> MAXPORTS_3
) {
3326 xhci
->numports_3
= MAXPORTS_3
;
3328 usbports
= MAX(xhci
->numports_2
, xhci
->numports_3
);
3329 xhci
->numports
= xhci
->numports_2
+ xhci
->numports_3
;
3331 usb_bus_new(&xhci
->bus
, sizeof(xhci
->bus
), &xhci_bus_ops
, dev
);
3333 for (i
= 0; i
< usbports
; i
++) {
3335 if (i
< xhci
->numports_2
) {
3336 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
3337 port
= &xhci
->ports
[i
+ xhci
->numports_3
];
3338 port
->portnr
= i
+ 1 + xhci
->numports_3
;
3340 port
= &xhci
->ports
[i
];
3341 port
->portnr
= i
+ 1;
3343 port
->uport
= &xhci
->uports
[i
];
3345 USB_SPEED_MASK_LOW
|
3346 USB_SPEED_MASK_FULL
|
3347 USB_SPEED_MASK_HIGH
;
3348 assert(i
< MAXPORTS
);
3349 snprintf(port
->name
, sizeof(port
->name
), "usb2 port #%d", i
+1);
3350 speedmask
|= port
->speedmask
;
3352 if (i
< xhci
->numports_3
) {
3353 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
3354 port
= &xhci
->ports
[i
];
3355 port
->portnr
= i
+ 1;
3357 port
= &xhci
->ports
[i
+ xhci
->numports_2
];
3358 port
->portnr
= i
+ 1 + xhci
->numports_2
;
3360 port
->uport
= &xhci
->uports
[i
];
3361 port
->speedmask
= USB_SPEED_MASK_SUPER
;
3362 assert(i
< MAXPORTS
);
3363 snprintf(port
->name
, sizeof(port
->name
), "usb3 port #%d", i
+1);
3364 speedmask
|= port
->speedmask
;
3366 usb_register_port(&xhci
->bus
, &xhci
->uports
[i
], xhci
, i
,
3367 &xhci_uport_ops
, speedmask
);
3371 static void usb_xhci_realize(struct PCIDevice
*dev
, Error
**errp
)
3376 XHCIState
*xhci
= XHCI(dev
);
3378 dev
->config
[PCI_CLASS_PROG
] = 0x30; /* xHCI */
3379 dev
->config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin 1 */
3380 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x10;
3381 dev
->config
[0x60] = 0x30; /* release number */
3383 if (strcmp(object_get_typename(OBJECT(dev
)), TYPE_NEC_XHCI
) == 0) {
3384 xhci
->nec_quirks
= true;
3386 if (xhci
->numintrs
> MAXINTRS
) {
3387 xhci
->numintrs
= MAXINTRS
;
3389 while (xhci
->numintrs
& (xhci
->numintrs
- 1)) { /* ! power of 2 */
3392 if (xhci
->numintrs
< 1) {
3395 if (xhci
->numslots
> MAXSLOTS
) {
3396 xhci
->numslots
= MAXSLOTS
;
3398 if (xhci
->numslots
< 1) {
3401 if (xhci_get_flag(xhci
, XHCI_FLAG_ENABLE_STREAMS
)) {
3402 xhci
->max_pstreams_mask
= 7; /* == 256 primary streams */
3404 xhci
->max_pstreams_mask
= 0;
3407 if (xhci
->msi
!= ON_OFF_AUTO_OFF
) {
3408 ret
= msi_init(dev
, 0x70, xhci
->numintrs
, true, false, &err
);
3409 /* Any error other than -ENOTSUP(board's MSI support is broken)
3410 * is a programming error */
3411 assert(!ret
|| ret
== -ENOTSUP
);
3412 if (ret
&& xhci
->msi
== ON_OFF_AUTO_ON
) {
3413 /* Can't satisfy user's explicit msi=on request, fail */
3414 error_append_hint(&err
, "You have to use msi=auto (default) or "
3415 "msi=off with this machine type.\n");
3416 error_propagate(errp
, err
);
3419 assert(!err
|| xhci
->msi
== ON_OFF_AUTO_AUTO
);
3420 /* With msi=auto, we fall back to MSI off silently */
3424 usb_xhci_init(xhci
);
3425 xhci
->mfwrap_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, xhci_mfwrap_timer
, xhci
);
3427 memory_region_init(&xhci
->mem
, OBJECT(xhci
), "xhci", LEN_REGS
);
3428 memory_region_init_io(&xhci
->mem_cap
, OBJECT(xhci
), &xhci_cap_ops
, xhci
,
3429 "capabilities", LEN_CAP
);
3430 memory_region_init_io(&xhci
->mem_oper
, OBJECT(xhci
), &xhci_oper_ops
, xhci
,
3431 "operational", 0x400);
3432 memory_region_init_io(&xhci
->mem_runtime
, OBJECT(xhci
), &xhci_runtime_ops
, xhci
,
3433 "runtime", LEN_RUNTIME
);
3434 memory_region_init_io(&xhci
->mem_doorbell
, OBJECT(xhci
), &xhci_doorbell_ops
, xhci
,
3435 "doorbell", LEN_DOORBELL
);
3437 memory_region_add_subregion(&xhci
->mem
, 0, &xhci
->mem_cap
);
3438 memory_region_add_subregion(&xhci
->mem
, OFF_OPER
, &xhci
->mem_oper
);
3439 memory_region_add_subregion(&xhci
->mem
, OFF_RUNTIME
, &xhci
->mem_runtime
);
3440 memory_region_add_subregion(&xhci
->mem
, OFF_DOORBELL
, &xhci
->mem_doorbell
);
3442 for (i
= 0; i
< xhci
->numports
; i
++) {
3443 XHCIPort
*port
= &xhci
->ports
[i
];
3444 uint32_t offset
= OFF_OPER
+ 0x400 + 0x10 * i
;
3446 memory_region_init_io(&port
->mem
, OBJECT(xhci
), &xhci_port_ops
, port
,
3448 memory_region_add_subregion(&xhci
->mem
, offset
, &port
->mem
);
3451 pci_register_bar(dev
, 0,
3452 PCI_BASE_ADDRESS_SPACE_MEMORY
|PCI_BASE_ADDRESS_MEM_TYPE_64
,
3455 if (pci_bus_is_express(pci_get_bus(dev
)) ||
3456 xhci_get_flag(xhci
, XHCI_FLAG_FORCE_PCIE_ENDCAP
)) {
3457 ret
= pcie_endpoint_cap_init(dev
, 0xa0);
3461 if (xhci
->msix
!= ON_OFF_AUTO_OFF
) {
3462 /* TODO check for errors, and should fail when msix=on */
3463 msix_init(dev
, xhci
->numintrs
,
3464 &xhci
->mem
, 0, OFF_MSIX_TABLE
,
3465 &xhci
->mem
, 0, OFF_MSIX_PBA
,
3470 static void usb_xhci_exit(PCIDevice
*dev
)
3473 XHCIState
*xhci
= XHCI(dev
);
3475 trace_usb_xhci_exit();
3477 for (i
= 0; i
< xhci
->numslots
; i
++) {
3478 xhci_disable_slot(xhci
, i
+ 1);
3481 if (xhci
->mfwrap_timer
) {
3482 timer_del(xhci
->mfwrap_timer
);
3483 timer_free(xhci
->mfwrap_timer
);
3484 xhci
->mfwrap_timer
= NULL
;
3487 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_cap
);
3488 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_oper
);
3489 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_runtime
);
3490 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_doorbell
);
3492 for (i
= 0; i
< xhci
->numports
; i
++) {
3493 XHCIPort
*port
= &xhci
->ports
[i
];
3494 memory_region_del_subregion(&xhci
->mem
, &port
->mem
);
3497 /* destroy msix memory region */
3498 if (dev
->msix_table
&& dev
->msix_pba
3499 && dev
->msix_entry_used
) {
3500 msix_uninit(dev
, &xhci
->mem
, &xhci
->mem
);
3503 usb_bus_release(&xhci
->bus
);
3506 static int usb_xhci_post_load(void *opaque
, int version_id
)
3508 XHCIState
*xhci
= opaque
;
3509 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
3511 XHCIEPContext
*epctx
;
3512 dma_addr_t dcbaap
, pctx
;
3513 uint32_t slot_ctx
[4];
3515 int slotid
, epid
, state
, intr
;
3517 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
3519 for (slotid
= 1; slotid
<= xhci
->numslots
; slotid
++) {
3520 slot
= &xhci
->slots
[slotid
-1];
3521 if (!slot
->addressed
) {
3525 xhci_mask64(ldq_le_pci_dma(pci_dev
, dcbaap
+ 8 * slotid
));
3526 xhci_dma_read_u32s(xhci
, slot
->ctx
, slot_ctx
, sizeof(slot_ctx
));
3527 slot
->uport
= xhci_lookup_uport(xhci
, slot_ctx
);
3529 /* should not happen, but may trigger on guest bugs */
3531 slot
->addressed
= 0;
3534 assert(slot
->uport
&& slot
->uport
->dev
);
3536 for (epid
= 1; epid
<= 31; epid
++) {
3537 pctx
= slot
->ctx
+ 32 * epid
;
3538 xhci_dma_read_u32s(xhci
, pctx
, ep_ctx
, sizeof(ep_ctx
));
3539 state
= ep_ctx
[0] & EP_STATE_MASK
;
3540 if (state
== EP_DISABLED
) {
3543 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
3544 slot
->eps
[epid
-1] = epctx
;
3545 xhci_init_epctx(epctx
, pctx
, ep_ctx
);
3546 epctx
->state
= state
;
3547 if (state
== EP_RUNNING
) {
3548 /* kick endpoint after vmload is finished */
3549 timer_mod(epctx
->kick_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
3554 for (intr
= 0; intr
< xhci
->numintrs
; intr
++) {
3555 if (xhci
->intr
[intr
].msix_used
) {
3556 msix_vector_use(pci_dev
, intr
);
3558 msix_vector_unuse(pci_dev
, intr
);
3565 static const VMStateDescription vmstate_xhci_ring
= {
3566 .name
= "xhci-ring",
3568 .fields
= (VMStateField
[]) {
3569 VMSTATE_UINT64(dequeue
, XHCIRing
),
3570 VMSTATE_BOOL(ccs
, XHCIRing
),
3571 VMSTATE_END_OF_LIST()
3575 static const VMStateDescription vmstate_xhci_port
= {
3576 .name
= "xhci-port",
3578 .fields
= (VMStateField
[]) {
3579 VMSTATE_UINT32(portsc
, XHCIPort
),
3580 VMSTATE_END_OF_LIST()
3584 static const VMStateDescription vmstate_xhci_slot
= {
3585 .name
= "xhci-slot",
3587 .fields
= (VMStateField
[]) {
3588 VMSTATE_BOOL(enabled
, XHCISlot
),
3589 VMSTATE_BOOL(addressed
, XHCISlot
),
3590 VMSTATE_END_OF_LIST()
3594 static const VMStateDescription vmstate_xhci_event
= {
3595 .name
= "xhci-event",
3597 .fields
= (VMStateField
[]) {
3598 VMSTATE_UINT32(type
, XHCIEvent
),
3599 VMSTATE_UINT32(ccode
, XHCIEvent
),
3600 VMSTATE_UINT64(ptr
, XHCIEvent
),
3601 VMSTATE_UINT32(length
, XHCIEvent
),
3602 VMSTATE_UINT32(flags
, XHCIEvent
),
3603 VMSTATE_UINT8(slotid
, XHCIEvent
),
3604 VMSTATE_UINT8(epid
, XHCIEvent
),
3605 VMSTATE_END_OF_LIST()
3609 static bool xhci_er_full(void *opaque
, int version_id
)
3614 static const VMStateDescription vmstate_xhci_intr
= {
3615 .name
= "xhci-intr",
3617 .fields
= (VMStateField
[]) {
3619 VMSTATE_UINT32(iman
, XHCIInterrupter
),
3620 VMSTATE_UINT32(imod
, XHCIInterrupter
),
3621 VMSTATE_UINT32(erstsz
, XHCIInterrupter
),
3622 VMSTATE_UINT32(erstba_low
, XHCIInterrupter
),
3623 VMSTATE_UINT32(erstba_high
, XHCIInterrupter
),
3624 VMSTATE_UINT32(erdp_low
, XHCIInterrupter
),
3625 VMSTATE_UINT32(erdp_high
, XHCIInterrupter
),
3628 VMSTATE_BOOL(msix_used
, XHCIInterrupter
),
3629 VMSTATE_BOOL(er_pcs
, XHCIInterrupter
),
3630 VMSTATE_UINT64(er_start
, XHCIInterrupter
),
3631 VMSTATE_UINT32(er_size
, XHCIInterrupter
),
3632 VMSTATE_UINT32(er_ep_idx
, XHCIInterrupter
),
3634 /* event queue (used if ring is full) */
3635 VMSTATE_BOOL(er_full_unused
, XHCIInterrupter
),
3636 VMSTATE_UINT32_TEST(ev_buffer_put
, XHCIInterrupter
, xhci_er_full
),
3637 VMSTATE_UINT32_TEST(ev_buffer_get
, XHCIInterrupter
, xhci_er_full
),
3638 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer
, XHCIInterrupter
, EV_QUEUE
,
3640 vmstate_xhci_event
, XHCIEvent
),
3642 VMSTATE_END_OF_LIST()
3646 static const VMStateDescription vmstate_xhci
= {
3649 .post_load
= usb_xhci_post_load
,
3650 .fields
= (VMStateField
[]) {
3651 VMSTATE_PCI_DEVICE(parent_obj
, XHCIState
),
3652 VMSTATE_MSIX(parent_obj
, XHCIState
),
3654 VMSTATE_STRUCT_VARRAY_UINT32(ports
, XHCIState
, numports
, 1,
3655 vmstate_xhci_port
, XHCIPort
),
3656 VMSTATE_STRUCT_VARRAY_UINT32(slots
, XHCIState
, numslots
, 1,
3657 vmstate_xhci_slot
, XHCISlot
),
3658 VMSTATE_STRUCT_VARRAY_UINT32(intr
, XHCIState
, numintrs
, 1,
3659 vmstate_xhci_intr
, XHCIInterrupter
),
3661 /* Operational Registers */
3662 VMSTATE_UINT32(usbcmd
, XHCIState
),
3663 VMSTATE_UINT32(usbsts
, XHCIState
),
3664 VMSTATE_UINT32(dnctrl
, XHCIState
),
3665 VMSTATE_UINT32(crcr_low
, XHCIState
),
3666 VMSTATE_UINT32(crcr_high
, XHCIState
),
3667 VMSTATE_UINT32(dcbaap_low
, XHCIState
),
3668 VMSTATE_UINT32(dcbaap_high
, XHCIState
),
3669 VMSTATE_UINT32(config
, XHCIState
),
3671 /* Runtime Registers & state */
3672 VMSTATE_INT64(mfindex_start
, XHCIState
),
3673 VMSTATE_TIMER_PTR(mfwrap_timer
, XHCIState
),
3674 VMSTATE_STRUCT(cmd_ring
, XHCIState
, 1, vmstate_xhci_ring
, XHCIRing
),
3676 VMSTATE_END_OF_LIST()
3680 static Property xhci_properties
[] = {
3681 DEFINE_PROP_BIT("streams", XHCIState
, flags
,
3682 XHCI_FLAG_ENABLE_STREAMS
, true),
3683 DEFINE_PROP_UINT32("p2", XHCIState
, numports_2
, 4),
3684 DEFINE_PROP_UINT32("p3", XHCIState
, numports_3
, 4),
3685 DEFINE_PROP_END_OF_LIST(),
3688 static void xhci_instance_init(Object
*obj
)
3690 /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
3691 * line, therefore, no need to wait to realize like other devices */
3692 PCI_DEVICE(obj
)->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
3695 static void xhci_class_init(ObjectClass
*klass
, void *data
)
3697 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
3698 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3700 dc
->vmsd
= &vmstate_xhci
;
3701 dc
->props
= xhci_properties
;
3702 dc
->reset
= xhci_reset
;
3703 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
3704 k
->realize
= usb_xhci_realize
;
3705 k
->exit
= usb_xhci_exit
;
3706 k
->class_id
= PCI_CLASS_SERIAL_USB
;
3709 static const TypeInfo xhci_info
= {
3711 .parent
= TYPE_PCI_DEVICE
,
3712 .instance_size
= sizeof(XHCIState
),
3713 .class_init
= xhci_class_init
,
3714 .instance_init
= xhci_instance_init
,
3716 .interfaces
= (InterfaceInfo
[]) {
3717 { INTERFACE_PCIE_DEVICE
},
3718 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
3723 static void qemu_xhci_class_init(ObjectClass
*klass
, void *data
)
3725 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
3727 k
->vendor_id
= PCI_VENDOR_ID_REDHAT
;
3728 k
->device_id
= PCI_DEVICE_ID_REDHAT_XHCI
;
3732 static void qemu_xhci_instance_init(Object
*obj
)
3734 XHCIState
*xhci
= XHCI(obj
);
3736 xhci
->msi
= ON_OFF_AUTO_OFF
;
3737 xhci
->msix
= ON_OFF_AUTO_AUTO
;
3738 xhci
->numintrs
= MAXINTRS
;
3739 xhci
->numslots
= MAXSLOTS
;
3740 xhci_set_flag(xhci
, XHCI_FLAG_SS_FIRST
);
3743 static const TypeInfo qemu_xhci_info
= {
3744 .name
= TYPE_QEMU_XHCI
,
3745 .parent
= TYPE_XHCI
,
3746 .class_init
= qemu_xhci_class_init
,
3747 .instance_init
= qemu_xhci_instance_init
,
3750 static void xhci_register_types(void)
3752 type_register_static(&xhci_info
);
3753 type_register_static(&qemu_xhci_info
);
3756 type_init(xhci_register_types
)