2 * CRIS virtual CPU header
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 #include "exec/cpu-defs.h"
29 #define EXCP_BUSFAULT 3
33 /* CRIS-specific interrupt pending bits. */
34 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
36 /* CRUS CPU device objects interrupt lines. */
37 /* PIC passes the vector for the IRQ as the value of it sends over qemu_irq */
38 #define CRIS_CPU_IRQ 0
39 #define CRIS_CPU_NMI 1
41 /* Register aliases. R0 - R15 */
46 /* Support regs, P0 - P15 */
54 #define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */
67 #define Q_FLAG 0x80000000
68 #define M_FLAG_V32 0x40000000
69 #define PFIX_FLAG 0x800 /* CRISv10 Only. */
70 #define F_FLAG_V10 0x400
71 #define P_FLAG_V10 0x200
75 #define M_FLAG_V10 0x80
83 #define ALU_FLAGS 0x1F
85 /* Condition codes. */
108 typedef struct CPUArchState
{
110 /* P0 - P15 are referred to as special registers in the docs. */
113 /* Pseudo register for the PC. Not directly accessible on CRIS. */
116 /* Pseudo register for the kernel stack. */
124 /* Condition flag tracking. */
130 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
132 /* X flag at the time of cc snapshot. */
135 /* CRIS has certain insns that lockout interrupts. */
137 int interrupt_vector
;
141 /* FIXME: add a check in the translator to avoid writing to support
142 register sets beyond the 4th. The ISA allows up to 256! but in
143 practice there is no core that implements more than 4.
145 Support function registers are used to control units close to the
146 core. Accesses do not pass down the normal hierarchy.
148 uint32_t sregs
[4][16];
150 /* Linear feedback shift reg in the mmu. Used to provide pseudo
151 randomness for the 'hint' the mmu gives to sw for choosing valid
152 sets on TLB refills. */
153 uint32_t mmu_rand_lfsr
;
156 * We just store the stores to the tlbset here for later evaluation
157 * when the hw needs access to them.
159 * One for I and another for D.
161 TLBSet tlbsets
[2][4][16];
163 /* Fields up to this point are cleared by a CPU reset */
164 struct {} end_reset_fields
;
166 /* Members from load_info on are preserved across resets. */
172 * @env: #CPUCRISState
184 * @parent_realize: The parent class' realize handler.
185 * @parent_phases: The parent class' reset phase handlers.
186 * @vr: Version Register value.
190 struct CRISCPUClass
{
191 CPUClass parent_class
;
193 DeviceRealize parent_realize
;
194 ResettablePhases parent_phases
;
199 #ifndef CONFIG_USER_ONLY
200 extern const VMStateDescription vmstate_cris_cpu
;
202 void cris_cpu_do_interrupt(CPUState
*cpu
);
203 void crisv10_cpu_do_interrupt(CPUState
*cpu
);
204 bool cris_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
206 bool cris_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
207 MMUAccessType access_type
, int mmu_idx
,
208 bool probe
, uintptr_t retaddr
);
209 hwaddr
cris_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
212 void cris_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
);
214 int crisv10_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
215 int cris_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
216 int cris_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
218 void cris_initialize_tcg(void);
219 void cris_initialize_crisv10_tcg(void);
221 /* Instead of computing the condition codes after each CRIS instruction,
222 * QEMU just stores one operand (called CC_SRC), the result
223 * (called CC_DEST) and the type of operation (called CC_OP). When the
224 * condition codes are needed, the condition codes can be calculated
225 * using this information. Condition codes are not generated if they
226 * are only needed for conditional branches.
229 CC_OP_DYNAMIC
, /* Use env->cc_op */
256 /* CRIS uses 8k pages. */
257 #define MMAP_SHIFT TARGET_PAGE_BITS
259 #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
261 /* MMU modes definitions */
262 #define MMU_USER_IDX 1
263 static inline int cpu_mmu_index (CPUCRISState
*env
, bool ifetch
)
265 return !!(env
->pregs
[PR_CCS
] & U_FLAG
);
268 /* Support function regs. */
269 #define SFR_RW_GC_CFG 0][0
270 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
271 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
272 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
273 #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
274 #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
275 #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
276 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
278 #include "exec/cpu-all.h"
280 static inline void cpu_get_tb_cpu_state(CPUCRISState
*env
, vaddr
*pc
,
281 uint64_t *cs_base
, uint32_t *flags
)
285 *flags
= env
->dslot
|
286 (env
->pregs
[PR_CCS
] & (S_FLAG
| P_FLAG
| U_FLAG
287 | X_FLAG
| PFIX_FLAG
));
290 #define cpu_list cris_cpu_list
291 void cris_cpu_list(void);