4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * Copyright (c) 2012 SUSE LINUX Products GmbH
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu/qemu-print.h"
31 static void cris_cpu_set_pc(CPUState
*cs
, vaddr value
)
33 CRISCPU
*cpu
= CRIS_CPU(cs
);
38 static vaddr
cris_cpu_get_pc(CPUState
*cs
)
40 CRISCPU
*cpu
= CRIS_CPU(cs
);
45 static void cris_restore_state_to_opc(CPUState
*cs
,
46 const TranslationBlock
*tb
,
49 CRISCPU
*cpu
= CRIS_CPU(cs
);
51 cpu
->env
.pc
= data
[0];
54 static bool cris_cpu_has_work(CPUState
*cs
)
56 return cs
->interrupt_request
& (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_NMI
);
59 static void cris_cpu_reset_hold(Object
*obj
)
61 CPUState
*s
= CPU(obj
);
62 CRISCPU
*cpu
= CRIS_CPU(s
);
63 CRISCPUClass
*ccc
= CRIS_CPU_GET_CLASS(cpu
);
64 CPUCRISState
*env
= &cpu
->env
;
67 if (ccc
->parent_phases
.hold
) {
68 ccc
->parent_phases
.hold(obj
);
71 vr
= env
->pregs
[PR_VR
];
72 memset(env
, 0, offsetof(CPUCRISState
, end_reset_fields
));
73 env
->pregs
[PR_VR
] = vr
;
75 #if defined(CONFIG_USER_ONLY)
76 /* start in user mode with interrupts enabled. */
77 env
->pregs
[PR_CCS
] |= U_FLAG
| I_FLAG
| P_FLAG
;
80 env
->pregs
[PR_CCS
] = 0;
84 static ObjectClass
*cris_cpu_class_by_name(const char *cpu_model
)
89 #if defined(CONFIG_USER_ONLY)
90 if (strcasecmp(cpu_model
, "any") == 0) {
91 return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32"));
95 typename
= g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model
);
96 oc
= object_class_by_name(typename
);
98 if (oc
!= NULL
&& !object_class_dynamic_cast(oc
, TYPE_CRIS_CPU
)) {
104 /* Sort alphabetically by VR. */
105 static gint
cris_cpu_list_compare(gconstpointer a
, gconstpointer b
)
107 CRISCPUClass
*ccc_a
= CRIS_CPU_CLASS(a
);
108 CRISCPUClass
*ccc_b
= CRIS_CPU_CLASS(b
);
111 if (ccc_a
->vr
> ccc_b
->vr
) {
113 } else if (ccc_a
->vr
< ccc_b
->vr
) {
120 static void cris_cpu_list_entry(gpointer data
, gpointer user_data
)
122 ObjectClass
*oc
= data
;
123 const char *typename
= object_class_get_name(oc
);
126 name
= g_strndup(typename
, strlen(typename
) - strlen(CRIS_CPU_TYPE_SUFFIX
));
127 qemu_printf(" %s\n", name
);
131 void cris_cpu_list(void)
135 list
= object_class_get_list(TYPE_CRIS_CPU
, false);
136 list
= g_slist_sort(list
, cris_cpu_list_compare
);
137 qemu_printf("Available CPUs:\n");
138 g_slist_foreach(list
, cris_cpu_list_entry
, NULL
);
142 static void cris_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
144 CPUState
*cs
= CPU(dev
);
145 CRISCPUClass
*ccc
= CRIS_CPU_GET_CLASS(dev
);
146 Error
*local_err
= NULL
;
148 cpu_exec_realizefn(cs
, &local_err
);
149 if (local_err
!= NULL
) {
150 error_propagate(errp
, local_err
);
157 ccc
->parent_realize(dev
, errp
);
160 #ifndef CONFIG_USER_ONLY
161 static void cris_cpu_set_irq(void *opaque
, int irq
, int level
)
163 CRISCPU
*cpu
= opaque
;
164 CPUState
*cs
= CPU(cpu
);
165 int type
= irq
== CRIS_CPU_IRQ
? CPU_INTERRUPT_HARD
: CPU_INTERRUPT_NMI
;
167 if (irq
== CRIS_CPU_IRQ
) {
169 * The PIC passes us the vector for the IRQ as the value it sends
170 * over the qemu_irq line
172 cpu
->env
.interrupt_vector
= level
;
176 cpu_interrupt(cs
, type
);
178 cpu_reset_interrupt(cs
, type
);
183 static void cris_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
185 CRISCPU
*cc
= CRIS_CPU(cpu
);
186 CPUCRISState
*env
= &cc
->env
;
188 if (env
->pregs
[PR_VR
] != 32) {
189 info
->mach
= bfd_mach_cris_v0_v10
;
190 info
->print_insn
= print_insn_crisv10
;
192 info
->mach
= bfd_mach_cris_v32
;
193 info
->print_insn
= print_insn_crisv32
;
197 static void cris_cpu_initfn(Object
*obj
)
199 CRISCPU
*cpu
= CRIS_CPU(obj
);
200 CRISCPUClass
*ccc
= CRIS_CPU_GET_CLASS(obj
);
201 CPUCRISState
*env
= &cpu
->env
;
203 env
->pregs
[PR_VR
] = ccc
->vr
;
205 #ifndef CONFIG_USER_ONLY
206 /* IRQ and NMI lines. */
207 qdev_init_gpio_in(DEVICE(cpu
), cris_cpu_set_irq
, 2);
211 #ifndef CONFIG_USER_ONLY
212 #include "hw/core/sysemu-cpu-ops.h"
214 static const struct SysemuCPUOps cris_sysemu_ops
= {
215 .get_phys_page_debug
= cris_cpu_get_phys_page_debug
,
219 #include "hw/core/tcg-cpu-ops.h"
221 static const struct TCGCPUOps crisv10_tcg_ops
= {
222 .initialize
= cris_initialize_crisv10_tcg
,
223 .restore_state_to_opc
= cris_restore_state_to_opc
,
225 #ifndef CONFIG_USER_ONLY
226 .tlb_fill
= cris_cpu_tlb_fill
,
227 .cpu_exec_interrupt
= cris_cpu_exec_interrupt
,
228 .do_interrupt
= crisv10_cpu_do_interrupt
,
229 #endif /* !CONFIG_USER_ONLY */
232 static const struct TCGCPUOps crisv32_tcg_ops
= {
233 .initialize
= cris_initialize_tcg
,
234 .restore_state_to_opc
= cris_restore_state_to_opc
,
236 #ifndef CONFIG_USER_ONLY
237 .tlb_fill
= cris_cpu_tlb_fill
,
238 .cpu_exec_interrupt
= cris_cpu_exec_interrupt
,
239 .do_interrupt
= cris_cpu_do_interrupt
,
240 #endif /* !CONFIG_USER_ONLY */
243 static void crisv8_cpu_class_init(ObjectClass
*oc
, void *data
)
245 CPUClass
*cc
= CPU_CLASS(oc
);
246 CRISCPUClass
*ccc
= CRIS_CPU_CLASS(oc
);
249 cc
->gdb_read_register
= crisv10_cpu_gdb_read_register
;
250 cc
->tcg_ops
= &crisv10_tcg_ops
;
253 static void crisv9_cpu_class_init(ObjectClass
*oc
, void *data
)
255 CPUClass
*cc
= CPU_CLASS(oc
);
256 CRISCPUClass
*ccc
= CRIS_CPU_CLASS(oc
);
259 cc
->gdb_read_register
= crisv10_cpu_gdb_read_register
;
260 cc
->tcg_ops
= &crisv10_tcg_ops
;
263 static void crisv10_cpu_class_init(ObjectClass
*oc
, void *data
)
265 CPUClass
*cc
= CPU_CLASS(oc
);
266 CRISCPUClass
*ccc
= CRIS_CPU_CLASS(oc
);
269 cc
->gdb_read_register
= crisv10_cpu_gdb_read_register
;
270 cc
->tcg_ops
= &crisv10_tcg_ops
;
273 static void crisv11_cpu_class_init(ObjectClass
*oc
, void *data
)
275 CPUClass
*cc
= CPU_CLASS(oc
);
276 CRISCPUClass
*ccc
= CRIS_CPU_CLASS(oc
);
279 cc
->gdb_read_register
= crisv10_cpu_gdb_read_register
;
280 cc
->tcg_ops
= &crisv10_tcg_ops
;
283 static void crisv17_cpu_class_init(ObjectClass
*oc
, void *data
)
285 CPUClass
*cc
= CPU_CLASS(oc
);
286 CRISCPUClass
*ccc
= CRIS_CPU_CLASS(oc
);
289 cc
->gdb_read_register
= crisv10_cpu_gdb_read_register
;
290 cc
->tcg_ops
= &crisv10_tcg_ops
;
293 static void crisv32_cpu_class_init(ObjectClass
*oc
, void *data
)
295 CPUClass
*cc
= CPU_CLASS(oc
);
296 CRISCPUClass
*ccc
= CRIS_CPU_CLASS(oc
);
299 cc
->tcg_ops
= &crisv32_tcg_ops
;
302 static void cris_cpu_class_init(ObjectClass
*oc
, void *data
)
304 DeviceClass
*dc
= DEVICE_CLASS(oc
);
305 CPUClass
*cc
= CPU_CLASS(oc
);
306 CRISCPUClass
*ccc
= CRIS_CPU_CLASS(oc
);
307 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
309 device_class_set_parent_realize(dc
, cris_cpu_realizefn
,
310 &ccc
->parent_realize
);
312 resettable_class_set_parent_phases(rc
, NULL
, cris_cpu_reset_hold
, NULL
,
313 &ccc
->parent_phases
);
315 cc
->class_by_name
= cris_cpu_class_by_name
;
316 cc
->has_work
= cris_cpu_has_work
;
317 cc
->dump_state
= cris_cpu_dump_state
;
318 cc
->set_pc
= cris_cpu_set_pc
;
319 cc
->get_pc
= cris_cpu_get_pc
;
320 cc
->gdb_read_register
= cris_cpu_gdb_read_register
;
321 cc
->gdb_write_register
= cris_cpu_gdb_write_register
;
322 #ifndef CONFIG_USER_ONLY
323 dc
->vmsd
= &vmstate_cris_cpu
;
324 cc
->sysemu_ops
= &cris_sysemu_ops
;
327 cc
->gdb_num_core_regs
= 49;
328 cc
->gdb_stop_before_watchpoint
= true;
330 cc
->disas_set_info
= cris_disas_set_info
;
333 #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \
335 .parent = TYPE_CRIS_CPU, \
336 .class_init = initfn, \
337 .name = CRIS_CPU_TYPE_NAME(cpu_model), \
340 static const TypeInfo cris_cpu_model_type_infos
[] = {
342 .name
= TYPE_CRIS_CPU
,
344 .instance_size
= sizeof(CRISCPU
),
345 .instance_align
= __alignof(CRISCPU
),
346 .instance_init
= cris_cpu_initfn
,
348 .class_size
= sizeof(CRISCPUClass
),
349 .class_init
= cris_cpu_class_init
,
351 DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init
),
352 DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init
),
353 DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init
),
354 DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init
),
355 DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init
),
356 DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init
),
359 DEFINE_TYPES(cris_cpu_model_type_infos
)