hw/net/e1000e_core.h

   1 /*
   2  * Core code for QEMU e1000e emulation
   3  *
   4  * Software developer's manuals:
   5  * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
   6  *
   7  * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
   8  * Developed by Daynix Computing LTD (http://www.daynix.com)
   9  *
  10  * Authors:
  11  * Dmitry Fleytman <dmitry@daynix.com>
  12  * Leonid Bloch <leonid@daynix.com>
  13  * Yan Vugenfirer <yan@daynix.com>
  14  *
  15  * Based on work done by:
  16  * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
  17  * Copyright (c) 2008 Qumranet
  18  * Based on work done by:
  19  * Copyright (c) 2007 Dan Aloni
  20  * Copyright (c) 2004 Antony T Curtis
  21  *
  22  * This library is free software; you can redistribute it and/or
  23  * modify it under the terms of the GNU Lesser General Public
  24  * License as published by the Free Software Foundation; either
  25  * version 2.1 of the License, or (at your option) any later version.
  26  *
  27  * This library is distributed in the hope that it will be useful,
  28  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  29  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  30  * Lesser General Public License for more details.
  31  *
  32  * You should have received a copy of the GNU Lesser General Public
  33  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  34  */
  35
  36 #ifndef HW_NET_E1000E_CORE_H
  37 #define HW_NET_E1000E_CORE_H
  38
  39 #define E1000E_PHY_PAGE_SIZE    (0x20)
  40 #define E1000E_PHY_PAGES        (0x07)
  41 #define E1000E_MAC_SIZE         (0x8000)
  42 #define E1000E_EEPROM_SIZE      (64)
  43 #define E1000E_MSIX_VEC_NUM     (5)
  44 #define E1000E_NUM_QUEUES       (2)
  45
  46 typedef struct E1000Core E1000ECore;
  47
  48 enum { PHY_R = BIT(0),
  49        PHY_W = BIT(1),
  50        PHY_RW = PHY_R | PHY_W,
  51        PHY_ANYPAGE = BIT(2) };
  52
  53 typedef struct E1000IntrDelayTimer_st {
  54     QEMUTimer *timer;
  55     bool running;
  56     uint32_t delay_reg;
  57     uint32_t delay_resolution_ns;
  58     E1000ECore *core;
  59 } E1000IntrDelayTimer;
  60
  61 struct E1000Core {
  62     uint32_t mac[E1000E_MAC_SIZE];
  63     uint16_t phy[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE];
  64     uint16_t eeprom[E1000E_EEPROM_SIZE];
  65
  66     uint32_t rxbuf_sizes[E1000_PSRCTL_BUFFS_PER_DESC];
  67     uint32_t rx_desc_buf_size;
  68     uint32_t rxbuf_min_shift;
  69     uint8_t rx_desc_len;
  70
  71     QEMUTimer *autoneg_timer;
  72
  73     struct e1000e_tx {
  74         e1000x_txd_props props;
  75
  76         bool skip_cp;
  77         unsigned char sum_needed;
  78         bool cptse;
  79         struct NetTxPkt *tx_pkt;
  80     } tx[E1000E_NUM_QUEUES];
  81
  82     struct NetRxPkt *rx_pkt;
  83
  84     bool has_vnet;
  85     int max_queue_num;
  86
  87     /* Interrupt moderation management */
  88     uint32_t delayed_causes;
  89
  90     E1000IntrDelayTimer radv;
  91     E1000IntrDelayTimer rdtr;
  92     E1000IntrDelayTimer raid;
  93
  94     E1000IntrDelayTimer tadv;
  95     E1000IntrDelayTimer tidv;
  96
  97     E1000IntrDelayTimer itr;
  98
  99     E1000IntrDelayTimer eitr[E1000E_MSIX_VEC_NUM];
 100
 101     VMChangeStateEntry *vmstate;
 102
 103     uint32_t itr_guest_value;
 104     uint32_t eitr_guest_value[E1000E_MSIX_VEC_NUM];
 105
 106     uint16_t vet;
 107
 108     uint8_t permanent_mac[ETH_ALEN];
 109
 110     NICState *owner_nic;
 111     PCIDevice *owner;
 112     void (*owner_start_recv)(PCIDevice *d);
 113
 114     int64_t timadj;
 115 };
 116
 117 void
 118 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size);
 119
 120 uint64_t
 121 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size);
 122
 123 void
 124 e1000e_core_pci_realize(E1000ECore      *regs,
 125                        const uint16_t *eeprom_templ,
 126                        uint32_t        eeprom_size,
 127                        const uint8_t  *macaddr);
 128
 129 void
 130 e1000e_core_reset(E1000ECore *core);
 131
 132 void
 133 e1000e_core_pre_save(E1000ECore *core);
 134
 135 int
 136 e1000e_core_post_load(E1000ECore *core);
 137
 138 void
 139 e1000e_core_set_link_status(E1000ECore *core);
 140
 141 void
 142 e1000e_core_pci_uninit(E1000ECore *core);
 143
 144 bool
 145 e1000e_can_receive(E1000ECore *core);
 146
 147 ssize_t
 148 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size);
 149
 150 ssize_t
 151 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt);
 152
 153 void
 154 e1000e_start_recv(E1000ECore *core);
 155
 156 #endif