2 * TI OMAP processors emulation.
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qapi/error.h"
25 #include "exec/address-spaces.h"
26 #include "sysemu/blockdev.h"
27 #include "sysemu/qtest.h"
28 #include "sysemu/reset.h"
29 #include "sysemu/runstate.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/arm/boot.h"
33 #include "hw/arm/omap.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "chardev/char-fe.h"
37 #include "hw/block/flash.h"
38 #include "hw/arm/soc_dma.h"
39 #include "hw/sysbus.h"
40 #include "hw/boards.h"
41 #include "audio/audio.h"
43 /* Enhanced Audio Controller (CODEC only) */
63 uint32_t (*txrx
)(void *opaque
, uint32_t, int);
66 #define EAC_BUF_LEN 1024
67 uint32_t rxbuf
[EAC_BUF_LEN
];
71 uint32_t txbuf
[EAC_BUF_LEN
];
80 /* These need to be moved to the actual codec */
83 SWVoiceOut
*out_voice
;
93 static inline void omap_eac_interrupt_update(struct omap_eac_s
*s
)
95 qemu_set_irq(s
->irq
, (s
->codec
.config
[1] >> 14) & 1); /* AURDI */
98 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s
*s
)
100 qemu_set_irq(s
->codec
.rxdrq
, (s
->codec
.rxavail
|| s
->codec
.rxlen
) &&
101 ((s
->codec
.config
[1] >> 12) & 1)); /* DMAREN */
104 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s
*s
)
106 qemu_set_irq(s
->codec
.txdrq
, s
->codec
.txlen
< s
->codec
.txavail
&&
107 ((s
->codec
.config
[1] >> 11) & 1)); /* DMAWEN */
110 static inline void omap_eac_in_refill(struct omap_eac_s
*s
)
112 int left
= MIN(EAC_BUF_LEN
- s
->codec
.rxlen
, s
->codec
.rxavail
) << 2;
113 int start
= ((s
->codec
.rxoff
+ s
->codec
.rxlen
) & (EAC_BUF_LEN
- 1)) << 2;
114 int leftwrap
= MIN(left
, (EAC_BUF_LEN
<< 2) - start
);
116 uint8_t *buf
= (uint8_t *) s
->codec
.rxbuf
+ start
;
120 while (leftwrap
&& (recv
= AUD_read(s
->codec
.in_voice
, buf
+ start
,
121 leftwrap
)) > 0) { /* Be defensive */
126 s
->codec
.rxavail
= 0;
128 s
->codec
.rxavail
-= start
>> 2;
129 s
->codec
.rxlen
+= start
>> 2;
131 if (recv
> 0 && left
> 0) {
133 while (left
&& (recv
= AUD_read(s
->codec
.in_voice
,
134 (uint8_t *) s
->codec
.rxbuf
+ start
,
135 left
)) > 0) { /* Be defensive */
140 s
->codec
.rxavail
= 0;
142 s
->codec
.rxavail
-= start
>> 2;
143 s
->codec
.rxlen
+= start
>> 2;
147 static inline void omap_eac_out_empty(struct omap_eac_s
*s
)
149 int left
= s
->codec
.txlen
<< 2;
153 while (left
&& (sent
= AUD_write(s
->codec
.out_voice
,
154 (uint8_t *) s
->codec
.txbuf
+ start
,
155 left
)) > 0) { /* Be defensive */
161 s
->codec
.txavail
= 0;
162 omap_eac_out_dmarequest_update(s
);
169 static void omap_eac_in_cb(void *opaque
, int avail_b
)
171 struct omap_eac_s
*s
= opaque
;
173 s
->codec
.rxavail
= avail_b
>> 2;
174 omap_eac_in_refill(s
);
175 /* TODO: possibly discard current buffer if overrun */
176 omap_eac_in_dmarequest_update(s
);
179 static void omap_eac_out_cb(void *opaque
, int free_b
)
181 struct omap_eac_s
*s
= opaque
;
183 s
->codec
.txavail
= free_b
>> 2;
185 omap_eac_out_empty(s
);
187 omap_eac_out_dmarequest_update(s
);
190 static void omap_eac_enable_update(struct omap_eac_s
*s
)
192 s
->codec
.enable
= !(s
->codec
.config
[1] & 1) && /* EACPWD */
193 (s
->codec
.config
[1] & 2) && /* AUDEN */
197 static const int omap_eac_fsint
[4] = {
204 static const int omap_eac_fsint2
[8] = {
213 static const int omap_eac_fsint3
[16] = {
222 0, 0, 0, 0, 0, 0, 0, 0,
225 static void omap_eac_rate_update(struct omap_eac_s
*s
)
229 fsint
[2] = (s
->codec
.config
[3] >> 9) & 0xf;
230 fsint
[1] = (s
->codec
.config
[2] >> 0) & 0x7;
231 fsint
[0] = (s
->codec
.config
[0] >> 6) & 0x3;
233 s
->codec
.rate
= omap_eac_fsint3
[fsint
[2]];
234 else if (fsint
[1] < 0x7)
235 s
->codec
.rate
= omap_eac_fsint2
[fsint
[1]];
237 s
->codec
.rate
= omap_eac_fsint
[fsint
[0]];
240 static void omap_eac_volume_update(struct omap_eac_s
*s
)
245 static void omap_eac_format_update(struct omap_eac_s
*s
)
247 struct audsettings fmt
;
249 /* The hardware buffers at most one sample */
253 if (s
->codec
.in_voice
) {
254 AUD_set_active_in(s
->codec
.in_voice
, 0);
255 AUD_close_in(&s
->codec
.card
, s
->codec
.in_voice
);
256 s
->codec
.in_voice
= NULL
;
258 if (s
->codec
.out_voice
) {
259 omap_eac_out_empty(s
);
260 AUD_set_active_out(s
->codec
.out_voice
, 0);
261 AUD_close_out(&s
->codec
.card
, s
->codec
.out_voice
);
262 s
->codec
.out_voice
= NULL
;
263 s
->codec
.txavail
= 0;
265 /* Discard what couldn't be written */
268 omap_eac_enable_update(s
);
269 if (!s
->codec
.enable
)
272 omap_eac_rate_update(s
);
273 fmt
.endianness
= ((s
->codec
.config
[0] >> 8) & 1); /* LI_BI */
274 fmt
.nchannels
= ((s
->codec
.config
[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
275 fmt
.freq
= s
->codec
.rate
;
276 /* TODO: signedness possibly depends on the CODEC hardware - or
277 * does I2S specify it? */
278 /* All register writes are 16 bits so we store 16-bit samples
279 * in the buffers regardless of AGCFR[B8_16] value. */
280 fmt
.fmt
= AUDIO_FORMAT_U16
;
282 s
->codec
.in_voice
= AUD_open_in(&s
->codec
.card
, s
->codec
.in_voice
,
283 "eac.codec.in", s
, omap_eac_in_cb
, &fmt
);
284 s
->codec
.out_voice
= AUD_open_out(&s
->codec
.card
, s
->codec
.out_voice
,
285 "eac.codec.out", s
, omap_eac_out_cb
, &fmt
);
287 omap_eac_volume_update(s
);
289 AUD_set_active_in(s
->codec
.in_voice
, 1);
290 AUD_set_active_out(s
->codec
.out_voice
, 1);
293 static void omap_eac_reset(struct omap_eac_s
*s
)
319 s
->modem
.control
= 0x00;
320 s
->modem
.config
= 0x0000;
321 s
->bt
.control
= 0x00;
322 s
->bt
.config
= 0x0000;
323 s
->codec
.config
[0] = 0x0649;
324 s
->codec
.config
[1] = 0x0000;
325 s
->codec
.config
[2] = 0x0007;
326 s
->codec
.config
[3] = 0x1ffc;
330 s
->codec
.rxavail
= 0;
331 s
->codec
.txavail
= 0;
333 omap_eac_format_update(s
);
334 omap_eac_interrupt_update(s
);
337 static uint64_t omap_eac_read(void *opaque
, hwaddr addr
, unsigned size
)
339 struct omap_eac_s
*s
= opaque
;
343 return omap_badwidth_read16(opaque
, addr
);
347 case 0x000: /* CPCFR1 */
349 case 0x004: /* CPCFR2 */
351 case 0x008: /* CPCFR3 */
353 case 0x00c: /* CPCFR4 */
356 case 0x010: /* CPTCTL */
357 return s
->control
| ((s
->codec
.rxavail
+ s
->codec
.rxlen
> 0) << 7) |
358 ((s
->codec
.txlen
< s
->codec
.txavail
) << 5);
360 case 0x014: /* CPTTADR */
362 case 0x018: /* CPTDATL */
363 return s
->data
& 0xff;
364 case 0x01c: /* CPTDATH */
366 case 0x020: /* CPTVSLL */
368 case 0x024: /* CPTVSLH */
369 return s
->vtsl
| (3 << 5); /* CRDY1 | CRDY2 */
370 case 0x040: /* MPCTR */
371 return s
->modem
.control
;
372 case 0x044: /* MPMCCFR */
373 return s
->modem
.config
;
374 case 0x060: /* BPCTR */
375 return s
->bt
.control
;
376 case 0x064: /* BPMCCFR */
378 case 0x080: /* AMSCFR */
380 case 0x084: /* AMVCTR */
382 case 0x088: /* AM1VCTR */
384 case 0x08c: /* AM2VCTR */
386 case 0x090: /* AM3VCTR */
388 case 0x094: /* ASTCTR */
390 case 0x098: /* APD1LCR */
392 case 0x09c: /* APD1RCR */
394 case 0x0a0: /* APD2LCR */
396 case 0x0a4: /* APD2RCR */
398 case 0x0a8: /* APD3LCR */
400 case 0x0ac: /* APD3RCR */
402 case 0x0b0: /* APD4R */
404 case 0x0b4: /* ADWR */
405 /* This should be write-only? Docs list it as read-only. */
407 case 0x0b8: /* ADRDR */
408 if (likely(s
->codec
.rxlen
> 1)) {
409 ret
= s
->codec
.rxbuf
[s
->codec
.rxoff
++];
411 s
->codec
.rxoff
&= EAC_BUF_LEN
- 1;
413 } else if (s
->codec
.rxlen
) {
414 ret
= s
->codec
.rxbuf
[s
->codec
.rxoff
++];
416 s
->codec
.rxoff
&= EAC_BUF_LEN
- 1;
417 if (s
->codec
.rxavail
)
418 omap_eac_in_refill(s
);
419 omap_eac_in_dmarequest_update(s
);
423 case 0x0bc: /* AGCFR */
424 return s
->codec
.config
[0];
425 case 0x0c0: /* AGCTR */
426 return s
->codec
.config
[1] | ((s
->codec
.config
[1] & 2) << 14);
427 case 0x0c4: /* AGCFR2 */
428 return s
->codec
.config
[2];
429 case 0x0c8: /* AGCFR3 */
430 return s
->codec
.config
[3];
431 case 0x0cc: /* MBPDMACTR */
432 case 0x0d0: /* MPDDMARR */
433 case 0x0d8: /* MPUDMARR */
434 case 0x0e4: /* BPDDMARR */
435 case 0x0ec: /* BPUDMARR */
438 case 0x100: /* VERSION_NUMBER */
441 case 0x104: /* SYSCONFIG */
444 case 0x108: /* SYSSTATUS */
445 return 1 | 0xe; /* RESETDONE | stuff */
452 static void omap_eac_write(void *opaque
, hwaddr addr
,
453 uint64_t value
, unsigned size
)
455 struct omap_eac_s
*s
= opaque
;
458 omap_badwidth_write16(opaque
, addr
, value
);
463 case 0x098: /* APD1LCR */
464 case 0x09c: /* APD1RCR */
465 case 0x0a0: /* APD2LCR */
466 case 0x0a4: /* APD2RCR */
467 case 0x0a8: /* APD3LCR */
468 case 0x0ac: /* APD3RCR */
469 case 0x0b0: /* APD4R */
470 case 0x0b8: /* ADRDR */
471 case 0x0d0: /* MPDDMARR */
472 case 0x0d8: /* MPUDMARR */
473 case 0x0e4: /* BPDDMARR */
474 case 0x0ec: /* BPUDMARR */
475 case 0x100: /* VERSION_NUMBER */
476 case 0x108: /* SYSSTATUS */
480 case 0x000: /* CPCFR1 */
481 s
->config
[0] = value
& 0xff;
482 omap_eac_format_update(s
);
484 case 0x004: /* CPCFR2 */
485 s
->config
[1] = value
& 0xff;
486 omap_eac_format_update(s
);
488 case 0x008: /* CPCFR3 */
489 s
->config
[2] = value
& 0xff;
490 omap_eac_format_update(s
);
492 case 0x00c: /* CPCFR4 */
493 s
->config
[3] = value
& 0xff;
494 omap_eac_format_update(s
);
497 case 0x010: /* CPTCTL */
498 /* Assuming TXF and TXE bits are read-only... */
499 s
->control
= value
& 0x5f;
500 omap_eac_interrupt_update(s
);
503 case 0x014: /* CPTTADR */
504 s
->address
= value
& 0xff;
506 case 0x018: /* CPTDATL */
508 s
->data
|= value
& 0xff;
510 case 0x01c: /* CPTDATH */
512 s
->data
|= value
<< 8;
514 case 0x020: /* CPTVSLL */
515 s
->vtol
= value
& 0xf8;
517 case 0x024: /* CPTVSLH */
518 s
->vtsl
= value
& 0x9f;
520 case 0x040: /* MPCTR */
521 s
->modem
.control
= value
& 0x8f;
523 case 0x044: /* MPMCCFR */
524 s
->modem
.config
= value
& 0x7fff;
526 case 0x060: /* BPCTR */
527 s
->bt
.control
= value
& 0x8f;
529 case 0x064: /* BPMCCFR */
530 s
->bt
.config
= value
& 0x7fff;
532 case 0x080: /* AMSCFR */
533 s
->mixer
= value
& 0x0fff;
535 case 0x084: /* AMVCTR */
536 s
->gain
[0] = value
& 0xffff;
538 case 0x088: /* AM1VCTR */
539 s
->gain
[1] = value
& 0xff7f;
541 case 0x08c: /* AM2VCTR */
542 s
->gain
[2] = value
& 0xff7f;
544 case 0x090: /* AM3VCTR */
545 s
->gain
[3] = value
& 0xff7f;
547 case 0x094: /* ASTCTR */
548 s
->att
= value
& 0xff;
551 case 0x0b4: /* ADWR */
552 s
->codec
.txbuf
[s
->codec
.txlen
++] = value
;
553 if (unlikely(s
->codec
.txlen
== EAC_BUF_LEN
||
554 s
->codec
.txlen
== s
->codec
.txavail
)) {
555 if (s
->codec
.txavail
)
556 omap_eac_out_empty(s
);
557 /* Discard what couldn't be written */
562 case 0x0bc: /* AGCFR */
563 s
->codec
.config
[0] = value
& 0x07ff;
564 omap_eac_format_update(s
);
566 case 0x0c0: /* AGCTR */
567 s
->codec
.config
[1] = value
& 0x780f;
568 omap_eac_format_update(s
);
570 case 0x0c4: /* AGCFR2 */
571 s
->codec
.config
[2] = value
& 0x003f;
572 omap_eac_format_update(s
);
574 case 0x0c8: /* AGCFR3 */
575 s
->codec
.config
[3] = value
& 0xffff;
576 omap_eac_format_update(s
);
578 case 0x0cc: /* MBPDMACTR */
579 case 0x0d4: /* MPDDMAWR */
580 case 0x0e0: /* MPUDMAWR */
581 case 0x0e8: /* BPDDMAWR */
582 case 0x0f0: /* BPUDMAWR */
585 case 0x104: /* SYSCONFIG */
586 if (value
& (1 << 1)) /* SOFTRESET */
588 s
->sysconfig
= value
& 0x31d;
597 static const MemoryRegionOps omap_eac_ops
= {
598 .read
= omap_eac_read
,
599 .write
= omap_eac_write
,
600 .endianness
= DEVICE_NATIVE_ENDIAN
,
603 static struct omap_eac_s
*omap_eac_init(struct omap_target_agent_s
*ta
,
604 qemu_irq irq
, qemu_irq
*drq
, omap_clk fclk
, omap_clk iclk
)
606 struct omap_eac_s
*s
= g_new0(struct omap_eac_s
, 1);
609 s
->codec
.rxdrq
= *drq
++;
610 s
->codec
.txdrq
= *drq
;
613 if (current_machine
->audiodev
) {
614 s
->codec
.card
.name
= g_strdup(current_machine
->audiodev
);
615 s
->codec
.card
.state
= audio_state_by_name(s
->codec
.card
.name
, &error_fatal
);
617 AUD_register_card("OMAP EAC", &s
->codec
.card
, &error_fatal
);
619 memory_region_init_io(&s
->iomem
, NULL
, &omap_eac_ops
, s
, "omap.eac",
620 omap_l4_region_size(ta
, 0));
621 omap_l4_attach(ta
, 0, &s
->iomem
);
626 /* STI/XTI (emulation interface) console - reverse engineered only */
630 MemoryRegion iomem_fifo
;
638 uint32_t serial_config
;
641 #define STI_TRACE_CONSOLE_CHANNEL 239
642 #define STI_TRACE_CONTROL_CHANNEL 253
644 static inline void omap_sti_interrupt_update(struct omap_sti_s
*s
)
646 qemu_set_irq(s
->irq
, s
->irqst
& s
->irqen
);
649 static void omap_sti_reset(struct omap_sti_s
*s
)
655 s
->serial_config
= 0;
657 omap_sti_interrupt_update(s
);
660 static uint64_t omap_sti_read(void *opaque
, hwaddr addr
,
663 struct omap_sti_s
*s
= opaque
;
666 return omap_badwidth_read32(opaque
, addr
);
670 case 0x00: /* STI_REVISION */
673 case 0x10: /* STI_SYSCONFIG */
676 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
679 case 0x18: /* STI_IRQSTATUS */
682 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
685 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
686 case 0x28: /* STI_RX_DR / XTI_RXDATA */
690 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
691 return s
->clkcontrol
;
693 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
694 return s
->serial_config
;
701 static void omap_sti_write(void *opaque
, hwaddr addr
,
702 uint64_t value
, unsigned size
)
704 struct omap_sti_s
*s
= opaque
;
707 omap_badwidth_write32(opaque
, addr
, value
);
712 case 0x00: /* STI_REVISION */
713 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
717 case 0x10: /* STI_SYSCONFIG */
718 if (value
& (1 << 1)) /* SOFTRESET */
720 s
->sysconfig
= value
& 0xfe;
723 case 0x18: /* STI_IRQSTATUS */
725 omap_sti_interrupt_update(s
);
728 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
729 s
->irqen
= value
& 0xffff;
730 omap_sti_interrupt_update(s
);
733 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
734 s
->clkcontrol
= value
& 0xff;
737 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
738 s
->serial_config
= value
& 0xff;
741 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
742 case 0x28: /* STI_RX_DR / XTI_RXDATA */
752 static const MemoryRegionOps omap_sti_ops
= {
753 .read
= omap_sti_read
,
754 .write
= omap_sti_write
,
755 .endianness
= DEVICE_NATIVE_ENDIAN
,
758 static uint64_t omap_sti_fifo_read(void *opaque
, hwaddr addr
, unsigned size
)
764 static void omap_sti_fifo_write(void *opaque
, hwaddr addr
,
765 uint64_t value
, unsigned size
)
767 struct omap_sti_s
*s
= opaque
;
769 uint8_t byte
= value
;
772 omap_badwidth_write8(opaque
, addr
, size
);
776 if (ch
== STI_TRACE_CONTROL_CHANNEL
) {
777 /* Flush channel <i>value</i>. */
778 /* XXX this blocks entire thread. Rewrite to use
779 * qemu_chr_fe_write and background I/O callbacks */
780 qemu_chr_fe_write_all(&s
->chr
, (const uint8_t *) "\r", 1);
781 } else if (ch
== STI_TRACE_CONSOLE_CHANNEL
|| 1) {
782 if (value
== 0xc0 || value
== 0xc3) {
783 /* Open channel <i>ch</i>. */
784 } else if (value
== 0x00) {
785 qemu_chr_fe_write_all(&s
->chr
, (const uint8_t *) "\n", 1);
787 qemu_chr_fe_write_all(&s
->chr
, &byte
, 1);
792 static const MemoryRegionOps omap_sti_fifo_ops
= {
793 .read
= omap_sti_fifo_read
,
794 .write
= omap_sti_fifo_write
,
795 .endianness
= DEVICE_NATIVE_ENDIAN
,
798 static struct omap_sti_s
*omap_sti_init(struct omap_target_agent_s
*ta
,
799 MemoryRegion
*sysmem
,
800 hwaddr channel_base
, qemu_irq irq
, omap_clk clk
,
803 struct omap_sti_s
*s
= g_new0(struct omap_sti_s
, 1);
808 qemu_chr_fe_init(&s
->chr
, chr
?: qemu_chr_new("null", "null", NULL
),
811 memory_region_init_io(&s
->iomem
, NULL
, &omap_sti_ops
, s
, "omap.sti",
812 omap_l4_region_size(ta
, 0));
813 omap_l4_attach(ta
, 0, &s
->iomem
);
815 memory_region_init_io(&s
->iomem_fifo
, NULL
, &omap_sti_fifo_ops
, s
,
816 "omap.sti.fifo", 0x10000);
817 memory_region_add_subregion(sysmem
, channel_base
, &s
->iomem_fifo
);
822 /* L4 Interconnect */
824 #define L4TAO(n) ((n) + 39)
826 static const struct omap_l4_region_s omap_l4_region
[125] = {
827 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
828 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
829 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
830 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
831 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
832 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
833 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
834 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
835 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
836 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
837 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
838 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
839 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
840 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
841 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
842 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
843 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
844 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
845 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
846 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
847 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
848 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
849 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
850 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
851 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
852 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
853 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
854 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
855 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
856 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
857 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
858 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
859 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
860 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
861 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
862 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
863 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
864 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
865 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
866 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
867 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
868 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
869 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
870 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
871 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
872 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
873 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
874 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
875 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
876 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
877 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
878 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
879 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
880 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
881 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
882 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
883 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
884 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
885 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
886 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
887 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
888 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
889 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
890 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
891 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
892 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
893 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
894 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
895 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
896 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
897 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
898 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
899 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
900 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
901 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
902 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
903 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
904 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
905 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
906 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
907 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
908 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
909 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
910 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
911 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
912 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
913 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
914 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
915 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
916 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
917 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
918 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
919 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
920 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
921 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
922 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
923 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
924 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
925 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
926 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
927 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
928 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
929 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
930 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
931 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
932 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
933 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
934 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
935 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
936 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
937 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
938 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
939 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
940 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
941 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
942 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
943 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
944 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
945 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
946 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
947 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
948 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
949 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
950 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
951 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
954 static const struct omap_l4_agent_info_s omap_l4_agent_info
[54] = {
955 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
956 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
957 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
958 { L4TAO(3), 7, 3, 2 }, /* PRCM */
959 { L4TA(1), 10, 2, 1 }, /* BCM */
960 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
961 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
962 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
963 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
964 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
965 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
966 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
967 { L4TA(12), 38, 2, 1 }, /* sDMA */
968 { L4TA(13), 40, 5, 4 }, /* SSI */
969 { L4TAO(4), 45, 2, 1 }, /* USB */
970 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
971 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
972 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
973 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
974 { L4TA(18), 55, 2, 1 }, /* XTI */
975 { L4TA(19), 57, 2, 1 }, /* UART1 */
976 { L4TA(20), 59, 2, 1 }, /* UART2 */
977 { L4TA(21), 61, 2, 1 }, /* UART3 */
978 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
979 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
980 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
981 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
982 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
983 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
984 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
985 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
986 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
987 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
988 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
989 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
990 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
991 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
992 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
993 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
994 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
995 { L4TA(32), 97, 2, 1 }, /* EAC */
996 { L4TA(33), 99, 2, 1 }, /* FAC */
997 { L4TA(34), 101, 2, 1 }, /* IPC */
998 { L4TA(35), 103, 2, 1 }, /* SPI1 */
999 { L4TA(36), 105, 2, 1 }, /* SPI2 */
1000 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
1001 { L4TAO(10), 109, 2, 1 },
1002 { L4TAO(11), 111, 2, 1 }, /* RNG */
1003 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
1004 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
1005 { L4TA(37), 117, 2, 1 }, /* AES */
1006 { L4TA(38), 119, 2, 1 }, /* PKA */
1008 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
1011 #define omap_l4ta(bus, cs) \
1012 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TA(cs))
1013 #define omap_l4tao(bus, cs) \
1014 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TAO(cs))
1016 /* Power, Reset, and Clock Management */
1017 struct omap_prcm_s
{
1019 struct omap_mpu_state_s
*mpu
;
1020 MemoryRegion iomem0
;
1021 MemoryRegion iomem1
;
1028 uint32_t scratch
[20];
1032 uint32_t clkemul
[1];
1036 uint32_t clkctrl
[4];
1037 uint32_t clkidle
[7];
1038 uint32_t setuptime
[2];
1044 uint32_t rstctrl
[1];
1046 uint32_t rsttime_wkup
;
1051 int dpll_lock
, apll_lock
[2];
1054 static void omap_prcm_int_update(struct omap_prcm_s
*s
, int dom
)
1056 qemu_set_irq(s
->irq
[dom
], s
->irqst
[dom
] & s
->irqen
[dom
]);
1057 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
1060 static uint64_t omap_prcm_read(void *opaque
, hwaddr addr
,
1063 struct omap_prcm_s
*s
= opaque
;
1067 return omap_badwidth_read32(opaque
, addr
);
1071 case 0x000: /* PRCM_REVISION */
1074 case 0x010: /* PRCM_SYSCONFIG */
1075 return s
->sysconfig
;
1077 case 0x018: /* PRCM_IRQSTATUS_MPU */
1080 case 0x01c: /* PRCM_IRQENABLE_MPU */
1083 case 0x050: /* PRCM_VOLTCTRL */
1085 case 0x054: /* PRCM_VOLTST */
1086 return s
->voltctrl
& 3;
1088 case 0x060: /* PRCM_CLKSRC_CTRL */
1089 return s
->clksrc
[0];
1090 case 0x070: /* PRCM_CLKOUT_CTRL */
1091 return s
->clkout
[0];
1092 case 0x078: /* PRCM_CLKEMUL_CTRL */
1093 return s
->clkemul
[0];
1094 case 0x080: /* PRCM_CLKCFG_CTRL */
1095 case 0x084: /* PRCM_CLKCFG_STATUS */
1098 case 0x090: /* PRCM_VOLTSETUP */
1099 return s
->setuptime
[0];
1101 case 0x094: /* PRCM_CLKSSETUP */
1102 return s
->setuptime
[1];
1104 case 0x098: /* PRCM_POLCTRL */
1105 return s
->clkpol
[0];
1107 case 0x0b0: /* GENERAL_PURPOSE1 */
1108 case 0x0b4: /* GENERAL_PURPOSE2 */
1109 case 0x0b8: /* GENERAL_PURPOSE3 */
1110 case 0x0bc: /* GENERAL_PURPOSE4 */
1111 case 0x0c0: /* GENERAL_PURPOSE5 */
1112 case 0x0c4: /* GENERAL_PURPOSE6 */
1113 case 0x0c8: /* GENERAL_PURPOSE7 */
1114 case 0x0cc: /* GENERAL_PURPOSE8 */
1115 case 0x0d0: /* GENERAL_PURPOSE9 */
1116 case 0x0d4: /* GENERAL_PURPOSE10 */
1117 case 0x0d8: /* GENERAL_PURPOSE11 */
1118 case 0x0dc: /* GENERAL_PURPOSE12 */
1119 case 0x0e0: /* GENERAL_PURPOSE13 */
1120 case 0x0e4: /* GENERAL_PURPOSE14 */
1121 case 0x0e8: /* GENERAL_PURPOSE15 */
1122 case 0x0ec: /* GENERAL_PURPOSE16 */
1123 case 0x0f0: /* GENERAL_PURPOSE17 */
1124 case 0x0f4: /* GENERAL_PURPOSE18 */
1125 case 0x0f8: /* GENERAL_PURPOSE19 */
1126 case 0x0fc: /* GENERAL_PURPOSE20 */
1127 return s
->scratch
[(addr
- 0xb0) >> 2];
1129 case 0x140: /* CM_CLKSEL_MPU */
1130 return s
->clksel
[0];
1131 case 0x148: /* CM_CLKSTCTRL_MPU */
1132 return s
->clkctrl
[0];
1134 case 0x158: /* RM_RSTST_MPU */
1136 case 0x1c8: /* PM_WKDEP_MPU */
1138 case 0x1d4: /* PM_EVGENCTRL_MPU */
1140 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1141 return s
->evtime
[0];
1142 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1143 return s
->evtime
[1];
1144 case 0x1e0: /* PM_PWSTCTRL_MPU */
1146 case 0x1e4: /* PM_PWSTST_MPU */
1149 case 0x200: /* CM_FCLKEN1_CORE */
1151 case 0x204: /* CM_FCLKEN2_CORE */
1153 case 0x210: /* CM_ICLKEN1_CORE */
1155 case 0x214: /* CM_ICLKEN2_CORE */
1157 case 0x21c: /* CM_ICLKEN4_CORE */
1160 case 0x220: /* CM_IDLEST1_CORE */
1161 /* TODO: check the actual iclk status */
1163 case 0x224: /* CM_IDLEST2_CORE */
1164 /* TODO: check the actual iclk status */
1166 case 0x22c: /* CM_IDLEST4_CORE */
1167 /* TODO: check the actual iclk status */
1170 case 0x230: /* CM_AUTOIDLE1_CORE */
1171 return s
->clkidle
[0];
1172 case 0x234: /* CM_AUTOIDLE2_CORE */
1173 return s
->clkidle
[1];
1174 case 0x238: /* CM_AUTOIDLE3_CORE */
1175 return s
->clkidle
[2];
1176 case 0x23c: /* CM_AUTOIDLE4_CORE */
1177 return s
->clkidle
[3];
1179 case 0x240: /* CM_CLKSEL1_CORE */
1180 return s
->clksel
[1];
1181 case 0x244: /* CM_CLKSEL2_CORE */
1182 return s
->clksel
[2];
1184 case 0x248: /* CM_CLKSTCTRL_CORE */
1185 return s
->clkctrl
[1];
1187 case 0x2a0: /* PM_WKEN1_CORE */
1189 case 0x2a4: /* PM_WKEN2_CORE */
1192 case 0x2b0: /* PM_WKST1_CORE */
1194 case 0x2b4: /* PM_WKST2_CORE */
1196 case 0x2c8: /* PM_WKDEP_CORE */
1199 case 0x2e0: /* PM_PWSTCTRL_CORE */
1201 case 0x2e4: /* PM_PWSTST_CORE */
1202 return 0x000030 | (s
->power
[1] & 0xfc00);
1204 case 0x300: /* CM_FCLKEN_GFX */
1206 case 0x310: /* CM_ICLKEN_GFX */
1208 case 0x320: /* CM_IDLEST_GFX */
1209 /* TODO: check the actual iclk status */
1211 case 0x340: /* CM_CLKSEL_GFX */
1212 return s
->clksel
[3];
1213 case 0x348: /* CM_CLKSTCTRL_GFX */
1214 return s
->clkctrl
[2];
1215 case 0x350: /* RM_RSTCTRL_GFX */
1216 return s
->rstctrl
[0];
1217 case 0x358: /* RM_RSTST_GFX */
1219 case 0x3c8: /* PM_WKDEP_GFX */
1222 case 0x3e0: /* PM_PWSTCTRL_GFX */
1224 case 0x3e4: /* PM_PWSTST_GFX */
1225 return s
->power
[2] & 3;
1227 case 0x400: /* CM_FCLKEN_WKUP */
1229 case 0x410: /* CM_ICLKEN_WKUP */
1231 case 0x420: /* CM_IDLEST_WKUP */
1232 /* TODO: check the actual iclk status */
1234 case 0x430: /* CM_AUTOIDLE_WKUP */
1235 return s
->clkidle
[4];
1236 case 0x440: /* CM_CLKSEL_WKUP */
1237 return s
->clksel
[4];
1238 case 0x450: /* RM_RSTCTRL_WKUP */
1240 case 0x454: /* RM_RSTTIME_WKUP */
1241 return s
->rsttime_wkup
;
1242 case 0x458: /* RM_RSTST_WKUP */
1244 case 0x4a0: /* PM_WKEN_WKUP */
1246 case 0x4b0: /* PM_WKST_WKUP */
1249 case 0x500: /* CM_CLKEN_PLL */
1251 case 0x520: /* CM_IDLEST_CKGEN */
1252 ret
= 0x0000070 | (s
->apll_lock
[0] << 9) | (s
->apll_lock
[1] << 8);
1253 if (!(s
->clksel
[6] & 3))
1254 /* Core uses 32-kHz clock */
1256 else if (!s
->dpll_lock
)
1257 /* DPLL not locked, core uses ref_clk */
1260 /* Core uses DPLL */
1263 case 0x530: /* CM_AUTOIDLE_PLL */
1264 return s
->clkidle
[5];
1265 case 0x540: /* CM_CLKSEL1_PLL */
1266 return s
->clksel
[5];
1267 case 0x544: /* CM_CLKSEL2_PLL */
1268 return s
->clksel
[6];
1270 case 0x800: /* CM_FCLKEN_DSP */
1271 return s
->clken
[10];
1272 case 0x810: /* CM_ICLKEN_DSP */
1273 return s
->clken
[11];
1274 case 0x820: /* CM_IDLEST_DSP */
1275 /* TODO: check the actual iclk status */
1277 case 0x830: /* CM_AUTOIDLE_DSP */
1278 return s
->clkidle
[6];
1279 case 0x840: /* CM_CLKSEL_DSP */
1280 return s
->clksel
[7];
1281 case 0x848: /* CM_CLKSTCTRL_DSP */
1282 return s
->clkctrl
[3];
1283 case 0x850: /* RM_RSTCTRL_DSP */
1285 case 0x858: /* RM_RSTST_DSP */
1287 case 0x8c8: /* PM_WKDEP_DSP */
1289 case 0x8e0: /* PM_PWSTCTRL_DSP */
1291 case 0x8e4: /* PM_PWSTST_DSP */
1292 return 0x008030 | (s
->power
[3] & 0x3003);
1294 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1296 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1299 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1301 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1309 static void omap_prcm_apll_update(struct omap_prcm_s
*s
)
1313 mode
[0] = (s
->clken
[9] >> 6) & 3;
1314 s
->apll_lock
[0] = (mode
[0] == 3);
1315 mode
[1] = (s
->clken
[9] >> 2) & 3;
1316 s
->apll_lock
[1] = (mode
[1] == 3);
1317 /* TODO: update clocks */
1319 if (mode
[0] == 1 || mode
[0] == 2 || mode
[1] == 1 || mode
[1] == 2)
1320 fprintf(stderr
, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
1324 static void omap_prcm_dpll_update(struct omap_prcm_s
*s
)
1326 omap_clk dpll
= omap_findclk(s
->mpu
, "dpll");
1327 omap_clk dpll_x2
= omap_findclk(s
->mpu
, "dpll");
1328 omap_clk core
= omap_findclk(s
->mpu
, "core_clk");
1329 int mode
= (s
->clken
[9] >> 0) & 3;
1332 mult
= (s
->clksel
[5] >> 12) & 0x3ff;
1333 div
= (s
->clksel
[5] >> 8) & 0xf;
1334 if (mult
== 0 || mult
== 1)
1335 mode
= 1; /* Bypass */
1340 fprintf(stderr
, "%s: bad EN_DPLL\n", __func__
);
1342 case 1: /* Low-power bypass mode (Default) */
1343 case 2: /* Fast-relock bypass mode */
1344 omap_clk_setrate(dpll
, 1, 1);
1345 omap_clk_setrate(dpll_x2
, 1, 1);
1347 case 3: /* Lock mode */
1348 s
->dpll_lock
= 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
1350 omap_clk_setrate(dpll
, div
+ 1, mult
);
1351 omap_clk_setrate(dpll_x2
, div
+ 1, mult
* 2);
1355 switch ((s
->clksel
[6] >> 0) & 3) {
1357 omap_clk_reparent(core
, omap_findclk(s
->mpu
, "clk32-kHz"));
1360 omap_clk_reparent(core
, dpll
);
1364 omap_clk_reparent(core
, dpll_x2
);
1367 fprintf(stderr
, "%s: bad CORE_CLK_SRC\n", __func__
);
1372 static void omap_prcm_write(void *opaque
, hwaddr addr
,
1373 uint64_t value
, unsigned size
)
1375 struct omap_prcm_s
*s
= opaque
;
1378 omap_badwidth_write32(opaque
, addr
, value
);
1383 case 0x000: /* PRCM_REVISION */
1384 case 0x054: /* PRCM_VOLTST */
1385 case 0x084: /* PRCM_CLKCFG_STATUS */
1386 case 0x1e4: /* PM_PWSTST_MPU */
1387 case 0x220: /* CM_IDLEST1_CORE */
1388 case 0x224: /* CM_IDLEST2_CORE */
1389 case 0x22c: /* CM_IDLEST4_CORE */
1390 case 0x2c8: /* PM_WKDEP_CORE */
1391 case 0x2e4: /* PM_PWSTST_CORE */
1392 case 0x320: /* CM_IDLEST_GFX */
1393 case 0x3e4: /* PM_PWSTST_GFX */
1394 case 0x420: /* CM_IDLEST_WKUP */
1395 case 0x520: /* CM_IDLEST_CKGEN */
1396 case 0x820: /* CM_IDLEST_DSP */
1397 case 0x8e4: /* PM_PWSTST_DSP */
1401 case 0x010: /* PRCM_SYSCONFIG */
1402 s
->sysconfig
= value
& 1;
1405 case 0x018: /* PRCM_IRQSTATUS_MPU */
1406 s
->irqst
[0] &= ~value
;
1407 omap_prcm_int_update(s
, 0);
1409 case 0x01c: /* PRCM_IRQENABLE_MPU */
1410 s
->irqen
[0] = value
& 0x3f;
1411 omap_prcm_int_update(s
, 0);
1414 case 0x050: /* PRCM_VOLTCTRL */
1415 s
->voltctrl
= value
& 0xf1c3;
1418 case 0x060: /* PRCM_CLKSRC_CTRL */
1419 s
->clksrc
[0] = value
& 0xdb;
1420 /* TODO update clocks */
1423 case 0x070: /* PRCM_CLKOUT_CTRL */
1424 s
->clkout
[0] = value
& 0xbbbb;
1425 /* TODO update clocks */
1428 case 0x078: /* PRCM_CLKEMUL_CTRL */
1429 s
->clkemul
[0] = value
& 1;
1430 /* TODO update clocks */
1433 case 0x080: /* PRCM_CLKCFG_CTRL */
1436 case 0x090: /* PRCM_VOLTSETUP */
1437 s
->setuptime
[0] = value
& 0xffff;
1439 case 0x094: /* PRCM_CLKSSETUP */
1440 s
->setuptime
[1] = value
& 0xffff;
1443 case 0x098: /* PRCM_POLCTRL */
1444 s
->clkpol
[0] = value
& 0x701;
1447 case 0x0b0: /* GENERAL_PURPOSE1 */
1448 case 0x0b4: /* GENERAL_PURPOSE2 */
1449 case 0x0b8: /* GENERAL_PURPOSE3 */
1450 case 0x0bc: /* GENERAL_PURPOSE4 */
1451 case 0x0c0: /* GENERAL_PURPOSE5 */
1452 case 0x0c4: /* GENERAL_PURPOSE6 */
1453 case 0x0c8: /* GENERAL_PURPOSE7 */
1454 case 0x0cc: /* GENERAL_PURPOSE8 */
1455 case 0x0d0: /* GENERAL_PURPOSE9 */
1456 case 0x0d4: /* GENERAL_PURPOSE10 */
1457 case 0x0d8: /* GENERAL_PURPOSE11 */
1458 case 0x0dc: /* GENERAL_PURPOSE12 */
1459 case 0x0e0: /* GENERAL_PURPOSE13 */
1460 case 0x0e4: /* GENERAL_PURPOSE14 */
1461 case 0x0e8: /* GENERAL_PURPOSE15 */
1462 case 0x0ec: /* GENERAL_PURPOSE16 */
1463 case 0x0f0: /* GENERAL_PURPOSE17 */
1464 case 0x0f4: /* GENERAL_PURPOSE18 */
1465 case 0x0f8: /* GENERAL_PURPOSE19 */
1466 case 0x0fc: /* GENERAL_PURPOSE20 */
1467 s
->scratch
[(addr
- 0xb0) >> 2] = value
;
1470 case 0x140: /* CM_CLKSEL_MPU */
1471 s
->clksel
[0] = value
& 0x1f;
1472 /* TODO update clocks */
1474 case 0x148: /* CM_CLKSTCTRL_MPU */
1475 s
->clkctrl
[0] = value
& 0x1f;
1478 case 0x158: /* RM_RSTST_MPU */
1479 s
->rst
[0] &= ~value
;
1481 case 0x1c8: /* PM_WKDEP_MPU */
1482 s
->wkup
[0] = value
& 0x15;
1485 case 0x1d4: /* PM_EVGENCTRL_MPU */
1486 s
->ev
= value
& 0x1f;
1488 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1489 s
->evtime
[0] = value
;
1491 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1492 s
->evtime
[1] = value
;
1495 case 0x1e0: /* PM_PWSTCTRL_MPU */
1496 s
->power
[0] = value
& 0xc0f;
1499 case 0x200: /* CM_FCLKEN1_CORE */
1500 s
->clken
[0] = value
& 0xbfffffff;
1501 /* TODO update clocks */
1502 /* The EN_EAC bit only gets/puts func_96m_clk. */
1504 case 0x204: /* CM_FCLKEN2_CORE */
1505 s
->clken
[1] = value
& 0x00000007;
1506 /* TODO update clocks */
1508 case 0x210: /* CM_ICLKEN1_CORE */
1509 s
->clken
[2] = value
& 0xfffffff9;
1510 /* TODO update clocks */
1511 /* The EN_EAC bit only gets/puts core_l4_iclk. */
1513 case 0x214: /* CM_ICLKEN2_CORE */
1514 s
->clken
[3] = value
& 0x00000007;
1515 /* TODO update clocks */
1517 case 0x21c: /* CM_ICLKEN4_CORE */
1518 s
->clken
[4] = value
& 0x0000001f;
1519 /* TODO update clocks */
1522 case 0x230: /* CM_AUTOIDLE1_CORE */
1523 s
->clkidle
[0] = value
& 0xfffffff9;
1524 /* TODO update clocks */
1526 case 0x234: /* CM_AUTOIDLE2_CORE */
1527 s
->clkidle
[1] = value
& 0x00000007;
1528 /* TODO update clocks */
1530 case 0x238: /* CM_AUTOIDLE3_CORE */
1531 s
->clkidle
[2] = value
& 0x00000007;
1532 /* TODO update clocks */
1534 case 0x23c: /* CM_AUTOIDLE4_CORE */
1535 s
->clkidle
[3] = value
& 0x0000001f;
1536 /* TODO update clocks */
1539 case 0x240: /* CM_CLKSEL1_CORE */
1540 s
->clksel
[1] = value
& 0x0fffbf7f;
1541 /* TODO update clocks */
1544 case 0x244: /* CM_CLKSEL2_CORE */
1545 s
->clksel
[2] = value
& 0x00fffffc;
1546 /* TODO update clocks */
1549 case 0x248: /* CM_CLKSTCTRL_CORE */
1550 s
->clkctrl
[1] = value
& 0x7;
1553 case 0x2a0: /* PM_WKEN1_CORE */
1554 s
->wken
[0] = value
& 0x04667ff8;
1556 case 0x2a4: /* PM_WKEN2_CORE */
1557 s
->wken
[1] = value
& 0x00000005;
1560 case 0x2b0: /* PM_WKST1_CORE */
1561 s
->wkst
[0] &= ~value
;
1563 case 0x2b4: /* PM_WKST2_CORE */
1564 s
->wkst
[1] &= ~value
;
1567 case 0x2e0: /* PM_PWSTCTRL_CORE */
1568 s
->power
[1] = (value
& 0x00fc3f) | (1 << 2);
1571 case 0x300: /* CM_FCLKEN_GFX */
1572 s
->clken
[5] = value
& 6;
1573 /* TODO update clocks */
1575 case 0x310: /* CM_ICLKEN_GFX */
1576 s
->clken
[6] = value
& 1;
1577 /* TODO update clocks */
1579 case 0x340: /* CM_CLKSEL_GFX */
1580 s
->clksel
[3] = value
& 7;
1581 /* TODO update clocks */
1583 case 0x348: /* CM_CLKSTCTRL_GFX */
1584 s
->clkctrl
[2] = value
& 1;
1586 case 0x350: /* RM_RSTCTRL_GFX */
1587 s
->rstctrl
[0] = value
& 1;
1590 case 0x358: /* RM_RSTST_GFX */
1591 s
->rst
[1] &= ~value
;
1593 case 0x3c8: /* PM_WKDEP_GFX */
1594 s
->wkup
[1] = value
& 0x13;
1596 case 0x3e0: /* PM_PWSTCTRL_GFX */
1597 s
->power
[2] = (value
& 0x00c0f) | (3 << 2);
1600 case 0x400: /* CM_FCLKEN_WKUP */
1601 s
->clken
[7] = value
& 0xd;
1602 /* TODO update clocks */
1604 case 0x410: /* CM_ICLKEN_WKUP */
1605 s
->clken
[8] = value
& 0x3f;
1606 /* TODO update clocks */
1608 case 0x430: /* CM_AUTOIDLE_WKUP */
1609 s
->clkidle
[4] = value
& 0x0000003f;
1610 /* TODO update clocks */
1612 case 0x440: /* CM_CLKSEL_WKUP */
1613 s
->clksel
[4] = value
& 3;
1614 /* TODO update clocks */
1616 case 0x450: /* RM_RSTCTRL_WKUP */
1619 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
1621 case 0x454: /* RM_RSTTIME_WKUP */
1622 s
->rsttime_wkup
= value
& 0x1fff;
1624 case 0x458: /* RM_RSTST_WKUP */
1625 s
->rst
[2] &= ~value
;
1627 case 0x4a0: /* PM_WKEN_WKUP */
1628 s
->wken
[2] = value
& 0x00000005;
1630 case 0x4b0: /* PM_WKST_WKUP */
1631 s
->wkst
[2] &= ~value
;
1634 case 0x500: /* CM_CLKEN_PLL */
1635 if (value
& 0xffffff30)
1636 fprintf(stderr
, "%s: write 0s in CM_CLKEN_PLL for "
1637 "future compatibility\n", __func__
);
1638 if ((s
->clken
[9] ^ value
) & 0xcc) {
1639 s
->clken
[9] &= ~0xcc;
1640 s
->clken
[9] |= value
& 0xcc;
1641 omap_prcm_apll_update(s
);
1643 if ((s
->clken
[9] ^ value
) & 3) {
1645 s
->clken
[9] |= value
& 3;
1646 omap_prcm_dpll_update(s
);
1649 case 0x530: /* CM_AUTOIDLE_PLL */
1650 s
->clkidle
[5] = value
& 0x000000cf;
1651 /* TODO update clocks */
1653 case 0x540: /* CM_CLKSEL1_PLL */
1654 if (value
& 0xfc4000d7)
1655 fprintf(stderr
, "%s: write 0s in CM_CLKSEL1_PLL for "
1656 "future compatibility\n", __func__
);
1657 if ((s
->clksel
[5] ^ value
) & 0x003fff00) {
1658 s
->clksel
[5] = value
& 0x03bfff28;
1659 omap_prcm_dpll_update(s
);
1661 /* TODO update the other clocks */
1663 s
->clksel
[5] = value
& 0x03bfff28;
1665 case 0x544: /* CM_CLKSEL2_PLL */
1667 fprintf(stderr
, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
1668 "future compatibility\n", __func__
);
1669 if (s
->clksel
[6] != (value
& 3)) {
1670 s
->clksel
[6] = value
& 3;
1671 omap_prcm_dpll_update(s
);
1675 case 0x800: /* CM_FCLKEN_DSP */
1676 s
->clken
[10] = value
& 0x501;
1677 /* TODO update clocks */
1679 case 0x810: /* CM_ICLKEN_DSP */
1680 s
->clken
[11] = value
& 0x2;
1681 /* TODO update clocks */
1683 case 0x830: /* CM_AUTOIDLE_DSP */
1684 s
->clkidle
[6] = value
& 0x2;
1685 /* TODO update clocks */
1687 case 0x840: /* CM_CLKSEL_DSP */
1688 s
->clksel
[7] = value
& 0x3fff;
1689 /* TODO update clocks */
1691 case 0x848: /* CM_CLKSTCTRL_DSP */
1692 s
->clkctrl
[3] = value
& 0x101;
1694 case 0x850: /* RM_RSTCTRL_DSP */
1697 case 0x858: /* RM_RSTST_DSP */
1698 s
->rst
[3] &= ~value
;
1700 case 0x8c8: /* PM_WKDEP_DSP */
1701 s
->wkup
[2] = value
& 0x13;
1703 case 0x8e0: /* PM_PWSTCTRL_DSP */
1704 s
->power
[3] = (value
& 0x03017) | (3 << 2);
1707 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1708 s
->irqst
[1] &= ~value
;
1709 omap_prcm_int_update(s
, 1);
1711 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1712 s
->irqen
[1] = value
& 0x7;
1713 omap_prcm_int_update(s
, 1);
1716 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1717 s
->irqst
[2] &= ~value
;
1718 omap_prcm_int_update(s
, 2);
1720 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1721 s
->irqen
[2] = value
& 0x7;
1722 omap_prcm_int_update(s
, 2);
1731 static const MemoryRegionOps omap_prcm_ops
= {
1732 .read
= omap_prcm_read
,
1733 .write
= omap_prcm_write
,
1734 .endianness
= DEVICE_NATIVE_ENDIAN
,
1737 static void omap_prcm_reset(struct omap_prcm_s
*s
)
1746 s
->voltctrl
= 0x1040;
1768 s
->clkidle
[5] = 0x0c;
1770 s
->clksel
[0] = 0x01;
1771 s
->clksel
[1] = 0x02100121;
1772 s
->clksel
[2] = 0x00000000;
1773 s
->clksel
[3] = 0x01;
1775 s
->clksel
[7] = 0x0121;
1779 s
->wken
[0] = 0x04667ff8;
1780 s
->wken
[1] = 0x00000005;
1785 s
->power
[0] = 0x00c;
1787 s
->power
[2] = 0x0000c;
1791 omap_prcm_apll_update(s
);
1792 omap_prcm_dpll_update(s
);
1795 static void omap_prcm_coldreset(struct omap_prcm_s
*s
)
1797 s
->setuptime
[0] = 0;
1798 s
->setuptime
[1] = 0;
1799 memset(&s
->scratch
, 0, sizeof(s
->scratch
));
1808 s
->clksrc
[0] = 0x43;
1809 s
->clkout
[0] = 0x0303;
1811 s
->clkpol
[0] = 0x100;
1812 s
->rsttime_wkup
= 0x1002;
1817 static struct omap_prcm_s
*omap_prcm_init(struct omap_target_agent_s
*ta
,
1818 qemu_irq mpu_int
, qemu_irq dsp_int
, qemu_irq iva_int
,
1819 struct omap_mpu_state_s
*mpu
)
1821 struct omap_prcm_s
*s
= g_new0(struct omap_prcm_s
, 1);
1823 s
->irq
[0] = mpu_int
;
1824 s
->irq
[1] = dsp_int
;
1825 s
->irq
[2] = iva_int
;
1827 omap_prcm_coldreset(s
);
1829 memory_region_init_io(&s
->iomem0
, NULL
, &omap_prcm_ops
, s
, "omap.pcrm0",
1830 omap_l4_region_size(ta
, 0));
1831 memory_region_init_io(&s
->iomem1
, NULL
, &omap_prcm_ops
, s
, "omap.pcrm1",
1832 omap_l4_region_size(ta
, 1));
1833 omap_l4_attach(ta
, 0, &s
->iomem0
);
1834 omap_l4_attach(ta
, 1, &s
->iomem1
);
1839 /* System and Pinout control */
1840 struct omap_sysctl_s
{
1841 struct omap_mpu_state_s
*mpu
;
1847 uint32_t padconf
[0x45];
1849 uint32_t msuspendmux
[5];
1852 static uint32_t omap_sysctl_read8(void *opaque
, hwaddr addr
)
1855 struct omap_sysctl_s
*s
= opaque
;
1856 int pad_offset
, byte_offset
;
1860 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1861 pad_offset
= (addr
- 0x30) >> 2;
1862 byte_offset
= (addr
- 0x30) & (4 - 1);
1864 value
= s
->padconf
[pad_offset
];
1865 value
= (value
>> (byte_offset
* 8)) & 0xff;
1877 static uint32_t omap_sysctl_read(void *opaque
, hwaddr addr
)
1879 struct omap_sysctl_s
*s
= opaque
;
1882 case 0x000: /* CONTROL_REVISION */
1885 case 0x010: /* CONTROL_SYSCONFIG */
1886 return s
->sysconfig
;
1888 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1889 return s
->padconf
[(addr
- 0x30) >> 2];
1891 case 0x270: /* CONTROL_DEBOBS */
1894 case 0x274: /* CONTROL_DEVCONF */
1895 return s
->devconfig
;
1897 case 0x28c: /* CONTROL_EMU_SUPPORT */
1900 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
1901 return s
->msuspendmux
[0];
1902 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
1903 return s
->msuspendmux
[1];
1904 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
1905 return s
->msuspendmux
[2];
1906 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
1907 return s
->msuspendmux
[3];
1908 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
1909 return s
->msuspendmux
[4];
1910 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
1913 case 0x2b8: /* CONTROL_PSA_CTRL */
1914 return s
->psaconfig
;
1915 case 0x2bc: /* CONTROL_PSA_CMD */
1916 case 0x2c0: /* CONTROL_PSA_VALUE */
1919 case 0x2b0: /* CONTROL_SEC_CTRL */
1921 case 0x2d0: /* CONTROL_SEC_EMU */
1923 case 0x2d4: /* CONTROL_SEC_TAP */
1925 case 0x2b4: /* CONTROL_SEC_TEST */
1926 case 0x2f0: /* CONTROL_SEC_STATUS */
1927 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
1928 /* Secure mode is not present on general-pusrpose device. Outside
1929 * secure mode these values cannot be read or written. */
1932 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
1934 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
1935 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
1936 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
1937 /* No secure mode so no Extended Secure RAM present. */
1940 case 0x2f8: /* CONTROL_STATUS */
1941 /* Device Type => General-purpose */
1943 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
1945 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
1946 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
1947 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
1948 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
1951 case 0x310: /* CONTROL_RAND_KEY_0 */
1952 case 0x314: /* CONTROL_RAND_KEY_1 */
1953 case 0x318: /* CONTROL_RAND_KEY_2 */
1954 case 0x31c: /* CONTROL_RAND_KEY_3 */
1955 case 0x320: /* CONTROL_CUST_KEY_0 */
1956 case 0x324: /* CONTROL_CUST_KEY_1 */
1957 case 0x330: /* CONTROL_TEST_KEY_0 */
1958 case 0x334: /* CONTROL_TEST_KEY_1 */
1959 case 0x338: /* CONTROL_TEST_KEY_2 */
1960 case 0x33c: /* CONTROL_TEST_KEY_3 */
1961 case 0x340: /* CONTROL_TEST_KEY_4 */
1962 case 0x344: /* CONTROL_TEST_KEY_5 */
1963 case 0x348: /* CONTROL_TEST_KEY_6 */
1964 case 0x34c: /* CONTROL_TEST_KEY_7 */
1965 case 0x350: /* CONTROL_TEST_KEY_8 */
1966 case 0x354: /* CONTROL_TEST_KEY_9 */
1967 /* Can only be accessed in secure mode and when C_FieldAccEnable
1968 * bit is set in CONTROL_SEC_CTRL.
1969 * TODO: otherwise an interconnect access error is generated. */
1977 static void omap_sysctl_write8(void *opaque
, hwaddr addr
, uint32_t value
)
1979 struct omap_sysctl_s
*s
= opaque
;
1980 int pad_offset
, byte_offset
;
1984 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1985 pad_offset
= (addr
- 0x30) >> 2;
1986 byte_offset
= (addr
- 0x30) & (4 - 1);
1988 prev_value
= s
->padconf
[pad_offset
];
1989 prev_value
&= ~(0xff << (byte_offset
* 8));
1990 prev_value
|= ((value
& 0x1f1f1f1f) << (byte_offset
* 8)) & 0x1f1f1f1f;
1991 s
->padconf
[pad_offset
] = prev_value
;
2000 static void omap_sysctl_write(void *opaque
, hwaddr addr
, uint32_t value
)
2002 struct omap_sysctl_s
*s
= opaque
;
2005 case 0x000: /* CONTROL_REVISION */
2006 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
2007 case 0x2c0: /* CONTROL_PSA_VALUE */
2008 case 0x2f8: /* CONTROL_STATUS */
2009 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
2010 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
2011 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
2012 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
2013 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
2014 case 0x310: /* CONTROL_RAND_KEY_0 */
2015 case 0x314: /* CONTROL_RAND_KEY_1 */
2016 case 0x318: /* CONTROL_RAND_KEY_2 */
2017 case 0x31c: /* CONTROL_RAND_KEY_3 */
2018 case 0x320: /* CONTROL_CUST_KEY_0 */
2019 case 0x324: /* CONTROL_CUST_KEY_1 */
2020 case 0x330: /* CONTROL_TEST_KEY_0 */
2021 case 0x334: /* CONTROL_TEST_KEY_1 */
2022 case 0x338: /* CONTROL_TEST_KEY_2 */
2023 case 0x33c: /* CONTROL_TEST_KEY_3 */
2024 case 0x340: /* CONTROL_TEST_KEY_4 */
2025 case 0x344: /* CONTROL_TEST_KEY_5 */
2026 case 0x348: /* CONTROL_TEST_KEY_6 */
2027 case 0x34c: /* CONTROL_TEST_KEY_7 */
2028 case 0x350: /* CONTROL_TEST_KEY_8 */
2029 case 0x354: /* CONTROL_TEST_KEY_9 */
2033 case 0x010: /* CONTROL_SYSCONFIG */
2034 s
->sysconfig
= value
& 0x1e;
2037 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2038 /* XXX: should check constant bits */
2039 s
->padconf
[(addr
- 0x30) >> 2] = value
& 0x1f1f1f1f;
2042 case 0x270: /* CONTROL_DEBOBS */
2043 s
->obs
= value
& 0xff;
2046 case 0x274: /* CONTROL_DEVCONF */
2047 s
->devconfig
= value
& 0xffffc7ff;
2050 case 0x28c: /* CONTROL_EMU_SUPPORT */
2053 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2054 s
->msuspendmux
[0] = value
& 0x3fffffff;
2056 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2057 s
->msuspendmux
[1] = value
& 0x3fffffff;
2059 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2060 s
->msuspendmux
[2] = value
& 0x3fffffff;
2062 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2063 s
->msuspendmux
[3] = value
& 0x3fffffff;
2065 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2066 s
->msuspendmux
[4] = value
& 0x3fffffff;
2069 case 0x2b8: /* CONTROL_PSA_CTRL */
2070 s
->psaconfig
= value
& 0x1c;
2071 s
->psaconfig
|= (value
& 0x20) ? 2 : 1;
2073 case 0x2bc: /* CONTROL_PSA_CMD */
2076 case 0x2b0: /* CONTROL_SEC_CTRL */
2077 case 0x2b4: /* CONTROL_SEC_TEST */
2078 case 0x2d0: /* CONTROL_SEC_EMU */
2079 case 0x2d4: /* CONTROL_SEC_TAP */
2080 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2081 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2082 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2083 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2084 case 0x2f0: /* CONTROL_SEC_STATUS */
2085 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2094 static uint64_t omap_sysctl_readfn(void *opaque
, hwaddr addr
,
2099 return omap_sysctl_read8(opaque
, addr
);
2101 return omap_badwidth_read32(opaque
, addr
); /* TODO */
2103 return omap_sysctl_read(opaque
, addr
);
2105 g_assert_not_reached();
2109 static void omap_sysctl_writefn(void *opaque
, hwaddr addr
,
2110 uint64_t value
, unsigned size
)
2114 omap_sysctl_write8(opaque
, addr
, value
);
2117 omap_badwidth_write32(opaque
, addr
, value
); /* TODO */
2120 omap_sysctl_write(opaque
, addr
, value
);
2123 g_assert_not_reached();
2127 static const MemoryRegionOps omap_sysctl_ops
= {
2128 .read
= omap_sysctl_readfn
,
2129 .write
= omap_sysctl_writefn
,
2130 .valid
.min_access_size
= 1,
2131 .valid
.max_access_size
= 4,
2132 .endianness
= DEVICE_NATIVE_ENDIAN
,
2135 static void omap_sysctl_reset(struct omap_sysctl_s
*s
)
2137 /* (power-on reset) */
2140 s
->devconfig
= 0x0c000000;
2141 s
->msuspendmux
[0] = 0x00000000;
2142 s
->msuspendmux
[1] = 0x00000000;
2143 s
->msuspendmux
[2] = 0x00000000;
2144 s
->msuspendmux
[3] = 0x00000000;
2145 s
->msuspendmux
[4] = 0x00000000;
2148 s
->padconf
[0x00] = 0x000f0f0f;
2149 s
->padconf
[0x01] = 0x00000000;
2150 s
->padconf
[0x02] = 0x00000000;
2151 s
->padconf
[0x03] = 0x00000000;
2152 s
->padconf
[0x04] = 0x00000000;
2153 s
->padconf
[0x05] = 0x00000000;
2154 s
->padconf
[0x06] = 0x00000000;
2155 s
->padconf
[0x07] = 0x00000000;
2156 s
->padconf
[0x08] = 0x08080800;
2157 s
->padconf
[0x09] = 0x08080808;
2158 s
->padconf
[0x0a] = 0x08080808;
2159 s
->padconf
[0x0b] = 0x08080808;
2160 s
->padconf
[0x0c] = 0x08080808;
2161 s
->padconf
[0x0d] = 0x08080800;
2162 s
->padconf
[0x0e] = 0x08080808;
2163 s
->padconf
[0x0f] = 0x08080808;
2164 s
->padconf
[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
2165 s
->padconf
[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
2166 s
->padconf
[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
2167 s
->padconf
[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
2168 s
->padconf
[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
2169 s
->padconf
[0x15] = 0x18181818;
2170 s
->padconf
[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
2171 s
->padconf
[0x17] = 0x1f001f00;
2172 s
->padconf
[0x18] = 0x1f1f1f1f;
2173 s
->padconf
[0x19] = 0x00000000;
2174 s
->padconf
[0x1a] = 0x1f180000;
2175 s
->padconf
[0x1b] = 0x00001f1f;
2176 s
->padconf
[0x1c] = 0x1f001f00;
2177 s
->padconf
[0x1d] = 0x00000000;
2178 s
->padconf
[0x1e] = 0x00000000;
2179 s
->padconf
[0x1f] = 0x08000000;
2180 s
->padconf
[0x20] = 0x08080808;
2181 s
->padconf
[0x21] = 0x08080808;
2182 s
->padconf
[0x22] = 0x0f080808;
2183 s
->padconf
[0x23] = 0x0f0f0f0f;
2184 s
->padconf
[0x24] = 0x000f0f0f;
2185 s
->padconf
[0x25] = 0x1f1f1f0f;
2186 s
->padconf
[0x26] = 0x080f0f1f;
2187 s
->padconf
[0x27] = 0x070f1808;
2188 s
->padconf
[0x28] = 0x0f070707;
2189 s
->padconf
[0x29] = 0x000f0f1f;
2190 s
->padconf
[0x2a] = 0x0f0f0f1f;
2191 s
->padconf
[0x2b] = 0x08000000;
2192 s
->padconf
[0x2c] = 0x0000001f;
2193 s
->padconf
[0x2d] = 0x0f0f1f00;
2194 s
->padconf
[0x2e] = 0x1f1f0f0f;
2195 s
->padconf
[0x2f] = 0x0f1f1f1f;
2196 s
->padconf
[0x30] = 0x0f0f0f0f;
2197 s
->padconf
[0x31] = 0x0f1f0f1f;
2198 s
->padconf
[0x32] = 0x0f0f0f0f;
2199 s
->padconf
[0x33] = 0x0f1f0f1f;
2200 s
->padconf
[0x34] = 0x1f1f0f0f;
2201 s
->padconf
[0x35] = 0x0f0f1f1f;
2202 s
->padconf
[0x36] = 0x0f0f1f0f;
2203 s
->padconf
[0x37] = 0x0f0f0f0f;
2204 s
->padconf
[0x38] = 0x1f18180f;
2205 s
->padconf
[0x39] = 0x1f1f1f1f;
2206 s
->padconf
[0x3a] = 0x00001f1f;
2207 s
->padconf
[0x3b] = 0x00000000;
2208 s
->padconf
[0x3c] = 0x00000000;
2209 s
->padconf
[0x3d] = 0x0f0f0f0f;
2210 s
->padconf
[0x3e] = 0x18000f0f;
2211 s
->padconf
[0x3f] = 0x00070000;
2212 s
->padconf
[0x40] = 0x00000707;
2213 s
->padconf
[0x41] = 0x0f1f0700;
2214 s
->padconf
[0x42] = 0x1f1f070f;
2215 s
->padconf
[0x43] = 0x0008081f;
2216 s
->padconf
[0x44] = 0x00000800;
2219 static struct omap_sysctl_s
*omap_sysctl_init(struct omap_target_agent_s
*ta
,
2220 omap_clk iclk
, struct omap_mpu_state_s
*mpu
)
2222 struct omap_sysctl_s
*s
= g_new0(struct omap_sysctl_s
, 1);
2225 omap_sysctl_reset(s
);
2227 memory_region_init_io(&s
->iomem
, NULL
, &omap_sysctl_ops
, s
, "omap.sysctl",
2228 omap_l4_region_size(ta
, 0));
2229 omap_l4_attach(ta
, 0, &s
->iomem
);
2234 /* General chip reset */
2235 static void omap2_mpu_reset(void *opaque
)
2237 struct omap_mpu_state_s
*mpu
= opaque
;
2239 omap_dma_reset(mpu
->dma
);
2240 omap_prcm_reset(mpu
->prcm
);
2241 omap_sysctl_reset(mpu
->sysc
);
2242 omap_gp_timer_reset(mpu
->gptimer
[0]);
2243 omap_gp_timer_reset(mpu
->gptimer
[1]);
2244 omap_gp_timer_reset(mpu
->gptimer
[2]);
2245 omap_gp_timer_reset(mpu
->gptimer
[3]);
2246 omap_gp_timer_reset(mpu
->gptimer
[4]);
2247 omap_gp_timer_reset(mpu
->gptimer
[5]);
2248 omap_gp_timer_reset(mpu
->gptimer
[6]);
2249 omap_gp_timer_reset(mpu
->gptimer
[7]);
2250 omap_gp_timer_reset(mpu
->gptimer
[8]);
2251 omap_gp_timer_reset(mpu
->gptimer
[9]);
2252 omap_gp_timer_reset(mpu
->gptimer
[10]);
2253 omap_gp_timer_reset(mpu
->gptimer
[11]);
2254 omap_synctimer_reset(mpu
->synctimer
);
2255 omap_sdrc_reset(mpu
->sdrc
);
2256 omap_gpmc_reset(mpu
->gpmc
);
2257 omap_dss_reset(mpu
->dss
);
2258 omap_uart_reset(mpu
->uart
[0]);
2259 omap_uart_reset(mpu
->uart
[1]);
2260 omap_uart_reset(mpu
->uart
[2]);
2261 omap_mmc_reset(mpu
->mmc
);
2262 omap_mcspi_reset(mpu
->mcspi
[0]);
2263 omap_mcspi_reset(mpu
->mcspi
[1]);
2264 cpu_reset(CPU(mpu
->cpu
));
2267 static int omap2_validate_addr(struct omap_mpu_state_s
*s
,
2273 static const struct dma_irq_map omap2_dma_irq_map
[] = {
2274 { 0, OMAP_INT_24XX_SDMA_IRQ0
},
2275 { 0, OMAP_INT_24XX_SDMA_IRQ1
},
2276 { 0, OMAP_INT_24XX_SDMA_IRQ2
},
2277 { 0, OMAP_INT_24XX_SDMA_IRQ3
},
2280 struct omap_mpu_state_s
*omap2420_mpu_init(MemoryRegion
*sdram
,
2281 const char *cpu_type
)
2283 struct omap_mpu_state_s
*s
= g_new0(struct omap_mpu_state_s
, 1);
2284 qemu_irq dma_irqs
[4];
2287 SysBusDevice
*busdev
;
2288 struct omap_target_agent_s
*ta
;
2289 MemoryRegion
*sysmem
= get_system_memory();
2292 s
->mpu_model
= omap2420
;
2293 s
->cpu
= ARM_CPU(cpu_create(cpu_type
));
2294 s
->sram_size
= OMAP242X_SRAM_SIZE
;
2296 s
->wakeup
= qemu_allocate_irq(omap_mpu_wakeup
, s
, 0);
2301 /* Memory-mapped stuff */
2302 memory_region_init_ram(&s
->sram
, NULL
, "omap2.sram", s
->sram_size
,
2304 memory_region_add_subregion(sysmem
, OMAP2_SRAM_BASE
, &s
->sram
);
2306 s
->l4
= omap_l4_init(sysmem
, OMAP2_L4_BASE
, 54);
2308 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
2309 s
->ih
[0] = qdev_new("omap2-intc");
2310 qdev_prop_set_uint8(s
->ih
[0], "revision", 0x21);
2311 omap_intc_set_fclk(OMAP_INTC(s
->ih
[0]), omap_findclk(s
, "mpu_intc_fclk"));
2312 omap_intc_set_iclk(OMAP_INTC(s
->ih
[0]), omap_findclk(s
, "mpu_intc_iclk"));
2313 busdev
= SYS_BUS_DEVICE(s
->ih
[0]);
2314 sysbus_realize_and_unref(busdev
, &error_fatal
);
2315 sysbus_connect_irq(busdev
, 0,
2316 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_IRQ
));
2317 sysbus_connect_irq(busdev
, 1,
2318 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_FIQ
));
2319 sysbus_mmio_map(busdev
, 0, 0x480fe000);
2320 s
->prcm
= omap_prcm_init(omap_l4tao(s
->l4
, 3),
2321 qdev_get_gpio_in(s
->ih
[0],
2322 OMAP_INT_24XX_PRCM_MPU_IRQ
),
2325 s
->sysc
= omap_sysctl_init(omap_l4tao(s
->l4
, 1),
2326 omap_findclk(s
, "omapctrl_iclk"), s
);
2328 for (i
= 0; i
< 4; i
++) {
2329 dma_irqs
[i
] = qdev_get_gpio_in(s
->ih
[omap2_dma_irq_map
[i
].ih
],
2330 omap2_dma_irq_map
[i
].intr
);
2332 s
->dma
= omap_dma4_init(0x48056000, dma_irqs
, sysmem
, s
, 256, 32,
2333 omap_findclk(s
, "sdma_iclk"),
2334 omap_findclk(s
, "sdma_fclk"));
2335 s
->port
->addr_valid
= omap2_validate_addr
;
2337 /* Register SDRAM and SRAM ports for fast DMA transfers. */
2338 soc_dma_port_add_mem(s
->dma
, memory_region_get_ram_ptr(sdram
),
2339 OMAP2_Q2_BASE
, memory_region_size(sdram
));
2340 soc_dma_port_add_mem(s
->dma
, memory_region_get_ram_ptr(&s
->sram
),
2341 OMAP2_SRAM_BASE
, s
->sram_size
);
2343 s
->uart
[0] = omap2_uart_init(sysmem
, omap_l4ta(s
->l4
, 19),
2344 qdev_get_gpio_in(s
->ih
[0],
2345 OMAP_INT_24XX_UART1_IRQ
),
2346 omap_findclk(s
, "uart1_fclk"),
2347 omap_findclk(s
, "uart1_iclk"),
2348 s
->drq
[OMAP24XX_DMA_UART1_TX
],
2349 s
->drq
[OMAP24XX_DMA_UART1_RX
],
2352 s
->uart
[1] = omap2_uart_init(sysmem
, omap_l4ta(s
->l4
, 20),
2353 qdev_get_gpio_in(s
->ih
[0],
2354 OMAP_INT_24XX_UART2_IRQ
),
2355 omap_findclk(s
, "uart2_fclk"),
2356 omap_findclk(s
, "uart2_iclk"),
2357 s
->drq
[OMAP24XX_DMA_UART2_TX
],
2358 s
->drq
[OMAP24XX_DMA_UART2_RX
],
2360 serial_hd(0) ? serial_hd(1) : NULL
);
2361 s
->uart
[2] = omap2_uart_init(sysmem
, omap_l4ta(s
->l4
, 21),
2362 qdev_get_gpio_in(s
->ih
[0],
2363 OMAP_INT_24XX_UART3_IRQ
),
2364 omap_findclk(s
, "uart3_fclk"),
2365 omap_findclk(s
, "uart3_iclk"),
2366 s
->drq
[OMAP24XX_DMA_UART3_TX
],
2367 s
->drq
[OMAP24XX_DMA_UART3_RX
],
2369 serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL
);
2371 s
->gptimer
[0] = omap_gp_timer_init(omap_l4ta(s
->l4
, 7),
2372 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPTIMER1
),
2373 omap_findclk(s
, "wu_gpt1_clk"),
2374 omap_findclk(s
, "wu_l4_iclk"));
2375 s
->gptimer
[1] = omap_gp_timer_init(omap_l4ta(s
->l4
, 8),
2376 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPTIMER2
),
2377 omap_findclk(s
, "core_gpt2_clk"),
2378 omap_findclk(s
, "core_l4_iclk"));
2379 s
->gptimer
[2] = omap_gp_timer_init(omap_l4ta(s
->l4
, 22),
2380 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPTIMER3
),
2381 omap_findclk(s
, "core_gpt3_clk"),
2382 omap_findclk(s
, "core_l4_iclk"));
2383 s
->gptimer
[3] = omap_gp_timer_init(omap_l4ta(s
->l4
, 23),
2384 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPTIMER4
),
2385 omap_findclk(s
, "core_gpt4_clk"),
2386 omap_findclk(s
, "core_l4_iclk"));
2387 s
->gptimer
[4] = omap_gp_timer_init(omap_l4ta(s
->l4
, 24),
2388 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPTIMER5
),
2389 omap_findclk(s
, "core_gpt5_clk"),
2390 omap_findclk(s
, "core_l4_iclk"));
2391 s
->gptimer
[5] = omap_gp_timer_init(omap_l4ta(s
->l4
, 25),
2392 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPTIMER6
),
2393 omap_findclk(s
, "core_gpt6_clk"),
2394 omap_findclk(s
, "core_l4_iclk"));
2395 s
->gptimer
[6] = omap_gp_timer_init(omap_l4ta(s
->l4
, 26),
2396 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPTIMER7
),
2397 omap_findclk(s
, "core_gpt7_clk"),
2398 omap_findclk(s
, "core_l4_iclk"));
2399 s
->gptimer
[7] = omap_gp_timer_init(omap_l4ta(s
->l4
, 27),
2400 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPTIMER8
),
2401 omap_findclk(s
, "core_gpt8_clk"),
2402 omap_findclk(s
, "core_l4_iclk"));
2403 s
->gptimer
[8] = omap_gp_timer_init(omap_l4ta(s
->l4
, 28),
2404 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPTIMER9
),
2405 omap_findclk(s
, "core_gpt9_clk"),
2406 omap_findclk(s
, "core_l4_iclk"));
2407 s
->gptimer
[9] = omap_gp_timer_init(omap_l4ta(s
->l4
, 29),
2408 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPTIMER10
),
2409 omap_findclk(s
, "core_gpt10_clk"),
2410 omap_findclk(s
, "core_l4_iclk"));
2411 s
->gptimer
[10] = omap_gp_timer_init(omap_l4ta(s
->l4
, 30),
2412 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPTIMER11
),
2413 omap_findclk(s
, "core_gpt11_clk"),
2414 omap_findclk(s
, "core_l4_iclk"));
2415 s
->gptimer
[11] = omap_gp_timer_init(omap_l4ta(s
->l4
, 31),
2416 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPTIMER12
),
2417 omap_findclk(s
, "core_gpt12_clk"),
2418 omap_findclk(s
, "core_l4_iclk"));
2420 omap_tap_init(omap_l4ta(s
->l4
, 2), s
);
2422 s
->synctimer
= omap_synctimer_init(omap_l4tao(s
->l4
, 2), s
,
2423 omap_findclk(s
, "clk32-kHz"),
2424 omap_findclk(s
, "core_l4_iclk"));
2426 s
->i2c
[0] = qdev_new("omap_i2c");
2427 qdev_prop_set_uint8(s
->i2c
[0], "revision", 0x34);
2428 omap_i2c_set_iclk(OMAP_I2C(s
->i2c
[0]), omap_findclk(s
, "i2c1.iclk"));
2429 omap_i2c_set_fclk(OMAP_I2C(s
->i2c
[0]), omap_findclk(s
, "i2c1.fclk"));
2430 busdev
= SYS_BUS_DEVICE(s
->i2c
[0]);
2431 sysbus_realize_and_unref(busdev
, &error_fatal
);
2432 sysbus_connect_irq(busdev
, 0,
2433 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_I2C1_IRQ
));
2434 sysbus_connect_irq(busdev
, 1, s
->drq
[OMAP24XX_DMA_I2C1_TX
]);
2435 sysbus_connect_irq(busdev
, 2, s
->drq
[OMAP24XX_DMA_I2C1_RX
]);
2436 sysbus_mmio_map(busdev
, 0, omap_l4_region_base(omap_l4tao(s
->l4
, 5), 0));
2438 s
->i2c
[1] = qdev_new("omap_i2c");
2439 qdev_prop_set_uint8(s
->i2c
[1], "revision", 0x34);
2440 omap_i2c_set_iclk(OMAP_I2C(s
->i2c
[1]), omap_findclk(s
, "i2c2.iclk"));
2441 omap_i2c_set_fclk(OMAP_I2C(s
->i2c
[1]), omap_findclk(s
, "i2c2.fclk"));
2442 busdev
= SYS_BUS_DEVICE(s
->i2c
[1]);
2443 sysbus_realize_and_unref(busdev
, &error_fatal
);
2444 sysbus_connect_irq(busdev
, 0,
2445 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_I2C2_IRQ
));
2446 sysbus_connect_irq(busdev
, 1, s
->drq
[OMAP24XX_DMA_I2C2_TX
]);
2447 sysbus_connect_irq(busdev
, 2, s
->drq
[OMAP24XX_DMA_I2C2_RX
]);
2448 sysbus_mmio_map(busdev
, 0, omap_l4_region_base(omap_l4tao(s
->l4
, 6), 0));
2450 s
->gpio
= qdev_new("omap2-gpio");
2451 qdev_prop_set_int32(s
->gpio
, "mpu_model", s
->mpu_model
);
2452 omap2_gpio_set_iclk(OMAP2_GPIO(s
->gpio
), omap_findclk(s
, "gpio_iclk"));
2453 omap2_gpio_set_fclk(OMAP2_GPIO(s
->gpio
), 0, omap_findclk(s
, "gpio1_dbclk"));
2454 omap2_gpio_set_fclk(OMAP2_GPIO(s
->gpio
), 1, omap_findclk(s
, "gpio2_dbclk"));
2455 omap2_gpio_set_fclk(OMAP2_GPIO(s
->gpio
), 2, omap_findclk(s
, "gpio3_dbclk"));
2456 omap2_gpio_set_fclk(OMAP2_GPIO(s
->gpio
), 3, omap_findclk(s
, "gpio4_dbclk"));
2457 if (s
->mpu_model
== omap2430
) {
2458 omap2_gpio_set_fclk(OMAP2_GPIO(s
->gpio
), 4,
2459 omap_findclk(s
, "gpio5_dbclk"));
2461 busdev
= SYS_BUS_DEVICE(s
->gpio
);
2462 sysbus_realize_and_unref(busdev
, &error_fatal
);
2463 sysbus_connect_irq(busdev
, 0,
2464 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPIO_BANK1
));
2465 sysbus_connect_irq(busdev
, 3,
2466 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPIO_BANK2
));
2467 sysbus_connect_irq(busdev
, 6,
2468 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPIO_BANK3
));
2469 sysbus_connect_irq(busdev
, 9,
2470 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPIO_BANK4
));
2471 if (s
->mpu_model
== omap2430
) {
2472 sysbus_connect_irq(busdev
, 12,
2473 qdev_get_gpio_in(s
->ih
[0],
2474 OMAP_INT_243X_GPIO_BANK5
));
2476 ta
= omap_l4ta(s
->l4
, 3);
2477 sysbus_mmio_map(busdev
, 0, omap_l4_region_base(ta
, 1));
2478 sysbus_mmio_map(busdev
, 1, omap_l4_region_base(ta
, 0));
2479 sysbus_mmio_map(busdev
, 2, omap_l4_region_base(ta
, 2));
2480 sysbus_mmio_map(busdev
, 3, omap_l4_region_base(ta
, 4));
2481 sysbus_mmio_map(busdev
, 4, omap_l4_region_base(ta
, 5));
2483 s
->sdrc
= omap_sdrc_init(sysmem
, 0x68009000);
2484 s
->gpmc
= omap_gpmc_init(s
, 0x6800a000,
2485 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_GPMC_IRQ
),
2486 s
->drq
[OMAP24XX_DMA_GPMC
]);
2488 dinfo
= drive_get(IF_SD
, 0, 0);
2489 if (!dinfo
&& !qtest_enabled()) {
2490 warn_report("missing SecureDigital device");
2492 s
->mmc
= omap2_mmc_init(omap_l4tao(s
->l4
, 9),
2493 dinfo
? blk_by_legacy_dinfo(dinfo
) : NULL
,
2494 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_MMC_IRQ
),
2495 &s
->drq
[OMAP24XX_DMA_MMC1_TX
],
2496 omap_findclk(s
, "mmc_fclk"), omap_findclk(s
, "mmc_iclk"));
2498 s
->mcspi
[0] = omap_mcspi_init(omap_l4ta(s
->l4
, 35), 4,
2499 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_MCSPI1_IRQ
),
2500 &s
->drq
[OMAP24XX_DMA_SPI1_TX0
],
2501 omap_findclk(s
, "spi1_fclk"),
2502 omap_findclk(s
, "spi1_iclk"));
2503 s
->mcspi
[1] = omap_mcspi_init(omap_l4ta(s
->l4
, 36), 2,
2504 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_MCSPI2_IRQ
),
2505 &s
->drq
[OMAP24XX_DMA_SPI2_TX0
],
2506 omap_findclk(s
, "spi2_fclk"),
2507 omap_findclk(s
, "spi2_iclk"));
2509 s
->dss
= omap_dss_init(omap_l4ta(s
->l4
, 10), sysmem
, 0x68000800,
2510 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
2511 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_DSS_IRQ
),
2512 s
->drq
[OMAP24XX_DMA_DSS
],
2513 omap_findclk(s
, "dss_clk1"), omap_findclk(s
, "dss_clk2"),
2514 omap_findclk(s
, "dss_54m_clk"),
2515 omap_findclk(s
, "dss_l3_iclk"),
2516 omap_findclk(s
, "dss_l4_iclk"));
2518 omap_sti_init(omap_l4ta(s
->l4
, 18), sysmem
, 0x54000000,
2519 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_STI
),
2520 omap_findclk(s
, "emul_ck"),
2521 serial_hd(0) && serial_hd(1) && serial_hd(2) ?
2522 serial_hd(3) : NULL
);
2524 s
->eac
= omap_eac_init(omap_l4ta(s
->l4
, 32),
2525 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_24XX_EAC_IRQ
),
2526 /* Ten consecutive lines */
2527 &s
->drq
[OMAP24XX_DMA_EAC_AC_RD
],
2528 omap_findclk(s
, "func_96m_clk"),
2529 omap_findclk(s
, "core_l4_iclk"));
2531 /* All register mappings (including those not currently implemented):
2532 * SystemControlMod 48000000 - 48000fff
2533 * SystemControlL4 48001000 - 48001fff
2534 * 32kHz Timer Mod 48004000 - 48004fff
2535 * 32kHz Timer L4 48005000 - 48005fff
2536 * PRCM ModA 48008000 - 480087ff
2537 * PRCM ModB 48008800 - 48008fff
2538 * PRCM L4 48009000 - 48009fff
2539 * TEST-BCM Mod 48012000 - 48012fff
2540 * TEST-BCM L4 48013000 - 48013fff
2541 * TEST-TAP Mod 48014000 - 48014fff
2542 * TEST-TAP L4 48015000 - 48015fff
2543 * GPIO1 Mod 48018000 - 48018fff
2544 * GPIO Top 48019000 - 48019fff
2545 * GPIO2 Mod 4801a000 - 4801afff
2546 * GPIO L4 4801b000 - 4801bfff
2547 * GPIO3 Mod 4801c000 - 4801cfff
2548 * GPIO4 Mod 4801e000 - 4801efff
2549 * WDTIMER1 Mod 48020000 - 48010fff
2550 * WDTIMER Top 48021000 - 48011fff
2551 * WDTIMER2 Mod 48022000 - 48012fff
2552 * WDTIMER L4 48023000 - 48013fff
2553 * WDTIMER3 Mod 48024000 - 48014fff
2554 * WDTIMER3 L4 48025000 - 48015fff
2555 * WDTIMER4 Mod 48026000 - 48016fff
2556 * WDTIMER4 L4 48027000 - 48017fff
2557 * GPTIMER1 Mod 48028000 - 48018fff
2558 * GPTIMER1 L4 48029000 - 48019fff
2559 * GPTIMER2 Mod 4802a000 - 4801afff
2560 * GPTIMER2 L4 4802b000 - 4801bfff
2561 * L4-Config AP 48040000 - 480407ff
2562 * L4-Config IP 48040800 - 48040fff
2563 * L4-Config LA 48041000 - 48041fff
2564 * ARM11ETB Mod 48048000 - 48049fff
2565 * ARM11ETB L4 4804a000 - 4804afff
2566 * DISPLAY Top 48050000 - 480503ff
2567 * DISPLAY DISPC 48050400 - 480507ff
2568 * DISPLAY RFBI 48050800 - 48050bff
2569 * DISPLAY VENC 48050c00 - 48050fff
2570 * DISPLAY L4 48051000 - 48051fff
2571 * CAMERA Top 48052000 - 480523ff
2572 * CAMERA core 48052400 - 480527ff
2573 * CAMERA DMA 48052800 - 48052bff
2574 * CAMERA MMU 48052c00 - 48052fff
2575 * CAMERA L4 48053000 - 48053fff
2576 * SDMA Mod 48056000 - 48056fff
2577 * SDMA L4 48057000 - 48057fff
2578 * SSI Top 48058000 - 48058fff
2579 * SSI GDD 48059000 - 48059fff
2580 * SSI Port1 4805a000 - 4805afff
2581 * SSI Port2 4805b000 - 4805bfff
2582 * SSI L4 4805c000 - 4805cfff
2583 * USB Mod 4805e000 - 480fefff
2584 * USB L4 4805f000 - 480fffff
2585 * WIN_TRACER1 Mod 48060000 - 48060fff
2586 * WIN_TRACER1 L4 48061000 - 48061fff
2587 * WIN_TRACER2 Mod 48062000 - 48062fff
2588 * WIN_TRACER2 L4 48063000 - 48063fff
2589 * WIN_TRACER3 Mod 48064000 - 48064fff
2590 * WIN_TRACER3 L4 48065000 - 48065fff
2591 * WIN_TRACER4 Top 48066000 - 480660ff
2592 * WIN_TRACER4 ETT 48066100 - 480661ff
2593 * WIN_TRACER4 WT 48066200 - 480662ff
2594 * WIN_TRACER4 L4 48067000 - 48067fff
2595 * XTI Mod 48068000 - 48068fff
2596 * XTI L4 48069000 - 48069fff
2597 * UART1 Mod 4806a000 - 4806afff
2598 * UART1 L4 4806b000 - 4806bfff
2599 * UART2 Mod 4806c000 - 4806cfff
2600 * UART2 L4 4806d000 - 4806dfff
2601 * UART3 Mod 4806e000 - 4806efff
2602 * UART3 L4 4806f000 - 4806ffff
2603 * I2C1 Mod 48070000 - 48070fff
2604 * I2C1 L4 48071000 - 48071fff
2605 * I2C2 Mod 48072000 - 48072fff
2606 * I2C2 L4 48073000 - 48073fff
2607 * McBSP1 Mod 48074000 - 48074fff
2608 * McBSP1 L4 48075000 - 48075fff
2609 * McBSP2 Mod 48076000 - 48076fff
2610 * McBSP2 L4 48077000 - 48077fff
2611 * GPTIMER3 Mod 48078000 - 48078fff
2612 * GPTIMER3 L4 48079000 - 48079fff
2613 * GPTIMER4 Mod 4807a000 - 4807afff
2614 * GPTIMER4 L4 4807b000 - 4807bfff
2615 * GPTIMER5 Mod 4807c000 - 4807cfff
2616 * GPTIMER5 L4 4807d000 - 4807dfff
2617 * GPTIMER6 Mod 4807e000 - 4807efff
2618 * GPTIMER6 L4 4807f000 - 4807ffff
2619 * GPTIMER7 Mod 48080000 - 48080fff
2620 * GPTIMER7 L4 48081000 - 48081fff
2621 * GPTIMER8 Mod 48082000 - 48082fff
2622 * GPTIMER8 L4 48083000 - 48083fff
2623 * GPTIMER9 Mod 48084000 - 48084fff
2624 * GPTIMER9 L4 48085000 - 48085fff
2625 * GPTIMER10 Mod 48086000 - 48086fff
2626 * GPTIMER10 L4 48087000 - 48087fff
2627 * GPTIMER11 Mod 48088000 - 48088fff
2628 * GPTIMER11 L4 48089000 - 48089fff
2629 * GPTIMER12 Mod 4808a000 - 4808afff
2630 * GPTIMER12 L4 4808b000 - 4808bfff
2631 * EAC Mod 48090000 - 48090fff
2632 * EAC L4 48091000 - 48091fff
2633 * FAC Mod 48092000 - 48092fff
2634 * FAC L4 48093000 - 48093fff
2635 * MAILBOX Mod 48094000 - 48094fff
2636 * MAILBOX L4 48095000 - 48095fff
2637 * SPI1 Mod 48098000 - 48098fff
2638 * SPI1 L4 48099000 - 48099fff
2639 * SPI2 Mod 4809a000 - 4809afff
2640 * SPI2 L4 4809b000 - 4809bfff
2641 * MMC/SDIO Mod 4809c000 - 4809cfff
2642 * MMC/SDIO L4 4809d000 - 4809dfff
2643 * MS_PRO Mod 4809e000 - 4809efff
2644 * MS_PRO L4 4809f000 - 4809ffff
2645 * RNG Mod 480a0000 - 480a0fff
2646 * RNG L4 480a1000 - 480a1fff
2647 * DES3DES Mod 480a2000 - 480a2fff
2648 * DES3DES L4 480a3000 - 480a3fff
2649 * SHA1MD5 Mod 480a4000 - 480a4fff
2650 * SHA1MD5 L4 480a5000 - 480a5fff
2651 * AES Mod 480a6000 - 480a6fff
2652 * AES L4 480a7000 - 480a7fff
2653 * PKA Mod 480a8000 - 480a9fff
2654 * PKA L4 480aa000 - 480aafff
2655 * MG Mod 480b0000 - 480b0fff
2656 * MG L4 480b1000 - 480b1fff
2657 * HDQ/1-wire Mod 480b2000 - 480b2fff
2658 * HDQ/1-wire L4 480b3000 - 480b3fff
2659 * MPU interrupt 480fe000 - 480fefff
2660 * STI channel base 54000000 - 5400ffff
2661 * IVA RAM 5c000000 - 5c01ffff
2662 * IVA ROM 5c020000 - 5c027fff
2663 * IMG_BUF_A 5c040000 - 5c040fff
2664 * IMG_BUF_B 5c042000 - 5c042fff
2665 * VLCDS 5c048000 - 5c0487ff
2666 * IMX_COEF 5c049000 - 5c04afff
2667 * IMX_CMD 5c051000 - 5c051fff
2668 * VLCDQ 5c053000 - 5c0533ff
2669 * VLCDH 5c054000 - 5c054fff
2670 * SEQ_CMD 5c055000 - 5c055fff
2671 * IMX_REG 5c056000 - 5c0560ff
2672 * VLCD_REG 5c056100 - 5c0561ff
2673 * SEQ_REG 5c056200 - 5c0562ff
2674 * IMG_BUF_REG 5c056300 - 5c0563ff
2675 * SEQIRQ_REG 5c056400 - 5c0564ff
2676 * OCP_REG 5c060000 - 5c060fff
2677 * SYSC_REG 5c070000 - 5c070fff
2678 * MMU_REG 5d000000 - 5d000fff
2679 * sDMA R 68000400 - 680005ff
2680 * sDMA W 68000600 - 680007ff
2681 * Display Control 68000800 - 680009ff
2682 * DSP subsystem 68000a00 - 68000bff
2683 * MPU subsystem 68000c00 - 68000dff
2684 * IVA subsystem 68001000 - 680011ff
2685 * USB 68001200 - 680013ff
2686 * Camera 68001400 - 680015ff
2687 * VLYNQ (firewall) 68001800 - 68001bff
2688 * VLYNQ 68001e00 - 68001fff
2689 * SSI 68002000 - 680021ff
2690 * L4 68002400 - 680025ff
2691 * DSP (firewall) 68002800 - 68002bff
2692 * DSP subsystem 68002e00 - 68002fff
2693 * IVA (firewall) 68003000 - 680033ff
2694 * IVA 68003600 - 680037ff
2695 * GFX 68003a00 - 68003bff
2696 * CMDWR emulation 68003c00 - 68003dff
2697 * SMS 68004000 - 680041ff
2698 * OCM 68004200 - 680043ff
2699 * GPMC 68004400 - 680045ff
2700 * RAM (firewall) 68005000 - 680053ff
2701 * RAM (err login) 68005400 - 680057ff
2702 * ROM (firewall) 68005800 - 68005bff
2703 * ROM (err login) 68005c00 - 68005fff
2704 * GPMC (firewall) 68006000 - 680063ff
2705 * GPMC (err login) 68006400 - 680067ff
2706 * SMS (err login) 68006c00 - 68006fff
2707 * SMS registers 68008000 - 68008fff
2708 * SDRC registers 68009000 - 68009fff
2709 * GPMC registers 6800a000 6800afff
2712 qemu_register_reset(omap2_mpu_reset
, s
);