host/include/generic/host/atomic128: Fix compilation problem with Clang 17
[qemu/kevin.git] / hw / arm / mps2.c
blob292a180ad27eac0800f265e9a39f17d173058b35
1 /*
2 * ARM V2M MPS2 board emulation.
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
13 * FPGA but is otherwise the same as the 2). Since the CPU itself
14 * and most of the devices are in the FPGA, the details of the board
15 * as seen by the guest depend significantly on the FPGA image.
16 * We model the following FPGA images:
17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
18 * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
19 * "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500
20 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
22 * Links to the TRM for the board itself and to the various Application
23 * Notes which document the FPGA images can be found here:
24 * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
27 #include "qemu/osdep.h"
28 #include "qemu/units.h"
29 #include "qemu/cutils.h"
30 #include "qapi/error.h"
31 #include "qemu/error-report.h"
32 #include "hw/arm/boot.h"
33 #include "hw/arm/armv7m.h"
34 #include "hw/or-irq.h"
35 #include "hw/boards.h"
36 #include "exec/address-spaces.h"
37 #include "sysemu/sysemu.h"
38 #include "hw/qdev-properties.h"
39 #include "hw/misc/unimp.h"
40 #include "hw/char/cmsdk-apb-uart.h"
41 #include "hw/timer/cmsdk-apb-timer.h"
42 #include "hw/timer/cmsdk-apb-dualtimer.h"
43 #include "hw/misc/mps2-scc.h"
44 #include "hw/misc/mps2-fpgaio.h"
45 #include "hw/ssi/pl022.h"
46 #include "hw/i2c/arm_sbcon_i2c.h"
47 #include "hw/net/lan9118.h"
48 #include "net/net.h"
49 #include "hw/watchdog/cmsdk-apb-watchdog.h"
50 #include "hw/qdev-clock.h"
51 #include "qapi/qmp/qlist.h"
52 #include "qom/object.h"
54 typedef enum MPS2FPGAType {
55 FPGA_AN385,
56 FPGA_AN386,
57 FPGA_AN500,
58 FPGA_AN511,
59 } MPS2FPGAType;
61 struct MPS2MachineClass {
62 MachineClass parent;
63 MPS2FPGAType fpga_type;
64 uint32_t scc_id;
65 bool has_block_ram;
66 hwaddr ethernet_base;
67 hwaddr psram_base;
70 struct MPS2MachineState {
71 MachineState parent;
73 ARMv7MState armv7m;
74 MemoryRegion ssram1;
75 MemoryRegion ssram1_m;
76 MemoryRegion ssram23;
77 MemoryRegion ssram23_m;
78 MemoryRegion blockram;
79 MemoryRegion blockram_m1;
80 MemoryRegion blockram_m2;
81 MemoryRegion blockram_m3;
82 MemoryRegion sram;
83 /* FPGA APB subsystem */
84 MPS2SCC scc;
85 MPS2FPGAIO fpgaio;
86 /* CMSDK APB subsystem */
87 CMSDKAPBDualTimer dualtimer;
88 CMSDKAPBWatchdog watchdog;
89 CMSDKAPBTimer timer[2];
90 Clock *sysclk;
91 Clock *refclk;
94 #define TYPE_MPS2_MACHINE "mps2"
95 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
96 #define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386")
97 #define TYPE_MPS2_AN500_MACHINE MACHINE_TYPE_NAME("mps2-an500")
98 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
100 OBJECT_DECLARE_TYPE(MPS2MachineState, MPS2MachineClass, MPS2_MACHINE)
102 /* Main SYSCLK frequency in Hz */
103 #define SYSCLK_FRQ 25000000
106 * The Application Notes don't say anything about how the
107 * systick reference clock is configured. (Quite possibly
108 * they don't have one at all.) This 1MHz clock matches the
109 * pre-existing behaviour that used to be hardcoded in the
110 * armv7m_systick implementation.
112 #define REFCLK_FRQ (1 * 1000 * 1000)
114 /* Initialize the auxiliary RAM region @mr and map it into
115 * the memory map at @base.
117 static void make_ram(MemoryRegion *mr, const char *name,
118 hwaddr base, hwaddr size)
120 memory_region_init_ram(mr, NULL, name, size, &error_fatal);
121 memory_region_add_subregion(get_system_memory(), base, mr);
124 /* Create an alias of an entire original MemoryRegion @orig
125 * located at @base in the memory map.
127 static void make_ram_alias(MemoryRegion *mr, const char *name,
128 MemoryRegion *orig, hwaddr base)
130 memory_region_init_alias(mr, NULL, name, orig, 0,
131 memory_region_size(orig));
132 memory_region_add_subregion(get_system_memory(), base, mr);
135 static void mps2_common_init(MachineState *machine)
137 MPS2MachineState *mms = MPS2_MACHINE(machine);
138 MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
139 MemoryRegion *system_memory = get_system_memory();
140 MachineClass *mc = MACHINE_GET_CLASS(machine);
141 DeviceState *armv7m, *sccdev;
142 QList *oscclk;
143 int i;
145 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
146 error_report("This board can only be used with CPU %s",
147 mc->default_cpu_type);
148 exit(1);
151 if (machine->ram_size != mc->default_ram_size) {
152 char *sz = size_to_str(mc->default_ram_size);
153 error_report("Invalid RAM size, should be %s", sz);
154 g_free(sz);
155 exit(EXIT_FAILURE);
158 /* This clock doesn't need migration because it is fixed-frequency */
159 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
160 clock_set_hz(mms->sysclk, SYSCLK_FRQ);
162 mms->refclk = clock_new(OBJECT(machine), "REFCLK");
163 clock_set_hz(mms->refclk, REFCLK_FRQ);
165 /* The FPGA images have an odd combination of different RAMs,
166 * because in hardware they are different implementations and
167 * connected to different buses, giving varying performance/size
168 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
169 * call the 16MB our "system memory", as it's the largest lump.
171 * AN385/AN386/AN511:
172 * 0x21000000 .. 0x21ffffff : PSRAM (16MB)
173 * AN385/AN386/AN500:
174 * 0x00000000 .. 0x003fffff : ZBT SSRAM1
175 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
176 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
177 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
178 * AN385/AN386 only:
179 * 0x01000000 .. 0x01003fff : block RAM (16K)
180 * 0x01004000 .. 0x01007fff : mirror of above
181 * 0x01008000 .. 0x0100bfff : mirror of above
182 * 0x0100c000 .. 0x0100ffff : mirror of above
183 * AN511 only:
184 * 0x00000000 .. 0x0003ffff : FPGA block RAM
185 * 0x00400000 .. 0x007fffff : ZBT SSRAM1
186 * 0x20000000 .. 0x2001ffff : SRAM
187 * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
188 * AN500 only:
189 * 0x60000000 .. 0x60ffffff : PSRAM (16MB)
191 * The AN385/AN386 has a feature where the lowest 16K can be mapped
192 * either to the bottom of the ZBT SSRAM1 or to the block RAM.
193 * This is of no use for QEMU so we don't implement it (as if
194 * zbt_boot_ctrl is always zero).
196 memory_region_add_subregion(system_memory, mmc->psram_base, machine->ram);
198 if (mmc->has_block_ram) {
199 make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000);
200 make_ram_alias(&mms->blockram_m1, "mps.blockram_m1",
201 &mms->blockram, 0x01004000);
202 make_ram_alias(&mms->blockram_m2, "mps.blockram_m2",
203 &mms->blockram, 0x01008000);
204 make_ram_alias(&mms->blockram_m3, "mps.blockram_m3",
205 &mms->blockram, 0x0100c000);
208 switch (mmc->fpga_type) {
209 case FPGA_AN385:
210 case FPGA_AN386:
211 case FPGA_AN500:
212 make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
213 make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
214 make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
215 make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
216 &mms->ssram23, 0x20400000);
217 break;
218 case FPGA_AN511:
219 make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000);
220 make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000);
221 make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000);
222 make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000);
223 break;
224 default:
225 g_assert_not_reached();
228 object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M);
229 armv7m = DEVICE(&mms->armv7m);
230 switch (mmc->fpga_type) {
231 case FPGA_AN385:
232 case FPGA_AN386:
233 case FPGA_AN500:
234 qdev_prop_set_uint32(armv7m, "num-irq", 32);
235 break;
236 case FPGA_AN511:
237 qdev_prop_set_uint32(armv7m, "num-irq", 64);
238 break;
239 default:
240 g_assert_not_reached();
242 qdev_connect_clock_in(armv7m, "cpuclk", mms->sysclk);
243 qdev_connect_clock_in(armv7m, "refclk", mms->refclk);
244 qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
245 qdev_prop_set_bit(armv7m, "enable-bitband", true);
246 object_property_set_link(OBJECT(&mms->armv7m), "memory",
247 OBJECT(system_memory), &error_abort);
248 sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal);
250 create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
251 create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
252 create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);
253 create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000);
254 create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000);
255 create_unimplemented_device("PSRAM", 0x21000000, 0x01000000);
256 /* These three ranges all cover multiple devices; we may implement
257 * some of them below (in which case the real device takes precedence
258 * over the unimplemented-region mapping).
260 create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
261 0x40000000, 0x00010000);
262 create_unimplemented_device("CMSDK AHB peripheral region @0x40010000",
263 0x40010000, 0x00010000);
264 create_unimplemented_device("Extra peripheral region @0x40020000",
265 0x40020000, 0x00010000);
267 create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
268 create_unimplemented_device("VGA", 0x41000000, 0x0200000);
270 switch (mmc->fpga_type) {
271 case FPGA_AN385:
272 case FPGA_AN386:
273 case FPGA_AN500:
275 /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
276 * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
278 Object *orgate;
279 DeviceState *orgate_dev;
281 orgate = object_new(TYPE_OR_IRQ);
282 object_property_set_int(orgate, "num-lines", 6, &error_fatal);
283 qdev_realize(DEVICE(orgate), NULL, &error_fatal);
284 orgate_dev = DEVICE(orgate);
285 qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
287 for (i = 0; i < 5; i++) {
288 DeviceState *dev;
289 SysBusDevice *s;
291 static const hwaddr uartbase[] = {0x40004000, 0x40005000,
292 0x40006000, 0x40007000,
293 0x40009000};
294 /* RX irq number; TX irq is always one greater */
295 static const int uartirq[] = {0, 2, 4, 18, 20};
296 qemu_irq txovrint = NULL, rxovrint = NULL;
298 if (i < 3) {
299 txovrint = qdev_get_gpio_in(orgate_dev, i * 2);
300 rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
303 dev = qdev_new(TYPE_CMSDK_APB_UART);
304 s = SYS_BUS_DEVICE(dev);
305 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
306 qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ);
307 sysbus_realize_and_unref(s, &error_fatal);
308 sysbus_mmio_map(s, 0, uartbase[i]);
309 sysbus_connect_irq(s, 0, qdev_get_gpio_in(armv7m, uartirq[i] + 1));
310 sysbus_connect_irq(s, 1, qdev_get_gpio_in(armv7m, uartirq[i]));
311 sysbus_connect_irq(s, 2, txovrint);
312 sysbus_connect_irq(s, 3, rxovrint);
314 break;
316 case FPGA_AN511:
318 /* The overflow IRQs for all UARTs are ORed together.
319 * Tx and Rx IRQs for each UART are ORed together.
321 Object *orgate;
322 DeviceState *orgate_dev;
324 orgate = object_new(TYPE_OR_IRQ);
325 object_property_set_int(orgate, "num-lines", 10, &error_fatal);
326 qdev_realize(DEVICE(orgate), NULL, &error_fatal);
327 orgate_dev = DEVICE(orgate);
328 qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
330 for (i = 0; i < 5; i++) {
331 /* system irq numbers for the combined tx/rx for each UART */
332 static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56};
333 static const hwaddr uartbase[] = {0x40004000, 0x40005000,
334 0x4002c000, 0x4002d000,
335 0x4002e000};
336 Object *txrx_orgate;
337 DeviceState *txrx_orgate_dev, *dev;
338 SysBusDevice *s;
340 txrx_orgate = object_new(TYPE_OR_IRQ);
341 object_property_set_int(txrx_orgate, "num-lines", 2, &error_fatal);
342 qdev_realize(DEVICE(txrx_orgate), NULL, &error_fatal);
343 txrx_orgate_dev = DEVICE(txrx_orgate);
344 qdev_connect_gpio_out(txrx_orgate_dev, 0,
345 qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
347 dev = qdev_new(TYPE_CMSDK_APB_UART);
348 s = SYS_BUS_DEVICE(dev);
349 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
350 qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ);
351 sysbus_realize_and_unref(s, &error_fatal);
352 sysbus_mmio_map(s, 0, uartbase[i]);
353 sysbus_connect_irq(s, 0, qdev_get_gpio_in(txrx_orgate_dev, 0));
354 sysbus_connect_irq(s, 1, qdev_get_gpio_in(txrx_orgate_dev, 1));
355 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
356 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
358 break;
360 default:
361 g_assert_not_reached();
363 for (i = 0; i < 4; i++) {
364 static const hwaddr gpiobase[] = {0x40010000, 0x40011000,
365 0x40012000, 0x40013000};
366 create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000);
369 /* CMSDK APB subsystem */
370 for (i = 0; i < ARRAY_SIZE(mms->timer); i++) {
371 g_autofree char *name = g_strdup_printf("timer%d", i);
372 hwaddr base = 0x40000000 + i * 0x1000;
373 int irqno = 8 + i;
374 SysBusDevice *sbd;
376 object_initialize_child(OBJECT(mms), name, &mms->timer[i],
377 TYPE_CMSDK_APB_TIMER);
378 sbd = SYS_BUS_DEVICE(&mms->timer[i]);
379 qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk);
380 sysbus_realize_and_unref(sbd, &error_fatal);
381 sysbus_mmio_map(sbd, 0, base);
382 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno));
385 object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
386 TYPE_CMSDK_APB_DUALTIMER);
387 qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk);
388 sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
389 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
390 qdev_get_gpio_in(armv7m, 10));
391 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
392 object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
393 TYPE_CMSDK_APB_WATCHDOG);
394 qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk);
395 sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
396 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
397 qdev_get_gpio_in_named(armv7m, "NMI", 0));
398 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0x40008000);
400 /* FPGA APB subsystem */
401 object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
402 sccdev = DEVICE(&mms->scc);
403 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
404 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
405 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
406 /* All these FPGA images have the same OSCCLK configuration */
407 oscclk = qlist_new();
408 qlist_append_int(oscclk, 50000000);
409 qlist_append_int(oscclk, 24576000);
410 qlist_append_int(oscclk, 25000000);
411 qdev_prop_set_array(sccdev, "oscclk", oscclk);
413 sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
414 sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
415 object_initialize_child(OBJECT(mms), "fpgaio",
416 &mms->fpgaio, TYPE_MPS2_FPGAIO);
417 qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000);
418 sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
419 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000);
420 sysbus_create_simple(TYPE_PL022, 0x40025000, /* External ADC */
421 qdev_get_gpio_in(armv7m, 22));
422 for (i = 0; i < 2; i++) {
423 static const int spi_irqno[] = {11, 24};
424 static const hwaddr spibase[] = {0x40020000, /* APB */
425 0x40021000, /* LCD */
426 0x40026000, /* Shield0 */
427 0x40027000}; /* Shield1 */
428 DeviceState *orgate_dev;
429 Object *orgate;
430 int j;
432 orgate = object_new(TYPE_OR_IRQ);
433 object_property_set_int(orgate, "num-lines", 2, &error_fatal);
434 orgate_dev = DEVICE(orgate);
435 qdev_realize(orgate_dev, NULL, &error_fatal);
436 qdev_connect_gpio_out(orgate_dev, 0,
437 qdev_get_gpio_in(armv7m, spi_irqno[i]));
438 for (j = 0; j < 2; j++) {
439 sysbus_create_simple(TYPE_PL022, spibase[2 * i + j],
440 qdev_get_gpio_in(orgate_dev, j));
443 for (i = 0; i < 4; i++) {
444 static const hwaddr i2cbase[] = {0x40022000, /* Touch */
445 0x40023000, /* Audio */
446 0x40029000, /* Shield0 */
447 0x4002a000}; /* Shield1 */
448 DeviceState *dev;
450 dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL);
451 if (i < 2) {
453 * internal-only bus: mark it full to avoid user-created
454 * i2c devices being plugged into it.
456 BusState *qbus = qdev_get_child_bus(dev, "i2c");
457 qbus_mark_full(qbus);
460 create_unimplemented_device("i2s", 0x40024000, 0x400);
462 /* In hardware this is a LAN9220; the LAN9118 is software compatible
463 * except that it doesn't support the checksum-offload feature.
465 lan9118_init(&nd_table[0], mmc->ethernet_base,
466 qdev_get_gpio_in(armv7m,
467 mmc->fpga_type == FPGA_AN511 ? 47 : 13));
469 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
470 0, 0x400000);
473 static void mps2_class_init(ObjectClass *oc, void *data)
475 MachineClass *mc = MACHINE_CLASS(oc);
477 mc->init = mps2_common_init;
478 mc->max_cpus = 1;
479 mc->default_ram_size = 16 * MiB;
480 mc->default_ram_id = "mps.ram";
483 static void mps2_an385_class_init(ObjectClass *oc, void *data)
485 MachineClass *mc = MACHINE_CLASS(oc);
486 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
488 mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
489 mmc->fpga_type = FPGA_AN385;
490 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
491 mmc->scc_id = 0x41043850;
492 mmc->psram_base = 0x21000000;
493 mmc->ethernet_base = 0x40200000;
494 mmc->has_block_ram = true;
497 static void mps2_an386_class_init(ObjectClass *oc, void *data)
499 MachineClass *mc = MACHINE_CLASS(oc);
500 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
502 mc->desc = "ARM MPS2 with AN386 FPGA image for Cortex-M4";
503 mmc->fpga_type = FPGA_AN386;
504 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
505 mmc->scc_id = 0x41043860;
506 mmc->psram_base = 0x21000000;
507 mmc->ethernet_base = 0x40200000;
508 mmc->has_block_ram = true;
511 static void mps2_an500_class_init(ObjectClass *oc, void *data)
513 MachineClass *mc = MACHINE_CLASS(oc);
514 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
516 mc->desc = "ARM MPS2 with AN500 FPGA image for Cortex-M7";
517 mmc->fpga_type = FPGA_AN500;
518 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m7");
519 mmc->scc_id = 0x41045000;
520 mmc->psram_base = 0x60000000;
521 mmc->ethernet_base = 0xa0000000;
522 mmc->has_block_ram = false;
525 static void mps2_an511_class_init(ObjectClass *oc, void *data)
527 MachineClass *mc = MACHINE_CLASS(oc);
528 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
530 mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
531 mmc->fpga_type = FPGA_AN511;
532 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
533 mmc->scc_id = 0x41045110;
534 mmc->psram_base = 0x21000000;
535 mmc->ethernet_base = 0x40200000;
536 mmc->has_block_ram = false;
539 static const TypeInfo mps2_info = {
540 .name = TYPE_MPS2_MACHINE,
541 .parent = TYPE_MACHINE,
542 .abstract = true,
543 .instance_size = sizeof(MPS2MachineState),
544 .class_size = sizeof(MPS2MachineClass),
545 .class_init = mps2_class_init,
548 static const TypeInfo mps2_an385_info = {
549 .name = TYPE_MPS2_AN385_MACHINE,
550 .parent = TYPE_MPS2_MACHINE,
551 .class_init = mps2_an385_class_init,
554 static const TypeInfo mps2_an386_info = {
555 .name = TYPE_MPS2_AN386_MACHINE,
556 .parent = TYPE_MPS2_MACHINE,
557 .class_init = mps2_an386_class_init,
560 static const TypeInfo mps2_an500_info = {
561 .name = TYPE_MPS2_AN500_MACHINE,
562 .parent = TYPE_MPS2_MACHINE,
563 .class_init = mps2_an500_class_init,
566 static const TypeInfo mps2_an511_info = {
567 .name = TYPE_MPS2_AN511_MACHINE,
568 .parent = TYPE_MPS2_MACHINE,
569 .class_init = mps2_an511_class_init,
572 static void mps2_machine_init(void)
574 type_register_static(&mps2_info);
575 type_register_static(&mps2_an385_info);
576 type_register_static(&mps2_an386_info);
577 type_register_static(&mps2_an500_info);
578 type_register_static(&mps2_an511_info);
581 type_init(mps2_machine_init);