4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
7 * Copyright 2016 IBM Corp.
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
13 #include "qemu/osdep.h"
14 #include "qemu/units.h"
15 #include "qapi/error.h"
16 #include "hw/misc/unimp.h"
17 #include "hw/arm/aspeed_soc.h"
18 #include "hw/char/serial.h"
19 #include "qemu/module.h"
20 #include "qemu/error-report.h"
21 #include "hw/i2c/aspeed_i2c.h"
23 #include "sysemu/sysemu.h"
25 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
27 static const hwaddr aspeed_soc_ast2400_memmap
[] = {
28 [ASPEED_DEV_SPI_BOOT
] = ASPEED_SOC_SPI_BOOT_ADDR
,
29 [ASPEED_DEV_IOMEM
] = 0x1E600000,
30 [ASPEED_DEV_FMC
] = 0x1E620000,
31 [ASPEED_DEV_SPI1
] = 0x1E630000,
32 [ASPEED_DEV_EHCI1
] = 0x1E6A1000,
33 [ASPEED_DEV_VIC
] = 0x1E6C0000,
34 [ASPEED_DEV_SDMC
] = 0x1E6E0000,
35 [ASPEED_DEV_SCU
] = 0x1E6E2000,
36 [ASPEED_DEV_HACE
] = 0x1E6E3000,
37 [ASPEED_DEV_XDMA
] = 0x1E6E7000,
38 [ASPEED_DEV_VIDEO
] = 0x1E700000,
39 [ASPEED_DEV_ADC
] = 0x1E6E9000,
40 [ASPEED_DEV_SRAM
] = 0x1E720000,
41 [ASPEED_DEV_SDHCI
] = 0x1E740000,
42 [ASPEED_DEV_GPIO
] = 0x1E780000,
43 [ASPEED_DEV_RTC
] = 0x1E781000,
44 [ASPEED_DEV_TIMER1
] = 0x1E782000,
45 [ASPEED_DEV_WDT
] = 0x1E785000,
46 [ASPEED_DEV_PWM
] = 0x1E786000,
47 [ASPEED_DEV_LPC
] = 0x1E789000,
48 [ASPEED_DEV_IBT
] = 0x1E789140,
49 [ASPEED_DEV_I2C
] = 0x1E78A000,
50 [ASPEED_DEV_PECI
] = 0x1E78B000,
51 [ASPEED_DEV_ETH1
] = 0x1E660000,
52 [ASPEED_DEV_ETH2
] = 0x1E680000,
53 [ASPEED_DEV_UART1
] = 0x1E783000,
54 [ASPEED_DEV_UART2
] = 0x1E78D000,
55 [ASPEED_DEV_UART3
] = 0x1E78E000,
56 [ASPEED_DEV_UART4
] = 0x1E78F000,
57 [ASPEED_DEV_UART5
] = 0x1E784000,
58 [ASPEED_DEV_VUART
] = 0x1E787000,
59 [ASPEED_DEV_SDRAM
] = 0x40000000,
62 static const hwaddr aspeed_soc_ast2500_memmap
[] = {
63 [ASPEED_DEV_SPI_BOOT
] = ASPEED_SOC_SPI_BOOT_ADDR
,
64 [ASPEED_DEV_IOMEM
] = 0x1E600000,
65 [ASPEED_DEV_FMC
] = 0x1E620000,
66 [ASPEED_DEV_SPI1
] = 0x1E630000,
67 [ASPEED_DEV_SPI2
] = 0x1E631000,
68 [ASPEED_DEV_EHCI1
] = 0x1E6A1000,
69 [ASPEED_DEV_EHCI2
] = 0x1E6A3000,
70 [ASPEED_DEV_VIC
] = 0x1E6C0000,
71 [ASPEED_DEV_SDMC
] = 0x1E6E0000,
72 [ASPEED_DEV_SCU
] = 0x1E6E2000,
73 [ASPEED_DEV_HACE
] = 0x1E6E3000,
74 [ASPEED_DEV_XDMA
] = 0x1E6E7000,
75 [ASPEED_DEV_ADC
] = 0x1E6E9000,
76 [ASPEED_DEV_VIDEO
] = 0x1E700000,
77 [ASPEED_DEV_SRAM
] = 0x1E720000,
78 [ASPEED_DEV_SDHCI
] = 0x1E740000,
79 [ASPEED_DEV_GPIO
] = 0x1E780000,
80 [ASPEED_DEV_RTC
] = 0x1E781000,
81 [ASPEED_DEV_TIMER1
] = 0x1E782000,
82 [ASPEED_DEV_WDT
] = 0x1E785000,
83 [ASPEED_DEV_PWM
] = 0x1E786000,
84 [ASPEED_DEV_LPC
] = 0x1E789000,
85 [ASPEED_DEV_IBT
] = 0x1E789140,
86 [ASPEED_DEV_I2C
] = 0x1E78A000,
87 [ASPEED_DEV_PECI
] = 0x1E78B000,
88 [ASPEED_DEV_ETH1
] = 0x1E660000,
89 [ASPEED_DEV_ETH2
] = 0x1E680000,
90 [ASPEED_DEV_UART1
] = 0x1E783000,
91 [ASPEED_DEV_UART2
] = 0x1E78D000,
92 [ASPEED_DEV_UART3
] = 0x1E78E000,
93 [ASPEED_DEV_UART4
] = 0x1E78F000,
94 [ASPEED_DEV_UART5
] = 0x1E784000,
95 [ASPEED_DEV_VUART
] = 0x1E787000,
96 [ASPEED_DEV_SDRAM
] = 0x80000000,
99 static const int aspeed_soc_ast2400_irqmap
[] = {
100 [ASPEED_DEV_UART1
] = 9,
101 [ASPEED_DEV_UART2
] = 32,
102 [ASPEED_DEV_UART3
] = 33,
103 [ASPEED_DEV_UART4
] = 34,
104 [ASPEED_DEV_UART5
] = 10,
105 [ASPEED_DEV_VUART
] = 8,
106 [ASPEED_DEV_FMC
] = 19,
107 [ASPEED_DEV_EHCI1
] = 5,
108 [ASPEED_DEV_EHCI2
] = 13,
109 [ASPEED_DEV_SDMC
] = 0,
110 [ASPEED_DEV_SCU
] = 21,
111 [ASPEED_DEV_ADC
] = 31,
112 [ASPEED_DEV_GPIO
] = 20,
113 [ASPEED_DEV_RTC
] = 22,
114 [ASPEED_DEV_TIMER1
] = 16,
115 [ASPEED_DEV_TIMER2
] = 17,
116 [ASPEED_DEV_TIMER3
] = 18,
117 [ASPEED_DEV_TIMER4
] = 35,
118 [ASPEED_DEV_TIMER5
] = 36,
119 [ASPEED_DEV_TIMER6
] = 37,
120 [ASPEED_DEV_TIMER7
] = 38,
121 [ASPEED_DEV_TIMER8
] = 39,
122 [ASPEED_DEV_WDT
] = 27,
123 [ASPEED_DEV_PWM
] = 28,
124 [ASPEED_DEV_LPC
] = 8,
125 [ASPEED_DEV_I2C
] = 12,
126 [ASPEED_DEV_PECI
] = 15,
127 [ASPEED_DEV_ETH1
] = 2,
128 [ASPEED_DEV_ETH2
] = 3,
129 [ASPEED_DEV_XDMA
] = 6,
130 [ASPEED_DEV_SDHCI
] = 26,
131 [ASPEED_DEV_HACE
] = 4,
134 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
136 static qemu_irq
aspeed_soc_ast2400_get_irq(AspeedSoCState
*s
, int dev
)
138 Aspeed2400SoCState
*a
= ASPEED2400_SOC(s
);
139 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
141 return qdev_get_gpio_in(DEVICE(&a
->vic
), sc
->irqmap
[dev
]);
144 static void aspeed_ast2400_soc_init(Object
*obj
)
146 Aspeed2400SoCState
*a
= ASPEED2400_SOC(obj
);
147 AspeedSoCState
*s
= ASPEED_SOC(obj
);
148 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
153 if (sscanf(sc
->name
, "%7s", socname
) != 1) {
154 g_assert_not_reached();
157 for (i
= 0; i
< sc
->num_cpus
; i
++) {
158 object_initialize_child(obj
, "cpu[*]", &a
->cpu
[i
], sc
->cpu_type
);
161 snprintf(typename
, sizeof(typename
), "aspeed.scu-%s", socname
);
162 object_initialize_child(obj
, "scu", &s
->scu
, typename
);
163 qdev_prop_set_uint32(DEVICE(&s
->scu
), "silicon-rev",
165 object_property_add_alias(obj
, "hw-strap1", OBJECT(&s
->scu
),
167 object_property_add_alias(obj
, "hw-strap2", OBJECT(&s
->scu
),
169 object_property_add_alias(obj
, "hw-prot-key", OBJECT(&s
->scu
),
172 object_initialize_child(obj
, "vic", &a
->vic
, TYPE_ASPEED_VIC
);
174 object_initialize_child(obj
, "rtc", &s
->rtc
, TYPE_ASPEED_RTC
);
176 snprintf(typename
, sizeof(typename
), "aspeed.timer-%s", socname
);
177 object_initialize_child(obj
, "timerctrl", &s
->timerctrl
, typename
);
179 snprintf(typename
, sizeof(typename
), "aspeed.adc-%s", socname
);
180 object_initialize_child(obj
, "adc", &s
->adc
, typename
);
182 snprintf(typename
, sizeof(typename
), "aspeed.i2c-%s", socname
);
183 object_initialize_child(obj
, "i2c", &s
->i2c
, typename
);
185 object_initialize_child(obj
, "peci", &s
->peci
, TYPE_ASPEED_PECI
);
187 snprintf(typename
, sizeof(typename
), "aspeed.fmc-%s", socname
);
188 object_initialize_child(obj
, "fmc", &s
->fmc
, typename
);
190 for (i
= 0; i
< sc
->spis_num
; i
++) {
191 snprintf(typename
, sizeof(typename
), "aspeed.spi%d-%s", i
+ 1, socname
);
192 object_initialize_child(obj
, "spi[*]", &s
->spi
[i
], typename
);
195 for (i
= 0; i
< sc
->ehcis_num
; i
++) {
196 object_initialize_child(obj
, "ehci[*]", &s
->ehci
[i
],
200 snprintf(typename
, sizeof(typename
), "aspeed.sdmc-%s", socname
);
201 object_initialize_child(obj
, "sdmc", &s
->sdmc
, typename
);
202 object_property_add_alias(obj
, "ram-size", OBJECT(&s
->sdmc
),
205 for (i
= 0; i
< sc
->wdts_num
; i
++) {
206 snprintf(typename
, sizeof(typename
), "aspeed.wdt-%s", socname
);
207 object_initialize_child(obj
, "wdt[*]", &s
->wdt
[i
], typename
);
210 for (i
= 0; i
< sc
->macs_num
; i
++) {
211 object_initialize_child(obj
, "ftgmac100[*]", &s
->ftgmac100
[i
],
215 for (i
= 0; i
< sc
->uarts_num
; i
++) {
216 object_initialize_child(obj
, "uart[*]", &s
->uart
[i
], TYPE_SERIAL_MM
);
219 snprintf(typename
, sizeof(typename
), TYPE_ASPEED_XDMA
"-%s", socname
);
220 object_initialize_child(obj
, "xdma", &s
->xdma
, typename
);
222 snprintf(typename
, sizeof(typename
), "aspeed.gpio-%s", socname
);
223 object_initialize_child(obj
, "gpio", &s
->gpio
, typename
);
225 object_initialize_child(obj
, "sdc", &s
->sdhci
, TYPE_ASPEED_SDHCI
);
227 object_property_set_int(OBJECT(&s
->sdhci
), "num-slots", 2, &error_abort
);
229 /* Init sd card slot class here so that they're under the correct parent */
230 for (i
= 0; i
< ASPEED_SDHCI_NUM_SLOTS
; ++i
) {
231 object_initialize_child(obj
, "sdhci[*]", &s
->sdhci
.slots
[i
],
235 object_initialize_child(obj
, "lpc", &s
->lpc
, TYPE_ASPEED_LPC
);
237 snprintf(typename
, sizeof(typename
), "aspeed.hace-%s", socname
);
238 object_initialize_child(obj
, "hace", &s
->hace
, typename
);
240 object_initialize_child(obj
, "iomem", &s
->iomem
, TYPE_UNIMPLEMENTED_DEVICE
);
241 object_initialize_child(obj
, "video", &s
->video
, TYPE_UNIMPLEMENTED_DEVICE
);
244 static void aspeed_ast2400_soc_realize(DeviceState
*dev
, Error
**errp
)
247 Aspeed2400SoCState
*a
= ASPEED2400_SOC(dev
);
248 AspeedSoCState
*s
= ASPEED_SOC(dev
);
249 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
251 g_autofree
char *sram_name
= NULL
;
253 /* Default boot region (SPI memory or ROMs) */
254 memory_region_init(&s
->spi_boot_container
, OBJECT(s
),
255 "aspeed.spi_boot_container", 0x10000000);
256 memory_region_add_subregion(s
->memory
, sc
->memmap
[ASPEED_DEV_SPI_BOOT
],
257 &s
->spi_boot_container
);
260 aspeed_mmio_map_unimplemented(s
, SYS_BUS_DEVICE(&s
->iomem
), "aspeed.io",
261 sc
->memmap
[ASPEED_DEV_IOMEM
],
262 ASPEED_SOC_IOMEM_SIZE
);
264 /* Video engine stub */
265 aspeed_mmio_map_unimplemented(s
, SYS_BUS_DEVICE(&s
->video
), "aspeed.video",
266 sc
->memmap
[ASPEED_DEV_VIDEO
], 0x1000);
269 for (i
= 0; i
< sc
->num_cpus
; i
++) {
270 object_property_set_link(OBJECT(&a
->cpu
[i
]), "memory",
271 OBJECT(s
->memory
), &error_abort
);
272 if (!qdev_realize(DEVICE(&a
->cpu
[i
]), NULL
, errp
)) {
278 sram_name
= g_strdup_printf("aspeed.sram.%d", CPU(&a
->cpu
[0])->cpu_index
);
279 memory_region_init_ram(&s
->sram
, OBJECT(s
), sram_name
, sc
->sram_size
, &err
);
281 error_propagate(errp
, err
);
284 memory_region_add_subregion(s
->memory
,
285 sc
->memmap
[ASPEED_DEV_SRAM
], &s
->sram
);
288 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->scu
), errp
)) {
291 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->scu
), 0, sc
->memmap
[ASPEED_DEV_SCU
]);
294 if (!sysbus_realize(SYS_BUS_DEVICE(&a
->vic
), errp
)) {
297 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&a
->vic
), 0, sc
->memmap
[ASPEED_DEV_VIC
]);
298 sysbus_connect_irq(SYS_BUS_DEVICE(&a
->vic
), 0,
299 qdev_get_gpio_in(DEVICE(&a
->cpu
), ARM_CPU_IRQ
));
300 sysbus_connect_irq(SYS_BUS_DEVICE(&a
->vic
), 1,
301 qdev_get_gpio_in(DEVICE(&a
->cpu
), ARM_CPU_FIQ
));
304 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->rtc
), errp
)) {
307 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->rtc
), 0, sc
->memmap
[ASPEED_DEV_RTC
]);
308 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->rtc
), 0,
309 aspeed_soc_get_irq(s
, ASPEED_DEV_RTC
));
312 object_property_set_link(OBJECT(&s
->timerctrl
), "scu", OBJECT(&s
->scu
),
314 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->timerctrl
), errp
)) {
317 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->timerctrl
), 0,
318 sc
->memmap
[ASPEED_DEV_TIMER1
]);
319 for (i
= 0; i
< ASPEED_TIMER_NR_TIMERS
; i
++) {
320 qemu_irq irq
= aspeed_soc_get_irq(s
, ASPEED_DEV_TIMER1
+ i
);
321 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timerctrl
), i
, irq
);
325 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->adc
), errp
)) {
328 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->adc
), 0, sc
->memmap
[ASPEED_DEV_ADC
]);
329 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->adc
), 0,
330 aspeed_soc_get_irq(s
, ASPEED_DEV_ADC
));
333 if (!aspeed_soc_uart_realize(s
, errp
)) {
338 object_property_set_link(OBJECT(&s
->i2c
), "dram", OBJECT(s
->dram_mr
),
340 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->i2c
), errp
)) {
343 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->i2c
), 0, sc
->memmap
[ASPEED_DEV_I2C
]);
344 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
), 0,
345 aspeed_soc_get_irq(s
, ASPEED_DEV_I2C
));
348 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->peci
), errp
)) {
351 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->peci
), 0,
352 sc
->memmap
[ASPEED_DEV_PECI
]);
353 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->peci
), 0,
354 aspeed_soc_get_irq(s
, ASPEED_DEV_PECI
));
356 /* FMC, The number of CS is set at the board level */
357 object_property_set_link(OBJECT(&s
->fmc
), "dram", OBJECT(s
->dram_mr
),
359 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->fmc
), errp
)) {
362 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->fmc
), 0, sc
->memmap
[ASPEED_DEV_FMC
]);
363 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->fmc
), 1,
364 ASPEED_SMC_GET_CLASS(&s
->fmc
)->flash_window_base
);
365 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->fmc
), 0,
366 aspeed_soc_get_irq(s
, ASPEED_DEV_FMC
));
368 /* Set up an alias on the FMC CE0 region (boot default) */
369 MemoryRegion
*fmc0_mmio
= &s
->fmc
.flashes
[0].mmio
;
370 memory_region_init_alias(&s
->spi_boot
, OBJECT(s
), "aspeed.spi_boot",
371 fmc0_mmio
, 0, memory_region_size(fmc0_mmio
));
372 memory_region_add_subregion(&s
->spi_boot_container
, 0x0, &s
->spi_boot
);
375 for (i
= 0; i
< sc
->spis_num
; i
++) {
376 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->spi
[i
]), errp
)) {
379 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
380 sc
->memmap
[ASPEED_DEV_SPI1
+ i
]);
381 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->spi
[i
]), 1,
382 ASPEED_SMC_GET_CLASS(&s
->spi
[i
])->flash_window_base
);
386 for (i
= 0; i
< sc
->ehcis_num
; i
++) {
387 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->ehci
[i
]), errp
)) {
390 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->ehci
[i
]), 0,
391 sc
->memmap
[ASPEED_DEV_EHCI1
+ i
]);
392 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ehci
[i
]), 0,
393 aspeed_soc_get_irq(s
, ASPEED_DEV_EHCI1
+ i
));
396 /* SDMC - SDRAM Memory Controller */
397 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sdmc
), errp
)) {
400 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->sdmc
), 0,
401 sc
->memmap
[ASPEED_DEV_SDMC
]);
404 for (i
= 0; i
< sc
->wdts_num
; i
++) {
405 AspeedWDTClass
*awc
= ASPEED_WDT_GET_CLASS(&s
->wdt
[i
]);
406 hwaddr wdt_offset
= sc
->memmap
[ASPEED_DEV_WDT
] + i
* awc
->iosize
;
408 object_property_set_link(OBJECT(&s
->wdt
[i
]), "scu", OBJECT(&s
->scu
),
410 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->wdt
[i
]), errp
)) {
413 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->wdt
[i
]), 0, wdt_offset
);
417 if (!aspeed_soc_dram_init(s
, errp
)) {
422 for (i
= 0; i
< sc
->macs_num
; i
++) {
423 object_property_set_bool(OBJECT(&s
->ftgmac100
[i
]), "aspeed", true,
425 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), errp
)) {
428 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
429 sc
->memmap
[ASPEED_DEV_ETH1
+ i
]);
430 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
431 aspeed_soc_get_irq(s
, ASPEED_DEV_ETH1
+ i
));
435 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->xdma
), errp
)) {
438 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->xdma
), 0,
439 sc
->memmap
[ASPEED_DEV_XDMA
]);
440 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->xdma
), 0,
441 aspeed_soc_get_irq(s
, ASPEED_DEV_XDMA
));
444 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->gpio
), errp
)) {
447 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->gpio
), 0,
448 sc
->memmap
[ASPEED_DEV_GPIO
]);
449 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
), 0,
450 aspeed_soc_get_irq(s
, ASPEED_DEV_GPIO
));
453 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sdhci
), errp
)) {
456 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->sdhci
), 0,
457 sc
->memmap
[ASPEED_DEV_SDHCI
]);
458 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sdhci
), 0,
459 aspeed_soc_get_irq(s
, ASPEED_DEV_SDHCI
));
462 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->lpc
), errp
)) {
465 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->lpc
), 0, sc
->memmap
[ASPEED_DEV_LPC
]);
467 /* Connect the LPC IRQ to the VIC */
468 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 0,
469 aspeed_soc_get_irq(s
, ASPEED_DEV_LPC
));
472 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
473 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by
474 * contrast, on the AST2600, the subdevice IRQs are connected straight to
477 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output
478 * to the VIC is at offset 0.
480 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_1
,
481 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_1
));
483 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_2
,
484 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_2
));
486 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_3
,
487 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_3
));
489 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_4
,
490 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_4
));
493 object_property_set_link(OBJECT(&s
->hace
), "dram", OBJECT(s
->dram_mr
),
495 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->hace
), errp
)) {
498 aspeed_mmio_map(s
, SYS_BUS_DEVICE(&s
->hace
), 0,
499 sc
->memmap
[ASPEED_DEV_HACE
]);
500 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->hace
), 0,
501 aspeed_soc_get_irq(s
, ASPEED_DEV_HACE
));
504 static void aspeed_soc_ast2400_class_init(ObjectClass
*oc
, void *data
)
506 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
507 DeviceClass
*dc
= DEVICE_CLASS(oc
);
509 dc
->realize
= aspeed_ast2400_soc_realize
;
510 /* Reason: Uses serial_hds and nd_table in realize() directly */
511 dc
->user_creatable
= false;
513 sc
->name
= "ast2400-a1";
514 sc
->cpu_type
= ARM_CPU_TYPE_NAME("arm926");
515 sc
->silicon_rev
= AST2400_A1_SILICON_REV
;
516 sc
->sram_size
= 0x8000;
522 sc
->irqmap
= aspeed_soc_ast2400_irqmap
;
523 sc
->memmap
= aspeed_soc_ast2400_memmap
;
525 sc
->get_irq
= aspeed_soc_ast2400_get_irq
;
528 static void aspeed_soc_ast2500_class_init(ObjectClass
*oc
, void *data
)
530 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
531 DeviceClass
*dc
= DEVICE_CLASS(oc
);
533 dc
->realize
= aspeed_ast2400_soc_realize
;
534 /* Reason: Uses serial_hds and nd_table in realize() directly */
535 dc
->user_creatable
= false;
537 sc
->name
= "ast2500-a1";
538 sc
->cpu_type
= ARM_CPU_TYPE_NAME("arm1176");
539 sc
->silicon_rev
= AST2500_A1_SILICON_REV
;
540 sc
->sram_size
= 0x9000;
546 sc
->irqmap
= aspeed_soc_ast2500_irqmap
;
547 sc
->memmap
= aspeed_soc_ast2500_memmap
;
549 sc
->get_irq
= aspeed_soc_ast2400_get_irq
;
552 static const TypeInfo aspeed_soc_ast2400_types
[] = {
554 .name
= TYPE_ASPEED2400_SOC
,
555 .parent
= TYPE_ASPEED_SOC
,
556 .instance_init
= aspeed_ast2400_soc_init
,
557 .instance_size
= sizeof(Aspeed2400SoCState
),
560 .name
= "ast2400-a1",
561 .parent
= TYPE_ASPEED2400_SOC
,
562 .class_init
= aspeed_soc_ast2400_class_init
,
564 .name
= "ast2500-a1",
565 .parent
= TYPE_ASPEED2400_SOC
,
566 .class_init
= aspeed_soc_ast2500_class_init
,
570 DEFINE_TYPES(aspeed_soc_ast2400_types
)