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hw/i386/pc: Use qdev_prop_set_array()
[qemu/kevin.git] / hw / i386 / pc.c
blob29b9964733ed118f330753c04146bebf4580cddf
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial.h"
29 #include "hw/char/parallel.h"
30 #include "hw/hyperv/hv-balloon.h"
31 #include "hw/i386/fw_cfg.h"
32 #include "hw/i386/vmport.h"
33 #include "sysemu/cpus.h"
34 #include "hw/ide/internal.h"
35 #include "hw/timer/hpet.h"
36 #include "hw/loader.h"
37 #include "hw/rtc/mc146818rtc.h"
38 #include "hw/intc/i8259.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/input/i8042.h"
41 #include "hw/audio/pcspk.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/xen.h"
44 #include "sysemu/reset.h"
45 #include "kvm/kvm_i386.h"
46 #include "hw/xen/xen.h"
47 #include "qapi/qmp/qlist.h"
48 #include "qemu/error-report.h"
49 #include "hw/acpi/cpu_hotplug.h"
50 #include "acpi-build.h"
51 #include "hw/mem/nvdimm.h"
52 #include "hw/cxl/cxl_host.h"
53 #include "hw/usb.h"
54 #include "hw/i386/intel_iommu.h"
55 #include "hw/net/ne2000-isa.h"
56 #include "hw/virtio/virtio-iommu.h"
57 #include "hw/virtio/virtio-md-pci.h"
58 #include "hw/i386/kvm/xen_overlay.h"
59 #include "hw/i386/kvm/xen_evtchn.h"
60 #include "hw/i386/kvm/xen_gnttab.h"
61 #include "hw/i386/kvm/xen_xenstore.h"
62 #include "hw/mem/memory-device.h"
63 #include "e820_memory_layout.h"
64 #include "trace.h"
65 #include CONFIG_DEVICES
66
67 #ifdef CONFIG_XEN_EMU
68 #include "hw/xen/xen-legacy-backend.h"
69 #include "hw/xen/xen-bus.h"
70 #endif
71
72 /*
73 * Helper for setting model-id for CPU models that changed model-id
74 * depending on QEMU versions up to QEMU 2.4.
75 */
76 #define PC_CPU_MODEL_IDS(v) \
77 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
78 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
79 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
80
81 GlobalProperty pc_compat_8_1[] = {};
82 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1);
83
84 GlobalProperty pc_compat_8_0[] = {
85 { "virtio-mem", "unplugged-inaccessible", "auto" },
86 };
87 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0);
88
89 GlobalProperty pc_compat_7_2[] = {
90 { "ICH9-LPC", "noreboot", "true" },
91 };
92 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
93
94 GlobalProperty pc_compat_7_1[] = {};
95 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
96
97 GlobalProperty pc_compat_7_0[] = {};
98 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
99
100 GlobalProperty pc_compat_6_2[] = {
101 { "virtio-mem", "unplugged-inaccessible", "off" },
102 };
103 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
104
105 GlobalProperty pc_compat_6_1[] = {
106 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
107 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
108 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
109 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
110 };
111 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
112
113 GlobalProperty pc_compat_6_0[] = {
114 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
115 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
116 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
117 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
118 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
119 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
120 };
121 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
122
123 GlobalProperty pc_compat_5_2[] = {
124 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
125 };
126 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
127
128 GlobalProperty pc_compat_5_1[] = {
129 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
130 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
131 };
132 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
133
134 GlobalProperty pc_compat_5_0[] = {
135 };
136 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
137
138 GlobalProperty pc_compat_4_2[] = {
139 { "mch", "smbase-smram", "off" },
140 };
141 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
142
143 GlobalProperty pc_compat_4_1[] = {};
144 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
145
146 GlobalProperty pc_compat_4_0[] = {};
147 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
148
149 GlobalProperty pc_compat_3_1[] = {
150 { "intel-iommu", "dma-drain", "off" },
151 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
152 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
153 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
154 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
155 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
156 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
157 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
158 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
159 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
160 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
161 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
162 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
163 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
164 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
165 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
166 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
167 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
168 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
169 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
170 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
171 };
172 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
173
174 GlobalProperty pc_compat_3_0[] = {
175 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
176 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
177 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
178 };
179 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
180
181 GlobalProperty pc_compat_2_12[] = {
182 { TYPE_X86_CPU, "legacy-cache", "on" },
183 { TYPE_X86_CPU, "topoext", "off" },
184 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
185 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
186 };
187 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
188
189 GlobalProperty pc_compat_2_11[] = {
190 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
191 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
192 };
193 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
194
195 GlobalProperty pc_compat_2_10[] = {
196 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
197 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
198 { "q35-pcihost", "x-pci-hole64-fix", "off" },
199 };
200 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
201
202 GlobalProperty pc_compat_2_9[] = {
203 { "mch", "extended-tseg-mbytes", "0" },
204 };
205 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
206
207 GlobalProperty pc_compat_2_8[] = {
208 { TYPE_X86_CPU, "tcg-cpuid", "off" },
209 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
210 { "ICH9-LPC", "x-smi-broadcast", "off" },
211 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
212 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
213 };
214 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
215
216 GlobalProperty pc_compat_2_7[] = {
217 { TYPE_X86_CPU, "l3-cache", "off" },
218 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
219 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
220 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
221 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
222 { "isa-pcspk", "migrate", "off" },
223 };
224 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
225
226 GlobalProperty pc_compat_2_6[] = {
227 { TYPE_X86_CPU, "cpuid-0xb", "off" },
228 { "vmxnet3", "romfile", "" },
229 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
230 { "apic-common", "legacy-instance-id", "on", }
231 };
232 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
233
234 GlobalProperty pc_compat_2_5[] = {};
235 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
236
237 GlobalProperty pc_compat_2_4[] = {
238 PC_CPU_MODEL_IDS("2.4.0")
239 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
240 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
241 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
242 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
243 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
244 { TYPE_X86_CPU, "check", "off" },
245 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
246 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
247 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
248 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
249 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
250 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
251 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
252 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
253 };
254 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
255
256 GlobalProperty pc_compat_2_3[] = {
257 PC_CPU_MODEL_IDS("2.3.0")
258 { TYPE_X86_CPU, "arat", "off" },
259 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
260 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
261 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
262 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
263 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
264 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
265 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
266 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
267 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
268 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
269 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
270 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
271 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
272 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
273 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
274 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
275 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
276 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
277 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
278 };
279 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
280
281 GlobalProperty pc_compat_2_2[] = {
282 PC_CPU_MODEL_IDS("2.2.0")
283 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
284 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
285 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
286 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
287 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
288 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
289 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
290 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
291 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
292 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
293 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
294 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
295 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
296 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
297 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
298 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
299 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
300 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
301 };
302 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
303
304 GlobalProperty pc_compat_2_1[] = {
305 PC_CPU_MODEL_IDS("2.1.0")
306 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
307 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
308 };
309 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
310
311 GlobalProperty pc_compat_2_0[] = {
312 PC_CPU_MODEL_IDS("2.0.0")
313 { "virtio-scsi-pci", "any_layout", "off" },
314 { "PIIX4_PM", "memory-hotplug-support", "off" },
315 { "apic", "version", "0x11" },
316 { "nec-usb-xhci", "superspeed-ports-first", "off" },
317 { "nec-usb-xhci", "force-pcie-endcap", "on" },
318 { "pci-serial", "prog_if", "0" },
319 { "pci-serial-2x", "prog_if", "0" },
320 { "pci-serial-4x", "prog_if", "0" },
321 { "virtio-net-pci", "guest_announce", "off" },
322 { "ICH9-LPC", "memory-hotplug-support", "off" },
323 };
324 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
325
326 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
327 {
328 GSIState *s;
329
330 s = g_new0(GSIState, 1);
331 if (kvm_ioapic_in_kernel()) {
332 kvm_pc_setup_irq_routing(pci_enabled);
333 }
334 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
335
336 return s;
337 }
338
339 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
340 unsigned size)
341 {
342 }
343
344 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
345 {
346 return 0xffffffffffffffffULL;
347 }
348
349 /* MS-DOS compatibility mode FPU exception support */
350 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
351 unsigned size)
352 {
353 if (tcg_enabled()) {
354 cpu_set_ignne();
355 }
356 }
357
358 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
359 {
360 return 0xffffffffffffffffULL;
361 }
362
363 /* PC cmos mappings */
364
365 #define REG_EQUIPMENT_BYTE 0x14
366
367 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs,
368 int16_t cylinders, int8_t heads, int8_t sectors)
369 {
370 mc146818rtc_set_cmos_data(s, type_ofs, 47);
371 mc146818rtc_set_cmos_data(s, info_ofs, cylinders);
372 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8);
373 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads);
374 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff);
375 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff);
376 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
377 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders);
378 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8);
379 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors);
380 }
381
382 /* convert boot_device letter to something recognizable by the bios */
383 static int boot_device2nibble(char boot_device)
384 {
385 switch(boot_device) {
386 case 'a':
387 case 'b':
388 return 0x01; /* floppy boot */
389 case 'c':
390 return 0x02; /* hard drive boot */
391 case 'd':
392 return 0x03; /* CD-ROM boot */
393 case 'n':
394 return 0x04; /* Network boot */
395 }
396 return 0;
397 }
398
399 static void set_boot_dev(MC146818RtcState *s, const char *boot_device,
400 Error **errp)
401 {
402 #define PC_MAX_BOOT_DEVICES 3
403 int nbds, bds[3] = { 0, };
404 int i;
405
406 nbds = strlen(boot_device);
407 if (nbds > PC_MAX_BOOT_DEVICES) {
408 error_setg(errp, "Too many boot devices for PC");
409 return;
410 }
411 for (i = 0; i < nbds; i++) {
412 bds[i] = boot_device2nibble(boot_device[i]);
413 if (bds[i] == 0) {
414 error_setg(errp, "Invalid boot device for PC: '%c'",
415 boot_device[i]);
416 return;
417 }
418 }
419 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]);
420 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
421 }
422
423 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
424 {
425 set_boot_dev(opaque, boot_device, errp);
426 }
427
428 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy)
429 {
430 int val, nb, i;
431 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
432 FLOPPY_DRIVE_TYPE_NONE };
433
434 /* floppy type */
435 if (floppy) {
436 for (i = 0; i < 2; i++) {
437 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
438 }
439 }
440 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
441 cmos_get_fd_drive_type(fd_type[1]);
442 mc146818rtc_set_cmos_data(rtc_state, 0x10, val);
443
444 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE);
445 nb = 0;
446 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
447 nb++;
448 }
449 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
450 nb++;
451 }
452 switch (nb) {
453 case 0:
454 break;
455 case 1:
456 val |= 0x01; /* 1 drive, ready for boot */
457 break;
458 case 2:
459 val |= 0x41; /* 2 drives, ready for boot */
460 break;
461 }
462 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val);
463 }
464
465 typedef struct pc_cmos_init_late_arg {
466 MC146818RtcState *rtc_state;
467 BusState *idebus[2];
468 } pc_cmos_init_late_arg;
469
470 typedef struct check_fdc_state {
471 ISADevice *floppy;
472 bool multiple;
473 } CheckFdcState;
474
475 static int check_fdc(Object *obj, void *opaque)
476 {
477 CheckFdcState *state = opaque;
478 Object *fdc;
479 uint32_t iobase;
480 Error *local_err = NULL;
481
482 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
483 if (!fdc) {
484 return 0;
485 }
486
487 iobase = object_property_get_uint(obj, "iobase", &local_err);
488 if (local_err || iobase != 0x3f0) {
489 error_free(local_err);
490 return 0;
491 }
492
493 if (state->floppy) {
494 state->multiple = true;
495 } else {
496 state->floppy = ISA_DEVICE(obj);
497 }
498 return 0;
499 }
500
501 static const char * const fdc_container_path[] = {
502 "/unattached", "/peripheral", "/peripheral-anon"
503 };
504
505 /*
506 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
507 * and ACPI objects.
508 */
509 static ISADevice *pc_find_fdc0(void)
510 {
511 int i;
512 Object *container;
513 CheckFdcState state = { 0 };
514
515 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
516 container = container_get(qdev_get_machine(), fdc_container_path[i]);
517 object_child_foreach(container, check_fdc, &state);
518 }
519
520 if (state.multiple) {
521 warn_report("multiple floppy disk controllers with "
522 "iobase=0x3f0 have been found");
523 error_printf("the one being picked for CMOS setup might not reflect "
524 "your intent");
525 }
526
527 return state.floppy;
528 }
529
530 static void pc_cmos_init_late(void *opaque)
531 {
532 pc_cmos_init_late_arg *arg = opaque;
533 MC146818RtcState *s = arg->rtc_state;
534 int16_t cylinders;
535 int8_t heads, sectors;
536 int val;
537 int i, trans;
538
539 val = 0;
540 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
541 &cylinders, &heads, &sectors) >= 0) {
542 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
543 val |= 0xf0;
544 }
545 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
546 &cylinders, &heads, &sectors) >= 0) {
547 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
548 val |= 0x0f;
549 }
550 mc146818rtc_set_cmos_data(s, 0x12, val);
551
552 val = 0;
553 for (i = 0; i < 4; i++) {
554 /* NOTE: ide_get_geometry() returns the physical
555 geometry. It is always such that: 1 <= sects <= 63, 1
556 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
557 geometry can be different if a translation is done. */
558 if (arg->idebus[i / 2] &&
559 ide_get_geometry(arg->idebus[i / 2], i % 2,
560 &cylinders, &heads, &sectors) >= 0) {
561 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
562 assert((trans & ~3) == 0);
563 val |= trans << (i * 2);
564 }
565 }
566 mc146818rtc_set_cmos_data(s, 0x39, val);
567
568 pc_cmos_init_floppy(s, pc_find_fdc0());
569
570 qemu_unregister_reset(pc_cmos_init_late, opaque);
571 }
572
573 void pc_cmos_init(PCMachineState *pcms,
574 BusState *idebus0, BusState *idebus1,
575 ISADevice *rtc)
576 {
577 int val;
578 static pc_cmos_init_late_arg arg;
579 X86MachineState *x86ms = X86_MACHINE(pcms);
580 MC146818RtcState *s = MC146818_RTC(rtc);
581
582 /* various important CMOS locations needed by PC/Bochs bios */
583
584 /* memory size */
585 /* base memory (first MiB) */
586 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
587 mc146818rtc_set_cmos_data(s, 0x15, val);
588 mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
589 /* extended memory (next 64MiB) */
590 if (x86ms->below_4g_mem_size > 1 * MiB) {
591 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
592 } else {
593 val = 0;
594 }
595 if (val > 65535)
596 val = 65535;
597 mc146818rtc_set_cmos_data(s, 0x17, val);
598 mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
599 mc146818rtc_set_cmos_data(s, 0x30, val);
600 mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
601 /* memory between 16MiB and 4GiB */
602 if (x86ms->below_4g_mem_size > 16 * MiB) {
603 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
604 } else {
605 val = 0;
606 }
607 if (val > 65535)
608 val = 65535;
609 mc146818rtc_set_cmos_data(s, 0x34, val);
610 mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
611 /* memory above 4GiB */
612 val = x86ms->above_4g_mem_size / 65536;
613 mc146818rtc_set_cmos_data(s, 0x5b, val);
614 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
615 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
616
617 object_property_add_link(OBJECT(pcms), "rtc_state",
618 TYPE_ISA_DEVICE,
619 (Object **)&x86ms->rtc,
620 object_property_allow_set_link,
621 OBJ_PROP_LINK_STRONG);
622 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
623 &error_abort);
624
625 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
626
627 val = 0;
628 val |= 0x02; /* FPU is there */
629 val |= 0x04; /* PS/2 mouse installed */
630 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val);
631
632 /* hard drives and FDC */
633 arg.rtc_state = s;
634 arg.idebus[0] = idebus0;
635 arg.idebus[1] = idebus1;
636 qemu_register_reset(pc_cmos_init_late, &arg);
637 }
638
639 static void handle_a20_line_change(void *opaque, int irq, int level)
640 {
641 X86CPU *cpu = opaque;
642
643 /* XXX: send to all CPUs ? */
644 /* XXX: add logic to handle multiple A20 line sources */
645 x86_cpu_set_a20(cpu, level);
646 }
647
648 #define NE2000_NB_MAX 6
649
650 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
651 0x280, 0x380 };
652 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
653
654 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
655 {
656 static int nb_ne2k = 0;
657
658 if (nb_ne2k == NE2000_NB_MAX)
659 return;
660 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
661 ne2000_irq[nb_ne2k], nd);
662 nb_ne2k++;
663 }
664
665 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
666 {
667 X86CPU *cpu = opaque;
668
669 if (level) {
670 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
671 }
672 }
673
674 static
675 void pc_machine_done(Notifier *notifier, void *data)
676 {
677 PCMachineState *pcms = container_of(notifier,
678 PCMachineState, machine_done);
679 X86MachineState *x86ms = X86_MACHINE(pcms);
680
681 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state,
682 &error_fatal);
683
684 if (pcms->cxl_devices_state.is_enabled) {
685 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
686 }
687
688 /* set the number of CPUs */
689 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
690
691 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
692
693 acpi_setup();
694 if (x86ms->fw_cfg) {
695 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
696 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
697 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
698 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
699 }
700 }
701
702 void pc_guest_info_init(PCMachineState *pcms)
703 {
704 X86MachineState *x86ms = X86_MACHINE(pcms);
705
706 x86ms->apic_xrupt_override = true;
707 pcms->machine_done.notify = pc_machine_done;
708 qemu_add_machine_init_done_notifier(&pcms->machine_done);
709 }
710
711 /* setup pci memory address space mapping into system address space */
712 void pc_pci_as_mapping_init(MemoryRegion *system_memory,
713 MemoryRegion *pci_address_space)
714 {
715 /* Set to lower priority than RAM */
716 memory_region_add_subregion_overlap(system_memory, 0x0,
717 pci_address_space, -1);
718 }
719
720 void xen_load_linux(PCMachineState *pcms)
721 {
722 int i;
723 FWCfgState *fw_cfg;
724 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
725 X86MachineState *x86ms = X86_MACHINE(pcms);
726
727 assert(MACHINE(pcms)->kernel_filename != NULL);
728
729 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
730 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
731 rom_set_fw(fw_cfg);
732
733 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
734 pcmc->pvh_enabled);
735 for (i = 0; i < nb_option_roms; i++) {
736 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
737 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
738 !strcmp(option_rom[i].name, "pvh.bin") ||
739 !strcmp(option_rom[i].name, "multiboot.bin") ||
740 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
741 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
742 }
743 x86ms->fw_cfg = fw_cfg;
744 }
745
746 #define PC_ROM_MIN_VGA 0xc0000
747 #define PC_ROM_MIN_OPTION 0xc8000
748 #define PC_ROM_MAX 0xe0000
749 #define PC_ROM_ALIGN 0x800
750 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
751
752 static hwaddr pc_above_4g_end(PCMachineState *pcms)
753 {
754 X86MachineState *x86ms = X86_MACHINE(pcms);
755
756 if (pcms->sgx_epc.size != 0) {
757 return sgx_epc_above_4g_end(&pcms->sgx_epc);
758 }
759
760 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
761 }
762
763 static void pc_get_device_memory_range(PCMachineState *pcms,
764 hwaddr *base,
765 ram_addr_t *device_mem_size)
766 {
767 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
768 MachineState *machine = MACHINE(pcms);
769 ram_addr_t size;
770 hwaddr addr;
771
772 size = machine->maxram_size - machine->ram_size;
773 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
774
775 if (pcmc->enforce_aligned_dimm) {
776 /* size device region assuming 1G page max alignment per slot */
777 size += (1 * GiB) * machine->ram_slots;
778 }
779
780 *base = addr;
781 *device_mem_size = size;
782 }
783
784 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
785 {
786 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
787 MachineState *ms = MACHINE(pcms);
788 hwaddr cxl_base;
789 ram_addr_t size;
790
791 if (pcmc->has_reserved_memory &&
792 (ms->ram_size < ms->maxram_size)) {
793 pc_get_device_memory_range(pcms, &cxl_base, &size);
794 cxl_base += size;
795 } else {
796 cxl_base = pc_above_4g_end(pcms);
797 }
798
799 return cxl_base;
800 }
801
802 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
803 {
804 uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
805
806 if (pcms->cxl_devices_state.fixed_windows) {
807 GList *it;
808
809 start = ROUND_UP(start, 256 * MiB);
810 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
811 CXLFixedWindow *fw = it->data;
812 start += fw->size;
813 }
814 }
815
816 return start;
817 }
818
819 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
820 {
821 X86CPU *cpu = X86_CPU(first_cpu);
822 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
823 MachineState *ms = MACHINE(pcms);
824
825 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
826 /* 64-bit systems */
827 return pc_pci_hole64_start() + pci_hole64_size - 1;
828 }
829
830 /* 32-bit systems */
831 if (pcmc->broken_32bit_mem_addr_check) {
832 /* old value for compatibility reasons */
833 return ((hwaddr)1 << cpu->phys_bits) - 1;
834 }
835
836 /*
837 * 32-bit systems don't have hole64 but they might have a region for
838 * memory devices. Even if additional hotplugged memory devices might
839 * not be usable by most guest OSes, we need to still consider them for
840 * calculating the highest possible GPA so that we can properly report
841 * if someone configures them on a CPU that cannot possibly address them.
842 */
843 if (pcmc->has_reserved_memory &&
844 (ms->ram_size < ms->maxram_size)) {
845 hwaddr devmem_start;
846 ram_addr_t devmem_size;
847
848 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size);
849 devmem_start += devmem_size;
850 return devmem_start - 1;
851 }
852
853 /* configuration without any memory hotplug */
854 return pc_above_4g_end(pcms) - 1;
855 }
856
857 /*
858 * AMD systems with an IOMMU have an additional hole close to the
859 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
860 * on kernel version, VFIO may or may not let you DMA map those ranges.
861 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
862 * with certain memory sizes. It's also wrong to use those IOVA ranges
863 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
864 * The ranges reserved for Hyper-Transport are:
865 *
866 * FD_0000_0000h - FF_FFFF_FFFFh
867 *
868 * The ranges represent the following:
869 *
870 * Base Address Top Address Use
871 *
872 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
873 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
874 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
875 * FD_F910_0000h FD_F91F_FFFFh System Management
876 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
877 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
878 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
879 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
880 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
881 * FE_2000_0000h FF_FFFF_FFFFh Reserved
882 *
883 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
884 * Table 3: Special Address Controls (GPA) for more information.
885 */
886 #define AMD_HT_START 0xfd00000000UL
887 #define AMD_HT_END 0xffffffffffUL
888 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
889 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
890
891 void pc_memory_init(PCMachineState *pcms,
892 MemoryRegion *system_memory,
893 MemoryRegion *rom_memory,
894 uint64_t pci_hole64_size)
895 {
896 int linux_boot, i;
897 MemoryRegion *option_rom_mr;
898 MemoryRegion *ram_below_4g, *ram_above_4g;
899 FWCfgState *fw_cfg;
900 MachineState *machine = MACHINE(pcms);
901 MachineClass *mc = MACHINE_GET_CLASS(machine);
902 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
903 X86MachineState *x86ms = X86_MACHINE(pcms);
904 hwaddr maxphysaddr, maxusedaddr;
905 hwaddr cxl_base, cxl_resv_end = 0;
906 X86CPU *cpu = X86_CPU(first_cpu);
907
908 assert(machine->ram_size == x86ms->below_4g_mem_size +
909 x86ms->above_4g_mem_size);
910
911 linux_boot = (machine->kernel_filename != NULL);
912
913 /*
914 * The HyperTransport range close to the 1T boundary is unique to AMD
915 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
916 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
917 * older machine types (<= 7.0) for compatibility purposes.
918 */
919 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
920 /* Bail out if max possible address does not cross HT range */
921 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
922 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
923 }
924
925 /*
926 * Advertise the HT region if address space covers the reserved
927 * region or if we relocate.
928 */
929 if (cpu->phys_bits >= 40) {
930 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
931 }
932 }
933
934 /*
935 * phys-bits is required to be appropriately configured
936 * to make sure max used GPA is reachable.
937 */
938 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
939 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
940 if (maxphysaddr < maxusedaddr) {
941 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
942 " phys-bits too low (%u)",
943 maxphysaddr, maxusedaddr, cpu->phys_bits);
944 exit(EXIT_FAILURE);
945 }
946
947 /*
948 * Split single memory region and use aliases to address portions of it,
949 * done for backwards compatibility with older qemus.
950 */
951 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
952 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
953 0, x86ms->below_4g_mem_size);
954 memory_region_add_subregion(system_memory, 0, ram_below_4g);
955 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
956 if (x86ms->above_4g_mem_size > 0) {
957 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
958 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
959 machine->ram,
960 x86ms->below_4g_mem_size,
961 x86ms->above_4g_mem_size);
962 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
963 ram_above_4g);
964 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
965 E820_RAM);
966 }
967
968 if (pcms->sgx_epc.size != 0) {
969 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
970 }
971
972 if (!pcmc->has_reserved_memory &&
973 (machine->ram_slots ||
974 (machine->maxram_size > machine->ram_size))) {
975
976 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
977 mc->name);
978 exit(EXIT_FAILURE);
979 }
980
981 /* initialize device memory address space */
982 if (pcmc->has_reserved_memory &&
983 (machine->ram_size < machine->maxram_size)) {
984 ram_addr_t device_mem_size;
985 hwaddr device_mem_base;
986
987 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
988 error_report("unsupported amount of memory slots: %"PRIu64,
989 machine->ram_slots);
990 exit(EXIT_FAILURE);
991 }
992
993 if (QEMU_ALIGN_UP(machine->maxram_size,
994 TARGET_PAGE_SIZE) != machine->maxram_size) {
995 error_report("maximum memory size must by aligned to multiple of "
996 "%d bytes", TARGET_PAGE_SIZE);
997 exit(EXIT_FAILURE);
998 }
999
1000 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size);
1001
1002 if (device_mem_base + device_mem_size < device_mem_size) {
1003 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1004 machine->maxram_size);
1005 exit(EXIT_FAILURE);
1006 }
1007 machine_memory_devices_init(machine, device_mem_base, device_mem_size);
1008 }
1009
1010 if (pcms->cxl_devices_state.is_enabled) {
1011 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1012 hwaddr cxl_size = MiB;
1013
1014 cxl_base = pc_get_cxl_range_start(pcms);
1015 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1016 memory_region_add_subregion(system_memory, cxl_base, mr);
1017 cxl_resv_end = cxl_base + cxl_size;
1018 if (pcms->cxl_devices_state.fixed_windows) {
1019 hwaddr cxl_fmw_base;
1020 GList *it;
1021
1022 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1023 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
1024 CXLFixedWindow *fw = it->data;
1025
1026 fw->base = cxl_fmw_base;
1027 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1028 "cxl-fixed-memory-region", fw->size);
1029 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
1030 cxl_fmw_base += fw->size;
1031 cxl_resv_end = cxl_fmw_base;
1032 }
1033 }
1034 }
1035
1036 /* Initialize PC system firmware */
1037 pc_system_firmware_init(pcms, rom_memory);
1038
1039 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1040 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1041 &error_fatal);
1042 if (pcmc->pci_enabled) {
1043 memory_region_set_readonly(option_rom_mr, true);
1044 }
1045 memory_region_add_subregion_overlap(rom_memory,
1046 PC_ROM_MIN_VGA,
1047 option_rom_mr,
1048 1);
1049
1050 fw_cfg = fw_cfg_arch_create(machine,
1051 x86ms->boot_cpus, x86ms->apic_id_limit);
1052
1053 rom_set_fw(fw_cfg);
1054
1055 if (machine->device_memory) {
1056 uint64_t *val = g_malloc(sizeof(*val));
1057 uint64_t res_mem_end = machine->device_memory->base;
1058
1059 if (!pcmc->broken_reserved_end) {
1060 res_mem_end += memory_region_size(&machine->device_memory->mr);
1061 }
1062
1063 if (pcms->cxl_devices_state.is_enabled) {
1064 res_mem_end = cxl_resv_end;
1065 }
1066 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1067 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1068 }
1069
1070 if (linux_boot) {
1071 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1072 pcmc->pvh_enabled);
1073 }
1074
1075 for (i = 0; i < nb_option_roms; i++) {
1076 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1077 }
1078 x86ms->fw_cfg = fw_cfg;
1079
1080 /* Init default IOAPIC address space */
1081 x86ms->ioapic_as = &address_space_memory;
1082
1083 /* Init ACPI memory hotplug IO base address */
1084 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1085 }
1086
1087 /*
1088 * The 64bit pci hole starts after "above 4G RAM" and
1089 * potentially the space reserved for memory hotplug.
1090 */
1091 uint64_t pc_pci_hole64_start(void)
1092 {
1093 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1094 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1095 MachineState *ms = MACHINE(pcms);
1096 uint64_t hole64_start = 0;
1097 ram_addr_t size = 0;
1098
1099 if (pcms->cxl_devices_state.is_enabled) {
1100 hole64_start = pc_get_cxl_range_end(pcms);
1101 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1102 pc_get_device_memory_range(pcms, &hole64_start, &size);
1103 if (!pcmc->broken_reserved_end) {
1104 hole64_start += size;
1105 }
1106 } else {
1107 hole64_start = pc_above_4g_end(pcms);
1108 }
1109
1110 return ROUND_UP(hole64_start, 1 * GiB);
1111 }
1112
1113 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1114 {
1115 DeviceState *dev = NULL;
1116
1117 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1118 if (pci_bus) {
1119 PCIDevice *pcidev = pci_vga_init(pci_bus);
1120 dev = pcidev ? &pcidev->qdev : NULL;
1121 } else if (isa_bus) {
1122 ISADevice *isadev = isa_vga_init(isa_bus);
1123 dev = isadev ? DEVICE(isadev) : NULL;
1124 }
1125 rom_reset_order_override();
1126 return dev;
1127 }
1128
1129 static const MemoryRegionOps ioport80_io_ops = {
1130 .write = ioport80_write,
1131 .read = ioport80_read,
1132 .endianness = DEVICE_NATIVE_ENDIAN,
1133 .impl = {
1134 .min_access_size = 1,
1135 .max_access_size = 1,
1136 },
1137 };
1138
1139 static const MemoryRegionOps ioportF0_io_ops = {
1140 .write = ioportF0_write,
1141 .read = ioportF0_read,
1142 .endianness = DEVICE_NATIVE_ENDIAN,
1143 .impl = {
1144 .min_access_size = 1,
1145 .max_access_size = 1,
1146 },
1147 };
1148
1149 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1150 bool create_i8042, bool no_vmport)
1151 {
1152 int i;
1153 DriveInfo *fd[MAX_FD];
1154 qemu_irq *a20_line;
1155 ISADevice *fdc, *i8042, *port92, *vmmouse;
1156
1157 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1158 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1159
1160 for (i = 0; i < MAX_FD; i++) {
1161 fd[i] = drive_get(IF_FLOPPY, 0, i);
1162 create_fdctrl |= !!fd[i];
1163 }
1164 if (create_fdctrl) {
1165 fdc = isa_new(TYPE_ISA_FDC);
1166 if (fdc) {
1167 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1168 isa_fdc_init_drives(fdc, fd);
1169 }
1170 }
1171
1172 if (!create_i8042) {
1173 return;
1174 }
1175
1176 i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1177 if (!no_vmport) {
1178 isa_create_simple(isa_bus, TYPE_VMPORT);
1179 vmmouse = isa_try_new("vmmouse");
1180 } else {
1181 vmmouse = NULL;
1182 }
1183 if (vmmouse) {
1184 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1185 &error_abort);
1186 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1187 }
1188 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1189
1190 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1191 i8042_setup_a20_line(i8042, a20_line[0]);
1192 qdev_connect_gpio_out_named(DEVICE(port92),
1193 PORT92_A20_LINE, 0, a20_line[1]);
1194 g_free(a20_line);
1195 }
1196
1197 void pc_basic_device_init(struct PCMachineState *pcms,
1198 ISABus *isa_bus, qemu_irq *gsi,
1199 ISADevice *rtc_state,
1200 bool create_fdctrl,
1201 uint32_t hpet_irqs)
1202 {
1203 int i;
1204 DeviceState *hpet = NULL;
1205 int pit_isa_irq = 0;
1206 qemu_irq pit_alt_irq = NULL;
1207 ISADevice *pit = NULL;
1208 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1209 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1210 X86MachineState *x86ms = X86_MACHINE(pcms);
1211
1212 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1213 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1214
1215 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1216 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1217
1218 /*
1219 * Check if an HPET shall be created.
1220 */
1221 if (pcms->hpet_enabled) {
1222 qemu_irq rtc_irq;
1223
1224 hpet = qdev_try_new(TYPE_HPET);
1225 if (!hpet) {
1226 error_report("couldn't create HPET device");
1227 exit(1);
1228 }
1229 /*
1230 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*,
1231 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set
1232 * the property, use whatever mask they specified.
1233 */
1234 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1235 HPET_INTCAP, NULL);
1236 if (!compat) {
1237 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1238 }
1239 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1240 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1241
1242 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1243 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1244 }
1245 pit_isa_irq = -1;
1246 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1247 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1248
1249 /* overwrite connection created by south bridge */
1250 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq);
1251 }
1252
1253 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state),
1254 "date");
1255
1256 #ifdef CONFIG_XEN_EMU
1257 if (xen_mode == XEN_EMULATE) {
1258 xen_overlay_create();
1259 xen_evtchn_create(IOAPIC_NUM_PINS, gsi);
1260 xen_gnttab_create();
1261 xen_xenstore_create();
1262 if (pcms->bus) {
1263 pci_create_simple(pcms->bus, -1, "xen-platform");
1264 }
1265 pcms->xenbus = xen_bus_init();
1266 xen_be_init();
1267 }
1268 #endif
1269
1270 qemu_register_boot_set(pc_boot_set, rtc_state);
1271
1272 if (!xen_enabled() &&
1273 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1274 if (kvm_pit_in_kernel()) {
1275 pit = kvm_pit_init(isa_bus, 0x40);
1276 } else {
1277 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1278 }
1279 if (hpet) {
1280 /* connect PIT to output control line of the HPET */
1281 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1282 }
1283 object_property_set_link(OBJECT(pcms->pcspk), "pit",
1284 OBJECT(pit), &error_fatal);
1285 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal);
1286 }
1287
1288 /* Super I/O */
1289 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1290 pcms->vmport != ON_OFF_AUTO_ON);
1291 }
1292
1293 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus,
1294 BusState *xen_bus)
1295 {
1296 MachineClass *mc = MACHINE_CLASS(pcmc);
1297 int i;
1298
1299 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1300 for (i = 0; i < nb_nics; i++) {
1301 NICInfo *nd = &nd_table[i];
1302 const char *model = nd->model ? nd->model : mc->default_nic;
1303
1304 if (xen_bus && (!nd->model || g_str_equal(model, "xen-net-device"))) {
1305 DeviceState *dev = qdev_new("xen-net-device");
1306 qdev_set_nic_properties(dev, nd);
1307 qdev_realize_and_unref(dev, xen_bus, &error_fatal);
1308 } else if (g_str_equal(model, "ne2k_isa")) {
1309 pc_init_ne2k_isa(isa_bus, nd);
1310 } else {
1311 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1312 }
1313 }
1314 rom_reset_order_override();
1315 }
1316
1317 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1318 {
1319 qemu_irq *i8259;
1320
1321 if (kvm_pic_in_kernel()) {
1322 i8259 = kvm_i8259_init(isa_bus);
1323 } else if (xen_enabled()) {
1324 i8259 = xen_interrupt_controller_init();
1325 } else {
1326 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1327 }
1328
1329 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1330 i8259_irqs[i] = i8259[i];
1331 }
1332
1333 g_free(i8259);
1334 }
1335
1336 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1337 Error **errp)
1338 {
1339 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1340 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1341 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1342 const MachineState *ms = MACHINE(hotplug_dev);
1343 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1344 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1345 Error *local_err = NULL;
1346
1347 /*
1348 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1349 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1350 * addition to cover this case.
1351 */
1352 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1353 error_setg(errp,
1354 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1355 return;
1356 }
1357
1358 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1359 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1360 return;
1361 }
1362
1363 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1364 if (local_err) {
1365 error_propagate(errp, local_err);
1366 return;
1367 }
1368
1369 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1370 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1371 }
1372
1373 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1374 DeviceState *dev, Error **errp)
1375 {
1376 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1377 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1378 MachineState *ms = MACHINE(hotplug_dev);
1379 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1380
1381 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1382
1383 if (is_nvdimm) {
1384 nvdimm_plug(ms->nvdimms_state);
1385 }
1386
1387 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1388 }
1389
1390 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1391 DeviceState *dev, Error **errp)
1392 {
1393 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1394
1395 /*
1396 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1397 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1398 * addition to cover this case.
1399 */
1400 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1401 error_setg(errp,
1402 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1403 return;
1404 }
1405
1406 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1407 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1408 return;
1409 }
1410
1411 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1412 errp);
1413 }
1414
1415 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1416 DeviceState *dev, Error **errp)
1417 {
1418 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1419 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1420 Error *local_err = NULL;
1421
1422 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1423 if (local_err) {
1424 goto out;
1425 }
1426
1427 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1428 qdev_unrealize(dev);
1429 out:
1430 error_propagate(errp, local_err);
1431 }
1432
1433 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev,
1434 DeviceState *dev, Error **errp)
1435 {
1436 /* The vmbus handler has no hotplug handler; we should never end up here. */
1437 g_assert(!dev->hotplugged);
1438 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1439 errp);
1440 }
1441
1442 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev,
1443 DeviceState *dev, Error **errp)
1444 {
1445 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1446 }
1447
1448 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1449 DeviceState *dev, Error **errp)
1450 {
1451 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1452 pc_memory_pre_plug(hotplug_dev, dev, errp);
1453 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1454 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1455 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1456 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1457 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1458 /* Declare the APIC range as the reserved MSI region */
1459 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1460 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1461 QList *reserved_regions = qlist_new();
1462
1463 qlist_append_str(reserved_regions, resv_prop_str);
1464 qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
1465
1466 g_free(resv_prop_str);
1467 }
1468
1469 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1470 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1471 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1472
1473 if (pcms->iommu) {
1474 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1475 "for x86 yet.");
1476 return;
1477 }
1478 pcms->iommu = dev;
1479 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1480 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp);
1481 }
1482 }
1483
1484 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1485 DeviceState *dev, Error **errp)
1486 {
1487 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1488 pc_memory_plug(hotplug_dev, dev, errp);
1489 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1490 x86_cpu_plug(hotplug_dev, dev, errp);
1491 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1492 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1493 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1494 pc_hv_balloon_plug(hotplug_dev, dev, errp);
1495 }
1496 }
1497
1498 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1499 DeviceState *dev, Error **errp)
1500 {
1501 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1502 pc_memory_unplug_request(hotplug_dev, dev, errp);
1503 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1504 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1505 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1506 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
1507 errp);
1508 } else {
1509 error_setg(errp, "acpi: device unplug request for not supported device"
1510 " type: %s", object_get_typename(OBJECT(dev)));
1511 }
1512 }
1513
1514 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1515 DeviceState *dev, Error **errp)
1516 {
1517 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1518 pc_memory_unplug(hotplug_dev, dev, errp);
1519 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1520 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1521 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1522 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1523 } else {
1524 error_setg(errp, "acpi: device unplug for not supported device"
1525 " type: %s", object_get_typename(OBJECT(dev)));
1526 }
1527 }
1528
1529 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1530 DeviceState *dev)
1531 {
1532 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1533 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1534 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
1535 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1536 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) ||
1537 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1538 return HOTPLUG_HANDLER(machine);
1539 }
1540
1541 return NULL;
1542 }
1543
1544 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1545 void *opaque, Error **errp)
1546 {
1547 PCMachineState *pcms = PC_MACHINE(obj);
1548 OnOffAuto vmport = pcms->vmport;
1549
1550 visit_type_OnOffAuto(v, name, &vmport, errp);
1551 }
1552
1553 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1554 void *opaque, Error **errp)
1555 {
1556 PCMachineState *pcms = PC_MACHINE(obj);
1557
1558 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1559 }
1560
1561 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1562 {
1563 PCMachineState *pcms = PC_MACHINE(obj);
1564
1565 return pcms->smbus_enabled;
1566 }
1567
1568 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1569 {
1570 PCMachineState *pcms = PC_MACHINE(obj);
1571
1572 pcms->smbus_enabled = value;
1573 }
1574
1575 static bool pc_machine_get_sata(Object *obj, Error **errp)
1576 {
1577 PCMachineState *pcms = PC_MACHINE(obj);
1578
1579 return pcms->sata_enabled;
1580 }
1581
1582 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1583 {
1584 PCMachineState *pcms = PC_MACHINE(obj);
1585
1586 pcms->sata_enabled = value;
1587 }
1588
1589 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1590 {
1591 PCMachineState *pcms = PC_MACHINE(obj);
1592
1593 return pcms->hpet_enabled;
1594 }
1595
1596 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1597 {
1598 PCMachineState *pcms = PC_MACHINE(obj);
1599
1600 pcms->hpet_enabled = value;
1601 }
1602
1603 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1604 {
1605 PCMachineState *pcms = PC_MACHINE(obj);
1606
1607 return pcms->i8042_enabled;
1608 }
1609
1610 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1611 {
1612 PCMachineState *pcms = PC_MACHINE(obj);
1613
1614 pcms->i8042_enabled = value;
1615 }
1616
1617 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1618 {
1619 PCMachineState *pcms = PC_MACHINE(obj);
1620
1621 return pcms->default_bus_bypass_iommu;
1622 }
1623
1624 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1625 Error **errp)
1626 {
1627 PCMachineState *pcms = PC_MACHINE(obj);
1628
1629 pcms->default_bus_bypass_iommu = value;
1630 }
1631
1632 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1633 void *opaque, Error **errp)
1634 {
1635 PCMachineState *pcms = PC_MACHINE(obj);
1636 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1637
1638 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1639 }
1640
1641 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1642 void *opaque, Error **errp)
1643 {
1644 PCMachineState *pcms = PC_MACHINE(obj);
1645
1646 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1647 }
1648
1649 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1650 const char *name, void *opaque,
1651 Error **errp)
1652 {
1653 PCMachineState *pcms = PC_MACHINE(obj);
1654 uint64_t value = pcms->max_ram_below_4g;
1655
1656 visit_type_size(v, name, &value, errp);
1657 }
1658
1659 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1660 const char *name, void *opaque,
1661 Error **errp)
1662 {
1663 PCMachineState *pcms = PC_MACHINE(obj);
1664 uint64_t value;
1665
1666 if (!visit_type_size(v, name, &value, errp)) {
1667 return;
1668 }
1669 if (value > 4 * GiB) {
1670 error_setg(errp,
1671 "Machine option 'max-ram-below-4g=%"PRIu64
1672 "' expects size less than or equal to 4G", value);
1673 return;
1674 }
1675
1676 if (value < 1 * MiB) {
1677 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1678 "BIOS may not work with less than 1MiB", value);
1679 }
1680
1681 pcms->max_ram_below_4g = value;
1682 }
1683
1684 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1685 const char *name, void *opaque,
1686 Error **errp)
1687 {
1688 PCMachineState *pcms = PC_MACHINE(obj);
1689 uint64_t value = pcms->max_fw_size;
1690
1691 visit_type_size(v, name, &value, errp);
1692 }
1693
1694 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1695 const char *name, void *opaque,
1696 Error **errp)
1697 {
1698 PCMachineState *pcms = PC_MACHINE(obj);
1699 uint64_t value;
1700
1701 if (!visit_type_size(v, name, &value, errp)) {
1702 return;
1703 }
1704
1705 /*
1706 * We don't have a theoretically justifiable exact lower bound on the base
1707 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1708 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1709 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to
1710 * 16MiB in size.
1711 */
1712 if (value > 16 * MiB) {
1713 error_setg(errp,
1714 "User specified max allowed firmware size %" PRIu64 " is "
1715 "greater than 16MiB. If combined firmware size exceeds "
1716 "16MiB the system may not boot, or experience intermittent"
1717 "stability issues.",
1718 value);
1719 return;
1720 }
1721
1722 pcms->max_fw_size = value;
1723 }
1724
1725
1726 static void pc_machine_initfn(Object *obj)
1727 {
1728 PCMachineState *pcms = PC_MACHINE(obj);
1729 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1730
1731 #ifdef CONFIG_VMPORT
1732 pcms->vmport = ON_OFF_AUTO_AUTO;
1733 #else
1734 pcms->vmport = ON_OFF_AUTO_OFF;
1735 #endif /* CONFIG_VMPORT */
1736 pcms->max_ram_below_4g = 0; /* use default */
1737 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
1738 pcms->south_bridge = pcmc->default_south_bridge;
1739
1740 /* acpi build is enabled by default if machine supports it */
1741 pcms->acpi_build_enabled = pcmc->has_acpi_build;
1742 pcms->smbus_enabled = true;
1743 pcms->sata_enabled = true;
1744 pcms->i8042_enabled = true;
1745 pcms->max_fw_size = 8 * MiB;
1746 #ifdef CONFIG_HPET
1747 pcms->hpet_enabled = true;
1748 #endif
1749 pcms->default_bus_bypass_iommu = false;
1750
1751 pc_system_flash_create(pcms);
1752 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1753 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1754 OBJECT(pcms->pcspk), "audiodev");
1755 cxl_machine_init(obj, &pcms->cxl_devices_state);
1756 }
1757
1758 int pc_machine_kvm_type(MachineState *machine, const char *kvm_type)
1759 {
1760 return 0;
1761 }
1762
1763 static void pc_machine_reset(MachineState *machine, ShutdownCause reason)
1764 {
1765 CPUState *cs;
1766 X86CPU *cpu;
1767
1768 qemu_devices_reset(reason);
1769
1770 /* Reset APIC after devices have been reset to cancel
1771 * any changes that qemu_devices_reset() might have done.
1772 */
1773 CPU_FOREACH(cs) {
1774 cpu = X86_CPU(cs);
1775
1776 x86_cpu_after_reset(cpu);
1777 }
1778 }
1779
1780 static void pc_machine_wakeup(MachineState *machine)
1781 {
1782 cpu_synchronize_all_states();
1783 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE);
1784 cpu_synchronize_all_post_reset();
1785 }
1786
1787 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1788 {
1789 X86IOMMUState *iommu = x86_iommu_get_default();
1790 IntelIOMMUState *intel_iommu;
1791
1792 if (iommu &&
1793 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1794 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1795 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1796 if (!intel_iommu->caching_mode) {
1797 error_setg(errp, "Device assignment is not allowed without "
1798 "enabling caching-mode=on for Intel IOMMU.");
1799 return false;
1800 }
1801 }
1802
1803 return true;
1804 }
1805
1806 static void pc_machine_class_init(ObjectClass *oc, void *data)
1807 {
1808 MachineClass *mc = MACHINE_CLASS(oc);
1809 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1810 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1811
1812 pcmc->pci_enabled = true;
1813 pcmc->has_acpi_build = true;
1814 pcmc->rsdp_in_ram = true;
1815 pcmc->smbios_defaults = true;
1816 pcmc->smbios_uuid_encoded = true;
1817 pcmc->gigabyte_align = true;
1818 pcmc->has_reserved_memory = true;
1819 pcmc->kvmclock_enabled = true;
1820 pcmc->enforce_aligned_dimm = true;
1821 pcmc->enforce_amd_1tb_hole = true;
1822 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1823 * to be used at the moment, 32K should be enough for a while. */
1824 pcmc->acpi_data_size = 0x20000 + 0x8000;
1825 pcmc->pvh_enabled = true;
1826 pcmc->kvmclock_create_always = true;
1827 pcmc->resizable_acpi_blob = true;
1828 assert(!mc->get_hotplug_handler);
1829 mc->get_hotplug_handler = pc_get_hotplug_handler;
1830 mc->hotplug_allowed = pc_hotplug_allowed;
1831 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1832 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1833 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1834 mc->auto_enable_numa_with_memhp = true;
1835 mc->auto_enable_numa_with_memdev = true;
1836 mc->has_hotpluggable_cpus = true;
1837 mc->default_boot_order = "cad";
1838 mc->block_default_type = IF_IDE;
1839 mc->max_cpus = 255;
1840 mc->reset = pc_machine_reset;
1841 mc->wakeup = pc_machine_wakeup;
1842 hc->pre_plug = pc_machine_device_pre_plug_cb;
1843 hc->plug = pc_machine_device_plug_cb;
1844 hc->unplug_request = pc_machine_device_unplug_request_cb;
1845 hc->unplug = pc_machine_device_unplug_cb;
1846 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1847 mc->nvdimm_supported = true;
1848 mc->smp_props.dies_supported = true;
1849 mc->default_ram_id = "pc.ram";
1850 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64;
1851
1852 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1853 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1854 NULL, NULL);
1855 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1856 "Maximum ram below the 4G boundary (32bit boundary)");
1857
1858 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1859 pc_machine_get_vmport, pc_machine_set_vmport,
1860 NULL, NULL);
1861 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1862 "Enable vmport (pc & q35)");
1863
1864 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1865 pc_machine_get_smbus, pc_machine_set_smbus);
1866 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1867 "Enable/disable system management bus");
1868
1869 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1870 pc_machine_get_sata, pc_machine_set_sata);
1871 object_class_property_set_description(oc, PC_MACHINE_SATA,
1872 "Enable/disable Serial ATA bus");
1873
1874 object_class_property_add_bool(oc, "hpet",
1875 pc_machine_get_hpet, pc_machine_set_hpet);
1876 object_class_property_set_description(oc, "hpet",
1877 "Enable/disable high precision event timer emulation");
1878
1879 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1880 pc_machine_get_i8042, pc_machine_set_i8042);
1881
1882 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1883 pc_machine_get_default_bus_bypass_iommu,
1884 pc_machine_set_default_bus_bypass_iommu);
1885
1886 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1887 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1888 NULL, NULL);
1889 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1890 "Maximum combined firmware size");
1891
1892 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1893 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1894 NULL, NULL);
1895 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1896 "SMBIOS Entry Point type [32, 64]");
1897 }
1898
1899 static const TypeInfo pc_machine_info = {
1900 .name = TYPE_PC_MACHINE,
1901 .parent = TYPE_X86_MACHINE,
1902 .abstract = true,
1903 .instance_size = sizeof(PCMachineState),
1904 .instance_init = pc_machine_initfn,
1905 .class_size = sizeof(PCMachineClass),
1906 .class_init = pc_machine_class_init,
1907 .interfaces = (InterfaceInfo[]) {
1908 { TYPE_HOTPLUG_HANDLER },
1909 { }
1910 },
1911 };
1912
1913 static void pc_machine_register_types(void)
1914 {
1915 type_register_static(&pc_machine_info);
1916 }
1917
1918 type_init(pc_machine_register_types)
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